* See the COPYING file in the top-level directory.
*/
-static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
CPUState *cpu = env_cpu(env);
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
- trace_guest_mem_before_exec(cpu, addr, info);
- trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
-
- return info;
+ trace_guest_rmw_before_exec(cpu, addr, oi);
}
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW);
}
#if HAVE_ATOMIC128
-static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
-
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
- return info;
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
}
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
}
-static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
-
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
- return info;
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
}
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
#endif
*/
#include "qemu/plugin.h"
-#include "trace/mem.h"
#if DATA_SIZE == 16
# define SUFFIX o
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ABI_TYPE cmpv, ABI_TYPE newv,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, cmpv, newv);
#else
ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
#endif
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return ret;
}
#if DATA_SIZE >= 16
#if HAVE_ATOMIC128
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
DATA_TYPE val;
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
+ atomic_trace_ld_pre(env, addr, oi);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
- atomic_trace_ld_post(env, addr, info);
+ atomic_trace_ld_post(env, addr, oi);
return val;
}
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
+ atomic_trace_st_pre(env, addr, oi);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_st_post(env, addr, info);
+ atomic_trace_st_post(env, addr, oi);
}
#endif
#else
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
ret = qatomic_xchg__nocheck(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return ret;
}
#define GEN_ATOMIC_HELPER(X) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
DATA_TYPE ret; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
ret = qatomic_##X(haddr, val); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return ret; \
}
*/
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
XDATA_TYPE cmp, old, new, val = xval; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
smp_mb(); \
cmp = qatomic_read__nocheck(haddr); \
do { \
cmp = qatomic_cmpxchg__nocheck(haddr, old, new); \
} while (cmp != old); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return RET; \
}
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ABI_TYPE cmpv, ABI_TYPE newv,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
#else
ret = qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
#endif
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return BSWAP(ret);
}
#if DATA_SIZE >= 16
#if HAVE_ATOMIC128
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
DATA_TYPE val;
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
+ atomic_trace_ld_pre(env, addr, oi);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
- atomic_trace_ld_post(env, addr, info);
+ atomic_trace_ld_post(env, addr, oi);
return BSWAP(val);
}
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
+ atomic_trace_st_pre(env, addr, oi);
val = BSWAP(val);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_st_post(env, addr, info);
+ atomic_trace_st_post(env, addr, oi);
}
#endif
#else
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
ABI_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return BSWAP(ret);
}
#define GEN_ATOMIC_HELPER(X) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
DATA_TYPE ret; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
ret = qatomic_##X(haddr, BSWAP(val)); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return BSWAP(ret); \
}
*/
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
XDATA_TYPE ldo, ldn, old, new, val = xval; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
smp_mb(); \
ldn = qatomic_read__nocheck(haddr); \
do { \
ldn = qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
} while (ldo != ldn); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return RET; \
}
#include "qemu/atomic128.h"
#include "exec/translate-all.h"
#include "trace/trace-root.h"
-#include "trace/mem.h"
#include "tb-hash.h"
#include "internal.h"
#ifdef CONFIG_PLUGIN
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
*/
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, int size, int prot,
+ MemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
size_t mmu_idx = get_mmuidx(oi);
*/
typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
static inline uint64_t QEMU_ALWAYS_INLINE
load_memop(const void *haddr, MemOp op)
}
static inline uint64_t QEMU_ALWAYS_INLINE
-load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
+load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
uintptr_t retaddr, MemOp op, bool code_read,
FullLoadHelper *full_load)
{
*/
static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu);
}
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_ldub_mmu(env, addr, oi, retaddr);
}
static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
full_le_lduw_mmu);
}
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_le_lduw_mmu(env, addr, oi, retaddr);
}
static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
full_be_lduw_mmu);
}
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_be_lduw_mmu(env, addr, oi, retaddr);
}
static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
full_le_ldul_mmu);
}
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_le_ldul_mmu(env, addr, oi, retaddr);
}
static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
full_be_ldul_mmu);
}
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_be_ldul_mmu(env, addr, oi, retaddr);
}
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
helper_le_ldq_mmu);
}
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
helper_be_ldq_mmu);
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
}
int mmu_idx, uintptr_t retaddr,
MemOp op, FullLoadHelper *full_load)
{
- uint16_t meminfo;
- TCGMemOpIdx oi;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
uint64_t ret;
- meminfo = trace_mem_get_info(op, mmu_idx, false);
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
- op &= ~MO_SIGN;
- oi = make_memop_idx(op, mmu_idx);
ret = full_load(env, addr, oi, retaddr);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB,
- full_ldub_mmu);
+ return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
- full_be_lduw_mmu);
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
- full_le_lduw_mmu);
+ return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
uintptr_t index, index2;
CPUTLBEntry *entry, *entry2;
target_ulong page2, tlb_addr, tlb_addr2;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
size_t size2;
int i;
static inline void QEMU_ALWAYS_INLINE
store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
+ MemOpIdx oi, uintptr_t retaddr, MemOp op)
{
uintptr_t mmu_idx = get_mmuidx(oi);
uintptr_t index = tlb_index(env, mmu_idx, addr);
void __attribute__((noinline))
helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_UB);
}
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEUW);
}
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEUW);
}
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEUL);
}
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEUL);
}
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEQ);
}
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEQ);
}
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
int mmu_idx, uintptr_t retaddr, MemOp op)
{
- TCGMemOpIdx oi;
- uint16_t meminfo;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
- meminfo = trace_mem_get_info(op, mmu_idx, true);
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
- oi = make_memop_idx(op, mmu_idx);
store_helper(env, addr, val, oi, retaddr, op);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
/* Code access functions. */
static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
}
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
return full_ldub_code(env, addr, oi, 0);
}
static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
}
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
return full_lduw_code(env, addr, oi, 0);
}
static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
}
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
return full_ldl_code(env, addr, oi, 0);
}
static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
}
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
return full_ldq_code(env, addr, oi, 0);
}
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
-#include "trace/mem.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"
#include "exec/translator.h"
const union mem_gen_fn *f, TCGv addr,
uint32_t info, bool is_mem)
{
- int wr = !!(info & TRACE_MEM_ST);
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
- gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, wr);
+ gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, rw);
if (is_mem) {
f->mem_fn(addr, info);
} else {
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "trace/trace-root.h"
-#include "trace/mem.h"
+#include "internal.h"
#undef EAX
#undef ECX
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldub_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsb_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int8_t)cpu_ldub_data(env, ptr);
}
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = lduw_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsw_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int16_t)cpu_lduw_be_data(env, ptr);
}
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldl_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
uint64_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldq_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = lduw_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsw_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int16_t)cpu_lduw_le_data(env, ptr);
}
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldl_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
uint64_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldq_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsb_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr);
}
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsw_be_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr);
}
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsw_le_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr);
}
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stb_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stw_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stl_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stq_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stw_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stl_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stq_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
*/
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, int size, int prot,
+ MemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
/* Enforce qemu required alignment. */
return ret;
}
-BlockDriverState *bdrv_new_open_driver(BlockDriver *drv, const char *node_name,
- int flags, Error **errp)
+/*
+ * Create and open a block node.
+ *
+ * @options is a QDict of options to pass to the block drivers, or NULL for an
+ * empty set of options. The reference to the QDict belongs to the block layer
+ * after the call (even on failure), so if the caller intends to reuse the
+ * dictionary, it needs to use qobject_ref() before calling bdrv_open.
+ */
+BlockDriverState *bdrv_new_open_driver_opts(BlockDriver *drv,
+ const char *node_name,
+ QDict *options, int flags,
+ Error **errp)
{
BlockDriverState *bs;
int ret;
bs = bdrv_new();
bs->open_flags = flags;
- bs->explicit_options = qdict_new();
- bs->options = qdict_new();
+ bs->options = options ?: qdict_new();
+ bs->explicit_options = qdict_clone_shallow(bs->options);
bs->opaque = NULL;
update_options_from_flags(bs->options, flags);
return bs;
}
+/* Create and open a block node. */
+BlockDriverState *bdrv_new_open_driver(BlockDriver *drv, const char *node_name,
+ int flags, Error **errp)
+{
+ return bdrv_new_open_driver_opts(drv, node_name, NULL, flags, errp);
+}
+
QemuOptsList bdrv_runtime_opts = {
.name = "bdrv_common",
.head = QTAILQ_HEAD_INITIALIZER(bdrv_runtime_opts.head),
g_free(bs);
}
-BlockDriverState *bdrv_insert_node(BlockDriverState *bs, QDict *node_options,
+
+/*
+ * Replace @bs by newly created block node.
+ *
+ * @options is a QDict of options to pass to the block drivers, or NULL for an
+ * empty set of options. The reference to the QDict belongs to the block layer
+ * after the call (even on failure), so if the caller intends to reuse the
+ * dictionary, it needs to use qobject_ref() before calling bdrv_open.
+ */
+BlockDriverState *bdrv_insert_node(BlockDriverState *bs, QDict *options,
int flags, Error **errp)
{
- BlockDriverState *new_node_bs;
- Error *local_err = NULL;
+ ERRP_GUARD();
+ int ret;
+ BlockDriverState *new_node_bs = NULL;
+ const char *drvname, *node_name;
+ BlockDriver *drv;
+
+ drvname = qdict_get_try_str(options, "driver");
+ if (!drvname) {
+ error_setg(errp, "driver is not specified");
+ goto fail;
+ }
+
+ drv = bdrv_find_format(drvname);
+ if (!drv) {
+ error_setg(errp, "Unknown driver: '%s'", drvname);
+ goto fail;
+ }
+
+ node_name = qdict_get_try_str(options, "node-name");
- new_node_bs = bdrv_open(NULL, NULL, node_options, flags, errp);
- if (new_node_bs == NULL) {
+ new_node_bs = bdrv_new_open_driver_opts(drv, node_name, options, flags,
+ errp);
+ options = NULL; /* bdrv_new_open_driver() eats options */
+ if (!new_node_bs) {
error_prepend(errp, "Could not create node: ");
- return NULL;
+ goto fail;
}
bdrv_drained_begin(bs);
- bdrv_replace_node(bs, new_node_bs, &local_err);
+ ret = bdrv_replace_node(bs, new_node_bs, errp);
bdrv_drained_end(bs);
- if (local_err) {
- bdrv_unref(new_node_bs);
- error_propagate(errp, local_err);
- return NULL;
+ if (ret < 0) {
+ error_prepend(errp, "Could not replace node: ");
+ goto fail;
}
return new_node_bs;
+
+fail:
+ qobject_unref(options);
+ bdrv_unref(new_node_bs);
+ return NULL;
}
/*
return ROUND_DOWN(max, blk_get_request_alignment(blk));
}
+int blk_get_max_hw_iov(BlockBackend *blk)
+{
+ return MIN_NON_ZERO(blk->root->bs->bl.max_hw_iov,
+ blk->root->bs->bl.max_iov);
+}
+
int blk_get_max_iov(BlockBackend *blk)
{
return blk->root->bs->bl.max_iov;
ret = hdev_get_max_segments(s->fd, &st);
if (ret > 0) {
- bs->bl.max_iov = ret;
+ bs->bl.max_hw_iov = ret;
}
}
}
dst->min_mem_alignment = MAX(dst->min_mem_alignment,
src->min_mem_alignment);
dst->max_iov = MIN_NON_ZERO(dst->max_iov, src->max_iov);
+ dst->max_hw_iov = MIN_NON_ZERO(dst->max_hw_iov, src->max_hw_iov);
}
typedef struct BdrvRefreshLimitsState {
}
do_cc() {
- do_compiler "$cc" "$@"
+ do_compiler "$cc" $CPU_CFLAGS "$@"
}
do_cxx() {
- do_compiler "$cxx" "$@"
+ do_compiler "$cxx" $CPU_CFLAGS "$@"
}
# Append $2 to the variable named $1, with space separation
eval "cross_cc_${cpu}=\$cc"
cross_cc_vars="$cross_cc_vars cross_cc_${cpu}"
-QEMU_CFLAGS="$CPU_CFLAGS $QEMU_CFLAGS"
# For user-mode emulation the host arch has to be one we explicitly
# support, even if we're using TCI.
python="$python -B"
if test -z "$meson"; then
- if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.55.3; then
+ if test "$explicit_python" = no && has meson && version_ge "$(meson --version)" 0.59.2; then
meson=meson
elif test $git_submodules_action != 'ignore' ; then
meson=git
echo "c_link_args = [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross
echo "cpp_link_args = [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross
echo "[binaries]" >> $cross
- echo "c = [$(meson_quote $cc)]" >> $cross
- test -n "$cxx" && echo "cpp = [$(meson_quote $cxx)]" >> $cross
- test -n "$objcc" && echo "objc = [$(meson_quote $objcc)]" >> $cross
+ echo "c = [$(meson_quote $cc $CPU_CFLAGS)]" >> $cross
+ test -n "$cxx" && echo "cpp = [$(meson_quote $cxx $CPU_CFLAGS)]" >> $cross
+ test -n "$objcc" && echo "objc = [$(meson_quote $objcc $CPU_CFLAGS)]" >> $cross
echo "ar = [$(meson_quote $ar)]" >> $cross
echo "nm = [$(meson_quote $nm)]" >> $cross
echo "pkgconfig = [$(meson_quote $pkg_config_exe)]" >> $cross
mv $cross config-meson.cross
rm -rf meson-private meson-info meson-logs
- unset staticpic
- if ! version_ge "$($meson --version)" 0.56.0; then
- staticpic=$(if test "$pie" = yes; then echo true; else echo false; fi)
- fi
NINJA=$ninja $meson setup \
--prefix "$prefix" \
--libdir "$libdir" \
-Dwerror=$(if test "$werror" = yes; then echo true; else echo false; fi) \
-Dstrip=$(if test "$strip_opt" = yes; then echo true; else echo false; fi) \
-Db_pie=$(if test "$pie" = yes; then echo true; else echo false; fi) \
- ${staticpic:+-Db_staticpic=$staticpic} \
-Db_coverage=$(if test "$gcov" = yes; then echo true; else echo false; fi) \
-Db_lto=$lto -Dcfi=$cfi -Dcfi_debug=$cfi_debug \
-Dmalloc=$malloc -Dmalloc_trim=$malloc_trim -Dsparse=$sparse \
perl -i -ne '
s/^gettext = true$/gettext = auto/;
s/^gettext = false$/gettext = disabled/;
+ /^b_staticpic/ && next;
print;' meson-private/cmd_line.txt
fi
fi
rv_op_fsflags = 316,
rv_op_fsrmi = 317,
rv_op_fsflagsi = 318,
+ rv_op_bseti = 319,
+ rv_op_bclri = 320,
+ rv_op_binvi = 321,
+ rv_op_bexti = 322,
+ rv_op_rori = 323,
+ rv_op_clz = 324,
+ rv_op_ctz = 325,
+ rv_op_cpop = 326,
+ rv_op_sext_h = 327,
+ rv_op_sext_b = 328,
+ rv_op_xnor = 329,
+ rv_op_orn = 330,
+ rv_op_andn = 331,
+ rv_op_rol = 332,
+ rv_op_ror = 333,
+ rv_op_sh1add = 334,
+ rv_op_sh2add = 335,
+ rv_op_sh3add = 336,
+ rv_op_sh1add_uw = 337,
+ rv_op_sh2add_uw = 338,
+ rv_op_sh3add_uw = 339,
+ rv_op_clmul = 340,
+ rv_op_clmulr = 341,
+ rv_op_clmulh = 342,
+ rv_op_min = 343,
+ rv_op_minu = 344,
+ rv_op_max = 345,
+ rv_op_maxu = 346,
+ rv_op_clzw = 347,
+ rv_op_ctzw = 348,
+ rv_op_cpopw = 349,
+ rv_op_slli_uw = 350,
+ rv_op_add_uw = 351,
+ rv_op_rolw = 352,
+ rv_op_rorw = 353,
+ rv_op_rev8 = 354,
+ rv_op_zext_h = 355,
+ rv_op_roriw = 356,
+ rv_op_orc_b = 357,
+ rv_op_bset = 358,
+ rv_op_bclr = 359,
+ rv_op_binv = 360,
+ rv_op_bext = 361,
} rv_op;
/* structures */
{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
+ { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
};
/* CSR names */
case 0: op = rv_op_addi; break;
case 1:
switch (((inst >> 27) & 0b11111)) {
- case 0: op = rv_op_slli; break;
+ case 0b00000: op = rv_op_slli; break;
+ case 0b00101: op = rv_op_bseti; break;
+ case 0b01001: op = rv_op_bclri; break;
+ case 0b01101: op = rv_op_binvi; break;
+ case 0b01100:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_clz; break;
+ case 0b0000001: op = rv_op_ctz; break;
+ case 0b0000010: op = rv_op_cpop; break;
+ /* 0b0000011 */
+ case 0b0000100: op = rv_op_sext_b; break;
+ case 0b0000101: op = rv_op_sext_h; break;
+ }
+ break;
}
break;
case 2: op = rv_op_slti; break;
case 4: op = rv_op_xori; break;
case 5:
switch (((inst >> 27) & 0b11111)) {
- case 0: op = rv_op_srli; break;
- case 8: op = rv_op_srai; break;
+ case 0b00000: op = rv_op_srli; break;
+ case 0b00101: op = rv_op_orc_b; break;
+ case 0b01000: op = rv_op_srai; break;
+ case 0b01001: op = rv_op_bexti; break;
+ case 0b01100: op = rv_op_rori; break;
+ case 0b01101:
+ switch ((inst >> 20) & 0b1111111) {
+ case 0b0111000: op = rv_op_rev8; break;
+ }
+ break;
}
break;
case 6: op = rv_op_ori; break;
case 1:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_slliw; break;
+ case 4: op = rv_op_slli_uw; break;
+ case 48:
+ switch ((inst >> 20) & 0b11111) {
+ case 0b00000: op = rv_op_clzw; break;
+ case 0b00001: op = rv_op_ctzw; break;
+ case 0b00010: op = rv_op_cpopw; break;
+ }
+ break;
}
break;
case 5:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break;
+ case 48: op = rv_op_roriw; break;
}
break;
}
case 13: op = rv_op_divu; break;
case 14: op = rv_op_rem; break;
case 15: op = rv_op_remu; break;
+ case 36:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_zext_h; break;
+ }
+ break;
+ case 41: op = rv_op_clmul; break;
+ case 42: op = rv_op_clmulr; break;
+ case 43: op = rv_op_clmulh; break;
+ case 44: op = rv_op_min; break;
+ case 45: op = rv_op_minu; break;
+ case 46: op = rv_op_max; break;
+ case 47: op = rv_op_maxu; break;
+ case 130: op = rv_op_sh1add; break;
+ case 132: op = rv_op_sh2add; break;
+ case 134: op = rv_op_sh3add; break;
+ case 161: op = rv_op_bset; break;
case 256: op = rv_op_sub; break;
+ case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
+ case 262: op = rv_op_orn; break;
+ case 263: op = rv_op_andn; break;
+ case 289: op = rv_op_bclr; break;
+ case 293: op = rv_op_bext; break;
+ case 385: op = rv_op_rol; break;
+ case 386: op = rv_op_ror; break;
+ case 417: op = rv_op_binv; break;
}
break;
case 13: op = rv_op_lui; break;
case 13: op = rv_op_divuw; break;
case 14: op = rv_op_remw; break;
case 15: op = rv_op_remuw; break;
+ case 32: op = rv_op_add_uw; break;
+ case 36:
+ switch ((inst >> 20) & 0b11111) {
+ case 0: op = rv_op_zext_h; break;
+ }
+ break;
+ case 130: op = rv_op_sh1add_uw; break;
+ case 132: op = rv_op_sh2add_uw; break;
+ case 134: op = rv_op_sh3add_uw; break;
case 256: op = rv_op_subw; break;
case 261: op = rv_op_sraw; break;
+ case 385: op = rv_op_rolw; break;
+ case 389: op = rv_op_rorw; break;
}
break;
case 16:
if build_docs
SPHINX_ARGS += ['-Dversion=' + meson.project_version(), '-Drelease=' + config_host['PKGVERSION']]
- sphinx_extn_depends = [ meson.source_root() / 'docs/sphinx/depfile.py',
- meson.source_root() / 'docs/sphinx/hxtool.py',
- meson.source_root() / 'docs/sphinx/kerneldoc.py',
- meson.source_root() / 'docs/sphinx/kernellog.py',
- meson.source_root() / 'docs/sphinx/qapidoc.py',
- meson.source_root() / 'docs/sphinx/qmp_lexer.py',
+ sphinx_extn_depends = [ meson.current_source_dir() / 'sphinx/depfile.py',
+ meson.current_source_dir() / 'sphinx/hxtool.py',
+ meson.current_source_dir() / 'sphinx/kerneldoc.py',
+ meson.current_source_dir() / 'sphinx/kernellog.py',
+ meson.current_source_dir() / 'sphinx/qapidoc.py',
+ meson.current_source_dir() / 'sphinx/qmp_lexer.py',
qapi_gen_depends ]
- sphinx_template_files = [ meson.source_root() / 'docs/_templates/footer.html' ]
+ sphinx_template_files = [ meson.project_source_root() / 'docs/_templates/footer.html' ]
have_ga = have_tools and config_host.has_key('CONFIG_GUEST_AGENT')
--- /dev/null
+Paravirtualized KVM features
+============================
+
+Description
+-----------
+
+In some cases when implementing hardware interfaces in software is slow, ``KVM``
+implements its own paravirtualized interfaces.
+
+Setup
+-----
+
+Paravirtualized ``KVM`` features are represented as CPU flags. The following
+features are enabled by default for any CPU model when ``KVM`` acceleration is
+enabled:
+
+- ``kvmclock``
+- ``kvm-nopiodelay``
+- ``kvm-asyncpf``
+- ``kvm-steal-time``
+- ``kvm-pv-eoi``
+- ``kvmclock-stable-bit``
+
+``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split
+irqchip (e.g. "-machine ...,kernel-irqchip=split -cpu ...,x2apic").
+
+Note: when CPU model ``host`` is used, QEMU passes through all supported
+paravirtualized ``KVM`` features to the guest.
+
+Existing features
+-----------------
+
+``kvmclock``
+ Expose a ``KVM`` specific paravirtualized clocksource to the guest. Supported
+ since Linux v2.6.26.
+
+``kvm-nopiodelay``
+ The guest doesn't need to perform delays on PIO operations. Supported since
+ Linux v2.6.26.
+
+``kvm-mmu``
+ This feature is deprecated.
+
+``kvm-asyncpf``
+ Enable asynchronous page fault mechanism. Supported since Linux v2.6.38.
+ Note: since Linux v5.10 the feature is deprecated and not enabled by ``KVM``.
+ Use ``kvm-asyncpf-int`` instead.
+
+``kvm-steal-time``
+ Enable stolen (when guest vCPU is not running) time accounting. Supported
+ since Linux v3.1.
+
+``kvm-pv-eoi``
+ Enable paravirtualized end-of-interrupt signaling. Supported since Linux
+ v3.10.
+
+``kvm-pv-unhalt``
+ Enable paravirtualized spinlocks support. Supported since Linux v3.12.
+
+``kvm-pv-tlb-flush``
+ Enable paravirtualized TLB flush mechanism. Supported since Linux v4.16.
+
+``kvm-pv-ipi``
+ Enable paravirtualized IPI mechanism. Supported since Linux v4.19.
+
+``kvm-poll-control``
+ Enable host-side polling on HLT control from the guest. Supported since Linux
+ v5.10.
+
+``kvm-pv-sched-yield``
+ Enable paravirtualized sched yield feature. Supported since Linux v5.10.
+
+``kvm-asyncpf-int``
+ Enable interrupt based asynchronous page fault mechanism. Supported since Linux
+ v5.10.
+
+``kvm-msi-ext-dest-id``
+ Support 'Extended Destination ID' for external interrupts. The feature allows
+ to use up to 32768 CPUs without IRQ remapping (but other limits may apply making
+ the number of supported vCPUs for a given configuration lower). Supported since
+ Linux v5.10.
+
+``kvmclock-stable-bit``
+ Tell the guest that guest visible TSC value can be fully trusted for kvmclock
+ computations and no warps are expected. Supported since Linux v2.6.35.
+
+Supplementary features
+----------------------
+
+``kvm-pv-enforce-cpuid``
+ Limit the supported paravirtualized feature set to the exposed features only.
+ Note, by default, ``KVM`` allows the guest to use all currently supported
+ paravirtualized features even when they were not announced in guest visible
+ CPUIDs. Supported since Linux v5.10.
+
+
+Useful links
+------------
+
+Please refer to Documentation/virt/kvm in Linux for additional details.
:maxdepth: 1
i386/cpu
+ i386/kvm-pv
i386/sgx
.. _pcsys_005freq:
#include "hw/i386/acpi-build.h"
void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry)
+ const CPUArchIdList *apic_ids, GArray *entry,
+ bool force_enabled)
{
}
g_array_append_val(array, val);
}
+static void build_append_padded_str(GArray *array, const char *str,
+ size_t maxlen, char pad)
+{
+ size_t i;
+ size_t len = strlen(str);
+
+ g_assert(len <= maxlen);
+ g_array_append_vals(array, str, len);
+ for (i = maxlen - len; i > 0; i--) {
+ g_array_append_val(array, pad);
+ }
+}
+
static void build_append_array(GArray *array, GArray *val)
{
g_array_append_vals(array, val->data, val->len);
return var;
}
-void
-build_header(BIOSLinker *linker, GArray *table_data,
- AcpiTableHeader *h, const char *sig, int len, uint8_t rev,
- const char *oem_id, const char *oem_table_id)
-{
- unsigned tbl_offset = (char *)h - table_data->data;
- unsigned checksum_offset = (char *)&h->checksum - table_data->data;
- memcpy(&h->signature, sig, 4);
- h->length = cpu_to_le32(len);
- h->revision = rev;
-
- strpadcpy((char *)h->oem_id, sizeof h->oem_id, oem_id, ' ');
- strpadcpy((char *)h->oem_table_id, sizeof h->oem_table_id,
- oem_table_id, ' ');
-
- h->oem_revision = cpu_to_le32(1);
- memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME8, 4);
- h->asl_compiler_revision = cpu_to_le32(1);
- /* Checksum to be filled in by Guest linker */
+void acpi_table_begin(AcpiTable *desc, GArray *array)
+{
+
+ desc->array = array;
+ desc->table_offset = array->len;
+
+ /*
+ * ACPI spec 1.0b
+ * 5.2.3 System Description Table Header
+ */
+ g_assert(strlen(desc->sig) == 4);
+ g_array_append_vals(array, desc->sig, 4); /* Signature */
+ /*
+ * reserve space for Length field, which will be patched by
+ * acpi_table_end() when the table creation is finished.
+ */
+ build_append_int_noprefix(array, 0, 4); /* Length */
+ build_append_int_noprefix(array, desc->rev, 1); /* Revision */
+ build_append_int_noprefix(array, 0, 1); /* Checksum */
+ build_append_padded_str(array, desc->oem_id, 6, ' '); /* OEMID */
+ /* OEM Table ID */
+ build_append_padded_str(array, desc->oem_table_id, 8, ' ');
+ build_append_int_noprefix(array, 1, 4); /* OEM Revision */
+ g_array_append_vals(array, ACPI_BUILD_APPNAME8, 4); /* Creator ID */
+ build_append_int_noprefix(array, 1, 4); /* Creator Revision */
+}
+
+void acpi_table_end(BIOSLinker *linker, AcpiTable *desc)
+{
+ /*
+ * ACPI spec 1.0b
+ * 5.2.3 System Description Table Header
+ * Table 5-2 DESCRIPTION_HEADER Fields
+ */
+ const unsigned checksum_offset = 9;
+ uint32_t table_len = desc->array->len - desc->table_offset;
+ uint32_t table_len_le = cpu_to_le32(table_len);
+ gchar *len_ptr = &desc->array->data[desc->table_offset + 4];
+
+ /* patch "Length" field that has been reserved by acpi_table_begin()
+ * to the actual length, i.e. accumulated table length from
+ * acpi_table_begin() till acpi_table_end()
+ */
+ memcpy(len_ptr, &table_len_le, sizeof table_len_le);
+
bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
- tbl_offset, len, checksum_offset);
+ desc->table_offset, table_len, desc->table_offset + checksum_offset);
}
void *acpi_data_push(GArray *table_data, unsigned size)
32);
}
-/* Build rsdt table */
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
void
build_rsdt(GArray *table_data, BIOSLinker *linker, GArray *table_offsets,
const char *oem_id, const char *oem_table_id)
{
int i;
- unsigned rsdt_entries_offset;
- AcpiRsdtDescriptorRev1 *rsdt;
- int rsdt_start = table_data->len;
- const unsigned table_data_len = (sizeof(uint32_t) * table_offsets->len);
- const unsigned rsdt_entry_size = sizeof(rsdt->table_offset_entry[0]);
- const size_t rsdt_len = sizeof(*rsdt) + table_data_len;
-
- rsdt = acpi_data_push(table_data, rsdt_len);
- rsdt_entries_offset = (char *)rsdt->table_offset_entry - table_data->data;
+ AcpiTable table = { .sig = "RSDT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
+
+ acpi_table_begin(&table, table_data);
for (i = 0; i < table_offsets->len; ++i) {
uint32_t ref_tbl_offset = g_array_index(table_offsets, uint32_t, i);
- uint32_t rsdt_entry_offset = rsdt_entries_offset + rsdt_entry_size * i;
+ uint32_t rsdt_entry_offset = table.array->len;
- /* rsdt->table_offset_entry to be filled by Guest linker */
+ /* reserve space for entry */
+ build_append_int_noprefix(table.array, 0, 4);
+
+ /* mark position of RSDT entry to be filled by Guest linker */
bios_linker_loader_add_pointer(linker,
- ACPI_BUILD_TABLE_FILE, rsdt_entry_offset, rsdt_entry_size,
+ ACPI_BUILD_TABLE_FILE, rsdt_entry_offset, 4,
ACPI_BUILD_TABLE_FILE, ref_tbl_offset);
+
}
- build_header(linker, table_data,
- (void *)(table_data->data + rsdt_start),
- "RSDT", rsdt_len, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
-/* Build xsdt table */
+/*
+ * ACPI 2.0 eXtended System Description Table (XSDT)
+ */
void
build_xsdt(GArray *table_data, BIOSLinker *linker, GArray *table_offsets,
const char *oem_id, const char *oem_table_id)
{
int i;
- unsigned xsdt_entries_offset;
- AcpiXsdtDescriptorRev2 *xsdt;
- int xsdt_start = table_data->len;
- const unsigned table_data_len = (sizeof(uint64_t) * table_offsets->len);
- const unsigned xsdt_entry_size = sizeof(xsdt->table_offset_entry[0]);
- const size_t xsdt_len = sizeof(*xsdt) + table_data_len;
-
- xsdt = acpi_data_push(table_data, xsdt_len);
- xsdt_entries_offset = (char *)xsdt->table_offset_entry - table_data->data;
+ AcpiTable table = { .sig = "XSDT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
for (i = 0; i < table_offsets->len; ++i) {
uint64_t ref_tbl_offset = g_array_index(table_offsets, uint32_t, i);
- uint64_t xsdt_entry_offset = xsdt_entries_offset + xsdt_entry_size * i;
+ uint64_t xsdt_entry_offset = table.array->len;
- /* xsdt->table_offset_entry to be filled by Guest linker */
+ /* reserve space for entry */
+ build_append_int_noprefix(table.array, 0, 8);
+
+ /* mark position of RSDT entry to be filled by Guest linker */
bios_linker_loader_add_pointer(linker,
- ACPI_BUILD_TABLE_FILE, xsdt_entry_offset, xsdt_entry_size,
+ ACPI_BUILD_TABLE_FILE, xsdt_entry_offset, 8,
ACPI_BUILD_TABLE_FILE, ref_tbl_offset);
}
- build_header(linker, table_data,
- (void *)(table_data->data + xsdt_start),
- "XSDT", xsdt_len, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
-void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
+/*
+ * ACPI spec, Revision 4.0
+ * 5.2.16.2 Memory Affinity Structure
+ */
+void build_srat_memory(GArray *table_data, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags)
{
- numamem->type = ACPI_SRAT_MEMORY;
- numamem->length = sizeof(*numamem);
- numamem->proximity = cpu_to_le32(node);
- numamem->flags = cpu_to_le32(flags);
- numamem->base_addr = cpu_to_le64(base);
- numamem->range_length = cpu_to_le64(len);
+ build_append_int_noprefix(table_data, 1, 1); /* Type */
+ build_append_int_noprefix(table_data, 40, 1); /* Length */
+ build_append_int_noprefix(table_data, node, 4); /* Proximity Domain */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, base, 4); /* Base Address Low */
+ /* Base Address High */
+ build_append_int_noprefix(table_data, base >> 32, 4);
+ build_append_int_noprefix(table_data, len, 4); /* Length Low */
+ build_append_int_noprefix(table_data, len >> 32, 4); /* Length High */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ build_append_int_noprefix(table_data, flags, 4); /* Flags */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
}
/*
void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms,
const char *oem_id, const char *oem_table_id)
{
- int slit_start, i, j;
- slit_start = table_data->len;
+ int i, j;
int nb_numa_nodes = ms->numa_state->num_nodes;
+ AcpiTable table = { .sig = "SLIT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, table_data);
build_append_int_noprefix(table_data, nb_numa_nodes, 8);
for (i = 0; i < nb_numa_nodes; i++) {
1);
}
}
-
- build_header(linker, table_data,
- (void *)(table_data->data + slit_start),
- "SLIT",
- table_data->len - slit_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
/* build rev1/rev3/rev5.1 FADT */
const char *oem_id, const char *oem_table_id)
{
int off;
- int fadt_start = tbl->len;
+ AcpiTable table = { .sig = "FACP", .rev = f->rev,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
- acpi_data_push(tbl, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, tbl);
/* FACS address to be filled by Guest linker at runtime */
off = tbl->len;
build_append_int_noprefix(tbl, f->flags, 4); /* Flags */
if (f->rev == 1) {
- goto build_hdr;
+ goto done;
}
build_append_gas_from_struct(tbl, &f->reset_reg); /* RESET_REG */
build_append_gas(tbl, AML_AS_SYSTEM_MEMORY, 0 , 0, 0, 0); /* X_GPE1_BLK */
if (f->rev <= 4) {
- goto build_hdr;
+ goto done;
}
/* SLEEP_CONTROL_REG */
/* TODO: extra fields need to be added to support revisions above rev5 */
assert(f->rev == 5);
-build_hdr:
- build_header(linker, tbl, (void *)(tbl->data + fadt_start),
- "FACP", tbl->len - fadt_start, f->rev, oem_id, oem_table_id);
+done:
+ acpi_table_end(linker, &table);
}
#ifdef CONFIG_TPM
const char *oem_id, const char *oem_table_id)
{
uint8_t start_method_params[12] = {};
- unsigned log_addr_offset, tpm2_start;
+ unsigned log_addr_offset;
uint64_t control_area_start_address;
TPMIf *tpmif = tpm_find();
uint32_t start_method;
+ AcpiTable table = { .sig = "TPM2", .rev = 4,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
- tpm2_start = table_data->len;
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, table_data);
/* Platform Class */
build_append_int_noprefix(table_data, TPM2_ACPI_CLASS_CLIENT, 2);
bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
log_addr_offset, 8,
ACPI_BUILD_TPMLOG_FILE, 0);
- build_header(linker, table_data,
- (void *)(table_data->data + tpm2_start),
- "TPM2", table_data->len - tpm2_start, 4, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
#endif
/* build _MAT object */
assert(adevc && adevc->madt_cpu);
- adevc->madt_cpu(adev, i, arch_ids, madt_buf);
- switch (madt_buf->data[0]) {
- case ACPI_APIC_PROCESSOR: {
- AcpiMadtProcessorApic *apic = (void *)madt_buf->data;
- apic->flags = cpu_to_le32(1);
- break;
- }
- case ACPI_APIC_LOCAL_X2APIC: {
- AcpiMadtProcessorX2Apic *apic = (void *)madt_buf->data;
- apic->flags = cpu_to_le32(1);
- break;
- }
- default:
- assert(0);
- }
+ adevc->madt_cpu(adev, i, arch_ids, madt_buf,
+ true); /* set enabled flag */
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len, (uint8_t *)madt_buf->data)));
g_array_free(madt_buf, true);
void acpi_build_hest(GArray *table_data, BIOSLinker *linker,
const char *oem_id, const char *oem_table_id)
{
- uint64_t hest_start = table_data->len;
+ AcpiTable table = { .sig = "HEST", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
- /* Hardware Error Source Table header*/
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, table_data);
/* Error Source Count */
build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4);
-
build_ghes_v2(table_data, ACPI_HEST_SRC_ID_SEA, linker);
- build_header(linker, table_data, (void *)(table_data->data + hest_start),
- "HEST", table_data->len - hest_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s,
HMAT_LB_Info *hmat_lb;
NumaHmatCacheOptions *hmat_cache;
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+
for (i = 0; i < numa_state->num_nodes; i++) {
flags = 0;
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *numa_state,
const char *oem_id, const char *oem_table_id)
{
- int hmat_start = table_data->len;
-
- /* reserve space for HMAT header */
- acpi_data_push(table_data, 40);
+ AcpiTable table = { .sig = "HMAT", .rev = 2,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
+ acpi_table_begin(&table, table_data);
hmat_build_table_structs(table_data, numa_state);
-
- build_header(linker, table_data,
- (void *)(table_data->data + hmat_start),
- "HMAT", table_data->len - hmat_start, 2, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
0x18, 0xb7, 0x8c, 0xdb);
-/*
- * NVDIMM Firmware Interface Table
- * @signature: "NFIT"
- *
- * It provides information that allows OSPM to enumerate NVDIMM present in
- * the platform and associate system physical address ranges created by the
- * NVDIMMs.
- *
- * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
- */
-struct NvdimmNfitHeader {
- ACPI_TABLE_HEADER_DEF
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct NvdimmNfitHeader NvdimmNfitHeader;
-
/*
* define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
* Interface Table (NFIT).
static GArray *nvdimm_build_device_structure(NVDIMMState *state)
{
- GSList *device_list = nvdimm_get_device_list();
+ GSList *device_list, *list = nvdimm_get_device_list();
GArray *structures = g_array_new(false, true /* clear */, 1);
- for (; device_list; device_list = device_list->next) {
+ for (device_list = list; device_list; device_list = device_list->next) {
DeviceState *dev = device_list->data;
/* build System Physical Address Range Structure. */
/* build NVDIMM Control Region Structure. */
nvdimm_build_structure_dcr(structures, dev);
}
- g_slist_free(device_list);
+ g_slist_free(list);
if (state->persistence) {
nvdimm_build_structure_caps(structures, state->persistence);
nvdimm_build_fit_buffer(state);
}
+/*
+ * NVDIMM Firmware Interface Table
+ * @signature: "NFIT"
+ *
+ * It provides information that allows OSPM to enumerate NVDIMM present in
+ * the platform and associate system physical address ranges created by the
+ * NVDIMMs.
+ *
+ * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
+ */
+
static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets,
GArray *table_data, BIOSLinker *linker,
const char *oem_id, const char *oem_table_id)
{
NvdimmFitBuffer *fit_buf = &state->fit_buf;
- unsigned int header;
+ AcpiTable table = { .sig = "NFIT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
acpi_add_table(table_offsets, table_data);
- /* NFIT header. */
- header = table_data->len;
- acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
+ acpi_table_begin(&table, table_data);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
/* NVDIMM device structures. */
g_array_append_vals(table_data, fit_buf->fit->data, fit_buf->fit->len);
-
- build_header(linker, table_data,
- (void *)(table_data->data + header), "NFIT",
- sizeof(NvdimmNfitHeader) + fit_buf->fit->len, 1, oem_id,
- oem_table_id);
+ acpi_table_end(linker, &table);
}
#define NVDIMM_DSM_MEMORY_SIZE 4096
NVDIMMState *nvdimm_state,
uint32_t ram_slots, const char *oem_id)
{
+ int mem_addr_offset;
Aml *ssdt, *sb_scope, *dev;
- int mem_addr_offset, nvdimm_ssdt;
+ AcpiTable table = { .sig = "SSDT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = "NVDIMM" };
acpi_add_table(table_offsets, table_data);
+ acpi_table_begin(&table, table_data);
ssdt = init_aml_allocator();
- acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
-
sb_scope = aml_scope("\\_SB");
dev = aml_device("NVDR");
aml_append(sb_scope, dev);
aml_append(ssdt, sb_scope);
- nvdimm_ssdt = table_data->len;
-
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
mem_addr_offset = build_append_named_dword(table_data,
bios_linker_loader_add_pointer(linker,
ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t),
NVDIMM_DSM_MEM_FILE, 0);
- build_header(linker, table_data,
- (void *)(table_data->data + nvdimm_ssdt),
- "SSDT", table_data->len - nvdimm_ssdt, 1, oem_id, "NVDIMM");
free_aml_allocator();
+ /*
+ * must be executed as the last so that pointer patching command above
+ * would be executed by guest before it recalculated checksum which were
+ * scheduled by acpi_table_end()
+ */
+ acpi_table_end(linker, &table);
}
void nvdimm_build_srat(GArray *table_data)
{
- GSList *device_list = nvdimm_get_device_list();
+ GSList *device_list, *list = nvdimm_get_device_list();
- for (; device_list; device_list = device_list->next) {
- AcpiSratMemoryAffinity *numamem = NULL;
+ for (device_list = list; device_list; device_list = device_list->next) {
DeviceState *dev = device_list->data;
Object *obj = OBJECT(dev);
uint64_t addr, size;
addr = object_property_get_uint(obj, PC_DIMM_ADDR_PROP, &error_abort);
size = object_property_get_uint(obj, PC_DIMM_SIZE_PROP, &error_abort);
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, addr, size, node,
+ build_srat_memory(table_data, addr, size, node,
MEM_AFFINITY_ENABLED | MEM_AFFINITY_NON_VOLATILE);
}
- g_slist_free(device_list);
+ g_slist_free(list);
}
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
#include "hw/acpi/pci.h"
#include "hw/pci/pcie_host.h"
+/*
+ * PCI Firmware Specification, Revision 3.0
+ * 4.1.2 MCFG Table Description.
+ */
void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info,
const char *oem_id, const char *oem_table_id)
{
- int mcfg_start = table_data->len;
+ AcpiTable table = { .sig = "MCFG", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
+
+ acpi_table_begin(&table, table_data);
- /*
- * PCI Firmware Specification, Revision 3.0
- * 4.1.2 MCFG Table Description.
- */
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
/* Reserved */
build_append_int_noprefix(table_data, 0, 8);
-
/*
* Memory Mapped Enhanced Configuration Space Base Address Allocation
* Structure
/* Reserved */
build_append_int_noprefix(table_data, 0, 4);
- build_header(linker, table_data, (void *)(table_data->data + mcfg_start),
- "MCFG", table_data->len - mcfg_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
Aml *ssdt, *dev, *scope, *method, *addr, *if_ctx;
uint32_t vgia_offset;
QemuUUID guid_le;
+ AcpiTable table = { .sig = "SSDT", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = "VMGENID" };
/* Fill in the GUID values. These need to be converted to little-endian
* first, since that's what the guest expects
g_array_insert_vals(guid, VMGENID_GUID_OFFSET, guid_le.data,
ARRAY_SIZE(guid_le.data));
- /* Put this in a separate SSDT table */
+ /* Put VMGNEID into a separate SSDT table */
+ acpi_table_begin(&table, table_data);
ssdt = init_aml_allocator();
- /* Reserve space for header */
- acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
-
/* Storage for the GUID address */
vgia_offset = table_data->len +
build_append_named_dword(ssdt->buf, "VGIA");
ACPI_BUILD_TABLE_FILE, vgia_offset, sizeof(uint32_t),
VMGENID_GUID_FW_CFG_FILE, 0);
- build_header(linker, table_data,
- (void *)(table_data->data + table_data->len - ssdt->buf->len),
- "SSDT", ssdt->buf->len, 1, oem_id, "VMGENID");
+ /* must be called after above command to ensure correct table checksum */
+ acpi_table_end(linker, &table);
free_aml_allocator();
}
}
#endif
+#define ID_MAPPING_ENTRY_SIZE 20
+#define SMMU_V3_ENTRY_SIZE 60
+#define ROOT_COMPLEX_ENTRY_SIZE 32
+#define IORT_NODE_OFFSET 48
+
+static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
+ uint32_t id_count, uint32_t out_ref)
+{
+ /* Identity RID mapping covering the whole input RID range */
+ build_append_int_noprefix(table_data, input_base, 4); /* Input base */
+ build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */
+ build_append_int_noprefix(table_data, input_base, 4); /* Output base */
+ build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+}
+
+struct AcpiIortIdMapping {
+ uint32_t input_base;
+ uint32_t id_count;
+};
+typedef struct AcpiIortIdMapping AcpiIortIdMapping;
+
/* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
static int
iort_host_bridges(Object *obj, void *opaque)
return idmap_a->input_base - idmap_b->input_base;
}
+/*
+ * Input Output Remapping Table (IORT)
+ * Conforms to "IO Remapping Table System Software on ARM Platforms",
+ * Document number: ARM DEN 0049B, October 2015
+ */
static void
build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- int i, nb_nodes, rc_mapping_count, iort_start = table_data->len;
+ int i, nb_nodes, rc_mapping_count;
+ const uint32_t iort_node_offset = IORT_NODE_OFFSET;
+ size_t node_size, smmu_offset = 0;
AcpiIortIdMapping *idmap;
- AcpiIortItsGroup *its;
- AcpiIortTable *iort;
- AcpiIortSmmu3 *smmu;
- size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
- AcpiIortRC *rc;
GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
- iort = acpi_data_push(table_data, sizeof(*iort));
+ AcpiTable table = { .sig = "IORT", .rev = 0, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+ /* Table 2 The IORT */
+ acpi_table_begin(&table, table_data);
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
AcpiIortIdMapping next_range = {0};
nb_nodes = 2; /* RC, ITS */
rc_mapping_count = 1;
}
-
- iort_length = sizeof(*iort);
- iort->node_count = cpu_to_le32(nb_nodes);
- /*
- * Use a copy in case table_data->data moves during acpi_data_push
- * operations.
- */
- iort_node_offset = sizeof(*iort);
- iort->node_offset = cpu_to_le32(iort_node_offset);
-
- /* ITS group node */
- node_size = sizeof(*its) + sizeof(uint32_t);
- iort_length += node_size;
- its = acpi_data_push(table_data, node_size);
-
- its->type = ACPI_IORT_NODE_ITS_GROUP;
- its->length = cpu_to_le16(node_size);
- its->its_count = cpu_to_le32(1);
- its->identifiers[0] = 0; /* MADT translation_id */
+ /* Number of IORT Nodes */
+ build_append_int_noprefix(table_data, nb_nodes, 4);
+
+ /* Offset to Array of IORT Nodes */
+ build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+
+ /* 3.1.1.3 ITS group node */
+ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
+ node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 0, 1); /* Revision */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
+ build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
+ build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
+ /* GIC ITS Identifier Array */
+ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
- /* SMMUv3 node */
- smmu_offset = iort_node_offset + node_size;
- node_size = sizeof(*smmu) + sizeof(*idmap);
- iort_length += node_size;
- smmu = acpi_data_push(table_data, node_size);
-
- smmu->type = ACPI_IORT_NODE_SMMU_V3;
- smmu->length = cpu_to_le16(node_size);
- smmu->mapping_count = cpu_to_le32(1);
- smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
- smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
- smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
- smmu->event_gsiv = cpu_to_le32(irq);
- smmu->pri_gsiv = cpu_to_le32(irq + 1);
- smmu->sync_gsiv = cpu_to_le32(irq + 2);
- smmu->gerr_gsiv = cpu_to_le32(irq + 3);
-
- /* Identity RID mapping covering the whole input RID range */
- idmap = &smmu->id_mapping_array[0];
- idmap->input_base = 0;
- idmap->id_count = cpu_to_le32(0xFFFF);
- idmap->output_base = 0;
+ smmu_offset = table_data->len - table.table_offset;
+ /* 3.1.1.2 SMMUv3 */
+ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
+ node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 0, 1); /* Revision */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
+ /* Reference to ID Array */
+ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
+ /* Base address */
+ build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
+ /* Flags */
+ build_append_int_noprefix(table_data, 1 /* COHACC OverrideNote */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
+ /* Model */
+ build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
+ build_append_int_noprefix(table_data, irq, 4); /* Event */
+ build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
+ build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
+ build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
+
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort_node_offset);
+ build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
}
- /* Root Complex Node */
- node_size = sizeof(*rc) + sizeof(*idmap) * rc_mapping_count;
- iort_length += node_size;
- rc = acpi_data_push(table_data, node_size);
-
- rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
- rc->length = cpu_to_le16(node_size);
- rc->mapping_count = cpu_to_le32(rc_mapping_count);
- rc->mapping_offset = cpu_to_le32(sizeof(*rc));
-
- /* fully coherent device */
- rc->memory_properties.cache_coherency = cpu_to_le32(1);
- rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
- rc->pci_segment_number = 0; /* MCFG pci_segment */
-
+ /* Table 16 Root Complex Node */
+ build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
+ node_size = ROOT_COMPLEX_ENTRY_SIZE +
+ ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
+ build_append_int_noprefix(table_data, node_size, 2); /* Length */
+ build_append_int_noprefix(table_data, 0, 1); /* Revision */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ /* Number of ID mappings */
+ build_append_int_noprefix(table_data, rc_mapping_count, 4);
+ /* Reference to ID Array */
+ build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
+
+ /* Table 13 Memory access properties */
+ /* CCA: Cache Coherent Attribute */
+ build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
+ build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* MAF: Note Memory Access Flags */
+ build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DCAS = 1 */, 1);
+
+ build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
+ /* MCFG pci_segment */
+ build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
+
+ /* Output Reference */
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
AcpiIortIdMapping *range;
/* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
for (i = 0; i < smmu_idmaps->len; i++) {
- idmap = &rc->id_mapping_array[i];
range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
-
- idmap->input_base = cpu_to_le32(range->input_base);
- idmap->id_count = cpu_to_le32(range->id_count);
- idmap->output_base = cpu_to_le32(range->input_base);
/* output IORT node is the smmuv3 node */
- idmap->output_reference = cpu_to_le32(smmu_offset);
+ build_iort_id_mapping(table_data, range->input_base,
+ range->id_count, smmu_offset);
}
/* bypassed RIDs connect to ITS group node directly: RC -> ITS */
for (i = 0; i < its_idmaps->len; i++) {
- idmap = &rc->id_mapping_array[smmu_idmaps->len + i];
range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
-
- idmap->input_base = cpu_to_le32(range->input_base);
- idmap->id_count = cpu_to_le32(range->id_count);
- idmap->output_base = cpu_to_le32(range->input_base);
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort_node_offset);
+ build_iort_id_mapping(table_data, range->input_base,
+ range->id_count, iort_node_offset);
}
} else {
- /* Identity RID mapping covering the whole input RID range */
- idmap = &rc->id_mapping_array[0];
- idmap->input_base = cpu_to_le32(0);
- idmap->id_count = cpu_to_le32(0xFFFF);
- idmap->output_base = cpu_to_le32(0);
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort_node_offset);
+ build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
}
+ acpi_table_end(linker, &table);
g_array_free(smmu_idmaps, true);
g_array_free(its_idmaps, true);
-
- /*
- * Update the pointer address in case table_data->data moves during above
- * acpi_data_push operations.
- */
- iort = (AcpiIortTable *)(table_data->data + iort_start);
- iort->length = cpu_to_le32(iort_length);
-
- build_header(linker, table_data, (void *)(table_data->data + iort_start),
- "IORT", table_data->len - iort_start, 0, vms->oem_id,
- vms->oem_table_id);
}
+/*
+ * Serial Port Console Redirection Table (SPCR)
+ * Rev: 1.07
+ */
static void
build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- AcpiSerialPortConsoleRedirection *spcr;
- const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
- int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
- int spcr_start = table_data->len;
-
- spcr = acpi_data_push(table_data, sizeof(*spcr));
-
- spcr->interface_type = 0x3; /* ARM PL011 UART */
-
- spcr->base_address.space_id = AML_SYSTEM_MEMORY;
- spcr->base_address.bit_width = 8;
- spcr->base_address.bit_offset = 0;
- spcr->base_address.access_width = 1;
- spcr->base_address.address = cpu_to_le64(uart_memmap->base);
-
- spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
- spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
-
- spcr->baud = 3; /* Baud Rate: 3 = 9600 */
- spcr->parity = 0; /* No Parity */
- spcr->stopbits = 1; /* 1 Stop bit */
- spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
- spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
-
- spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
- spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
-
- build_header(linker, table_data, (void *)(table_data->data + spcr_start),
- "SPCR", table_data->len - spcr_start, 2, vms->oem_id,
- vms->oem_table_id);
+ AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ /* Interface Type */
+ build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
+ /* Base Address */
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
+ vms->memmap[VIRT_UART].base);
+ /* Interrupt Type */
+ build_append_int_noprefix(table_data,
+ (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
+ build_append_int_noprefix(table_data, 0, 1); /* IRQ */
+ /* Global System Interrupt */
+ build_append_int_noprefix(table_data,
+ vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
+ build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
+ build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
+ /* Stop Bits */
+ build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
+ /* Flow Control */
+ build_append_int_noprefix(table_data,
+ (1 << 1) /* RTS/CTS hardware flow control */, 1);
+ /* Terminal Type */
+ build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
+ build_append_int_noprefix(table_data, 0, 1); /* Language */
+ /* PCI Device ID */
+ build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
+ /* PCI Vendor ID */
+ build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
+ build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
+ build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+
+ acpi_table_end(linker, &table);
}
+/*
+ * ACPI spec, Revision 5.1
+ * 5.2.16 System Resource Affinity Table (SRAT)
+ */
static void
build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
- AcpiSystemResourceAffinityTable *srat;
- AcpiSratProcessorGiccAffinity *core;
- AcpiSratMemoryAffinity *numamem;
- int i, srat_start;
+ int i;
uint64_t mem_base;
MachineClass *mc = MACHINE_GET_CLASS(vms);
MachineState *ms = MACHINE(vms);
const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
+ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
- srat_start = table_data->len;
- srat = acpi_data_push(table_data, sizeof(*srat));
- srat->reserved1 = cpu_to_le32(1);
+ acpi_table_begin(&table, table_data);
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
for (i = 0; i < cpu_list->len; ++i) {
- core = acpi_data_push(table_data, sizeof(*core));
- core->type = ACPI_SRAT_PROCESSOR_GICC;
- core->length = sizeof(*core);
- core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
- core->acpi_processor_uid = cpu_to_le32(i);
- core->flags = cpu_to_le32(1);
+ uint32_t nodeid = cpu_list->cpus[i].props.node_id;
+ /*
+ * 5.2.16.4 GICC Affinity Structure
+ */
+ build_append_int_noprefix(table_data, 3, 1); /* Type */
+ build_append_int_noprefix(table_data, 18, 1); /* Length */
+ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+ /* Flags, Table 5-76 */
+ build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
}
mem_base = vms->memmap[VIRT_MEM].base;
for (i = 0; i < ms->numa_state->num_nodes; ++i) {
if (ms->numa_state->nodes[i].node_mem > 0) {
- numamem = acpi_data_push(table_data, sizeof(*numamem));
- build_srat_memory(numamem, mem_base,
+ build_srat_memory(table_data, mem_base,
ms->numa_state->nodes[i].node_mem, i,
MEM_AFFINITY_ENABLED);
mem_base += ms->numa_state->nodes[i].node_mem;
}
if (ms->device_memory) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, ms->device_memory->base,
+ build_srat_memory(table_data, ms->device_memory->base,
memory_region_size(&ms->device_memory->mr),
ms->numa_state->num_nodes - 1,
MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
}
- build_header(linker, table_data, (void *)(table_data->data + srat_start),
- "SRAT", table_data->len - srat_start, 3, vms->oem_id,
- vms->oem_table_id);
+ acpi_table_end(linker, &table);
}
-/* GTDT */
+/*
+ * ACPI spec, Revision 5.1
+ * 5.2.24 Generic Timer Description Table (GTDT)
+ */
static void
build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
- int gtdt_start = table_data->len;
- AcpiGenericTimerTable *gtdt;
- uint32_t irqflags;
-
- if (vmc->claim_edge_triggered_timers) {
- irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
- } else {
- irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
- }
-
- gtdt = acpi_data_push(table_data, sizeof *gtdt);
- /* The interrupt values are the same with the device tree when adding 16 */
- gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
- gtdt->secure_el1_flags = cpu_to_le32(irqflags);
-
- gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
- gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
- ACPI_GTDT_CAP_ALWAYS_ON);
-
- gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
- gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
-
- gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
- gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
+ /*
+ * Table 5-117 Flag Definitions
+ * set only "Timer interrupt Mode" and assume "Timer Interrupt
+ * polarity" bit as '0: Interrupt is Active high'
+ */
+ uint32_t irqflags = vmc->claim_edge_triggered_timers ?
+ 1 : /* Interrupt is Edge triggered */
+ 0; /* Interrupt is Level triggered */
+ AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+
+ /* CntControlBase Physical Address */
+ /* FIXME: invalid value, should be 0xFFFFFFFFFFFFFFFF if not impl. ? */
+ build_append_int_noprefix(table_data, 0, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
+ /*
+ * FIXME: clarify comment:
+ * The interrupt values are the same with the device tree when adding 16
+ */
+ /* Secure EL1 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
+ /* Secure EL1 timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* Non-Secure EL1 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
+ /* Non-Secure EL1 timer Flags */
+ build_append_int_noprefix(table_data, irqflags |
+ 1UL << 2, /* Always-on Capability */
+ 4);
+ /* Virtual timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
+ /* Virtual Timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* Non-Secure EL2 timer GSIV */
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
+ /* Non-Secure EL2 timer Flags */
+ build_append_int_noprefix(table_data, irqflags, 4);
+ /* CntReadBase Physical address */
+ build_append_int_noprefix(table_data, 0, 8);
+ /* Platform Timer Count */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Platform Timer Offset */
+ build_append_int_noprefix(table_data, 0, 4);
+
+ acpi_table_end(linker, &table);
+}
- build_header(linker, table_data,
- (void *)(table_data->data + gtdt_start), "GTDT",
- table_data->len - gtdt_start, 2, vms->oem_id,
- vms->oem_table_id);
+/*
+ * ACPI spec, Revision 5.1 Errata A
+ * 5.2.12 Multiple APIC Description Table (MADT)
+ */
+static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
+{
+ build_append_int_noprefix(table_data, 0xE, 1); /* Type */
+ build_append_int_noprefix(table_data, 16, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* Discovery Range Base Addres */
+ build_append_int_noprefix(table_data, base, 8);
+ build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
}
-/* MADT */
static void
build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
+ int i;
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
- int madt_start = table_data->len;
const MemMapEntry *memmap = vms->memmap;
- const int *irqmap = vms->irqmap;
- AcpiMadtGenericDistributor *gicd;
- AcpiMadtGenericMsiFrame *gic_msi;
- int i;
-
- acpi_data_push(table_data, sizeof(AcpiMultipleApicTable));
-
- gicd = acpi_data_push(table_data, sizeof *gicd);
- gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
- gicd->length = sizeof(*gicd);
- gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
- gicd->version = vms->gic_version;
+ AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ /* Local Interrupt Controller Address */
+ build_append_int_noprefix(table_data, 0, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+
+ /* 5.2.12.15 GIC Distributor Structure */
+ build_append_int_noprefix(table_data, 0xC, 1); /* Type */
+ build_append_int_noprefix(table_data, 24, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
+ /* GIC version */
+ build_append_int_noprefix(table_data, vms->gic_version, 1);
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
- AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
- sizeof(*gicc));
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
+ uint64_t physical_base_address = 0, gich = 0, gicv = 0;
+ uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
+ uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
+ PPI(VIRTUAL_PMU_IRQ) : 0;
- gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
- gicc->length = sizeof(*gicc);
if (vms->gic_version == 2) {
- gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
- gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
- gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
+ physical_base_address = memmap[VIRT_GIC_CPU].base;
+ gicv = memmap[VIRT_GIC_VCPU].base;
+ gich = memmap[VIRT_GIC_HYP].base;
}
- gicc->cpu_interface_number = cpu_to_le32(i);
- gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
- gicc->uid = cpu_to_le32(i);
- gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
- if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
- gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
- }
- if (vms->virt) {
- gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
- }
+ /* 5.2.12.14 GIC Structure */
+ build_append_int_noprefix(table_data, 0xB, 1); /* Type */
+ build_append_int_noprefix(table_data, 76, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, i, 4); /* GIC ID */
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+ /* Flags */
+ build_append_int_noprefix(table_data, 1, 4); /* Enabled */
+ /* Parking Protocol Version */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Performance Interrupt GSIV */
+ build_append_int_noprefix(table_data, pmu_interrupt, 4);
+ build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, physical_base_address, 8);
+ build_append_int_noprefix(table_data, gicv, 8); /* GICV */
+ build_append_int_noprefix(table_data, gich, 8); /* GICH */
+ /* VGIC Maintenance interrupt */
+ build_append_int_noprefix(table_data, vgic_interrupt, 4);
+ build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
+ /* MPIDR */
+ build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
}
if (vms->gic_version == 3) {
- AcpiMadtGenericTranslator *gic_its;
- int nb_redist_regions = virt_gicv3_redist_region_count(vms);
- AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
- sizeof *gicr);
-
- gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
- gicr->length = sizeof(*gicr);
- gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
- gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
-
- if (nb_redist_regions == 2) {
- gicr = acpi_data_push(table_data, sizeof(*gicr));
- gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
- gicr->length = sizeof(*gicr);
- gicr->base_address =
- cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
- gicr->range_length =
- cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
+ build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
+ memmap[VIRT_GIC_REDIST].size);
+ if (virt_gicv3_redist_region_count(vms) == 2) {
+ build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
+ memmap[VIRT_HIGH_GIC_REDIST2].size);
}
if (its_class_name() && !vmc->no_its) {
- gic_its = acpi_data_push(table_data, sizeof *gic_its);
- gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
- gic_its->length = sizeof(*gic_its);
- gic_its->translation_id = 0;
- gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
+ /*
+ * FIXME: Structure is from Revision 6.0 where 'GIC Structure'
+ * has additional fields on top of implemented 5.1 Errata A,
+ * to make it consistent with v6.0 we need to bump everything
+ * to v6.0
+ */
+ /*
+ * ACPI spec, Revision 6.0 Errata A
+ * (original 6.0 definition has invalid Length)
+ * 5.2.12.18 GIC ITS Structure
+ */
+ build_append_int_noprefix(table_data, 0xF, 1); /* Type */
+ build_append_int_noprefix(table_data, 20, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
}
} else {
- gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
- gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
- gic_msi->length = sizeof(*gic_msi);
- gic_msi->gic_msi_frame_id = 0;
- gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
- gic_msi->flags = cpu_to_le32(1);
- gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
- gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
+ const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
+
+ /* 5.2.12.16 GIC MSI Frame Structure */
+ build_append_int_noprefix(table_data, 0xD, 1); /* Type */
+ build_append_int_noprefix(table_data, 24, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
+ /* Physical Base Address */
+ build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
+ build_append_int_noprefix(table_data, 1, 4); /* Flags */
+ /* SPI Count */
+ build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
+ build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
}
-
- build_header(linker, table_data,
- (void *)(table_data->data + madt_start), "APIC",
- table_data->len - madt_start, 3, vms->oem_id,
- vms->oem_table_id);
+ acpi_table_end(linker, &table);
}
/* FADT */
MachineState *ms = MACHINE(vms);
const MemMapEntry *memmap = vms->memmap;
const int *irqmap = vms->irqmap;
+ AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
+ .oem_table_id = vms->oem_table_id };
+ acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
- /* Reserve space for header */
- acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
/* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
* While UEFI can use libfdt to disable the RTC device node in the DTB that
aml_append(dsdt, scope);
- /* copy AML table into ACPI tables blob and patch header there */
+ /* copy AML table into ACPI tables blob */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
- build_header(linker, table_data,
- (void *)(table_data->data + table_data->len - dsdt->buf->len),
- "DSDT", dsdt->buf->len, 2, vms->oem_id,
- vms->oem_table_id);
+
+ acpi_table_end(linker, &table);
free_aml_allocator();
}
dc->realize = ibex_uart_realize;
dc->vmsd = &vmstate_ibex_uart;
device_class_set_props(dc, ibex_uart_properties);
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo ibex_uart_info = {
#include "qemu/osdep.h"
#include "qemu/log.h"
-#include "chardev/char.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
#include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/qdev-properties.h"
+
+#define REGS_OFFSET 0x20
static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
{
MchpPfSoCMMUartState *s = opaque;
- if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+ addr >>= 2;
+ if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
- __func__, addr);
+ __func__, addr << 2);
return 0;
}
- return s->reg[addr / sizeof(uint32_t)];
+ return s->reg[addr];
}
static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
MchpPfSoCMMUartState *s = opaque;
uint32_t val32 = (uint32_t)value;
- if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+ addr >>= 2;
+ if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
- " v=0x%x\n", __func__, addr, val32);
+ " v=0x%x\n", __func__, addr << 2, val32);
return;
}
- s->reg[addr / sizeof(uint32_t)] = val32;
+ s->reg[addr] = val32;
}
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
},
};
-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
- hwaddr base, qemu_irq irq, Chardev *chr)
+static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
+{
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
+
+ memset(s->reg, 0, sizeof(s->reg));
+ device_cold_reset(DEVICE(&s->serial_mm));
+}
+
+static void mchp_pfsoc_mmuart_init(Object *obj)
+{
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
+
+ object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
+ object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
+}
+
+static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
{
- MchpPfSoCMMUartState *s;
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
+
+ qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
+ qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
+ qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
+ DEVICE_LITTLE_ENDIAN);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
+ return;
+ }
+
+ sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
- s = g_new0(MchpPfSoCMMUartState, 1);
+ memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
- memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
- "mchp.pfsoc.mmuart", 0x1000);
+ memory_region_add_subregion(&s->container, 0,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
+ "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
+ memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
+}
- s->base = base;
- s->irq = irq;
+static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
+ .name = "mchp.pfsoc.uart",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
+ MCHP_PFSOC_MMUART_REG_COUNT),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = mchp_pfsoc_mmuart_realize;
+ dc->reset = mchp_pfsoc_mmuart_reset;
+ dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
+static const TypeInfo mchp_pfsoc_mmuart_info = {
+ .name = TYPE_MCHP_PFSOC_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCMMUartState),
+ .instance_init = mchp_pfsoc_mmuart_init,
+ .class_init = mchp_pfsoc_mmuart_class_init,
+};
+
+static void mchp_pfsoc_mmuart_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_mmuart_info);
+}
+
+type_init(mchp_pfsoc_mmuart_register_types)
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+ hwaddr base,
+ qemu_irq irq, Chardev *chr)
+{
+ DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
- DEVICE_LITTLE_ENDIAN);
+ qdev_prop_set_chr(dev, "chardev", chr);
+ sysbus_realize(sbd, &error_fatal);
- memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
+ memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
+ sysbus_connect_irq(sbd, 0, irq);
- return s;
+ return MCHP_PFSOC_UART(dev);
}
dc->reset = shakti_uart_reset;
dc->realize = shakti_uart_realize;
device_class_set_props(dc, shakti_uart_properties);
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo shakti_uart_info = {
rc->phases.enter = sifive_uart_reset_enter;
rc->phases.hold = sifive_uart_reset_hold;
device_class_set_props(dc, sifive_uart_properties);
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static const TypeInfo sifive_uart_info = {
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-pci.h"
-GlobalProperty hw_compat_6_1[] = {};
+GlobalProperty hw_compat_6_1[] = {
+ { "vhost-user-vsock-device", "seqpacket", "off" },
+};
const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
GlobalProperty hw_compat_6_0[] = {
{ "nvme-ns", "eui64-default", "off"},
{ "e1000", "init-vet", "off" },
{ "e1000e", "init-vet", "off" },
+ { "vhost-vsock-device", "seqpacket", "off" },
};
const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
{
SiFivePDMAState *s = opaque;
int ch = SIFIVE_PDMA_CHAN_NO(offset);
- bool claimed;
+ bool claimed, run;
if (ch >= SIFIVE_PDMA_CHANS) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
offset &= 0xfff;
switch (offset) {
case DMA_CONTROL:
- claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+ claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
+ run = !!(s->chan[ch].control & CONTROL_RUN);
if (!claimed && (value & CONTROL_CLAIM)) {
/* reset Next* registers */
s->chan[ch].next_src = 0;
}
+ /* claim bit can only be cleared when run is low */
+ if (run && !(value & CONTROL_CLAIM)) {
+ value |= CONTROL_CLAIM;
+ }
+
s->chan[ch].control = value;
/*
* If channel was not claimed before run bit is set,
+ * or if the channel is disclaimed when run was low,
* DMA won't run.
*/
- if (!claimed) {
+ if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
s->chan[ch].control &= ~CONTROL_RUN;
return;
}
g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
}
-/* FACS */
+/*
+ * ACPI spec 1.0b,
+ * 5.2.6 Firmware ACPI Control Structure
+ */
static void
build_facs(GArray *table_data)
{
- AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
- memcpy(&facs->signature, "FACS", 4);
- facs->length = cpu_to_le32(sizeof(*facs));
+ const char *sig = "FACS";
+ const uint8_t reserved[40] = {};
+
+ g_array_append_vals(table_data, sig, 4); /* Signature */
+ build_append_int_noprefix(table_data, 64, 4); /* Length */
+ build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
+ build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
+ build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+ g_array_append_vals(table_data, reserved, 40); /* Reserved */
}
static void build_append_pcihp_notify_entry(Aml *method, int slot)
#endif
int i;
VMBusBridge *vmbus_bridge = vmbus_bridge_find();
+ AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
+ .oem_table_id = x86ms->oem_table_id };
+ acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
- /* Reserve space for header */
- acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
-
build_dbg_aml(dsdt);
if (misc->is_piix4) {
sb_scope = aml_scope("_SB");
/* copy AML table into ACPI tables blob and patch header there */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
- build_header(linker, table_data,
- (void *)(table_data->data + table_data->len - dsdt->buf->len),
- "DSDT", dsdt->buf->len, 1, x86ms->oem_id, x86ms->oem_table_id);
+ acpi_table_end(linker, &table);
free_aml_allocator();
}
+/*
+ * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
+ * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
+ */
static void
build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
const char *oem_table_id)
{
- Acpi20Hpet *hpet;
- int hpet_start = table_data->len;
+ AcpiTable table = { .sig = "HPET", .rev = 1,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
- hpet = acpi_data_push(table_data, sizeof(*hpet));
+ acpi_table_begin(&table, table_data);
/* Note timer_block_id value must be kept in sync with value advertised by
* emulated hpet
*/
- hpet->timer_block_id = cpu_to_le32(0x8086a201);
- hpet->addr.address = cpu_to_le64(HPET_BASE);
- build_header(linker, table_data,
- (void *)(table_data->data + hpet_start),
- "HPET", sizeof(*hpet), 1, oem_id, oem_table_id);
+ /* Event Timer Block ID */
+ build_append_int_noprefix(table_data, 0x8086a201, 4);
+ /* BASE_ADDRESS */
+ build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
+ /* HPET Number */
+ build_append_int_noprefix(table_data, 0, 1);
+ /* Main Counter Minimum Clock_tick in Periodic Mode */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Page Protection And OEM Attribute */
+ build_append_int_noprefix(table_data, 0, 1);
+ acpi_table_end(linker, &table);
}
#ifdef CONFIG_TPM
+/*
+ * TCPA Description Table
+ *
+ * Following Level 00, Rev 00.37 of specs:
+ * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
+ * 7.1.2 ACPI Table Layout
+ */
static void
build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
const char *oem_id, const char *oem_table_id)
{
- int tcpa_start = table_data->len;
- Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
- unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
- unsigned log_addr_offset =
- (char *)&tcpa->log_area_start_address - table_data->data;
-
- tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
- tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
- acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
+ unsigned log_addr_offset;
+ AcpiTable table = { .sig = "TCPA", .rev = 2,
+ .oem_id = oem_id, .oem_table_id = oem_table_id };
+
+ acpi_table_begin(&table, table_data);
+ /* Platform Class */
+ build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
+ /* Log Area Minimum Length (LAML) */
+ build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
+ /* Log Area Start Address (LASA) */
+ log_addr_offset = table_data->len;
+ build_append_int_noprefix(table_data, 0, 8);
+ /* allocate/reserve space for TPM log area */
+ acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
false /* high memory */);
-
/* log area start address to be filled by Guest linker */
- bios_linker_loader_add_pointer(linker,
- ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
- ACPI_BUILD_TPMLOG_FILE, 0);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
- build_header(linker, table_data,
- (void *)(table_data->data + tcpa_start),
- "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
#endif
#define HOLE_640K_START (640 * KiB)
#define HOLE_640K_END (1 * MiB)
+/*
+ * ACPI spec, Revision 3.0
+ * 5.2.15 System Resource Affinity Table (SRAT)
+ */
static void
build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
{
- AcpiSystemResourceAffinityTable *srat;
- AcpiSratMemoryAffinity *numamem;
-
int i;
- int srat_start, numa_start, slots;
+ int numa_mem_start, slots;
uint64_t mem_len, mem_base, next_base;
MachineClass *mc = MACHINE_GET_CLASS(machine);
X86MachineState *x86ms = X86_MACHINE(machine);
ram_addr_t hotpluggable_address_space_size =
object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
NULL);
+ AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
+ .oem_table_id = x86ms->oem_table_id };
- srat_start = table_data->len;
-
- srat = acpi_data_push(table_data, sizeof *srat);
- srat->reserved1 = cpu_to_le32(1);
+ acpi_table_begin(&table, table_data);
+ build_append_int_noprefix(table_data, 1, 4); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 8); /* Reserved */
for (i = 0; i < apic_ids->len; i++) {
int node_id = apic_ids->cpus[i].props.node_id;
uint32_t apic_id = apic_ids->cpus[i].arch_id;
if (apic_id < 255) {
- AcpiSratProcessorAffinity *core;
-
- core = acpi_data_push(table_data, sizeof *core);
- core->type = ACPI_SRAT_PROCESSOR_APIC;
- core->length = sizeof(*core);
- core->local_apic_id = apic_id;
- core->proximity_lo = node_id;
- memset(core->proximity_hi, 0, 3);
- core->local_sapic_eid = 0;
- core->flags = cpu_to_le32(1);
+ /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
+ build_append_int_noprefix(table_data, 0, 1); /* Type */
+ build_append_int_noprefix(table_data, 16, 1); /* Length */
+ /* Proximity Domain [7:0] */
+ build_append_int_noprefix(table_data, node_id, 1);
+ build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
+ /* Flags, Table 5-36 */
+ build_append_int_noprefix(table_data, 1, 4);
+ build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
+ /* Proximity Domain [31:8] */
+ build_append_int_noprefix(table_data, 0, 3);
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
} else {
- AcpiSratProcessorX2ApicAffinity *core;
-
- core = acpi_data_push(table_data, sizeof *core);
- core->type = ACPI_SRAT_PROCESSOR_x2APIC;
- core->length = sizeof(*core);
- core->x2apic_id = cpu_to_le32(apic_id);
- core->proximity_domain = cpu_to_le32(node_id);
- core->flags = cpu_to_le32(1);
+ /*
+ * ACPI spec, Revision 4.0
+ * 5.2.16.3 Processor Local x2APIC Affinity Structure
+ */
+ build_append_int_noprefix(table_data, 2, 1); /* Type */
+ build_append_int_noprefix(table_data, 24, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* Proximity Domain */
+ build_append_int_noprefix(table_data, node_id, 4);
+ build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
+ /* Flags, Table 5-39 */
+ build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
+ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
+ build_append_int_noprefix(table_data, 0, 4); /* Reserved */
}
}
-
/* the memory map is a bit tricky, it contains at least one hole
* from 640k-1M and possibly another one from 3.5G-4G.
*/
next_base = 0;
- numa_start = table_data->len;
+ numa_mem_start = table_data->len;
for (i = 1; i < nb_numa_nodes + 1; ++i) {
mem_base = next_base;
next_base > HOLE_640K_START) {
mem_len -= next_base - HOLE_640K_START;
if (mem_len > 0) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, mem_base, mem_len, i - 1,
+ build_srat_memory(table_data, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
next_base > x86ms->below_4g_mem_size) {
mem_len -= next_base - x86ms->below_4g_mem_size;
if (mem_len > 0) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, mem_base, mem_len, i - 1,
+ build_srat_memory(table_data, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
mem_base = 1ULL << 32;
}
if (mem_len > 0) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, mem_base, mem_len, i - 1,
+ build_srat_memory(table_data, mem_base, mem_len, i - 1,
MEM_AFFINITY_ENABLED);
}
}
nvdimm_build_srat(table_data);
}
- slots = (table_data->len - numa_start) / sizeof *numamem;
+ /*
+ * TODO: this part is not in ACPI spec and current linux kernel boots fine
+ * without these entries. But I recall there were issues the last time I
+ * tried to remove it with some ancient guest OS, however I can't remember
+ * what that was so keep this around for now
+ */
+ slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
for (; slots < nb_numa_nodes + 2; slots++) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
+ build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
}
/*
* providing _PXM method if necessary.
*/
if (hotpluggable_address_space_size) {
- numamem = acpi_data_push(table_data, sizeof *numamem);
- build_srat_memory(numamem, machine->device_memory->base,
+ build_srat_memory(table_data, machine->device_memory->base,
hotpluggable_address_space_size, nb_numa_nodes - 1,
MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
}
- build_header(linker, table_data,
- (void *)(table_data->data + srat_start),
- "SRAT",
- table_data->len - srat_start, 1, x86ms->oem_id,
- x86ms->oem_table_id);
+ acpi_table_end(linker, &table);
}
/*
static void
insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
{
+ const size_t device_scope_size = 6 /* device scope structure */ +
+ 2 /* 1 path entry */;
GArray *scope_blob = opaque;
- AcpiDmarDeviceScope *scope = NULL;
if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
/* Dmar Scope Type: 0x02 for PCI Bridge */
}
/* length */
- build_append_int_noprefix(scope_blob,
- sizeof(*scope) + sizeof(scope->path[0]), 1);
+ build_append_int_noprefix(scope_blob, device_scope_size, 1);
/* reserved */
build_append_int_noprefix(scope_blob, 0, 2);
/* enumeration_id */
}
/*
- * VT-d spec 8.1 DMA Remapping Reporting Structure
- * (version Oct. 2014 or later)
+ * Intel ® Virtualization Technology for Directed I/O
+ * Architecture Specification. Revision 3.3
+ * 8.1 DMA Remapping Reporting Structure
*/
static void
build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
const char *oem_table_id)
{
- int dmar_start = table_data->len;
-
- AcpiTableDmar *dmar;
- AcpiDmarHardwareUnit *drhd;
- AcpiDmarRootPortATS *atsr;
uint8_t dmar_flags = 0;
+ uint8_t rsvd10[10] = {};
+ /* Root complex IOAPIC uses one path only */
+ const size_t ioapic_scope_size = 6 /* device scope structure */ +
+ 2 /* 1 path entry */;
X86IOMMUState *iommu = x86_iommu_get_default();
- AcpiDmarDeviceScope *scope = NULL;
- /* Root complex IOAPIC use one path[0] only */
- size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
GArray *scope_blob = g_array_new(false, true, 1);
+ AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
+ .oem_table_id = oem_table_id };
+
/*
* A PCI bus walk, for each PCI host bridge.
* Insert scope for each PCI bridge and endpoint device which
dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
}
- dmar = acpi_data_push(table_data, sizeof(*dmar));
- dmar->host_address_width = intel_iommu->aw_bits - 1;
- dmar->flags = dmar_flags;
+ acpi_table_begin(&table, table_data);
+ /* Host Address Width */
+ build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
+ build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
+ g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
- /* DMAR Remapping Hardware Unit Definition structure */
- drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
- drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
- drhd->length =
- cpu_to_le16(sizeof(*drhd) + ioapic_scope_size + scope_blob->len);
- drhd->flags = 0; /* Don't include all pci device */
- drhd->pci_segment = cpu_to_le16(0);
- drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
+ /* 8.3 DMAR Remapping Hardware Unit Definition structure */
+ build_append_int_noprefix(table_data, 0, 2); /* Type */
+ /* Length */
+ build_append_int_noprefix(table_data,
+ 16 + ioapic_scope_size + scope_blob->len, 2);
+ /* Flags */
+ build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
+ 1);
+ build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
+ build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
+ /* Register Base Address */
+ build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
/* Scope definition for the root-complex IOAPIC. See VT-d spec
* 8.3.1 (version Oct. 2014 or later). */
- scope = &drhd->scope[0];
- scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
- scope->length = ioapic_scope_size;
- scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
- scope->bus = Q35_PSEUDO_BUS_PLATFORM;
- scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
- scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
+ build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
+ build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Reserved */
+ /* Enumeration ID */
+ build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
+ /* Start Bus Number */
+ build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
+ /* Path, {Device, Function} pair */
+ build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
+ build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
/* Add scope found above */
g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
g_array_free(scope_blob, true);
if (iommu->dt_supported) {
- atsr = acpi_data_push(table_data, sizeof(*atsr));
- atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
- atsr->length = cpu_to_le16(sizeof(*atsr));
- atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
- atsr->pci_segment = cpu_to_le16(0);
+ /* 8.5 Root Port ATS Capability Reporting Structure */
+ build_append_int_noprefix(table_data, 2, 2); /* Type */
+ build_append_int_noprefix(table_data, 8, 2); /* Length */
+ build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
+ build_append_int_noprefix(table_data, 0, 1); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
}
- build_header(linker, table_data, (void *)(table_data->data + dmar_start),
- "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
/*
build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
const char *oem_table_id)
{
- int waet_start = table_data->len;
+ AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
+ .oem_table_id = oem_table_id };
- /* WAET header */
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, table_data);
/*
* Set "ACPI PM timer good" flag.
*
* Which avoids costly VMExits caused by guest re-reading it unnecessarily.
*/
build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
-
- build_header(linker, table_data, (void *)(table_data->data + waet_start),
- "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
/*
const char *oem_table_id)
{
int ivhd_table_len = 24;
- int iommu_start = table_data->len;
AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
GArray *ivhd_blob = g_array_new(false, true, 1);
+ AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
+ .oem_table_id = oem_table_id };
- /* IVRS header */
- acpi_data_push(table_data, sizeof(AcpiTableHeader));
+ acpi_table_begin(&table, table_data);
/* IVinfo - IO virtualization information common to all
* IOMMU units in a system
*/
0x48, /* special device */
8);
}
-
- build_header(linker, table_data, (void *)(table_data->data + iommu_start),
- "IVRS", table_data->len - iommu_start, 1, oem_id,
- oem_table_id);
+ acpi_table_end(linker, &table);
}
typedef
#include "acpi-common.h"
void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry)
+ const CPUArchIdList *apic_ids, GArray *entry,
+ bool force_enabled)
{
uint32_t apic_id = apic_ids->cpus[uid].arch_id;
+ /* Flags – Local APIC Flags */
+ uint32_t flags = apic_ids->cpus[uid].cpu != NULL || force_enabled ?
+ 1 /* Enabled */ : 0;
/* ACPI spec says that LAPIC entry for non present
* CPU may be omitted from MADT or it must be marked
* should be put in MADT but kept disabled.
*/
if (apic_id < 255) {
- AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_PROCESSOR;
- apic->length = sizeof(*apic);
- apic->processor_id = uid;
- apic->local_apic_id = apic_id;
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
+ /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */
+ build_append_int_noprefix(entry, 0, 1); /* Type */
+ build_append_int_noprefix(entry, 8, 1); /* Length */
+ build_append_int_noprefix(entry, uid, 1); /* ACPI Processor ID */
+ build_append_int_noprefix(entry, apic_id, 1); /* APIC ID */
+ build_append_int_noprefix(entry, flags, 4); /* Flags */
} else {
- AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
-
- apic->type = ACPI_APIC_LOCAL_X2APIC;
- apic->length = sizeof(*apic);
- apic->uid = cpu_to_le32(uid);
- apic->x2apic_id = cpu_to_le32(apic_id);
- if (apic_ids->cpus[uid].cpu != NULL) {
- apic->flags = cpu_to_le32(1);
- } else {
- apic->flags = cpu_to_le32(0);
- }
+ /* Rev 4.0, 5.2.12.12 Processor Local x2APIC Structure */
+ build_append_int_noprefix(entry, 9, 1); /* Type */
+ build_append_int_noprefix(entry, 16, 1); /* Length */
+ build_append_int_noprefix(entry, 0, 2); /* Reserved */
+ build_append_int_noprefix(entry, apic_id, 4); /* X2APIC ID */
+ build_append_int_noprefix(entry, flags, 4); /* Flags */
+ build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
}
}
+static void build_ioapic(GArray *entry, uint8_t id, uint32_t addr, uint32_t irq)
+{
+ /* Rev 1.0b, 5.2.8.2 IO APIC */
+ build_append_int_noprefix(entry, 1, 1); /* Type */
+ build_append_int_noprefix(entry, 12, 1); /* Length */
+ build_append_int_noprefix(entry, id, 1); /* IO APIC ID */
+ build_append_int_noprefix(entry, 0, 1); /* Reserved */
+ build_append_int_noprefix(entry, addr, 4); /* IO APIC Address */
+ build_append_int_noprefix(entry, irq, 4); /* System Vector Base */
+}
+
+static void
+build_xrupt_override(GArray *entry, uint8_t src, uint32_t gsi, uint16_t flags)
+{
+ /* Rev 1.0b, 5.2.8.3.1 Interrupt Source Overrides */
+ build_append_int_noprefix(entry, 2, 1); /* Type */
+ build_append_int_noprefix(entry, 10, 1); /* Length */
+ build_append_int_noprefix(entry, 0, 1); /* Bus */
+ build_append_int_noprefix(entry, src, 1); /* Source */
+ /* Global System Interrupt Vector */
+ build_append_int_noprefix(entry, gsi, 4);
+ build_append_int_noprefix(entry, flags, 2); /* Flags */
+}
+
+/*
+ * ACPI spec, Revision 1.0b
+ * 5.2.8 Multiple APIC Description Table
+ */
void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
X86MachineState *x86ms, AcpiDeviceIf *adev,
const char *oem_id, const char *oem_table_id)
{
+ int i;
+ bool x2apic_mode = false;
MachineClass *mc = MACHINE_GET_CLASS(x86ms);
const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms));
- int madt_start = table_data->len;
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
- bool x2apic_mode = false;
+ AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = oem_id,
+ .oem_table_id = oem_table_id };
- AcpiMultipleApicTable *madt;
- AcpiMadtIoApic *io_apic;
- AcpiMadtIntsrcovr *intsrcovr;
- int i;
-
- madt = acpi_data_push(table_data, sizeof *madt);
- madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
- madt->flags = cpu_to_le32(1);
+ acpi_table_begin(&table, table_data);
+ /* Local APIC Address */
+ build_append_int_noprefix(table_data, APIC_DEFAULT_ADDRESS, 4);
+ build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
for (i = 0; i < apic_ids->len; i++) {
- adevc->madt_cpu(adev, i, apic_ids, table_data);
+ adevc->madt_cpu(adev, i, apic_ids, table_data, false);
if (apic_ids->cpus[i].arch_id > 254) {
x2apic_mode = true;
}
}
- io_apic = acpi_data_push(table_data, sizeof *io_apic);
- io_apic->type = ACPI_APIC_IO;
- io_apic->length = sizeof(*io_apic);
- io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
- io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
- io_apic->interrupt = cpu_to_le32(0);
-
+ build_ioapic(table_data, ACPI_BUILD_IOAPIC_ID, IO_APIC_DEFAULT_ADDRESS, 0);
if (x86ms->ioapic2) {
- AcpiMadtIoApic *io_apic2;
- io_apic2 = acpi_data_push(table_data, sizeof *io_apic);
- io_apic2->type = ACPI_APIC_IO;
- io_apic2->length = sizeof(*io_apic);
- io_apic2->io_apic_id = ACPI_BUILD_IOAPIC_ID + 1;
- io_apic2->address = cpu_to_le32(IO_APIC_SECONDARY_ADDRESS);
- io_apic2->interrupt = cpu_to_le32(IO_APIC_SECONDARY_IRQBASE);
+ build_ioapic(table_data, ACPI_BUILD_IOAPIC_ID + 1,
+ IO_APIC_SECONDARY_ADDRESS, IO_APIC_SECONDARY_IRQBASE);
}
if (x86ms->apic_xrupt_override) {
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = 0;
- intsrcovr->gsi = cpu_to_le32(2);
- intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
+ build_xrupt_override(table_data, 0, 2,
+ 0 /* Flags: Conforms to the specifications of the bus */);
}
for (i = 1; i < 16; i++) {
/* No need for a INT source override structure. */
continue;
}
- intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
- intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
- intsrcovr->length = sizeof(*intsrcovr);
- intsrcovr->source = i;
- intsrcovr->gsi = cpu_to_le32(i);
- intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
+ build_xrupt_override(table_data, i, i,
+ 0xd /* Flags: Active high, Level Triggered */);
}
if (x2apic_mode) {
- AcpiMadtLocalX2ApicNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->uid = 0xFFFFFFFF; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
+ /* Rev 4.0, 5.2.12.13 Local x2APIC NMI Structure*/
+ build_append_int_noprefix(table_data, 0xA, 1); /* Type */
+ build_append_int_noprefix(table_data, 12, 1); /* Length */
+ build_append_int_noprefix(table_data, 0, 2); /* Flags */
+ /* ACPI Processor UID */
+ build_append_int_noprefix(table_data, 0xFFFFFFFF /* all processors */,
+ 4);
+ /* Local x2APIC LINT# */
+ build_append_int_noprefix(table_data, 1 /* ACPI_LINT1 */, 1);
+ build_append_int_noprefix(table_data, 0, 3); /* Reserved */
} else {
- AcpiMadtLocalNmi *local_nmi;
-
- local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
- local_nmi->type = ACPI_APIC_LOCAL_NMI;
- local_nmi->length = sizeof(*local_nmi);
- local_nmi->processor_id = 0xff; /* all processors */
- local_nmi->flags = cpu_to_le16(0);
- local_nmi->lint = 1; /* ACPI_LINT1 */
+ /* Rev 1.0b, 5.2.8.3.3 Local APIC NMI */
+ build_append_int_noprefix(table_data, 4, 1); /* Type */
+ build_append_int_noprefix(table_data, 6, 1); /* Length */
+ /* ACPI Processor ID */
+ build_append_int_noprefix(table_data, 0xFF /* all processors */, 1);
+ build_append_int_noprefix(table_data, 0, 2); /* Flags */
+ /* Local APIC INTI# */
+ build_append_int_noprefix(table_data, 1 /* ACPI_LINT1 */, 1);
}
- build_header(linker, table_data,
- (void *)(table_data->data + madt_start), "APIC",
- table_data->len - madt_start, 1, oem_id, oem_table_id);
+ acpi_table_end(linker, &table);
}
Aml *dsdt, *sb_scope, *scope, *pkg;
bool ambiguous;
Object *isabus;
+ AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = x86ms->oem_id,
+ .oem_table_id = x86ms->oem_table_id };
isabus = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
assert(isabus);
assert(!ambiguous);
+ acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator();
- /* Reserve space for header */
- acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
-
sb_scope = aml_scope("_SB");
fw_cfg_add_acpi_dsdt(sb_scope, x86ms->fw_cfg);
isa_build_aml(ISA_BUS(isabus), sb_scope);
aml_append(scope, aml_name_decl("_S5", pkg));
aml_append(dsdt, scope);
- /* copy AML table into ACPI tables blob and patch header there */
+ /* copy AML bytecode into ACPI tables blob */
g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
- build_header(linker, table_data,
- (void *)(table_data->data + table_data->len - dsdt->buf->len),
- "DSDT", dsdt->buf->len, 2, x86ms->oem_id, x86ms->oem_table_id);
+
+ acpi_table_end(linker, &table);
free_aml_allocator();
}
AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR);
}
-static void amdvi_reset(DeviceState *dev)
+static void amdvi_sysbus_reset(DeviceState *dev)
{
AMDVIState *s = AMD_IOMMU_DEVICE(dev);
amdvi_init(s);
}
-static void amdvi_realize(DeviceState *dev, Error **errp)
+static void amdvi_sysbus_realize(DeviceState *dev, Error **errp)
{
int ret = 0;
AMDVIState *s = AMD_IOMMU_DEVICE(dev);
amdvi_init(s);
}
-static const VMStateDescription vmstate_amdvi = {
+static const VMStateDescription vmstate_amdvi_sysbus = {
.name = "amd-iommu",
.unmigratable = 1
};
-static void amdvi_instance_init(Object *klass)
+static void amdvi_sysbus_instance_init(Object *klass)
{
AMDVIState *s = AMD_IOMMU_DEVICE(klass);
object_initialize(&s->pci, sizeof(s->pci), TYPE_AMD_IOMMU_PCI);
}
-static void amdvi_class_init(ObjectClass *klass, void* data)
+static void amdvi_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
X86IOMMUClass *dc_class = X86_IOMMU_DEVICE_CLASS(klass);
- dc->reset = amdvi_reset;
- dc->vmsd = &vmstate_amdvi;
+ dc->reset = amdvi_sysbus_reset;
+ dc->vmsd = &vmstate_amdvi_sysbus;
dc->hotpluggable = false;
- dc_class->realize = amdvi_realize;
+ dc_class->realize = amdvi_sysbus_realize;
dc_class->int_remap = amdvi_int_remap;
/* Supported by the pc-q35-* machine types */
dc->user_creatable = true;
dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device";
}
-static const TypeInfo amdvi = {
+static const TypeInfo amdvi_sysbus = {
.name = TYPE_AMD_IOMMU_DEVICE,
.parent = TYPE_X86_IOMMU_DEVICE,
.instance_size = sizeof(AMDVIState),
- .instance_init = amdvi_instance_init,
- .class_init = amdvi_class_init
+ .instance_init = amdvi_sysbus_instance_init,
+ .class_init = amdvi_sysbus_class_init
};
-static const TypeInfo amdviPCI = {
+static void amdvi_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device";
+}
+
+static const TypeInfo amdvi_pci = {
.name = TYPE_AMD_IOMMU_PCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(AMDVIPCIState),
+ .class_init = amdvi_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
.class_init = amdvi_iommu_memory_region_class_init,
};
-static void amdviPCI_register_types(void)
+static void amdvi_register_types(void)
{
- type_register_static(&amdviPCI);
- type_register_static(&amdvi);
+ type_register_static(&amdvi_pci);
+ type_register_static(&amdvi_sysbus);
type_register_static(&amdvi_iommu_memory_region_info);
}
-type_init(amdviPCI_register_types);
+type_init(amdvi_register_types);
#include "hw/i386/fw_cfg.h"
#include "hw/intc/i8259.h"
#include "hw/rtc/mc146818rtc.h"
+#include "target/i386/sev_i386.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/irq.h"
const char *initrd_filename = machine->initrd_filename;
const char *dtb_filename = machine->dtb;
const char *kernel_cmdline = machine->kernel_cmdline;
+ SevKernelLoaderContext sev_load_ctx = {};
/* Align to 16 bytes as a paranoia measure */
cmdline_size = (strlen(kernel_cmdline) + 16) & ~15;
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
+ sev_load_ctx.cmdline_data = (char *)kernel_cmdline;
+ sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1;
if (protocol >= 0x202) {
stl_p(header + 0x228, cmdline_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
+ sev_load_ctx.initrd_data = initrd_data;
+ sev_load_ctx.initrd_size = initrd_size;
stl_p(header + 0x218, initrd_addr);
stl_p(header + 0x21c, initrd_size);
load_image_size(dtb_filename, setup_data->data, dtb_size);
}
- memcpy(setup, header, MIN(sizeof(header), setup_size));
+ /*
+ * If we're starting an encrypted VM, it will be OVMF based, which uses the
+ * efi stub for booting and doesn't require any values to be placed in the
+ * kernel header. We therefore don't update the header so the hash of the
+ * kernel on the other side of the fw_cfg interface matches the hash of the
+ * file the user passed in.
+ */
+ if (!sev_enabled()) {
+ memcpy(setup, header, MIN(sizeof(header), setup_size));
+ }
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
+ sev_load_ctx.kernel_data = (char *)kernel;
+ sev_load_ctx.kernel_size = kernel_size;
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
+ sev_load_ctx.setup_data = (char *)setup;
+ sev_load_ctx.setup_size = setup_size;
+
+ if (sev_enabled()) {
+ sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal);
+ }
option_rom[nb_option_roms].bootindex = 0;
option_rom[nb_option_roms].name = "linuxboot.bin";
#include "qemu/timer.h"
#include "qom/object.h"
+#if defined(__APPLE__) && defined(__MACH__)
+#include <IOKit/IOKitLib.h>
+
+enum {
+ kSMCSuccess = 0x00,
+ kSMCKeyNotFound = 0x84
+};
+
+enum {
+ kSMCUserClientOpen = 0x00,
+ kSMCUserClientClose = 0x01,
+ kSMCHandleYPCEvent = 0x02,
+ kSMCReadKey = 0x05,
+ kSMCGetKeyInfo = 0x09
+};
+
+typedef struct SMCVersion {
+ uint8_t major;
+ uint8_t minor;
+ uint8_t build;
+ uint8_t reserved;
+ uint16_t release;
+} SMCVersion;
+
+typedef struct SMCPLimitData {
+ uint16_t version;
+ uint16_t length;
+ uint32_t cpuPLimit;
+ uint32_t gpuPLimit;
+ uint32_t memPLimit;
+} SMCPLimitData;
+
+typedef struct SMCKeyInfoData {
+ IOByteCount dataSize;
+ uint32_t dataType;
+ uint8_t dataAttributes;
+} SMCKeyInfoData;
+
+typedef struct {
+ uint32_t key;
+ SMCVersion vers;
+ SMCPLimitData pLimitData;
+ SMCKeyInfoData keyInfo;
+ uint8_t result;
+ uint8_t status;
+ uint8_t data8;
+ uint32_t data32;
+ uint8_t bytes[32];
+} SMCParamStruct;
+
+static IOReturn smc_call_struct_method(uint32_t selector,
+ SMCParamStruct *inputStruct,
+ SMCParamStruct *outputStruct)
+{
+ IOReturn ret;
+
+ size_t inputStructCnt = sizeof(SMCParamStruct);
+ size_t outputStructCnt = sizeof(SMCParamStruct);
+
+ io_service_t smcService = IO_OBJECT_NULL;
+ io_connect_t smcConnect = IO_OBJECT_NULL;
+
+ smcService = IOServiceGetMatchingService(kIOMasterPortDefault,
+ IOServiceMatching("AppleSMC"));
+ if (smcService == IO_OBJECT_NULL) {
+ ret = kIOReturnNotFound;
+ goto exit;
+ }
+
+ ret = IOServiceOpen(smcService, mach_task_self(), 1, &smcConnect);
+ if (ret != kIOReturnSuccess) {
+ smcConnect = IO_OBJECT_NULL;
+ goto exit;
+ }
+ if (smcConnect == IO_OBJECT_NULL) {
+ ret = kIOReturnError;
+ goto exit;
+ }
+
+ ret = IOConnectCallMethod(smcConnect, kSMCUserClientOpen,
+ NULL, 0, NULL, 0,
+ NULL, NULL, NULL, NULL);
+ if (ret != kIOReturnSuccess) {
+ goto exit;
+ }
+
+ ret = IOConnectCallStructMethod(smcConnect, selector,
+ inputStruct, inputStructCnt,
+ outputStruct, &outputStructCnt);
+
+exit:
+ if (smcConnect != IO_OBJECT_NULL) {
+ IOConnectCallMethod(smcConnect, kSMCUserClientClose,
+ NULL, 0, NULL, 0, NULL,
+ NULL, NULL, NULL);
+ IOServiceClose(smcConnect);
+ }
+
+ return ret;
+}
+
+static IOReturn smc_read_key(uint32_t key,
+ uint8_t *bytes,
+ IOByteCount *dataSize)
+{
+ IOReturn ret;
+
+ SMCParamStruct inputStruct;
+ SMCParamStruct outputStruct;
+
+ if (key == 0 || bytes == NULL) {
+ ret = kIOReturnCannotWire;
+ goto exit;
+ }
+
+ /* determine key's data size */
+ memset(&inputStruct, 0, sizeof(SMCParamStruct));
+ inputStruct.data8 = kSMCGetKeyInfo;
+ inputStruct.key = key;
+
+ memset(&outputStruct, 0, sizeof(SMCParamStruct));
+ ret = smc_call_struct_method(kSMCHandleYPCEvent, &inputStruct, &outputStruct);
+ if (ret != kIOReturnSuccess) {
+ goto exit;
+ }
+ if (outputStruct.result == kSMCKeyNotFound) {
+ ret = kIOReturnNotFound;
+ goto exit;
+ }
+ if (outputStruct.result != kSMCSuccess) {
+ ret = kIOReturnInternalError;
+ goto exit;
+ }
+
+ /* get key value */
+ memset(&inputStruct, 0, sizeof(SMCParamStruct));
+ inputStruct.data8 = kSMCReadKey;
+ inputStruct.key = key;
+ inputStruct.keyInfo.dataSize = outputStruct.keyInfo.dataSize;
+
+ memset(&outputStruct, 0, sizeof(SMCParamStruct));
+ ret = smc_call_struct_method(kSMCHandleYPCEvent, &inputStruct, &outputStruct);
+ if (ret != kIOReturnSuccess) {
+ goto exit;
+ }
+ if (outputStruct.result == kSMCKeyNotFound) {
+ ret = kIOReturnNotFound;
+ goto exit;
+ }
+ if (outputStruct.result != kSMCSuccess) {
+ ret = kIOReturnInternalError;
+ goto exit;
+ }
+
+ memset(bytes, 0, *dataSize);
+ if (*dataSize > inputStruct.keyInfo.dataSize) {
+ *dataSize = inputStruct.keyInfo.dataSize;
+ }
+ memcpy(bytes, outputStruct.bytes, *dataSize);
+
+exit:
+ return ret;
+}
+#endif
+
/* #define DEBUG_SMC */
#define APPLESMC_DEFAULT_IOBASE 0x300
static void applesmc_isa_realize(DeviceState *dev, Error **errp)
{
AppleSMCState *s = APPLE_SMC(dev);
+ bool valid_key = false;
memory_region_init_io(&s->io_data, OBJECT(s), &applesmc_data_io_ops, s,
"applesmc-data", 1);
isa_register_ioport(&s->parent_obj, &s->io_err,
s->iobase + APPLESMC_ERR_PORT);
- if (!s->osk || (strlen(s->osk) != 64)) {
+ if (s->osk) {
+ valid_key = strlen(s->osk) == 64;
+ } else {
+#if defined(__APPLE__) && defined(__MACH__)
+ IOReturn ret;
+ IOByteCount size = 32;
+
+ ret = smc_read_key('OSK0', (uint8_t *) default_osk, &size);
+ if (ret != kIOReturnSuccess) {
+ goto failure;
+ }
+
+ ret = smc_read_key('OSK1', (uint8_t *) default_osk + size, &size);
+ if (ret != kIOReturnSuccess) {
+ goto failure;
+ }
+
+ warn_report("Using AppleSMC with host key");
+ valid_key = true;
+ s->osk = default_osk;
+failure:;
+#endif
+ }
+
+ if (!valid_key) {
warn_report("Using AppleSMC with invalid key");
s->osk = default_osk;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = shakti_c_soc_state_realize;
+ /*
+ * Reasons:
+ * - Creates CPUS in riscv_hart_realize(), and can create unintended
+ * CPUs
+ * - Uses serial_hds in realize function, thus can't be used twice
+ */
+ dc->user_creatable = false;
}
static void shakti_c_soc_instance_init(Object *obj)
page = r->req.cmd.buf[2];
if (page == 0xb0) {
uint64_t max_transfer = blk_get_max_hw_transfer(s->conf.blk);
- uint32_t max_iov = blk_get_max_iov(s->conf.blk);
+ uint32_t max_iov = blk_get_max_hw_iov(s->conf.blk);
assert(max_transfer);
max_transfer = MIN_NON_ZERO(max_transfer, max_iov * qemu_real_host_page_size)
{
VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
- return vhost_get_features(&vvc->vhost_dev, user_feature_bits, features);
+ features = vhost_get_features(&vvc->vhost_dev, user_feature_bits, features);
+
+ return vhost_vsock_common_get_features(vdev, features, errp);
}
static const VMStateDescription vuv_vmstate = {
#include "qemu/iov.h"
#include "monitor/monitor.h"
+const int feature_bits[] = {
+ VIRTIO_VSOCK_F_SEQPACKET,
+ VHOST_INVALID_FEATURE_BIT
+};
+
+uint64_t vhost_vsock_common_get_features(VirtIODevice *vdev, uint64_t features,
+ Error **errp)
+{
+ VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
+
+ if (vvc->seqpacket != ON_OFF_AUTO_OFF) {
+ virtio_add_feature(&features, VIRTIO_VSOCK_F_SEQPACKET);
+ }
+
+ features = vhost_get_features(&vvc->vhost_dev, feature_bits, features);
+
+ if (vvc->seqpacket == ON_OFF_AUTO_ON &&
+ !virtio_has_feature(features, VIRTIO_VSOCK_F_SEQPACKET)) {
+ error_setg(errp, "vhost-vsock backend doesn't support seqpacket");
+ }
+
+ return features;
+}
+
int vhost_vsock_common_start(VirtIODevice *vdev)
{
VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
virtio_cleanup(vdev);
}
+static Property vhost_vsock_common_properties[] = {
+ DEFINE_PROP_ON_OFF_AUTO("seqpacket", VHostVSockCommon, seqpacket,
+ ON_OFF_AUTO_AUTO),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void vhost_vsock_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
+ device_class_set_props(dc, vhost_vsock_common_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->guest_notifier_mask = vhost_vsock_common_guest_notifier_mask;
vdc->guest_notifier_pending = vhost_vsock_common_guest_notifier_pending;
#include "hw/virtio/vhost-vsock.h"
#include "monitor/monitor.h"
-const int feature_bits[] = {
- VIRTIO_VSOCK_F_SEQPACKET,
- VHOST_INVALID_FEATURE_BIT
-};
-
static void vhost_vsock_get_config(VirtIODevice *vdev, uint8_t *config)
{
VHostVSock *vsock = VHOST_VSOCK(vdev);
uint64_t requested_features,
Error **errp)
{
- VHostVSockCommon *vvc = VHOST_VSOCK_COMMON(vdev);
-
- virtio_add_feature(&requested_features, VIRTIO_VSOCK_F_SEQPACKET);
- return vhost_get_features(&vvc->vhost_dev, feature_bits,
- requested_features);
+ return vhost_vsock_common_get_features(vdev, requested_features, errp);
}
static const VMStateDescription vmstate_virtio_vhost_vsock = {
};
static const VMStateDescription vmstate_virtio_balloon_page_poison = {
- .name = "vitio-balloon-device/page-poison",
+ .name = "virtio-balloon-device/page-poison",
.version_id = 1,
.minimum_version_id = 1,
.needed = virtio_balloon_page_poison_support,
return VIRTQUEUE_READ_DESC_MORE;
}
+/* Called within rcu_read_lock(). */
static void virtqueue_split_get_avail_bytes(VirtQueue *vq,
unsigned int *in_bytes, unsigned int *out_bytes,
- unsigned max_in_bytes, unsigned max_out_bytes)
+ unsigned max_in_bytes, unsigned max_out_bytes,
+ VRingMemoryRegionCaches *caches)
{
VirtIODevice *vdev = vq->vdev;
unsigned int max, idx;
unsigned int total_bufs, in_total, out_total;
- VRingMemoryRegionCaches *caches;
MemoryRegionCache indirect_desc_cache = MEMORY_REGION_CACHE_INVALID;
int64_t len = 0;
int rc;
- RCU_READ_LOCK_GUARD();
-
idx = vq->last_avail_idx;
total_bufs = in_total = out_total = 0;
max = vq->vring.num;
- caches = vring_get_region_caches(vq);
- if (!caches) {
- goto err;
- }
while ((rc = virtqueue_num_heads(vq, idx)) > 0) {
MemoryRegionCache *desc_cache = &caches->desc;
return VIRTQUEUE_READ_DESC_MORE;
}
+/* Called within rcu_read_lock(). */
static void virtqueue_packed_get_avail_bytes(VirtQueue *vq,
unsigned int *in_bytes,
unsigned int *out_bytes,
unsigned max_in_bytes,
- unsigned max_out_bytes)
+ unsigned max_out_bytes,
+ VRingMemoryRegionCaches *caches)
{
VirtIODevice *vdev = vq->vdev;
unsigned int max, idx;
unsigned int total_bufs, in_total, out_total;
MemoryRegionCache *desc_cache;
- VRingMemoryRegionCaches *caches;
MemoryRegionCache indirect_desc_cache = MEMORY_REGION_CACHE_INVALID;
int64_t len = 0;
VRingPackedDesc desc;
bool wrap_counter;
- RCU_READ_LOCK_GUARD();
idx = vq->last_avail_idx;
wrap_counter = vq->last_avail_wrap_counter;
total_bufs = in_total = out_total = 0;
max = vq->vring.num;
- caches = vring_get_region_caches(vq);
- if (!caches) {
- goto err;
- }
for (;;) {
unsigned int num_bufs = total_bufs;
uint16_t desc_size;
VRingMemoryRegionCaches *caches;
+ RCU_READ_LOCK_GUARD();
+
if (unlikely(!vq->vring.desc)) {
goto err;
}
if (virtio_vdev_has_feature(vq->vdev, VIRTIO_F_RING_PACKED)) {
virtqueue_packed_get_avail_bytes(vq, in_bytes, out_bytes,
- max_in_bytes, max_out_bytes);
+ max_in_bytes, max_out_bytes,
+ caches);
} else {
virtqueue_split_get_avail_bytes(vq, in_bytes, out_bytes,
- max_in_bytes, max_out_bytes);
+ max_in_bytes, max_out_bytes,
+ caches);
}
return;
VirtIODevice *vdev = vq->vdev;
VRingPackedDesc desc;
+ RCU_READ_LOCK_GUARD();
+
caches = vring_get_region_caches(vq);
if (!caches) {
return 0;
const char *bdref_key, Error **errp);
BlockDriverState *bdrv_open(const char *filename, const char *reference,
QDict *options, int flags, Error **errp);
+BlockDriverState *bdrv_new_open_driver_opts(BlockDriver *drv,
+ const char *node_name,
+ QDict *options, int flags,
+ Error **errp);
BlockDriverState *bdrv_new_open_driver(BlockDriver *drv, const char *node_name,
int flags, Error **errp);
BlockReopenQueue *bdrv_reopen_queue(BlockReopenQueue *bs_queue,
* bdrv_drained_begin:
*
* Begin a quiesced section for exclusive access to the BDS, by disabling
- * external request sources including NBD server and device model. Note that
- * this doesn't block timers or coroutines from submitting more requests, which
- * means block_job_pause is still necessary.
+ * external request sources including NBD server, block jobs, and device model.
*
* This function can be recursive.
*/
*/
uint64_t max_hw_transfer;
+ /* Maximal number of scatter/gather elements allowed by the hardware.
+ * Applies whenever transfers to the device bypass the kernel I/O
+ * scheduler, for example with SG_IO. If larger than max_iov
+ * or if zero, blk_get_max_hw_iov will fall back to max_iov.
+ */
+ int max_hw_iov;
+
/* memory alignment, in bytes so that no bounce buffer is needed */
size_t min_mem_alignment;
MO_16 = 1,
MO_32 = 2,
MO_64 = 3,
- MO_SIZE = 3, /* Mask for the above. */
+ MO_128 = 4,
+ MO_256 = 5,
+ MO_512 = 6,
+ MO_1024 = 7,
+ MO_SIZE = 0x07, /* Mask for the above. */
- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
+ MO_SIGN = 0x08, /* Sign-extended, otherwise zero-extended. */
- MO_BSWAP = 8, /* Host reverse endian. */
+ MO_BSWAP = 0x10, /* Host reverse endian. */
#ifdef HOST_WORDS_BIGENDIAN
MO_LE = MO_BSWAP,
MO_BE = 0,
* - an alignment to a specified size, which may be more or less than
* the access size (MO_ALIGN_x where 'x' is a size in bytes);
*/
- MO_ASHIFT = 4,
- MO_AMASK = 7 << MO_ASHIFT,
+ MO_ASHIFT = 5,
+ MO_AMASK = 0x7 << MO_ASHIFT,
#ifdef NEED_CPU_H
#ifdef TARGET_ALIGNED_ONLY
MO_ALIGN = 0,
--- /dev/null
+/*
+ * Combine the MemOp and mmu_idx parameters into a single value.
+ *
+ * Authors:
+ * Richard Henderson <rth@twiddle.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef EXEC_MEMOPIDX_H
+#define EXEC_MEMOPIDX_H 1
+
+#include "exec/memop.h"
+
+typedef uint32_t MemOpIdx;
+
+/**
+ * make_memop_idx
+ * @op: memory operation
+ * @idx: mmu index
+ *
+ * Encode these values into a single parameter.
+ */
+static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
+{
+#ifdef CONFIG_DEBUG_TCG
+ assert(idx <= 15);
+#endif
+ return (op << 4) | idx;
+}
+
+/**
+ * get_memop
+ * @oi: combined op/idx parameter
+ *
+ * Extract the memory operation from the combined value.
+ */
+static inline MemOp get_memop(MemOpIdx oi)
+{
+ return oi >> 4;
+}
+
+/**
+ * get_mmuidx
+ * @oi: combined op/idx parameter
+ *
+ * Extract the mmu index from the combined value.
+ */
+static inline unsigned get_mmuidx(MemOpIdx oi)
+{
+ return oi & 15;
+}
+
+#endif
unsigned *xsdt_tbl_offset;
} AcpiRsdpData;
-/* Table structure from Linux kernel (the ACPI tables are under the
- BSD license) */
-
-
-#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
- uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
- uint32_t length; /* Length of table, in bytes, including header */ \
- uint8_t revision; /* ACPI Specification minor version # */ \
- uint8_t checksum; /* To make sum of entire table == 0 */ \
- uint8_t oem_id[6] \
- QEMU_NONSTRING; /* OEM identification */ \
- uint8_t oem_table_id[8] \
- QEMU_NONSTRING; /* OEM table identification */ \
- uint32_t oem_revision; /* OEM revision number */ \
- uint8_t asl_compiler_id[4] \
- QEMU_NONSTRING; /* ASL compiler vendor ID */ \
- uint32_t asl_compiler_revision; /* ASL compiler revision number */
-
-
-/* ACPI common table header */
-struct AcpiTableHeader {
- ACPI_TABLE_HEADER_DEF
-} QEMU_PACKED;
-typedef struct AcpiTableHeader AcpiTableHeader;
-
struct AcpiGenericAddress {
uint8_t space_id; /* Address space where struct or register exists */
uint8_t bit_width; /* Size in bits of given register */
uint8_t access_width; /* ACPI 3.0: Minimum Access size (ACPI 3.0),
ACPI 2.0: Reserved, Table 5-1 */
uint64_t address; /* 64-bit address of struct or register */
-} QEMU_PACKED;
+};
typedef struct AcpiFadtData {
struct AcpiGenericAddress pm1a_cnt; /* PM1a_CNT_BLK */
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
-/*
- * Serial Port Console Redirection Table (SPCR), Rev. 1.02
- *
- * For .interface_type see Debug Port Table 2 (DBG2) serial port
- * subtypes in Table 3, Rev. May 22, 2012
- */
-struct AcpiSerialPortConsoleRedirection {
- ACPI_TABLE_HEADER_DEF
- uint8_t interface_type;
- uint8_t reserved1[3];
- struct AcpiGenericAddress base_address;
- uint8_t interrupt_types;
- uint8_t irq;
- uint32_t gsi;
- uint8_t baud;
- uint8_t parity;
- uint8_t stopbits;
- uint8_t flowctrl;
- uint8_t term_type;
- uint8_t reserved2;
- uint16_t pci_device_id;
- uint16_t pci_vendor_id;
- uint8_t pci_bus;
- uint8_t pci_slot;
- uint8_t pci_func;
- uint32_t pci_flags;
- uint8_t pci_seg;
- uint32_t reserved3;
-} QEMU_PACKED;
-typedef struct AcpiSerialPortConsoleRedirection
- AcpiSerialPortConsoleRedirection;
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-struct AcpiRsdtDescriptorRev1 {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t table_offset_entry[]; /* Array of pointers to other */
- /* ACPI tables */
-} QEMU_PACKED;
-typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
-
-/*
- * ACPI 2.0 eXtended System Description Table (XSDT)
- */
-struct AcpiXsdtDescriptorRev2 {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint64_t table_offset_entry[]; /* Array of pointers to other */
- /* ACPI tables */
-} QEMU_PACKED;
-typedef struct AcpiXsdtDescriptorRev2 AcpiXsdtDescriptorRev2;
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-struct AcpiFacsDescriptorRev1 {
- uint32_t signature; /* ACPI Signature */
- uint32_t length; /* Length of structure, in bytes */
- uint32_t hardware_signature; /* Hardware configuration signature */
- uint32_t firmware_waking_vector; /* ACPI OS waking vector */
- uint32_t global_lock; /* Global Lock */
- uint32_t flags;
- uint8_t resverved3 [40]; /* Reserved - must be zero */
-} QEMU_PACKED;
-typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
-
-/*
- * Differentiated System Description Table (DSDT)
- */
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define ACPI_DUAL_PIC 0
-#define ACPI_MULTIPLE_APIC 1
-
-/* Master MADT */
-
-struct AcpiMultipleApicTable {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t local_apic_address; /* Physical address of local APIC */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
-
-/* Values for Type in APIC sub-headers */
-
-#define ACPI_APIC_PROCESSOR 0
-#define ACPI_APIC_IO 1
-#define ACPI_APIC_XRUPT_OVERRIDE 2
-#define ACPI_APIC_NMI 3
-#define ACPI_APIC_LOCAL_NMI 4
-#define ACPI_APIC_ADDRESS_OVERRIDE 5
-#define ACPI_APIC_IO_SAPIC 6
-#define ACPI_APIC_LOCAL_SAPIC 7
-#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_LOCAL_X2APIC 9
-#define ACPI_APIC_LOCAL_X2APIC_NMI 10
-#define ACPI_APIC_GENERIC_CPU_INTERFACE 11
-#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
-#define ACPI_APIC_GENERIC_MSI_FRAME 13
-#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
-#define ACPI_APIC_GENERIC_TRANSLATOR 15
-#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
- uint8_t type; \
- uint8_t length;
-
-/* Sub-structures for MADT */
-
-struct AcpiMadtProcessorApic {
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint8_t local_apic_id; /* Processor's local APIC id */
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
-
-struct AcpiMadtIoApic {
- ACPI_SUB_HEADER_DEF
- uint8_t io_apic_id; /* I/O APIC ID */
- uint8_t reserved; /* Reserved - must be zero */
- uint32_t address; /* APIC physical address */
- uint32_t interrupt; /* Global system interrupt where INTI
- * lines start */
-} QEMU_PACKED;
-typedef struct AcpiMadtIoApic AcpiMadtIoApic;
-
-struct AcpiMadtIntsrcovr {
- ACPI_SUB_HEADER_DEF
- uint8_t bus;
- uint8_t source;
- uint32_t gsi;
- uint16_t flags;
-} QEMU_PACKED;
-typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
-
-struct AcpiMadtLocalNmi {
- ACPI_SUB_HEADER_DEF
- uint8_t processor_id; /* ACPI processor id */
- uint16_t flags; /* MPS INTI flags */
- uint8_t lint; /* Local APIC LINT# */
-} QEMU_PACKED;
-typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
-
-struct AcpiMadtProcessorX2Apic {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t x2apic_id; /* Processor's local x2APIC ID */
- uint32_t flags;
- uint32_t uid; /* Processor object _UID */
-} QEMU_PACKED;
-typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic;
-
-struct AcpiMadtLocalX2ApicNmi {
- ACPI_SUB_HEADER_DEF
- uint16_t flags; /* MPS INTI flags */
- uint32_t uid; /* Processor object _UID */
- uint8_t lint; /* Local APIC LINT# */
- uint8_t reserved[3]; /* Local APIC LINT# */
-} QEMU_PACKED;
-typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi;
-
-struct AcpiMadtGenericCpuInterface {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t cpu_interface_number;
- uint32_t uid;
- uint32_t flags;
- uint32_t parking_version;
- uint32_t performance_interrupt;
- uint64_t parked_address;
- uint64_t base_address;
- uint64_t gicv_base_address;
- uint64_t gich_base_address;
- uint32_t vgic_interrupt;
- uint64_t gicr_base_address;
- uint64_t arm_mpidr;
-} QEMU_PACKED;
-
-typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;
-
-/* GICC CPU Interface Flags */
-#define ACPI_MADT_GICC_ENABLED 1
-
-struct AcpiMadtGenericDistributor {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t gic_id;
- uint64_t base_address;
- uint32_t global_irq_base;
- /* ACPI 5.1 Errata 1228 Present GIC version in MADT table */
- uint8_t version;
- uint8_t reserved2[3];
-} QEMU_PACKED;
-
-typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
-
-struct AcpiMadtGenericMsiFrame {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t gic_msi_frame_id;
- uint64_t base_address;
- uint32_t flags;
- uint16_t spi_count;
- uint16_t spi_base;
-} QEMU_PACKED;
-
-typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
-
-struct AcpiMadtGenericRedistributor {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint64_t base_address;
- uint32_t range_length;
-} QEMU_PACKED;
-
-typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
-
-struct AcpiMadtGenericTranslator {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t translation_id;
- uint64_t base_address;
- uint32_t reserved2;
-} QEMU_PACKED;
-
-typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
-
-/*
- * Generic Timer Description Table (GTDT)
- */
-#define ACPI_GTDT_INTERRUPT_MODE_LEVEL (0 << 0)
-#define ACPI_GTDT_INTERRUPT_MODE_EDGE (1 << 0)
-#define ACPI_GTDT_CAP_ALWAYS_ON (1 << 2)
-
-struct AcpiGenericTimerTable {
- ACPI_TABLE_HEADER_DEF
- uint64_t counter_block_addresss;
- uint32_t reserved;
- uint32_t secure_el1_interrupt;
- uint32_t secure_el1_flags;
- uint32_t non_secure_el1_interrupt;
- uint32_t non_secure_el1_flags;
- uint32_t virtual_timer_interrupt;
- uint32_t virtual_timer_flags;
- uint32_t non_secure_el2_interrupt;
- uint32_t non_secure_el2_flags;
- uint64_t counter_read_block_address;
- uint32_t platform_timer_count;
- uint32_t platform_timer_offset;
-} QEMU_PACKED;
-typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
-
-/*
- * HPET Description Table
- */
-struct Acpi20Hpet {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t timer_block_id;
- struct AcpiGenericAddress addr;
- uint8_t hpet_number;
- uint16_t min_tick;
- uint8_t page_protect;
-} QEMU_PACKED;
-typedef struct Acpi20Hpet Acpi20Hpet;
-
-/*
- * SRAT (NUMA topology description) table
- */
-
-struct AcpiSystemResourceAffinityTable {
- ACPI_TABLE_HEADER_DEF
- uint32_t reserved1;
- uint32_t reserved2[2];
-} QEMU_PACKED;
-typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
-
-#define ACPI_SRAT_PROCESSOR_APIC 0
-#define ACPI_SRAT_MEMORY 1
-#define ACPI_SRAT_PROCESSOR_x2APIC 2
-#define ACPI_SRAT_PROCESSOR_GICC 3
-
-struct AcpiSratProcessorAffinity {
- ACPI_SUB_HEADER_DEF
- uint8_t proximity_lo;
- uint8_t local_apic_id;
- uint32_t flags;
- uint8_t local_sapic_eid;
- uint8_t proximity_hi[3];
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
-
-struct AcpiSratProcessorX2ApicAffinity {
- ACPI_SUB_HEADER_DEF
- uint16_t reserved;
- uint32_t proximity_domain;
- uint32_t x2apic_id;
- uint32_t flags;
- uint32_t clk_domain;
- uint32_t reserved2;
-} QEMU_PACKED;
-typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity;
-
-struct AcpiSratMemoryAffinity {
- ACPI_SUB_HEADER_DEF
- uint32_t proximity;
- uint16_t reserved1;
- uint64_t base_addr;
- uint64_t range_length;
- uint32_t reserved2;
- uint32_t flags;
- uint32_t reserved3[2];
-} QEMU_PACKED;
-typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
-
-struct AcpiSratProcessorGiccAffinity {
- ACPI_SUB_HEADER_DEF
- uint32_t proximity;
- uint32_t acpi_processor_uid;
- uint32_t flags;
- uint32_t clock_domain;
-} QEMU_PACKED;
-
-typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity;
-
-/*
- * TCPA Description Table
- *
- * Following Level 00, Rev 00.37 of specs:
- * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
- */
-struct Acpi20Tcpa {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint16_t platform_class;
- uint32_t log_area_minimum_length;
- uint64_t log_area_start_address;
-} QEMU_PACKED;
-typedef struct Acpi20Tcpa Acpi20Tcpa;
-
-/* DMAR - DMA Remapping table r2.2 */
-struct AcpiTableDmar {
- ACPI_TABLE_HEADER_DEF
- uint8_t host_address_width; /* Maximum DMA physical addressability */
- uint8_t flags;
- uint8_t reserved[10];
-} QEMU_PACKED;
-typedef struct AcpiTableDmar AcpiTableDmar;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INTR_REMAP 1
-#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
-
-/* Values for sub-structure type for DMAR */
-enum {
- ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
- ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
- ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
- ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
- ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
- ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
-};
-
-/*
- * Sub-structures for DMAR
- */
-
-/* Device scope structure for DRHD. */
-struct AcpiDmarDeviceScope {
- uint8_t entry_type;
- uint8_t length;
- uint16_t reserved;
- uint8_t enumeration_id;
- uint8_t bus;
- struct {
- uint8_t device;
- uint8_t function;
- } path[];
-} QEMU_PACKED;
-typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
-
-/* Type 0: Hardware Unit Definition */
-struct AcpiDmarHardwareUnit {
- uint16_t type;
- uint16_t length;
- uint8_t flags;
- uint8_t reserved;
- uint16_t pci_segment; /* The PCI Segment associated with this unit */
- uint64_t address; /* Base address of remapping hardware register-set */
- AcpiDmarDeviceScope scope[];
-} QEMU_PACKED;
-typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
-
-/* Type 2: Root Port ATS Capability Reporting Structure */
-struct AcpiDmarRootPortATS {
- uint16_t type;
- uint16_t length;
- uint8_t flags;
- uint8_t reserved;
- uint16_t pci_segment;
- AcpiDmarDeviceScope scope[];
-} QEMU_PACKED;
-typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
-
-/* Masks for Flags field above */
-#define ACPI_DMAR_INCLUDE_PCI_ALL 1
-#define ACPI_DMAR_ATSR_ALL_PORTS 1
-
-/*
- * Input Output Remapping Table (IORT)
- * Conforms to "IO Remapping Table System Software on ARM Platforms",
- * Document number: ARM DEN 0049B, October 2015
- */
-
-struct AcpiIortTable {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t node_count;
- uint32_t node_offset;
- uint32_t reserved;
-} QEMU_PACKED;
-typedef struct AcpiIortTable AcpiIortTable;
-
-/*
- * IORT node types
- */
-
-#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
- uint8_t type; \
- uint16_t length; \
- uint8_t revision; \
- uint32_t reserved; \
- uint32_t mapping_count; \
- uint32_t mapping_offset;
-
-/* Values for node Type above */
-enum {
- ACPI_IORT_NODE_ITS_GROUP = 0x00,
- ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
- ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
- ACPI_IORT_NODE_SMMU = 0x03,
- ACPI_IORT_NODE_SMMU_V3 = 0x04
-};
-
-struct AcpiIortIdMapping {
- uint32_t input_base;
- uint32_t id_count;
- uint32_t output_base;
- uint32_t output_reference;
- uint32_t flags;
-} QEMU_PACKED;
-typedef struct AcpiIortIdMapping AcpiIortIdMapping;
-
-struct AcpiIortMemoryAccess {
- uint32_t cache_coherency;
- uint8_t hints;
- uint16_t reserved;
- uint8_t memory_flags;
-} QEMU_PACKED;
-typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
-
-struct AcpiIortItsGroup {
- ACPI_IORT_NODE_HEADER_DEF
- uint32_t its_count;
- uint32_t identifiers[];
-} QEMU_PACKED;
-typedef struct AcpiIortItsGroup AcpiIortItsGroup;
-
-#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
-
-struct AcpiIortSmmu3 {
- ACPI_IORT_NODE_HEADER_DEF
- uint64_t base_address;
- uint32_t flags;
- uint32_t reserved2;
- uint64_t vatos_address;
- uint32_t model;
- uint32_t event_gsiv;
- uint32_t pri_gsiv;
- uint32_t gerr_gsiv;
- uint32_t sync_gsiv;
- AcpiIortIdMapping id_mapping_array[];
-} QEMU_PACKED;
-typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
-
-struct AcpiIortRC {
- ACPI_IORT_NODE_HEADER_DEF
- AcpiIortMemoryAccess memory_properties;
- uint32_t ats_attribute;
- uint32_t pci_segment_number;
- AcpiIortIdMapping id_mapping_array[];
-} QEMU_PACKED;
-typedef struct AcpiIortRC AcpiIortRC;
-
#endif
void (*ospm_status)(AcpiDeviceIf *adev, ACPIOSTInfoList ***list);
void (*send_event)(AcpiDeviceIf *adev, AcpiEventStatusBits ev);
void (*madt_cpu)(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry);
+ const CPUArchIdList *apic_ids, GArray *entry,
+ bool force_enabled);
};
#endif
Aml *aml_object_type(Aml *object);
void build_append_int_noprefix(GArray *table, uint64_t value, int size);
-void
-build_header(BIOSLinker *linker, GArray *table_data,
- AcpiTableHeader *h, const char *sig, int len, uint8_t rev,
- const char *oem_id, const char *oem_table_id);
+
+typedef struct AcpiTable {
+ const char *sig;
+ const uint8_t rev;
+ const char *oem_id;
+ const char *oem_table_id;
+ /* private vars tracking table state */
+ GArray *array;
+ unsigned table_offset;
+} AcpiTable;
+
+/**
+ * acpi_table_begin:
+ * initializes table header and keeps track of
+ * table data/offsets
+ * @desc: ACPI table descriptor
+ * @array: blob where the ACPI table will be composed/stored.
+ */
+void acpi_table_begin(AcpiTable *desc, GArray *array);
+
+/**
+ * acpi_table_end:
+ * sets actual table length and tells bios loader
+ * where table is for the later initialization on
+ * guest side.
+ * @linker: reference to BIOSLinker object to use for the table
+ * @table: ACPI table descriptor that was used with @acpi_table_begin
+ * counterpart
+ */
+void acpi_table_end(BIOSLinker *linker, AcpiTable *table);
+
void *acpi_data_push(GArray *table_data, unsigned size);
unsigned acpi_data_len(GArray *table);
void acpi_add_table(GArray *table_offsets, GArray *table_data);
uint32_t mmio32_offset, uint64_t mmio64_offset,
uint16_t bus_nr_offset);
-void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
+void build_srat_memory(GArray *table_data, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);
void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms,
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/acpi/tco.h"
-#define ACPI_PCIHP_ADDR_ICH9 0x0cc4
+#define ACPI_PCIHP_ADDR_ICH9 0x0cc0
typedef struct ICH9LPCPMRegs {
/*
#ifndef HW_MCHP_PFSOC_MMUART_H
#define HW_MCHP_PFSOC_MMUART_H
+#include "hw/sysbus.h"
#include "hw/char/serial.h"
-#define MCHP_PFSOC_MMUART_REG_SIZE 52
+#define MCHP_PFSOC_MMUART_REG_COUNT 13
+
+#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
+OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
typedef struct MchpPfSoCMMUartState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion container;
MemoryRegion iomem;
- hwaddr base;
- qemu_irq irq;
- SerialMM *serial;
+ SerialMM serial_mm;
- uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
+ uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
} MchpPfSoCMMUartState;
/**
ObjectClass *(*class_by_name)(const char *cpu_model);
void (*parse_features)(const char *typename, char *str, Error **errp);
- int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
const char *deprecation_note;
- /* Keep non-pointer data at the end to minimize holes. */
- int gdb_num_core_regs;
- bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
/* when system emulation is not available, this pointer is NULL */
* class data that depends on the accelerator, see accel/accel-common.c.
*/
void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
+
+ /*
+ * Keep non-pointer data at the end to minimize holes.
+ */
+ int reset_dump_flags;
+ int gdb_num_core_regs;
+ bool gdb_stop_before_watchpoint;
};
/*
int *data_len);
void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
-
-/* acpi-build.c */
+/* hw/i386/acpi-common.c */
void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
- const CPUArchIdList *apic_ids, GArray *entry);
+ const CPUArchIdList *apic_ids, GArray *entry,
+ bool force_enabled);
/* sgx.c */
void pc_machine_init_sgx_epc(PCMachineState *pcms);
VirtQueue *trans_vq;
QEMUTimer *post_load_timer;
+
+ /* features */
+ OnOffAuto seqpacket;
};
int vhost_vsock_common_start(VirtIODevice *vdev);
int vhost_vsock_common_post_load(void *opaque, int version_id);
void vhost_vsock_common_realize(VirtIODevice *vdev, const char *name);
void vhost_vsock_common_unrealize(VirtIODevice *vdev);
+uint64_t vhost_vsock_common_get_features(VirtIODevice *vdev, uint64_t features,
+ Error **errp);
#endif /* _QEMU_VHOST_VSOCK_COMMON_H */
#include "qemu/error-report.h"
#include "qemu/queue.h"
#include "qemu/option.h"
+#include "exec/memopidx.h"
/*
* Events that plugins can subscribe to.
struct qemu_plugin_desc;
typedef QTAILQ_HEAD(, qemu_plugin_desc) QemuPluginList;
+/*
+ * Construct a qemu_plugin_meminfo_t.
+ */
+static inline qemu_plugin_meminfo_t
+make_plugin_meminfo(MemOpIdx oi, enum qemu_plugin_mem_rw rw)
+{
+ return oi | (rw << 16);
+}
+
+/*
+ * Extract the memory operation direction from a qemu_plugin_meminfo_t.
+ * Other portions may be extracted via get_memop and get_mmuidx.
+ */
+static inline enum qemu_plugin_mem_rw
+get_plugin_meminfo_rw(qemu_plugin_meminfo_t i)
+{
+ return i >> 16;
+}
+
#ifdef CONFIG_PLUGIN
extern QemuOptsList qemu_plugin_opts;
uint64_t a6, uint64_t a7, uint64_t a8);
void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret);
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t meminfo);
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw);
void qemu_plugin_flush_cb(void);
{ }
static inline void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
- uint32_t meminfo)
+ MemOpIdx oi,
+ enum qemu_plugin_mem_rw rw)
{ }
static inline void qemu_plugin_flush_cb(void)
uint32_t blk_get_max_transfer(BlockBackend *blk);
uint64_t blk_get_max_hw_transfer(BlockBackend *blk);
int blk_get_max_iov(BlockBackend *blk);
+int blk_get_max_hw_iov(BlockBackend *blk);
void blk_set_guest_block_size(BlockBackend *blk, int align);
void *blk_try_blockalign(BlockBackend *blk, size_t size);
void *blk_blockalign(BlockBackend *blk, size_t size);
#include "cpu.h"
#include "exec/memop.h"
+#include "exec/memopidx.h"
#include "qemu/bitops.h"
#include "qemu/plugin.h"
#include "qemu/queue.h"
return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
}
-/* Combine the MemOp and mmu_idx parameters into a single value. */
-typedef uint32_t TCGMemOpIdx;
-
-/**
- * make_memop_idx
- * @op: memory operation
- * @idx: mmu index
- *
- * Encode these values into a single parameter.
- */
-static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
-{
- tcg_debug_assert(idx <= 15);
- return (op << 4) | idx;
-}
-
-/**
- * get_memop
- * @oi: combined op/idx parameter
- *
- * Extract the memory operation from the combined value.
- */
-static inline MemOp get_memop(TCGMemOpIdx oi)
-{
- return oi >> 4;
-}
-
-/**
- * get_mmuidx
- * @oi: combined op/idx parameter
- *
- * Extract the mmu index from the combined value.
- */
-static inline unsigned get_mmuidx(TCGMemOpIdx oi)
-{
- return oi & 15;
-}
-
/**
* tcg_qemu_tb_exec:
* @env: pointer to CPUArchState for the CPU
: (qemu_build_not_reached_always(), 0)) \
: dup_const(VECE, C))
+#if TARGET_LONG_BITS == 64
+# define dup_const_tl dup_const
+#else
+# define dup_const_tl(VECE, C) \
+ (__builtin_constant_p(VECE) \
+ ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \
+ : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \
+ : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \
+ : (qemu_build_not_reached_always(), 0)) \
+ : (target_long)dup_const(VECE, C))
+#endif
+
/*
* Memory helpers that will be used by TCG generated code.
*/
#ifdef CONFIG_SOFTMMU
/* Value zero-extended to tcg register size. */
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
/* Value sign-extended to tcg register size. */
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
/* Temporary aliases until backends are converted. */
#ifdef TARGET_WORDS_BIGENDIAN
uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
(CPUArchState *env, target_ulong addr, TYPE val, \
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#ifdef CONFIG_ATOMIC64
#define GEN_ATOMIC_HELPER_ALL(NAME) \
Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#ifdef CONFIG_DEBUG_TCG
void tcg_assert_listed_vecop(TCGOpcode);
-Subproject commit 776acd2a805c9b42b4f0375150977df42130317f
+Subproject commit b25d94e7c77fda05a7fdfe8afe562cf9760d69da
-project('qemu', ['c'], meson_version: '>=0.55.0',
- default_options: ['warning_level=1', 'c_std=gnu11', 'cpp_std=gnu++11', 'b_colorout=auto'] +
- (meson.version().version_compare('>=0.56.0') ? [ 'b_staticpic=false' ] : []),
- version: run_command('head', meson.source_root() / 'VERSION').stdout().strip())
+project('qemu', ['c'], meson_version: '>=0.58.2',
+ default_options: ['warning_level=1', 'c_std=gnu11', 'cpp_std=gnu++11', 'b_colorout=auto',
+ 'b_staticpic=false'],
+ version: files('VERSION'))
not_found = dependency('', required: false)
-if meson.version().version_compare('>=0.56.0')
- keyval = import('keyval')
-else
- keyval = import('unstable-keyval')
-endif
+keyval = import('keyval')
ss = import('sourceset')
fs = import('fs')
tcg_arch = 'tci'
elif config_host['ARCH'] == 'sparc64'
tcg_arch = 'sparc'
- elif config_host['ARCH'] == 's390x'
- tcg_arch = 's390'
elif config_host['ARCH'] in ['x86_64', 'x32']
tcg_arch = 'i386'
elif config_host['ARCH'] == 'ppc64'
hxtool = find_program('scripts/hxtool')
shaderinclude = find_program('scripts/shaderinclude.pl')
qapi_gen = find_program('scripts/qapi-gen.py')
-qapi_gen_depends = [ meson.source_root() / 'scripts/qapi/__init__.py',
- meson.source_root() / 'scripts/qapi/commands.py',
- meson.source_root() / 'scripts/qapi/common.py',
- meson.source_root() / 'scripts/qapi/error.py',
- meson.source_root() / 'scripts/qapi/events.py',
- meson.source_root() / 'scripts/qapi/expr.py',
- meson.source_root() / 'scripts/qapi/gen.py',
- meson.source_root() / 'scripts/qapi/introspect.py',
- meson.source_root() / 'scripts/qapi/parser.py',
- meson.source_root() / 'scripts/qapi/schema.py',
- meson.source_root() / 'scripts/qapi/source.py',
- meson.source_root() / 'scripts/qapi/types.py',
- meson.source_root() / 'scripts/qapi/visit.py',
- meson.source_root() / 'scripts/qapi/common.py',
- meson.source_root() / 'scripts/qapi-gen.py'
+qapi_gen_depends = [ meson.current_source_dir() / 'scripts/qapi/__init__.py',
+ meson.current_source_dir() / 'scripts/qapi/commands.py',
+ meson.current_source_dir() / 'scripts/qapi/common.py',
+ meson.current_source_dir() / 'scripts/qapi/error.py',
+ meson.current_source_dir() / 'scripts/qapi/events.py',
+ meson.current_source_dir() / 'scripts/qapi/expr.py',
+ meson.current_source_dir() / 'scripts/qapi/gen.py',
+ meson.current_source_dir() / 'scripts/qapi/introspect.py',
+ meson.current_source_dir() / 'scripts/qapi/parser.py',
+ meson.current_source_dir() / 'scripts/qapi/schema.py',
+ meson.current_source_dir() / 'scripts/qapi/source.py',
+ meson.current_source_dir() / 'scripts/qapi/types.py',
+ meson.current_source_dir() / 'scripts/qapi/visit.py',
+ meson.current_source_dir() / 'scripts/qapi/common.py',
+ meson.current_source_dir() / 'scripts/qapi-gen.py'
]
tracetool = [
if target.endswith('-softmmu')
execs = [{
'name': 'qemu-system-' + target_name,
- 'gui': false,
+ 'win_subsystem': 'console',
'sources': files('softmmu/main.c'),
'dependencies': []
}]
if targetos == 'windows' and (sdl.found() or gtk.found())
execs += [{
'name': 'qemu-system-' + target_name + 'w',
- 'gui': true,
+ 'win_subsystem': 'windows',
'sources': files('softmmu/main.c'),
'dependencies': []
}]
specific_fuzz = specific_fuzz_ss.apply(config_target, strict: false)
execs += [{
'name': 'qemu-fuzz-' + target_name,
- 'gui': false,
+ 'win_subsystem': 'console',
'sources': specific_fuzz.sources(),
'dependencies': specific_fuzz.dependencies(),
}]
else
execs = [{
'name': 'qemu-' + target_name,
- 'gui': false,
+ 'win_subsystem': 'console',
'sources': [],
'dependencies': []
}]
link_language: link_language,
link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []),
link_args: link_args,
- gui_app: exe['gui'])
+ win_subsystem: exe['win_subsystem'])
if targetos == 'darwin'
icon = 'pc-bios/qemu.rsrc'
summary_info += {'git': config_host['GIT']}
summary_info += {'make': config_host['MAKE']}
summary_info += {'python': '@0@ (version: @1@)'.format(python.full_path(), python.language_version())}
-summary_info += {'sphinx-build': sphinx_build.found()}
+summary_info += {'sphinx-build': sphinx_build}
if config_host.has_key('HAVE_GDB_BIN')
summary_info += {'gdb': config_host['HAVE_GDB_BIN']}
endif
summary_info += {'genisoimage': config_host['GENISOIMAGE']}
if targetos == 'windows' and config_host.has_key('CONFIG_GUEST_AGENT')
- summary_info += {'wixl': wixl.found() ? wixl.full_path() : false}
+ summary_info += {'wixl': wixl}
endif
if slirp_opt != 'disabled' and 'CONFIG_SLIRP_SMBD' in config_host
summary_info += {'smbd': config_host['CONFIG_SMBD_COMMAND']}
summary_info += {'CFI debug support': get_option('cfi_debug')}
endif
summary_info += {'strip binaries': get_option('strip')}
-summary_info += {'sparse': sparse.found() ? sparse.full_path() : false}
+summary_info += {'sparse': sparse}
summary_info += {'mingw32 support': targetos == 'windows'}
# snarf the cross-compilation information for tests
summary_info += {'vvfat support': config_host.has_key('CONFIG_VVFAT')}
summary_info += {'qed support': config_host.has_key('CONFIG_QED')}
summary_info += {'parallels support': config_host.has_key('CONFIG_PARALLELS')}
- summary_info += {'FUSE exports': fuse.found()}
+ summary_info += {'FUSE exports': fuse}
endif
summary(summary_info, bool_yn: true, section: 'Block layer support')
# Crypto
summary_info = {}
summary_info += {'TLS priority': config_host['CONFIG_TLS_PRIORITY']}
-summary_info += {'GNUTLS support': gnutls.found()}
-summary_info += {'GNUTLS crypto': gnutls_crypto.found()}
-# TODO: add back version
-summary_info += {'libgcrypt': gcrypt.found()}
-# TODO: add back version
-summary_info += {'nettle': nettle.found()}
+summary_info += {'GNUTLS support': gnutls}
+if gnutls.found()
+ summary_info += {' GNUTLS crypto': gnutls_crypto.found()}
+endif
+summary_info += {'libgcrypt': gcrypt}
+summary_info += {'nettle': nettle}
if nettle.found()
summary_info += {' XTS': xts != 'private'}
endif
# Libraries
summary_info = {}
if targetos == 'darwin'
- summary_info += {'Cocoa support': cocoa.found()}
-endif
-# TODO: add back version
-summary_info += {'SDL support': sdl.found()}
-summary_info += {'SDL image support': sdl_image.found()}
-# TODO: add back version
-summary_info += {'GTK support': gtk.found()}
-summary_info += {'pixman': pixman.found()}
-# TODO: add back version
-summary_info += {'VTE support': vte.found()}
-# TODO: add back version
-summary_info += {'slirp support': slirp_opt == 'disabled' ? false : slirp_opt}
-summary_info += {'libtasn1': tasn1.found()}
-summary_info += {'PAM': pam.found()}
-summary_info += {'iconv support': iconv.found()}
-summary_info += {'curses support': curses.found()}
-# TODO: add back version
-summary_info += {'virgl support': virgl.found()}
-summary_info += {'curl support': curl.found()}
-summary_info += {'Multipath support': mpathpersist.found()}
-summary_info += {'VNC support': vnc.found()}
+ summary_info += {'Cocoa support': cocoa}
+endif
+summary_info += {'SDL support': sdl}
+summary_info += {'SDL image support': sdl_image}
+summary_info += {'GTK support': gtk}
+summary_info += {'pixman': pixman}
+summary_info += {'VTE support': vte}
+summary_info += {'slirp support': slirp_opt == 'internal' ? slirp_opt : slirp}
+summary_info += {'libtasn1': tasn1}
+summary_info += {'PAM': pam}
+summary_info += {'iconv support': iconv}
+summary_info += {'curses support': curses}
+summary_info += {'virgl support': virgl}
+summary_info += {'curl support': curl}
+summary_info += {'Multipath support': mpathpersist}
+summary_info += {'VNC support': vnc}
if vnc.found()
- summary_info += {'VNC SASL support': sasl.found()}
- summary_info += {'VNC JPEG support': jpeg.found()}
- summary_info += {'VNC PNG support': png.found()}
+ summary_info += {'VNC SASL support': sasl}
+ summary_info += {'VNC JPEG support': jpeg}
+ summary_info += {'VNC PNG support': png}
endif
-summary_info += {'brlapi support': brlapi.found()}
+summary_info += {'brlapi support': brlapi}
summary_info += {'vde support': config_host.has_key('CONFIG_VDE')}
summary_info += {'netmap support': config_host.has_key('CONFIG_NETMAP')}
summary_info += {'Linux AIO support': config_host.has_key('CONFIG_LINUX_AIO')}
-summary_info += {'Linux io_uring support': linux_io_uring.found()}
-summary_info += {'ATTR/XATTR support': libattr.found()}
+summary_info += {'Linux io_uring support': linux_io_uring}
+summary_info += {'ATTR/XATTR support': libattr}
summary_info += {'RDMA support': config_host.has_key('CONFIG_RDMA')}
summary_info += {'PVRDMA support': config_host.has_key('CONFIG_PVRDMA')}
summary_info += {'fdt support': fdt_opt == 'disabled' ? false : fdt_opt}
-summary_info += {'libcap-ng support': libcap_ng.found()}
-summary_info += {'bpf support': libbpf.found()}
+summary_info += {'libcap-ng support': libcap_ng}
+summary_info += {'bpf support': libbpf}
# TODO: add back protocol and server version
summary_info += {'spice support': config_host.has_key('CONFIG_SPICE')}
-summary_info += {'rbd support': rbd.found()}
+summary_info += {'rbd support': rbd}
summary_info += {'xfsctl support': config_host.has_key('CONFIG_XFS')}
-summary_info += {'smartcard support': cacard.found()}
-summary_info += {'U2F support': u2f.found()}
-summary_info += {'libusb': libusb.found()}
-summary_info += {'usb net redir': usbredir.found()}
+summary_info += {'smartcard support': cacard}
+summary_info += {'U2F support': u2f}
+summary_info += {'libusb': libusb}
+summary_info += {'usb net redir': usbredir}
summary_info += {'OpenGL support': config_host.has_key('CONFIG_OPENGL')}
-summary_info += {'GBM': gbm.found()}
-summary_info += {'libiscsi support': libiscsi.found()}
-summary_info += {'libnfs support': libnfs.found()}
+summary_info += {'GBM': gbm}
+summary_info += {'libiscsi support': libiscsi}
+summary_info += {'libnfs support': libnfs}
if targetos == 'windows'
if config_host.has_key('CONFIG_GUEST_AGENT')
summary_info += {'QGA VSS support': config_host.has_key('CONFIG_QGA_VSS')}
summary_info += {'QGA w32 disk info': config_host.has_key('CONFIG_QGA_NTDDSCSI')}
endif
endif
-summary_info += {'seccomp support': seccomp.found()}
-summary_info += {'GlusterFS support': glusterfs.found()}
+summary_info += {'seccomp support': seccomp}
+summary_info += {'GlusterFS support': glusterfs}
summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')}
summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')}
-summary_info += {'lzo support': lzo.found()}
-summary_info += {'snappy support': snappy.found()}
-summary_info += {'bzip2 support': libbzip2.found()}
-summary_info += {'lzfse support': liblzfse.found()}
-summary_info += {'zstd support': zstd.found()}
+summary_info += {'lzo support': lzo}
+summary_info += {'snappy support': snappy}
+summary_info += {'bzip2 support': libbzip2}
+summary_info += {'lzfse support': liblzfse}
+summary_info += {'zstd support': zstd}
summary_info += {'NUMA host support': config_host.has_key('CONFIG_NUMA')}
-summary_info += {'libxml2': libxml2.found()}
-summary_info += {'capstone': capstone_opt == 'disabled' ? false : capstone_opt}
-summary_info += {'libpmem support': libpmem.found()}
-summary_info += {'libdaxctl support': libdaxctl.found()}
-summary_info += {'libudev': libudev.found()}
+summary_info += {'libxml2': libxml2}
+summary_info += {'capstone': capstone_opt == 'internal' ? capstone_opt : capstone}
+summary_info += {'libpmem support': libpmem}
+summary_info += {'libdaxctl support': libdaxctl}
+summary_info += {'libudev': libudev}
+# Dummy dependency, keep .found()
summary_info += {'FUSE lseek': fuse_lseek.found()}
summary(summary_info, bool_yn: true, section: 'Dependencies')
{
DBMSaveState *s = &((DBMState *)opaque)->save;
SaveBitmapState *dbms = NULL;
+
+ qemu_mutex_lock_iothread();
if (init_dirty_bitmap_migration(s) < 0) {
+ qemu_mutex_unlock_iothread();
return -1;
}
send_bitmap_start(f, s, dbms);
}
qemu_put_bitmap_flags(f, DIRTY_BITMAP_MIG_FLAG_EOS);
-
+ qemu_mutex_unlock_iothread();
return 0;
}
} else if (s->state == MIGRATION_STATUS_POSTCOPY_ACTIVE) {
trace_migration_completion_postcopy_end();
+ qemu_mutex_lock_iothread();
qemu_savevm_state_complete_postcopy(s->to_dst_file);
+ qemu_mutex_unlock_iothread();
+
trace_migration_completion_postcopy_end_after_complete();
} else if (s->state == MIGRATION_STATUS_CANCELLING) {
goto fail;
#include "qemu/plugin-memory.h"
#include "hw/boards.h"
#endif
-#include "trace/mem.h"
/* Uninstall and Reset handlers */
unsigned qemu_plugin_mem_size_shift(qemu_plugin_meminfo_t info)
{
- return info & TRACE_MEM_SZ_SHIFT_MASK;
+ MemOp op = get_memop(info);
+ return op & MO_SIZE;
}
bool qemu_plugin_mem_is_sign_extended(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_SE);
+ MemOp op = get_memop(info);
+ return op & MO_SIGN;
}
bool qemu_plugin_mem_is_big_endian(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_BE);
+ MemOp op = get_memop(info);
+ return (op & MO_BSWAP) == MO_BE;
}
bool qemu_plugin_mem_is_store(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_ST);
+ return get_plugin_meminfo_rw(info) & QEMU_PLUGIN_MEM_W;
}
/*
{
#ifdef CONFIG_SOFTMMU
CPUState *cpu = current_cpu;
- unsigned int mmu_idx = info >> TRACE_MEM_MMU_SHIFT;
- hwaddr_info.is_store = info & TRACE_MEM_ST;
+ unsigned int mmu_idx = get_mmuidx(info);
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
+ hwaddr_info.is_store = (rw & QEMU_PLUGIN_MEM_W) != 0;
if (!tlb_plugin_lookup(cpu, vaddr, mmu_idx,
- info & TRACE_MEM_ST, &hwaddr_info)) {
+ hwaddr_info.is_store, &hwaddr_info)) {
error_report("invalid use of qemu_plugin_get_hwaddr");
return NULL;
}
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
-#include "trace/mem.h" /* mem_info macros */
#include "plugin.h"
#include "qemu/compiler.h"
}
}
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info)
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw)
{
GArray *arr = cpu->plugin_mem_cbs;
size_t i;
for (i = 0; i < arr->len; i++) {
struct qemu_plugin_dyn_cb *cb =
&g_array_index(arr, struct qemu_plugin_dyn_cb, i);
- int w = !!(info & TRACE_MEM_ST) + 1;
- if (!(w & cb->rw)) {
+ if (!(rw & cb->rw)) {
break;
}
switch (cb->type) {
case PLUGIN_CB_REGULAR:
- cb->f.vcpu_mem(cpu->cpu_index, info, vaddr, cb->userp);
+ cb->f.vcpu_mem(cpu->cpu_index, make_plugin_meminfo(oi, rw),
+ vaddr, cb->userp);
break;
case PLUGIN_CB_INLINE:
exec_inline_op(cb);
# Modules need more symbols than just those in plugins/qemu-plugins.symbols
if not enable_modules
if 'CONFIG_HAS_LD_DYNAMIC_LIST' in config_host
- plugin_ldflags = ['-Wl,--dynamic-list=' + (meson.build_root() / 'qemu-plugins-ld.symbols')]
+ plugin_ldflags = ['-Wl,--dynamic-list=' + (meson.project_build_root() / 'qemu-plugins-ld.symbols')]
elif 'CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST' in config_host
- plugin_ldflags = ['-Wl,-exported_symbols_list,' + (meson.build_root() / 'qemu-plugins-ld64.symbols')]
+ plugin_ldflags = ['-Wl,-exported_symbols_list,' + (meson.project_build_root() / 'qemu-plugins-ld64.symbols')]
endif
endif
if test['workdir'] is not None:
print('.test.dir.%d := %s' % (i, shlex.quote(test['workdir'])))
- if 'depends' in test:
- deps = (targets.get(x, []) for x in test['depends'])
- deps = itertools.chain.from_iterable(deps)
- else:
- deps = ['all']
+ deps = (targets.get(x, []) for x in test['depends'])
+ deps = itertools.chain.from_iterable(deps)
print('.test.name.%d := %s' % (i, test['name']))
print('.test.driver.%d := %s' % (i, driver))
" export the specified block node over NBD\n"
" (requires --nbd-server)\n"
"\n"
+#ifdef CONFIG_FUSE
" --export [type=]fuse,id=<id>,node-name=<node-name>,mountpoint=<file>\n"
" [,growable=on|off][,writable=on|off]\n"
" export the specified block node over FUSE\n"
"\n"
+#endif /* CONFIG_FUSE */
" --monitor [chardev=]name[,mode=control][,pretty[=on|off]]\n"
" configure a QMP monitor\n"
"\n"
clear_helper_retaddr();
#else
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
- TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
+ MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
uintptr_t ra = GETPC();
bool success;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
clear_helper_retaddr();
#else
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
- TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
+ MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
uintptr_t ra = GETPC();
bool success;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
Int128 oldv, cmpv, newv;
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
Int128 oldv, cmpv, newv;
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
{
bool threadmode, spsel;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
ARMMMUIdx mmu_idx;
uint32_t *frame_sp_p;
uint32_t frameptr;
int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
- switch (memop) {
+ switch ((unsigned)memop) {
case MO_8:
tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
break;
gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
#define fGEN_TCG_F2_sfclass(SHORTCODE) \
do { \
- TCGv imm = tcg_const_tl(uiV); \
+ TCGv imm = tcg_constant_tl(uiV); \
gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
- tcg_temp_free(imm); \
} while (0)
#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
#define fGEN_TCG_F2_dfclass(SHORTCODE) \
do { \
- TCGv imm = tcg_const_tl(uiV); \
+ TCGv imm = tcg_constant_tl(uiV); \
gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
- tcg_temp_free(imm); \
} while (0)
#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
if hex_common.need_part1(tag):
f.write(" TCGv part1 = tcg_const_tl(insn->part1);\n")
if hex_common.need_slot(tag):
- f.write(" TCGv slot = tcg_const_tl(insn->slot);\n")
+ f.write(" TCGv slot = tcg_constant_tl(insn->slot);\n")
f.write(" gen_helper_%s(" % (tag))
i=0
## If there is a scalar result, it is the return type
if hex_common.need_slot(tag): f.write(", slot")
if hex_common.need_part1(tag): f.write(", part1" )
f.write(");\n")
- if hex_common.need_slot(tag):
- f.write(" tcg_temp_free(slot);\n")
if hex_common.need_part1(tag):
f.write(" tcg_temp_free(part1);\n")
for immlett,bits,immshift in imms:
static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
{
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
TCGv slot_mask = tcg_temp_new();
tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
}
- tcg_temp_free(zero);
tcg_temp_free(slot_mask);
}
static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
{
TCGv val32 = tcg_temp_new();
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
TCGv slot_mask = tcg_temp_new();
tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
}
tcg_temp_free(val32);
- tcg_temp_free(zero);
tcg_temp_free(slot_mask);
}
tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
tcg_temp_free(p3_0);
} else if (reg_num == HEX_REG_PC - 1) {
- TCGv pc = tcg_const_tl(ctx->base.pc_next);
+ TCGv pc = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
- tcg_temp_free(pc);
} else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
TCGv pkt_cnt = tcg_temp_new();
TCGv insn_cnt = tcg_temp_new();
tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
- one = tcg_const_tl(0xff);
- zero = tcg_const_tl(0);
+ one = tcg_constant_tl(0xff);
+ zero = tcg_constant_tl(0);
tmp = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
ctx->mem_idx, MO_32);
tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
one, zero);
- tcg_temp_free(one);
- tcg_temp_free(zero);
tcg_temp_free(tmp);
tcg_gen_br(done);
tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
- one = tcg_const_i64(0xff);
- zero = tcg_const_i64(0);
+ one = tcg_constant_i64(0xff);
+ zero = tcg_constant_i64(0);
tmp = tcg_temp_new_i64();
tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
ctx->mem_idx, MO_64);
tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
one, zero);
tcg_gen_extrl_i64_i32(pred, tmp);
- tcg_temp_free_i64(one);
- tcg_temp_free_i64(zero);
tcg_temp_free_i64(tmp);
tcg_gen_br(done);
static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx, int slot)
{
- TCGv tmp = tcg_const_tl(src);
+ TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, ctx, slot);
- tcg_temp_free(tmp);
}
static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx, int slot)
{
- TCGv tmp = tcg_const_tl(src);
+ TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, ctx, slot);
- tcg_temp_free(tmp);
}
static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
DisasContext *ctx, int slot)
{
- TCGv tmp = tcg_const_tl(src);
+ TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, ctx, slot);
- tcg_temp_free(tmp);
}
static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
DisasContext *ctx, int slot)
{
- TCGv_i64 tmp = tcg_const_i64(src);
+ TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, ctx, slot);
- tcg_temp_free_i64(tmp);
}
static TCGv gen_8bitsof(TCGv result, TCGv value)
{
- TCGv zero = tcg_const_tl(0);
- TCGv ones = tcg_const_tl(0xff);
+ TCGv zero = tcg_constant_tl(0);
+ TCGv ones = tcg_constant_tl(0xff);
tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
- tcg_temp_free(zero);
- tcg_temp_free(ones);
return result;
}
DEF_HELPER_3(dfmpyfix, f64, env, f64, f64)
DEF_HELPER_4(dfmpyhh, f64, env, f64, f64, f64)
+
+DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int)
{
TCGv slot_mask = tcg_const_tl(1 << slot_num);
TCGv tmp = tcg_temp_new();
- TCGv zero = tcg_const_tl(0);
- TCGv one = tcg_const_tl(1);
+ TCGv zero = tcg_constant_tl(0);
tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask);
tcg_gen_andi_tl(tmp, pred, 1);
tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
slot_mask, hex_slot_cancelled);
tcg_temp_free(slot_mask);
tcg_temp_free(tmp);
- tcg_temp_free(zero);
- tcg_temp_free(one);
}
#define PRED_LOAD_CANCEL(PRED, EA) \
gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
'dectree_generated.h.inc',
output: 'dectree_generated.h.inc',
depends: [iset_py],
- command: ['env', 'PYTHONPATH=' + meson.current_build_dir(), files('dectree.py'), '@OUTPUT@'],
+ env: {'PYTHONPATH': meson.current_build_dir()},
+ command: [python, files('dectree.py'), '@OUTPUT@'],
)
hexagon_ss.add(dectree_generated)
return PeV;
}
+static void probe_store(CPUHexagonState *env, int slot, int mmu_idx)
+{
+ if (!(env->slot_cancelled & (1 << slot))) {
+ size1u_t width = env->mem_log_stores[slot].width;
+ target_ulong va = env->mem_log_stores[slot].va;
+ uintptr_t ra = GETPC();
+ probe_write(env, va, width, mmu_idx, ra);
+ }
+}
+
+/* Called during packet commit when there are two scalar stores */
+void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int mmu_idx)
+{
+ probe_store(env, 0, mmu_idx);
+}
+
/*
* mem_noshuf
* Section 5.5 of the Hexagon V67 Programmer's Reference Manual
static void gen_exception_raw(int excp)
{
- TCGv_i32 helper_tmp = tcg_const_i32(excp);
- gen_helper_raise_exception(cpu_env, helper_tmp);
- tcg_temp_free_i32(helper_tmp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exec_counters(DisasContext *ctx)
* write of the predicates.
*/
if (pkt->pkt_has_endloop) {
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
TCGv pred_written = tcg_temp_new();
for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i];
hex_new_pred_value[pred_num],
hex_pred[pred_num]);
}
- tcg_temp_free(zero);
tcg_temp_free(pred_written);
} else {
for (i = 0; i < ctx->preg_log_idx; i++) {
static void gen_check_store_width(DisasContext *ctx, int slot_num)
{
if (HEX_DEBUG) {
- TCGv slot = tcg_const_tl(slot_num);
- TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
+ TCGv slot = tcg_constant_tl(slot_num);
+ TCGv check = tcg_constant_tl(ctx->store_width[slot_num]);
gen_helper_debug_check_store_width(cpu_env, slot, check);
- tcg_temp_free(slot);
- tcg_temp_free(check);
}
}
* TCG generation time, we'll use a helper to
* avoid branching based on the width at runtime.
*/
- TCGv slot = tcg_const_tl(slot_num);
+ TCGv slot = tcg_constant_tl(slot_num);
gen_helper_commit_store(cpu_env, slot);
- tcg_temp_free(slot);
}
}
tcg_temp_free(address);
{
/*
* When a packet has two stores, the hardware processes
- * slot 1 and then slot 2. This will be important when
+ * slot 1 and then slot 0. This will be important when
* the memory accesses overlap.
*/
if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) {
if (pkt->pkt_has_dczeroa) {
/* Store 32 bytes of zero starting at (addr & ~0x1f) */
TCGv addr = tcg_temp_new();
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_temp_free(addr);
- tcg_temp_free_i64(zero);
}
}
static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
{
+ /*
+ * If there is more than one store in a packet, make sure they are all OK
+ * before proceeding with the rest of the packet commit.
+ *
+ * dczeroa has to be the only store operation in the packet, so we go
+ * ahead and process that first.
+ *
+ * When there are two scalar stores, we probe the one in slot 0.
+ *
+ * Note that we don't call the probe helper for packets with only one
+ * store. Therefore, we call process_store_log before anything else
+ * involved in committing the packet.
+ */
+ bool has_store_s0 = pkt->pkt_has_store_s0;
+ bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed);
+ if (pkt->pkt_has_dczeroa) {
+ /*
+ * The dczeroa will be the store in slot 0, check that we don't have
+ * a store in slot 1.
+ */
+ g_assert(has_store_s0 && !has_store_s1);
+ process_dczeroa(ctx, pkt);
+ } else if (has_store_s0 && has_store_s1) {
+ /*
+ * process_store_log will execute the slot 1 store first,
+ * so we only have to probe the store in slot 0
+ */
+ TCGv mem_idx = tcg_const_tl(ctx->mem_idx);
+ gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
+ tcg_temp_free(mem_idx);
+ }
+
+ process_store_log(ctx, pkt);
+
gen_reg_writes(ctx);
gen_pred_writes(ctx, pkt);
- process_store_log(ctx, pkt);
- process_dczeroa(ctx, pkt);
update_exec_counters(ctx, pkt);
if (HEX_DEBUG) {
TCGv has_st0 =
- tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
+ tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
TCGv has_st1 =
- tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
+ tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
/* Handy place to set a breakpoint at the end of execution */
gen_helper_debug_commit_end(cpu_env, has_st0, has_st1);
-
- tcg_temp_free(has_st0);
- tcg_temp_free(has_st1);
}
if (pkt->pkt_has_cof) {
error_setg(errp, "SEV is not available in this QEMU");
return NULL;
}
+
+bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp)
+{
+ g_assert_not_reached();
+}
#include "qemu/base64.h"
#include "qemu/module.h"
#include "qemu/uuid.h"
+#include "crypto/hash.h"
#include "sysemu/kvm.h"
#include "sev_i386.h"
#include "sysemu/sysemu.h"
uint32_t reset_addr;
} SevInfoBlock;
+#define SEV_HASH_TABLE_RV_GUID "7255371f-3a3b-4b04-927b-1da6efa8d454"
+typedef struct QEMU_PACKED SevHashTableDescriptor {
+ /* SEV hash table area guest address */
+ uint32_t base;
+ /* SEV hash table area size (in bytes) */
+ uint32_t size;
+} SevHashTableDescriptor;
+
+/* hard code sha256 digest size */
+#define HASH_SIZE 32
+
+typedef struct QEMU_PACKED SevHashTableEntry {
+ QemuUUID guid;
+ uint16_t len;
+ uint8_t hash[HASH_SIZE];
+} SevHashTableEntry;
+
+typedef struct QEMU_PACKED SevHashTable {
+ QemuUUID guid;
+ uint16_t len;
+ SevHashTableEntry cmdline;
+ SevHashTableEntry initrd;
+ SevHashTableEntry kernel;
+ uint8_t padding[];
+} SevHashTable;
+
static SevGuestState *sev_guest;
static Error *sev_mig_blocker;
return 0;
}
+static const QemuUUID sev_hash_table_header_guid = {
+ .data = UUID_LE(0x9438d606, 0x4f22, 0x4cc9, 0xb4, 0x79, 0xa7, 0x93,
+ 0xd4, 0x11, 0xfd, 0x21)
+};
+
+static const QemuUUID sev_kernel_entry_guid = {
+ .data = UUID_LE(0x4de79437, 0xabd2, 0x427f, 0xb8, 0x35, 0xd5, 0xb1,
+ 0x72, 0xd2, 0x04, 0x5b)
+};
+static const QemuUUID sev_initrd_entry_guid = {
+ .data = UUID_LE(0x44baf731, 0x3a2f, 0x4bd7, 0x9a, 0xf1, 0x41, 0xe2,
+ 0x91, 0x69, 0x78, 0x1d)
+};
+static const QemuUUID sev_cmdline_entry_guid = {
+ .data = UUID_LE(0x97d02dd8, 0xbd20, 0x4c94, 0xaa, 0x78, 0xe7, 0x71,
+ 0x4d, 0x36, 0xab, 0x2a)
+};
+
+/*
+ * Add the hashes of the linux kernel/initrd/cmdline to an encrypted guest page
+ * which is included in SEV's initial memory measurement.
+ */
+bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp)
+{
+ uint8_t *data;
+ SevHashTableDescriptor *area;
+ SevHashTable *ht;
+ uint8_t cmdline_hash[HASH_SIZE];
+ uint8_t initrd_hash[HASH_SIZE];
+ uint8_t kernel_hash[HASH_SIZE];
+ uint8_t *hashp;
+ size_t hash_len = HASH_SIZE;
+ int aligned_len;
+
+ if (!pc_system_ovmf_table_find(SEV_HASH_TABLE_RV_GUID, &data, NULL)) {
+ error_setg(errp, "SEV: kernel specified but OVMF has no hash table guid");
+ return false;
+ }
+ area = (SevHashTableDescriptor *)data;
+
+ /*
+ * Calculate hash of kernel command-line with the terminating null byte. If
+ * the user doesn't supply a command-line via -append, the 1-byte "\0" will
+ * be used.
+ */
+ hashp = cmdline_hash;
+ if (qcrypto_hash_bytes(QCRYPTO_HASH_ALG_SHA256, ctx->cmdline_data,
+ ctx->cmdline_size, &hashp, &hash_len, errp) < 0) {
+ return false;
+ }
+ assert(hash_len == HASH_SIZE);
+
+ /*
+ * Calculate hash of initrd. If the user doesn't supply an initrd via
+ * -initrd, an empty buffer will be used (ctx->initrd_size == 0).
+ */
+ hashp = initrd_hash;
+ if (qcrypto_hash_bytes(QCRYPTO_HASH_ALG_SHA256, ctx->initrd_data,
+ ctx->initrd_size, &hashp, &hash_len, errp) < 0) {
+ return false;
+ }
+ assert(hash_len == HASH_SIZE);
+
+ /* Calculate hash of the kernel */
+ hashp = kernel_hash;
+ struct iovec iov[2] = {
+ { .iov_base = ctx->setup_data, .iov_len = ctx->setup_size },
+ { .iov_base = ctx->kernel_data, .iov_len = ctx->kernel_size }
+ };
+ if (qcrypto_hash_bytesv(QCRYPTO_HASH_ALG_SHA256, iov, ARRAY_SIZE(iov),
+ &hashp, &hash_len, errp) < 0) {
+ return false;
+ }
+ assert(hash_len == HASH_SIZE);
+
+ /*
+ * Populate the hashes table in the guest's memory at the OVMF-designated
+ * area for the SEV hashes table
+ */
+ ht = qemu_map_ram_ptr(NULL, area->base);
+
+ ht->guid = sev_hash_table_header_guid;
+ ht->len = sizeof(*ht);
+
+ ht->cmdline.guid = sev_cmdline_entry_guid;
+ ht->cmdline.len = sizeof(ht->cmdline);
+ memcpy(ht->cmdline.hash, cmdline_hash, sizeof(ht->cmdline.hash));
+
+ ht->initrd.guid = sev_initrd_entry_guid;
+ ht->initrd.len = sizeof(ht->initrd);
+ memcpy(ht->initrd.hash, initrd_hash, sizeof(ht->initrd.hash));
+
+ ht->kernel.guid = sev_kernel_entry_guid;
+ ht->kernel.len = sizeof(ht->kernel);
+ memcpy(ht->kernel.hash, kernel_hash, sizeof(ht->kernel.hash));
+
+ /* When calling sev_encrypt_flash, the length has to be 16 byte aligned */
+ aligned_len = ROUND_UP(ht->len, 16);
+ if (aligned_len != ht->len) {
+ /* zero the excess data so the measurement can be reliably calculated */
+ memset(ht->padding, 0, aligned_len - ht->len);
+ }
+
+ if (sev_encrypt_flash((uint8_t *)ht, aligned_len, errp) < 0) {
+ return false;
+ }
+
+ return true;
+}
+
static void
sev_register_types(void)
{
#define SEV_POLICY_DOMAIN 0x10
#define SEV_POLICY_SEV 0x20
+typedef struct SevKernelLoaderContext {
+ char *setup_data;
+ size_t setup_size;
+ char *kernel_data;
+ size_t kernel_size;
+ char *initrd_data;
+ size_t initrd_size;
+ char *cmdline_data;
+ size_t cmdline_size;
+} SevKernelLoaderContext;
+
extern bool sev_es_enabled(void);
extern uint64_t sev_get_me_mask(void);
extern SevInfo *sev_get_info(void);
extern SevCapability *sev_get_capabilities(Error **errp);
extern SevAttestationReport *
sev_get_attestation_report(const char *mnonce, Error **errp);
+extern bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp);
#endif
{
uintptr_t ra = GETPC();
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
oldv = cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
}
Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra);
if (int128_eq(oldv, cmpv)) {
uintptr_t ra = GETPC();
#if defined(CONFIG_ATOMIC64)
int mmu_idx = cpu_mmu_index(env, 0);
- TCGMemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
#endif
if (parallel) {
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
#if !defined(CONFIG_USER_ONLY)
-#define MEMOP_IDX(DF) \
- TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
- cpu_mmu_index(env, false));
+#define MEMOP_IDX(DF) \
+ MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ cpu_mmu_index(env, false));
#else
#define MEMOP_IDX(DF)
#endif
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
-static const uint64_t adjacent_masks[] = {
- dup_const(MO_8, 0x55),
- dup_const(MO_8, 0x33),
- dup_const(MO_8, 0x0f),
- dup_const(MO_16, 0xff),
- dup_const(MO_32, 0xffff),
- UINT32_MAX
-};
-
-static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
-{
- return ((x & mask) << shift) | ((x & ~mask) >> shift);
-}
-
-static target_ulong do_grev(target_ulong rs1,
- target_ulong rs2,
- int bits)
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
{
- target_ulong x = rs1;
- int i, shift;
+ target_ulong result = 0;
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
- if (rs2 & shift) {
- x = do_swap(x, adjacent_masks[i], shift);
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
+ if ((rs2 >> i) & 1) {
+ result ^= (rs1 << i);
}
}
- return x;
-}
-
-target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
-{
- return do_grev(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
-{
- return do_grev(rs1, rs2, 32);
+ return result;
}
-static target_ulong do_gorc(target_ulong rs1,
- target_ulong rs2,
- int bits)
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
{
- target_ulong x = rs1;
- int i, shift;
+ target_ulong result = 0;
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
- if (rs2 & shift) {
- x |= do_swap(x, adjacent_masks[i], shift);
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
+ if ((rs2 >> i) & 1) {
+ result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
}
}
- return x;
-}
-
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-{
- return do_gorc(rs1, rs2, 32);
+ return result;
}
env->priv_ver = priv_ver;
}
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
- env->bext_ver = bext_ver;
-}
-
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
- if (cpu->cfg.ext_b) {
- int bext_version = BEXT_VERSION_0_93_0;
- target_misa |= RVB;
-
- if (cpu->cfg.bext_spec) {
- if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
- bext_version = BEXT_VERSION_0_93_0;
- } else {
- error_setg(errp,
- "Unsupported bitmanip spec version '%s'",
- cpu->cfg.bext_spec);
- return;
- }
- } else {
- qemu_log("bitmanip version is not specified, "
- "use the default value v0.93\n");
- }
- set_bext_version(env, bext_version);
- }
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+ DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+ DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+ DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+ DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
-#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define BEXT_VERSION_0_93_0 0x00009300
#define VEXT_VERSION_0_07_1 0x00000701
enum {
bool ext_f;
bool ext_d;
bool ext_c;
- bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_v;
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbs;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
bool riscv_cpu_is_32bit(CPURISCVState *env);
get_field(env->hstatus, HSTATUS_HU))) {
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
+
+ flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+ get_field(env->mstatus_hs, MSTATUS_FS));
}
#endif
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-# *** RV32B Standard Extension ***
-clz 011000 000000 ..... 001 ..... 0010011 @r2
-ctz 011000 000001 ..... 001 ..... 0010011 @r2
-cpop 011000 000010 ..... 001 ..... 0010011 @r2
-sext_b 011000 000100 ..... 001 ..... 0010011 @r2
-sext_h 011000 000101 ..... 001 ..... 0010011 @r2
+# *** RV32 Zba Standard Extension ***
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
+# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
+add_uw 0000100 .......... 000 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
+slli_uw 00001 ............ 001 ..... 0011011 @sh
+
+# *** RV32 Zbb Standard Extension ***
andn 0100000 .......... 111 ..... 0110011 @r
-orn 0100000 .......... 110 ..... 0110011 @r
-xnor 0100000 .......... 100 ..... 0110011 @r
-pack 0000100 .......... 100 ..... 0110011 @r
-packu 0100100 .......... 100 ..... 0110011 @r
-packh 0000100 .......... 111 ..... 0110011 @r
-min 0000101 .......... 100 ..... 0110011 @r
-minu 0000101 .......... 101 ..... 0110011 @r
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+cpop 011000 000010 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
-bset 0010100 .......... 001 ..... 0110011 @r
-bclr 0100100 .......... 001 ..... 0110011 @r
-binv 0110100 .......... 001 ..... 0110011 @r
-bext 0100100 .......... 101 ..... 0110011 @r
-slo 0010000 .......... 001 ..... 0110011 @r
-sro 0010000 .......... 101 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+orc_b 001010 000111 ..... 101 ..... 0010011 @r2
+orn 0100000 .......... 110 ..... 0110011 @r
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
rol 0110000 .......... 001 ..... 0110011 @r
-grev 0110100 .......... 101 ..... 0110011 @r
-gorc 0010100 .......... 101 ..... 0110011 @r
-sh1add 0010000 .......... 010 ..... 0110011 @r
-sh2add 0010000 .......... 100 ..... 0110011 @r
-sh3add 0010000 .......... 110 ..... 0110011 @r
-
-bseti 00101. ........... 001 ..... 0010011 @sh
-bclri 01001. ........... 001 ..... 0010011 @sh
-binvi 01101. ........... 001 ..... 0010011 @sh
-bexti 01001. ........... 101 ..... 0010011 @sh
-sloi 00100. ........... 001 ..... 0010011 @sh
-sroi 00100. ........... 101 ..... 0010011 @sh
-rori 01100. ........... 101 ..... 0010011 @sh
-grevi 01101. ........... 101 ..... 0010011 @sh
-gorci 00101. ........... 101 ..... 0010011 @sh
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
+xnor 0100000 .......... 100 ..... 0110011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
-# *** RV64B Standard Extension (in addition to RV32B) ***
+# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-
-packw 0000100 .......... 100 ..... 0111011 @r
-packuw 0100100 .......... 100 ..... 0111011 @r
-bsetw 0010100 .......... 001 ..... 0111011 @r
-bclrw 0100100 .......... 001 ..... 0111011 @r
-binvw 0110100 .......... 001 ..... 0111011 @r
-bextw 0100100 .......... 101 ..... 0111011 @r
-slow 0010000 .......... 001 ..... 0111011 @r
-srow 0010000 .......... 101 ..... 0111011 @r
-rorw 0110000 .......... 101 ..... 0111011 @r
+# The encoding for rev8 differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
rolw 0110000 .......... 001 ..... 0111011 @r
-grevw 0110100 .......... 101 ..... 0111011 @r
-gorcw 0010100 .......... 101 ..... 0111011 @r
-sh1add_uw 0010000 .......... 010 ..... 0111011 @r
-sh2add_uw 0010000 .......... 100 ..... 0111011 @r
-sh3add_uw 0010000 .......... 110 ..... 0111011 @r
-add_uw 0000100 .......... 000 ..... 0111011 @r
-
-bsetiw 0010100 .......... 001 ..... 0011011 @sh5
-bclriw 0100100 .......... 001 ..... 0011011 @sh5
-binviw 0110100 .......... 001 ..... 0011011 @sh5
-sloiw 0010000 .......... 001 ..... 0011011 @sh5
-sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
-greviw 0110100 .......... 101 ..... 0011011 @sh5
-gorciw 0010100 .......... 101 ..... 0011011 @sh5
+rorw 0110000 .......... 101 ..... 0111011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+
+# *** RV32 Zbc Standard Extension ***
+clmul 0000101 .......... 001 ..... 0110011 @r
+clmulh 0000101 .......... 011 ..... 0110011 @r
+clmulr 0000101 .......... 010 ..... 0110011 @r
-slli_uw 00001. ........... 001 ..... 0011011 @sh
+# *** RV32 Zbs Standard Extension ***
+bclr 0100100 .......... 001 ..... 0110011 @r
+bclri 01001. ........... 001 ..... 0010011 @sh
+bext 0100100 .......... 101 ..... 0110011 @r
+bexti 01001. ........... 101 ..... 0010011 @sh
+binv 0110100 .......... 001 ..... 0110011 @r
+binvi 01101. ........... 001 ..... 0010011 @sh
+bset 0010100 .......... 001 ..... 0110011 @r
+bseti 00101. ........... 001 ..... 0010011 @sh
/*
- * RISC-V translation routines for the RVB Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_ZBA(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZBB(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZBC(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZBS(ctx) do { \
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
+ return false; \
+ } \
+} while (0)
static void gen_clz(TCGv ret, TCGv arg1)
{
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, gen_clz);
}
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_deposit_tl(ret, arg1, arg2,
- TARGET_LONG_BITS / 2,
- TARGET_LONG_BITS / 2);
-}
-
-static bool trans_pack(DisasContext *ctx, arg_pack *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
-}
-
-static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
- tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
- tcg_temp_free(t);
-}
-
-static bool trans_packu(DisasContext *ctx, arg_packu *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
-}
-
-static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext8u_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
- tcg_temp_free(t);
-}
-
-static bool trans_packh(DisasContext *ctx, arg_packh *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
-}
-
static bool trans_min(DisasContext *ctx, arg_min *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
}
static bool trans_max(DisasContext *ctx, arg_max *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
}
static bool trans_minu(DisasContext *ctx, arg_minu *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
}
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
}
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
static bool trans_bset(DisasContext *ctx, arg_bset *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bset);
}
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
}
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bclr);
}
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
}
static bool trans_binv(DisasContext *ctx, arg_binv *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_binv);
}
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
}
static bool trans_bext(DisasContext *ctx, arg_bext *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift(ctx, a, EXT_NONE, gen_bext);
}
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBS(ctx);
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shl_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_slo(DisasContext *ctx, arg_slo *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shr_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_sro(DisasContext *ctx, arg_sro *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
-static bool trans_grev(DisasContext *ctx, arg_grev *a)
+static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
-static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
+static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
- if (shamt == TARGET_LONG_BITS - 8) {
- /* rev8, byte swaps */
- tcg_gen_bswap_tl(dest, src);
- } else {
- gen_helper_grev(dest, src, tcg_constant_tl(shamt));
- }
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
-static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+static void gen_orc_b(TCGv ret, TCGv source1)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
-}
+ TCGv tmp = tcg_temp_new();
+ TCGv ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ /* Set lsb in each byte if the byte was zero. */
+ tcg_gen_sub_tl(tmp, source1, ones);
+ tcg_gen_andc_tl(tmp, tmp, source1);
+ tcg_gen_shri_tl(tmp, tmp, 7);
+ tcg_gen_andc_tl(tmp, ones, tmp);
+
+ /* Replicate the lsb of each byte across the byte. */
+ tcg_gen_muli_tl(ret, tmp, 0xff);
+
+ tcg_temp_free(tmp);
}
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
}
#define GEN_SHADD(SHAMT) \
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
}
GEN_TRANS_SHADD(2)
GEN_TRANS_SHADD(3)
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
- tcg_gen_clzi_tl(ret, ret, 64);
- tcg_gen_subi_tl(ret, ret, 32);
-}
-
-static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
-}
-
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
- tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
- tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
-static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
-}
-
-static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext16s_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
- tcg_temp_free(t);
-}
-
-static bool trans_packw(DisasContext *ctx, arg_packw *a)
+static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+static void gen_clzw(TCGv ret, TCGv arg1)
{
TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, 16);
- tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
- tcg_gen_ext32s_tl(ret, ret);
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
tcg_temp_free(t);
}
-static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
-}
-
-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
-}
-
-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
-}
-
-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
-}
-
-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
-}
-
-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
-}
-
-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
-}
-
-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
-}
-
-static bool trans_slow(DisasContext *ctx, arg_slow *a)
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_clzw);
}
-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+static void gen_ctzw(TCGv ret, TCGv arg1)
{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
+ tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_tl(ret, ret, 64);
}
-static bool trans_srow(DisasContext *ctx, arg_srow *a)
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
}
-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
+ return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE, gen_rorw);
}
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
}
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBB(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
}
-static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
-static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
#define GEN_SHADD_UW(SHAMT) \
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
arg_sh##SHAMT##add_uw *a) \
{ \
REQUIRE_64BIT(ctx); \
- REQUIRE_EXT(ctx, RVB); \
+ REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
}
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
{
- tcg_gen_ext32u_tl(arg1, arg1);
- tcg_gen_add_tl(ret, arg1, arg2);
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext32u_tl(t, arg1);
+ tcg_gen_add_tl(ret, t, arg2);
+ tcg_temp_free(t);
}
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
}
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
+ REQUIRE_ZBA(ctx);
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
+
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
+}
+
+static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_clmulr(dst, src1, src2);
+ tcg_gen_shri_tl(dst, dst, 1);
+}
+
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
+}
+
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
+{
+ REQUIRE_ZBC(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
+}
target_ulong misa;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t mstatus_hs_fs;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
- target_ulong sd;
+ target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
- if (ctx->mstatus_fs == MSTATUS_FS) {
- return;
- }
- /* Remember the state change for the rest of the TB. */
- ctx->mstatus_fs = MSTATUS_FS;
+ if (ctx->mstatus_fs != MSTATUS_FS) {
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_fs = MSTATUS_FS;
- tmp = tcg_temp_new();
- sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_temp_free(tmp);
+ }
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
+ /* Remember the stage change for the rest of the TB. */
+ ctx->mstatus_hs_fs = MSTATUS_FS;
- if (ctx->virt_enabled) {
+ tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_temp_free(tmp);
}
- tcg_temp_free(tmp);
}
#else
static inline void mark_fs_dirty(DisasContext *ctx) { }
} \
} while (0)
+#define REQUIRE_32BIT(ctx) do { \
+ if (!is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_64BIT(ctx) do { \
if (is_32bit(ctx)) { \
return false; \
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
+ ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
g_assert(haddr);
memset(haddr, byte, size);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
int i;
if (likely(haddr)) {
#ifdef CONFIG_USER_ONLY
return ldub_p(*haddr + offset);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
uint8_t byte;
if (likely(*haddr)) {
#ifdef CONFIG_USER_ONLY
stb_p(*haddr + offset, byte);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
if (likely(*haddr)) {
stb_p(*haddr + offset, byte);
Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 oldv;
bool fail;
uint32_t *haddr = g2h(env_cpu(env), a1);
ov = qatomic_cmpxchg__nocheck(haddr, cv, nv);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
ov = cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
#endif
} else {
if (parallel) {
#ifdef CONFIG_ATOMIC64
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
ov = cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
#else
/* Note that we asserted !parallel above. */
cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
} else if (HAVE_CMPXCHG128) {
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
cc = !int128_eq(ov, cv);
} else {
cpu_stq_data_ra(env, a2 + 0, svh, ra);
cpu_stq_data_ra(env, a2 + 8, svl, ra);
} else if (HAVE_ATOMIC128) {
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
Int128 sv = int128_make128(svl, svh);
cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra);
} else {
uintptr_t ra = GETPC();
uint64_t hi, lo;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 v;
assert(HAVE_ATOMIC128);
{
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 v;
assert(HAVE_ATOMIC128);
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
- switch (memop) {
+ switch ((unsigned)memop) {
case ES_8:
tcg_gen_ld8u_i64(dst, cpu_env, offs);
break;
case ASI_SNF:
case ASI_SNFL:
{
- TCGMemOpIdx oi;
+ MemOpIdx oi;
int idx = (env->pstate & PS_PRIV
? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
: (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
--- /dev/null
+core-dc232b.c
+core-dc233c.c
+core-de212.c
+core-de233_fpu.c
+core-dsp3400.c
+core-fsf.c
+core-sample_controller.c
+core-test_kc705_be.c
+core-test_mmuhifi_c3.c
REGISTER_CORE($NAME)
EOF
+
+grep -qxf core-${NAME}.c "$BASE"/cores.list || \
+ echo core-${NAME}.c >> "$BASE"/cores.list
xtensa_ss = ss.source_set()
-xtensa_cores = run_command('sh', '-c', 'cd $MESON_SOURCE_ROOT/$MESON_SUBDIR ; ls -1 core-*.c')
-xtensa_ss.add(files(xtensa_cores.stdout().strip().split('\n')))
+xtensa_cores = fs.read('cores.list')
+xtensa_ss.add(files(xtensa_cores.strip().split('\n')))
xtensa_ss.add(files(
'cpu.c',
#include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
+ * MemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[4] = {
+static void * const qemu_ld_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_ldub_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_lduw_mmu,
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
+ * uintxx_t val, MemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
return true;
}
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGType ext, TCGReg data_reg, TCGReg addr_reg,
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
{
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi, TCGType ext)
+ MemOpIdx oi, TCGType ext)
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[8] = {
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGReg datalo, TCGReg datahi, TCGReg addrlo,
TCGReg addrhi, tcg_insn_unit *raddr,
tcg_insn_unit *label_ptr)
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
void *func;
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
* for a load or store, so that we can later generate the correct helper code
*/
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
- TCGMemOpIdx oi,
+ MemOpIdx oi,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
tcg_insn_unit *raddr,
*/
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg data_reg;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
*/
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
#if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.c.inc"
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
#endif
};
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
* Clobbers TMP0, TMP1, TMP2, TMP3.
*/
static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
+ TCGReg addrh, MemOpIdx oi,
tcg_insn_unit *label_ptr[2], bool is_load)
{
MemOp opc = get_memop(oi);
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
}
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
TCGType ext,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg v0;
int i;
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
int i;
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
CASE_OP_32_64(qemu_ld):
{
- TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
+ MemOpIdx oi = op->args[nb_oargs + nb_iargs];
MemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
#endif
}
-static const uint32_t qemu_ldx_opc[16] = {
+static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
[MO_UB] = LBZX,
[MO_UW] = LHZX,
[MO_UL] = LWZX,
[MO_BSWAP | MO_Q] = LDBRX,
};
-static const uint32_t qemu_stx_opc[16] = {
+static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
[MO_UB] = STBX,
[MO_UW] = STHX,
[MO_UL] = STWX,
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGReg datalo_reg, TCGReg datahi_reg,
TCGReg addrlo_reg, TCGReg addrhi_reg,
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
TCGReg hi, lo, arg = TCG_REG_R3;
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
TCGReg hi, lo, arg = TCG_REG_R3;
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
#include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
+ * MemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[8] = {
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
+ * uintxx_t val, MemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
}
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
+ TCGReg addrh, MemOpIdx oi,
tcg_insn_unit **label_ptr, bool is_load)
{
MemOp opc = get_memop(oi);
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
}
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
TCGType ext,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg a0 = tcg_target_call_iarg_regs[0];
TCGReg a1 = tcg_target_call_iarg_regs[1];
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
TCGReg a0 = tcg_target_call_iarg_regs[0];
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
+++ /dev/null
-/* SPDX-License-Identifier: MIT */
-/*
- * Define S390 target-specific constraint sets.
- * Copyright (c) 2021 Linaro
- */
-
-/*
- * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
- * Each operand should be a sequence of constraint letters as defined by
- * tcg-target-con-str.h; the constraint combination is inclusive or.
- */
-C_O0_I1(r)
-C_O0_I2(L, L)
-C_O0_I2(r, r)
-C_O0_I2(r, ri)
-C_O1_I1(r, L)
-C_O1_I1(r, r)
-C_O1_I2(r, 0, ri)
-C_O1_I2(r, 0, rI)
-C_O1_I2(r, 0, rJ)
-C_O1_I2(r, r, ri)
-C_O1_I2(r, rZ, r)
-C_O1_I4(r, r, ri, r, 0)
-C_O1_I4(r, r, ri, rI, 0)
-C_O2_I2(b, a, 0, r)
-C_O2_I3(b, a, 0, 1, r)
-C_O2_I4(r, r, 0, 1, rA, r)
-C_O2_I4(r, r, 0, 1, ri, r)
-C_O2_I4(r, r, 0, 1, r, r)
+++ /dev/null
-/* SPDX-License-Identifier: MIT */
-/*
- * Define S390 target-specific operand constraints.
- * Copyright (c) 2021 Linaro
- */
-
-/*
- * Define constraint letters for register sets:
- * REGS(letter, register_mask)
- */
-REGS('r', ALL_GENERAL_REGS)
-REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
-/*
- * A (single) even/odd pair for division.
- * TODO: Add something to the register allocator to allow
- * this kind of regno+1 pairing to be done more generally.
- */
-REGS('a', 1u << TCG_REG_R2)
-REGS('b', 1u << TCG_REG_R3)
-
-/*
- * Define constraint letters for constants:
- * CONST(letter, TCG_CT_CONST_* bit set)
- */
-CONST('A', TCG_CT_CONST_S33)
-CONST('I', TCG_CT_CONST_S16)
-CONST('J', TCG_CT_CONST_S32)
-CONST('Z', TCG_CT_CONST_ZERO)
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
- * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
- * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/* We only support generating code for 64-bit mode. */
-#if TCG_TARGET_REG_BITS != 64
-#error "unsupported code generation mode"
-#endif
-
-#include "../tcg-pool.c.inc"
-#include "elf.h"
-
-/* ??? The translation blocks produced by TCG are generally small enough to
- be entirely reachable with a 16-bit displacement. Leaving the option for
- a 32-bit displacement here Just In Case. */
-#define USE_LONG_BRANCHES 0
-
-#define TCG_CT_CONST_S16 0x100
-#define TCG_CT_CONST_S32 0x200
-#define TCG_CT_CONST_S33 0x400
-#define TCG_CT_CONST_ZERO 0x800
-
-#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
-/*
- * For softmmu, we need to avoid conflicts with the first 3
- * argument registers to perform the tlb lookup, and to call
- * the helper function.
- */
-#ifdef CONFIG_SOFTMMU
-#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
-#else
-#define SOFTMMU_RESERVE_REGS 0
-#endif
-
-
-/* Several places within the instruction set 0 means "no register"
- rather than TCG_REG_R0. */
-#define TCG_REG_NONE 0
-
-/* A scratch register that may be be used throughout the backend. */
-#define TCG_TMP0 TCG_REG_R1
-
-/* A scratch register that holds a pointer to the beginning of the TB.
- We don't need this when we have pc-relative loads with the general
- instructions extension facility. */
-#define TCG_REG_TB TCG_REG_R12
-#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
-
-#ifndef CONFIG_SOFTMMU
-#define TCG_GUEST_BASE_REG TCG_REG_R13
-#endif
-
-/* All of the following instructions are prefixed with their instruction
- format, and are defined as 8- or 16-bit quantities, even when the two
- halves of the 16-bit quantity may appear 32 bits apart in the insn.
- This makes it easy to copy the values from the tables in Appendix B. */
-typedef enum S390Opcode {
- RIL_AFI = 0xc209,
- RIL_AGFI = 0xc208,
- RIL_ALFI = 0xc20b,
- RIL_ALGFI = 0xc20a,
- RIL_BRASL = 0xc005,
- RIL_BRCL = 0xc004,
- RIL_CFI = 0xc20d,
- RIL_CGFI = 0xc20c,
- RIL_CLFI = 0xc20f,
- RIL_CLGFI = 0xc20e,
- RIL_CLRL = 0xc60f,
- RIL_CLGRL = 0xc60a,
- RIL_CRL = 0xc60d,
- RIL_CGRL = 0xc608,
- RIL_IIHF = 0xc008,
- RIL_IILF = 0xc009,
- RIL_LARL = 0xc000,
- RIL_LGFI = 0xc001,
- RIL_LGRL = 0xc408,
- RIL_LLIHF = 0xc00e,
- RIL_LLILF = 0xc00f,
- RIL_LRL = 0xc40d,
- RIL_MSFI = 0xc201,
- RIL_MSGFI = 0xc200,
- RIL_NIHF = 0xc00a,
- RIL_NILF = 0xc00b,
- RIL_OIHF = 0xc00c,
- RIL_OILF = 0xc00d,
- RIL_SLFI = 0xc205,
- RIL_SLGFI = 0xc204,
- RIL_XIHF = 0xc006,
- RIL_XILF = 0xc007,
-
- RI_AGHI = 0xa70b,
- RI_AHI = 0xa70a,
- RI_BRC = 0xa704,
- RI_CHI = 0xa70e,
- RI_CGHI = 0xa70f,
- RI_IIHH = 0xa500,
- RI_IIHL = 0xa501,
- RI_IILH = 0xa502,
- RI_IILL = 0xa503,
- RI_LGHI = 0xa709,
- RI_LLIHH = 0xa50c,
- RI_LLIHL = 0xa50d,
- RI_LLILH = 0xa50e,
- RI_LLILL = 0xa50f,
- RI_MGHI = 0xa70d,
- RI_MHI = 0xa70c,
- RI_NIHH = 0xa504,
- RI_NIHL = 0xa505,
- RI_NILH = 0xa506,
- RI_NILL = 0xa507,
- RI_OIHH = 0xa508,
- RI_OIHL = 0xa509,
- RI_OILH = 0xa50a,
- RI_OILL = 0xa50b,
-
- RIE_CGIJ = 0xec7c,
- RIE_CGRJ = 0xec64,
- RIE_CIJ = 0xec7e,
- RIE_CLGRJ = 0xec65,
- RIE_CLIJ = 0xec7f,
- RIE_CLGIJ = 0xec7d,
- RIE_CLRJ = 0xec77,
- RIE_CRJ = 0xec76,
- RIE_LOCGHI = 0xec46,
- RIE_RISBG = 0xec55,
-
- RRE_AGR = 0xb908,
- RRE_ALGR = 0xb90a,
- RRE_ALCR = 0xb998,
- RRE_ALCGR = 0xb988,
- RRE_CGR = 0xb920,
- RRE_CLGR = 0xb921,
- RRE_DLGR = 0xb987,
- RRE_DLR = 0xb997,
- RRE_DSGFR = 0xb91d,
- RRE_DSGR = 0xb90d,
- RRE_FLOGR = 0xb983,
- RRE_LGBR = 0xb906,
- RRE_LCGR = 0xb903,
- RRE_LGFR = 0xb914,
- RRE_LGHR = 0xb907,
- RRE_LGR = 0xb904,
- RRE_LLGCR = 0xb984,
- RRE_LLGFR = 0xb916,
- RRE_LLGHR = 0xb985,
- RRE_LRVR = 0xb91f,
- RRE_LRVGR = 0xb90f,
- RRE_LTGR = 0xb902,
- RRE_MLGR = 0xb986,
- RRE_MSGR = 0xb90c,
- RRE_MSR = 0xb252,
- RRE_NGR = 0xb980,
- RRE_OGR = 0xb981,
- RRE_SGR = 0xb909,
- RRE_SLGR = 0xb90b,
- RRE_SLBR = 0xb999,
- RRE_SLBGR = 0xb989,
- RRE_XGR = 0xb982,
-
- RRF_LOCR = 0xb9f2,
- RRF_LOCGR = 0xb9e2,
- RRF_NRK = 0xb9f4,
- RRF_NGRK = 0xb9e4,
- RRF_ORK = 0xb9f6,
- RRF_OGRK = 0xb9e6,
- RRF_SRK = 0xb9f9,
- RRF_SGRK = 0xb9e9,
- RRF_SLRK = 0xb9fb,
- RRF_SLGRK = 0xb9eb,
- RRF_XRK = 0xb9f7,
- RRF_XGRK = 0xb9e7,
-
- RR_AR = 0x1a,
- RR_ALR = 0x1e,
- RR_BASR = 0x0d,
- RR_BCR = 0x07,
- RR_CLR = 0x15,
- RR_CR = 0x19,
- RR_DR = 0x1d,
- RR_LCR = 0x13,
- RR_LR = 0x18,
- RR_LTR = 0x12,
- RR_NR = 0x14,
- RR_OR = 0x16,
- RR_SR = 0x1b,
- RR_SLR = 0x1f,
- RR_XR = 0x17,
-
- RSY_RLL = 0xeb1d,
- RSY_RLLG = 0xeb1c,
- RSY_SLLG = 0xeb0d,
- RSY_SLLK = 0xebdf,
- RSY_SRAG = 0xeb0a,
- RSY_SRAK = 0xebdc,
- RSY_SRLG = 0xeb0c,
- RSY_SRLK = 0xebde,
-
- RS_SLL = 0x89,
- RS_SRA = 0x8a,
- RS_SRL = 0x88,
-
- RXY_AG = 0xe308,
- RXY_AY = 0xe35a,
- RXY_CG = 0xe320,
- RXY_CLG = 0xe321,
- RXY_CLY = 0xe355,
- RXY_CY = 0xe359,
- RXY_LAY = 0xe371,
- RXY_LB = 0xe376,
- RXY_LG = 0xe304,
- RXY_LGB = 0xe377,
- RXY_LGF = 0xe314,
- RXY_LGH = 0xe315,
- RXY_LHY = 0xe378,
- RXY_LLGC = 0xe390,
- RXY_LLGF = 0xe316,
- RXY_LLGH = 0xe391,
- RXY_LMG = 0xeb04,
- RXY_LRV = 0xe31e,
- RXY_LRVG = 0xe30f,
- RXY_LRVH = 0xe31f,
- RXY_LY = 0xe358,
- RXY_NG = 0xe380,
- RXY_OG = 0xe381,
- RXY_STCY = 0xe372,
- RXY_STG = 0xe324,
- RXY_STHY = 0xe370,
- RXY_STMG = 0xeb24,
- RXY_STRV = 0xe33e,
- RXY_STRVG = 0xe32f,
- RXY_STRVH = 0xe33f,
- RXY_STY = 0xe350,
- RXY_XG = 0xe382,
-
- RX_A = 0x5a,
- RX_C = 0x59,
- RX_L = 0x58,
- RX_LA = 0x41,
- RX_LH = 0x48,
- RX_ST = 0x50,
- RX_STC = 0x42,
- RX_STH = 0x40,
-
- NOP = 0x0707,
-} S390Opcode;
-
-#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
- "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
-};
-#endif
-
-/* Since R6 is a potential argument register, choose it last of the
- call-saved registers. Likewise prefer the call-clobbered registers
- in reverse order to maximize the chance of avoiding the arguments. */
-static const int tcg_target_reg_alloc_order[] = {
- /* Call saved registers. */
- TCG_REG_R13,
- TCG_REG_R12,
- TCG_REG_R11,
- TCG_REG_R10,
- TCG_REG_R9,
- TCG_REG_R8,
- TCG_REG_R7,
- TCG_REG_R6,
- /* Call clobbered registers. */
- TCG_REG_R14,
- TCG_REG_R0,
- TCG_REG_R1,
- /* Argument registers, in reverse order of allocation. */
- TCG_REG_R5,
- TCG_REG_R4,
- TCG_REG_R3,
- TCG_REG_R2,
-};
-
-static const int tcg_target_call_iarg_regs[] = {
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
- TCG_REG_R6,
-};
-
-static const int tcg_target_call_oarg_regs[] = {
- TCG_REG_R2,
-};
-
-#define S390_CC_EQ 8
-#define S390_CC_LT 4
-#define S390_CC_GT 2
-#define S390_CC_OV 1
-#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
-#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
-#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
-#define S390_CC_NEVER 0
-#define S390_CC_ALWAYS 15
-
-/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
-static const uint8_t tcg_cond_to_s390_cond[] = {
- [TCG_COND_EQ] = S390_CC_EQ,
- [TCG_COND_NE] = S390_CC_NE,
- [TCG_COND_LT] = S390_CC_LT,
- [TCG_COND_LE] = S390_CC_LE,
- [TCG_COND_GT] = S390_CC_GT,
- [TCG_COND_GE] = S390_CC_GE,
- [TCG_COND_LTU] = S390_CC_LT,
- [TCG_COND_LEU] = S390_CC_LE,
- [TCG_COND_GTU] = S390_CC_GT,
- [TCG_COND_GEU] = S390_CC_GE,
-};
-
-/* Condition codes that result from a LOAD AND TEST. Here, we have no
- unsigned instruction variation, however since the test is vs zero we
- can re-map the outcomes appropriately. */
-static const uint8_t tcg_cond_to_ltr_cond[] = {
- [TCG_COND_EQ] = S390_CC_EQ,
- [TCG_COND_NE] = S390_CC_NE,
- [TCG_COND_LT] = S390_CC_LT,
- [TCG_COND_LE] = S390_CC_LE,
- [TCG_COND_GT] = S390_CC_GT,
- [TCG_COND_GE] = S390_CC_GE,
- [TCG_COND_LTU] = S390_CC_NEVER,
- [TCG_COND_LEU] = S390_CC_EQ,
- [TCG_COND_GTU] = S390_CC_NE,
- [TCG_COND_GEU] = S390_CC_ALWAYS,
-};
-
-#ifdef CONFIG_SOFTMMU
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LESL] = helper_le_ldsl_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BESL] = helper_be_ldsl_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
-};
-
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
-};
-#endif
-
-static const tcg_insn_unit *tb_ret_addr;
-uint64_t s390_facilities;
-
-static bool patch_reloc(tcg_insn_unit *src_rw, int type,
- intptr_t value, intptr_t addend)
-{
- const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
- intptr_t pcrel2;
- uint32_t old;
-
- value += addend;
- pcrel2 = (tcg_insn_unit *)value - src_rx;
-
- switch (type) {
- case R_390_PC16DBL:
- if (pcrel2 == (int16_t)pcrel2) {
- tcg_patch16(src_rw, pcrel2);
- return true;
- }
- break;
- case R_390_PC32DBL:
- if (pcrel2 == (int32_t)pcrel2) {
- tcg_patch32(src_rw, pcrel2);
- return true;
- }
- break;
- case R_390_20:
- if (value == sextract64(value, 0, 20)) {
- old = *(uint32_t *)src_rw & 0xf00000ff;
- old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
- tcg_patch32(src_rw, old);
- return true;
- }
- break;
- default:
- g_assert_not_reached();
- }
- return false;
-}
-
-/* Test if a constant matches the constraint. */
-static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-{
- if (ct & TCG_CT_CONST) {
- return 1;
- }
-
- if (type == TCG_TYPE_I32) {
- val = (int32_t)val;
- }
-
- /* The following are mutually exclusive. */
- if (ct & TCG_CT_CONST_S16) {
- return val == (int16_t)val;
- } else if (ct & TCG_CT_CONST_S32) {
- return val == (int32_t)val;
- } else if (ct & TCG_CT_CONST_S33) {
- return val >= -0xffffffffll && val <= 0xffffffffll;
- } else if (ct & TCG_CT_CONST_ZERO) {
- return val == 0;
- }
-
- return 0;
-}
-
-/* Emit instructions according to the given instruction format. */
-
-static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
-{
- tcg_out16(s, (op << 8) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
- TCGReg r1, TCGReg r2)
-{
- tcg_out32(s, (op << 16) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
- TCGReg r1, TCGReg r2, int m3)
-{
- tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
-}
-
-static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
-{
- tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
-}
-
-static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
- int i2, int m3)
-{
- tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
- tcg_out32(s, (i2 << 16) | (op & 0xff));
-}
-
-static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
-{
- tcg_out16(s, op | (r1 << 4));
- tcg_out32(s, i2);
-}
-
-static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
- TCGReg b2, TCGReg r3, int disp)
-{
- tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
- | (disp & 0xfff));
-}
-
-static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
- TCGReg b2, TCGReg r3, int disp)
-{
- tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
- tcg_out32(s, (op & 0xff) | (b2 << 28)
- | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
-}
-
-#define tcg_out_insn_RX tcg_out_insn_RS
-#define tcg_out_insn_RXY tcg_out_insn_RSY
-
-/* Emit an opcode with "type-checking" of the format. */
-#define tcg_out_insn(S, FMT, OP, ...) \
- glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
-
-
-/* emit 64-bit shifts */
-static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
- TCGReg src, TCGReg sh_reg, int sh_imm)
-{
- tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
-}
-
-/* emit 32-bit shifts */
-static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
- TCGReg sh_reg, int sh_imm)
-{
- tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
-}
-
-static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
-{
- if (src != dst) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, LR, dst, src);
- } else {
- tcg_out_insn(s, RRE, LGR, dst, src);
- }
- }
- return true;
-}
-
-static const S390Opcode lli_insns[4] = {
- RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
-};
-
-static bool maybe_out_small_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long sval)
-{
- tcg_target_ulong uval = sval;
- int i;
-
- if (type == TCG_TYPE_I32) {
- uval = (uint32_t)sval;
- sval = (int32_t)sval;
- }
-
- /* Try all 32-bit insns that can load it in one go. */
- if (sval >= -0x8000 && sval < 0x8000) {
- tcg_out_insn(s, RI, LGHI, ret, sval);
- return true;
- }
-
- for (i = 0; i < 4; i++) {
- tcg_target_long mask = 0xffffull << i*16;
- if ((uval & mask) == uval) {
- tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
- return true;
- }
- }
-
- return false;
-}
-
-/* load a register with an immediate value */
-static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long sval, bool in_prologue)
-{
- tcg_target_ulong uval;
-
- /* Try all 32-bit insns that can load it in one go. */
- if (maybe_out_small_movi(s, type, ret, sval)) {
- return;
- }
-
- uval = sval;
- if (type == TCG_TYPE_I32) {
- uval = (uint32_t)sval;
- sval = (int32_t)sval;
- }
-
- /* Try all 48-bit insns that can load it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (sval == (int32_t)sval) {
- tcg_out_insn(s, RIL, LGFI, ret, sval);
- return;
- }
- if (uval <= 0xffffffff) {
- tcg_out_insn(s, RIL, LLILF, ret, uval);
- return;
- }
- if ((uval & 0xffffffff) == 0) {
- tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
- return;
- }
- }
-
- /* Try for PC-relative address load. For odd addresses,
- attempt to use an offset from the start of the TB. */
- if ((sval & 1) == 0) {
- ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
- if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, LARL, ret, off);
- return;
- }
- } else if (USE_REG_TB && !in_prologue) {
- ptrdiff_t off = tcg_tbrel_diff(s, (void *)sval);
- if (off == sextract64(off, 0, 20)) {
- /* This is certain to be an address within TB, and therefore
- OFF will be negative; don't try RX_LA. */
- tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
- return;
- }
- }
-
- /* A 32-bit unsigned value can be loaded in 2 insns. And given
- that LLILL, LLIHL, LLILF above did not succeed, we know that
- both insns are required. */
- if (uval <= 0xffffffff) {
- tcg_out_insn(s, RI, LLILL, ret, uval);
- tcg_out_insn(s, RI, IILH, ret, uval >> 16);
- return;
- }
-
- /* Otherwise, stuff it in the constant pool. */
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
- tcg_out_insn(s, RIL, LGRL, ret, 0);
- new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
- } else if (USE_REG_TB && !in_prologue) {
- tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
- tcg_tbrel_diff(s, NULL));
- } else {
- TCGReg base = ret ? ret : TCG_TMP0;
- tcg_out_insn(s, RIL, LARL, base, 0);
- new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
- tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
- }
-}
-
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long sval)
-{
- tcg_out_movi_int(s, type, ret, sval, false);
-}
-
-/* Emit a load/store type instruction. Inputs are:
- DATA: The register to be loaded or stored.
- BASE+OFS: The effective address.
- OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
- OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
-
-static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
- TCGReg data, TCGReg base, TCGReg index,
- tcg_target_long ofs)
-{
- if (ofs < -0x80000 || ofs >= 0x80000) {
- /* Combine the low 20 bits of the offset with the actual load insn;
- the high 44 bits must come from an immediate load. */
- tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
- ofs = low;
-
- /* If we were already given an index register, add it in. */
- if (index != TCG_REG_NONE) {
- tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
- }
- index = TCG_TMP0;
- }
-
- if (opc_rx && ofs >= 0 && ofs < 0x1000) {
- tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
- } else {
- tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
- }
-}
-
-
-/* load data without address translation or endianness conversion */
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
- TCGReg base, intptr_t ofs)
-{
- if (type == TCG_TYPE_I32) {
- tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
- } else {
- tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
- }
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
- TCGReg base, intptr_t ofs)
-{
- if (type == TCG_TYPE_I32) {
- tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
- } else {
- tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
- }
-}
-
-static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- TCGReg base, intptr_t ofs)
-{
- return false;
-}
-
-/* load data from an absolute host address */
-static void tcg_out_ld_abs(TCGContext *s, TCGType type,
- TCGReg dest, const void *abs)
-{
- intptr_t addr = (intptr_t)abs;
-
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
- ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
- if (disp == (int32_t)disp) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RIL, LRL, dest, disp);
- } else {
- tcg_out_insn(s, RIL, LGRL, dest, disp);
- }
- return;
- }
- }
- if (USE_REG_TB) {
- ptrdiff_t disp = tcg_tbrel_diff(s, abs);
- if (disp == sextract64(disp, 0, 20)) {
- tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
- return;
- }
- }
-
- tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
- tcg_out_ld(s, type, dest, dest, addr & 0xffff);
-}
-
-static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
- int msb, int lsb, int ofs, int z)
-{
- /* Format RIE-f */
- tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
- tcg_out16(s, (msb << 8) | (z << 7) | lsb);
- tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
-}
-
-static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LGBR, dest, src);
- return;
- }
-
- if (type == TCG_TYPE_I32) {
- if (dest == src) {
- tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
- }
- tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
- tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
- }
-}
-
-static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LLGCR, dest, src);
- return;
- }
-
- if (dest == src) {
- tcg_out_movi(s, type, TCG_TMP0, 0xff);
- src = TCG_TMP0;
- } else {
- tcg_out_movi(s, type, dest, 0xff);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, src);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, src);
- }
-}
-
-static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LGHR, dest, src);
- return;
- }
-
- if (type == TCG_TYPE_I32) {
- if (dest == src) {
- tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
- }
- tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
- } else {
- tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
- tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
- }
-}
-
-static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
-{
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RRE, LLGHR, dest, src);
- return;
- }
-
- if (dest == src) {
- tcg_out_movi(s, type, TCG_TMP0, 0xffff);
- src = TCG_TMP0;
- } else {
- tcg_out_movi(s, type, dest, 0xffff);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, src);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, src);
- }
-}
-
-static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
-{
- tcg_out_insn(s, RRE, LGFR, dest, src);
-}
-
-static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
-{
- tcg_out_insn(s, RRE, LLGFR, dest, src);
-}
-
-/* Accept bit patterns like these:
- 0....01....1
- 1....10....0
- 1..10..01..1
- 0..01..10..0
- Copied from gcc sources. */
-static inline bool risbg_mask(uint64_t c)
-{
- uint64_t lsb;
- /* We don't change the number of transitions by inverting,
- so make sure we start with the LSB zero. */
- if (c & 1) {
- c = ~c;
- }
- /* Reject all zeros or all ones. */
- if (c == 0) {
- return false;
- }
- /* Find the first transition. */
- lsb = c & -c;
- /* Invert to look for a second transition. */
- c = ~c;
- /* Erase the first transition. */
- c &= -lsb;
- /* Find the second transition, if any. */
- lsb = c & -c;
- /* Match if all the bits are 1's, or if c is zero. */
- return c == -lsb;
-}
-
-static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
-{
- int msb, lsb;
- if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
- /* Achieve wraparound by swapping msb and lsb. */
- msb = 64 - ctz64(~val);
- lsb = clz64(~val) - 1;
- } else {
- msb = clz64(val);
- lsb = 63 - ctz64(val);
- }
- tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
-}
-
-static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- static const S390Opcode ni_insns[4] = {
- RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
- };
- static const S390Opcode nif_insns[2] = {
- RIL_NILF, RIL_NIHF
- };
- uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
- int i;
-
- /* Look for the zero-extensions. */
- if ((val & valid) == 0xffffffff) {
- tgen_ext32u(s, dest, dest);
- return;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- if ((val & valid) == 0xff) {
- tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
- return;
- }
- if ((val & valid) == 0xffff) {
- tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
- return;
- }
- }
-
- /* Try all 32-bit insns that can perform it in one go. */
- for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = ~(0xffffull << i*16);
- if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
- return;
- }
- }
-
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = ~(0xffffffffull << i*32);
- if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
- return;
- }
- }
- }
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
- tgen_andi_risbg(s, dest, dest, val);
- return;
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (USE_REG_TB) {
- if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
- tcg_tbrel_diff(s, NULL));
- return;
- }
- } else {
- tcg_out_movi(s, type, TCG_TMP0, val);
- }
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
- }
-}
-
-static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- static const S390Opcode oi_insns[4] = {
- RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
- };
- static const S390Opcode oif_insns[2] = {
- RIL_OILF, RIL_OIHF
- };
-
- int i;
-
- /* Look for no-op. */
- if (unlikely(val == 0)) {
- return;
- }
-
- /* Try all 32-bit insns that can perform it in one go. */
- for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = (0xffffull << i*16);
- if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
- return;
- }
- }
-
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = (0xffffffffull << i*32);
- if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
- return;
- }
- }
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
- }
- } else if (USE_REG_TB) {
- tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val, R_390_20, s->code_ptr - 2,
- tcg_tbrel_diff(s, NULL));
- } else {
- /* Perform the OR via sequential modifications to the high and
- low parts. Do this via recursion to handle 16-bit vs 32-bit
- masks in each half. */
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
- tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
- tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
- }
-}
-
-static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
-{
- /* Try all 48-bit insns that can perform it in one go. */
- if (s390_facilities & FACILITY_EXT_IMM) {
- if ((val & 0xffffffff00000000ull) == 0) {
- tcg_out_insn(s, RIL, XILF, dest, val);
- return;
- }
- if ((val & 0x00000000ffffffffull) == 0) {
- tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
- return;
- }
- }
-
- /* Use the constant pool if USE_REG_TB, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, XR, dest, TCG_TMP0);
- } else {
- tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
- }
- } else if (USE_REG_TB) {
- tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, val, R_390_20, s->code_ptr - 2,
- tcg_tbrel_diff(s, NULL));
- } else {
- /* Perform the xor by parts. */
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
- if (val & 0xffffffff) {
- tcg_out_insn(s, RIL, XILF, dest, val);
- }
- if (val > 0xffffffff) {
- tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
- }
- }
-}
-
-static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
- TCGArg c2, bool c2const, bool need_carry)
-{
- bool is_unsigned = is_unsigned_cond(c);
- S390Opcode op;
-
- if (c2const) {
- if (c2 == 0) {
- if (!(is_unsigned && need_carry)) {
- if (type == TCG_TYPE_I32) {
- tcg_out_insn(s, RR, LTR, r1, r1);
- } else {
- tcg_out_insn(s, RRE, LTGR, r1, r1);
- }
- return tcg_cond_to_ltr_cond[c];
- }
- }
-
- if (!is_unsigned && c2 == (int16_t)c2) {
- op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);
- tcg_out_insn_RI(s, op, r1, c2);
- goto exit;
- }
-
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RIL_CLFI : RIL_CFI);
- tcg_out_insn_RIL(s, op, r1, c2);
- goto exit;
- } else if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) {
- op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
- tcg_out_insn_RIL(s, op, r1, c2);
- goto exit;
- }
- }
-
- /* Use the constant pool, but not for small constants. */
- if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {
- c2 = TCG_TMP0;
- /* fall through to reg-reg */
- } else if (USE_REG_TB) {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RXY_CLY : RXY_CY);
- tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2,
- 4 - tcg_tbrel_diff(s, NULL));
- } else {
- op = (is_unsigned ? RXY_CLG : RXY_CG);
- tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
- new_pool_label(s, c2, R_390_20, s->code_ptr - 2,
- tcg_tbrel_diff(s, NULL));
- }
- goto exit;
- } else {
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RIL_CLRL : RIL_CRL);
- tcg_out_insn_RIL(s, op, r1, 0);
- new_pool_label(s, (uint32_t)c2, R_390_PC32DBL,
- s->code_ptr - 2, 2 + 4);
- } else {
- op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);
- tcg_out_insn_RIL(s, op, r1, 0);
- new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);
- }
- goto exit;
- }
- }
-
- if (type == TCG_TYPE_I32) {
- op = (is_unsigned ? RR_CLR : RR_CR);
- tcg_out_insn_RR(s, op, r1, c2);
- } else {
- op = (is_unsigned ? RRE_CLGR : RRE_CGR);
- tcg_out_insn_RRE(s, op, r1, c2);
- }
-
- exit:
- return tcg_cond_to_s390_cond[c];
-}
-
-static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
- TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
-{
- int cc;
- bool have_loc;
-
- /* With LOC2, we can always emit the minimum 3 insns. */
- if (s390_facilities & FACILITY_LOAD_ON_COND2) {
- /* Emit: d = 0, d = (cc ? 1 : d). */
- cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
- tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
- return;
- }
-
- have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
-
- /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
- restart:
- switch (cond) {
- case TCG_COND_NE:
- /* X != 0 is X > 0. */
- if (c2const && c2 == 0) {
- cond = TCG_COND_GTU;
- } else {
- break;
- }
- /* fallthru */
-
- case TCG_COND_GTU:
- case TCG_COND_GT:
- /* The result of a compare has CC=2 for GT and CC=3 unused.
- ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
- tgen_cmp(s, type, cond, c1, c2, c2const, true);
- tcg_out_movi(s, type, dest, 0);
- tcg_out_insn(s, RRE, ALCGR, dest, dest);
- return;
-
- case TCG_COND_EQ:
- /* X == 0 is X <= 0. */
- if (c2const && c2 == 0) {
- cond = TCG_COND_LEU;
- } else {
- break;
- }
- /* fallthru */
-
- case TCG_COND_LEU:
- case TCG_COND_LE:
- /* As above, but we're looking for borrow, or !carry.
- The second insn computes d - d - borrow, or -1 for true
- and 0 for false. So we must mask to 1 bit afterward. */
- tgen_cmp(s, type, cond, c1, c2, c2const, true);
- tcg_out_insn(s, RRE, SLBGR, dest, dest);
- tgen_andi(s, type, dest, 1);
- return;
-
- case TCG_COND_GEU:
- case TCG_COND_LTU:
- case TCG_COND_LT:
- case TCG_COND_GE:
- /* Swap operands so that we can use LEU/GTU/GT/LE. */
- if (c2const) {
- if (have_loc) {
- break;
- }
- tcg_out_movi(s, type, TCG_TMP0, c2);
- c2 = c1;
- c2const = 0;
- c1 = TCG_TMP0;
- } else {
- TCGReg t = c1;
- c1 = c2;
- c2 = t;
- }
- cond = tcg_swap_cond(cond);
- goto restart;
-
- default:
- g_assert_not_reached();
- }
-
- cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
- if (have_loc) {
- /* Emit: d = 0, t = 1, d = (cc ? t : d). */
- tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
- tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
- tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
- } else {
- /* Emit: d = 1; if (cc) goto over; d = 0; over: */
- tcg_out_movi(s, type, dest, 1);
- tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
- tcg_out_movi(s, type, dest, 0);
- }
-}
-
-static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
- TCGReg c1, TCGArg c2, int c2const,
- TCGArg v3, int v3const)
-{
- int cc;
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
- if (v3const) {
- tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
- } else {
- tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
- }
- } else {
- c = tcg_invert_cond(c);
- cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
-
- /* Emit: if (cc) goto over; dest = r3; over: */
- tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
- tcg_out_insn(s, RRE, LGR, dest, v3);
- }
-}
-
-static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
- TCGArg a2, int a2const)
-{
- /* Since this sets both R and R+1, we have no choice but to store the
- result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
- QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
- tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
-
- if (a2const && a2 == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
- } else {
- if (a2const) {
- tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
- } else {
- tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
- }
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
- /* Emit: if (one bit found) dest = r0. */
- tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
- } else {
- /* Emit: if (no one bit found) goto over; dest = r0; over: */
- tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
- tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
- }
- }
-}
-
-static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
- int ofs, int len, int z)
-{
- int lsb = (63 - ofs);
- int msb = lsb - (len - 1);
- tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
-}
-
-static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
- int ofs, int len)
-{
- tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
-}
-
-static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest)
-{
- ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
- if (off == (int16_t)off) {
- tcg_out_insn(s, RI, BRC, cc, off);
- } else if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, BRCL, cc, off);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
- tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
- }
-}
-
-static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
-{
- if (l->has_value) {
- tgen_gotoi(s, cc, l->u.value_ptr);
- } else if (USE_LONG_BRANCHES) {
- tcg_out16(s, RIL_BRCL | (cc << 4));
- tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2);
- s->code_ptr += 2;
- } else {
- tcg_out16(s, RI_BRC | (cc << 4));
- tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
- s->code_ptr += 1;
- }
-}
-
-static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
- TCGReg r1, TCGReg r2, TCGLabel *l)
-{
- tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
- tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
- tcg_out16(s, 0);
- tcg_out16(s, cc << 12 | (opc & 0xff));
-}
-
-static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
- TCGReg r1, int i2, TCGLabel *l)
-{
- tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
- tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
- tcg_out16(s, 0);
- tcg_out16(s, (i2 << 8) | (opc & 0xff));
-}
-
-static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
- TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
-{
- int cc;
-
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
- bool is_unsigned = is_unsigned_cond(c);
- bool in_range;
- S390Opcode opc;
-
- cc = tcg_cond_to_s390_cond[c];
-
- if (!c2const) {
- opc = (type == TCG_TYPE_I32
- ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
- : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
- tgen_compare_branch(s, opc, cc, r1, c2, l);
- return;
- }
-
- /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
- If the immediate we've been given does not fit that range, we'll
- fall back to separate compare and branch instructions using the
- larger comparison range afforded by COMPARE IMMEDIATE. */
- if (type == TCG_TYPE_I32) {
- if (is_unsigned) {
- opc = RIE_CLIJ;
- in_range = (uint32_t)c2 == (uint8_t)c2;
- } else {
- opc = RIE_CIJ;
- in_range = (int32_t)c2 == (int8_t)c2;
- }
- } else {
- if (is_unsigned) {
- opc = RIE_CLGIJ;
- in_range = (uint64_t)c2 == (uint8_t)c2;
- } else {
- opc = RIE_CGIJ;
- in_range = (int64_t)c2 == (int8_t)c2;
- }
- }
- if (in_range) {
- tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
- return;
- }
- }
-
- cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
- tgen_branch(s, cc, l);
-}
-
-static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest)
-{
- ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
- if (off == (int32_t)off) {
- tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
- tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
- }
-}
-
-static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
- TCGReg base, TCGReg index, int disp)
-{
- switch (opc & (MO_SSIZE | MO_BSWAP)) {
- case MO_UB:
- tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
- break;
- case MO_SB:
- tcg_out_insn(s, RXY, LGB, data, base, index, disp);
- break;
-
- case MO_UW | MO_BSWAP:
- /* swapped unsigned halfword load with upper bits zeroed */
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
- tgen_ext16u(s, TCG_TYPE_I64, data, data);
- break;
- case MO_UW:
- tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
- break;
-
- case MO_SW | MO_BSWAP:
- /* swapped sign-extended halfword load */
- tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
- tgen_ext16s(s, TCG_TYPE_I64, data, data);
- break;
- case MO_SW:
- tcg_out_insn(s, RXY, LGH, data, base, index, disp);
- break;
-
- case MO_UL | MO_BSWAP:
- /* swapped unsigned int load with upper bits zeroed */
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
- tgen_ext32u(s, data, data);
- break;
- case MO_UL:
- tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
- break;
-
- case MO_SL | MO_BSWAP:
- /* swapped sign-extended int load */
- tcg_out_insn(s, RXY, LRV, data, base, index, disp);
- tgen_ext32s(s, data, data);
- break;
- case MO_SL:
- tcg_out_insn(s, RXY, LGF, data, base, index, disp);
- break;
-
- case MO_Q | MO_BSWAP:
- tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
- break;
- case MO_Q:
- tcg_out_insn(s, RXY, LG, data, base, index, disp);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
- TCGReg base, TCGReg index, int disp)
-{
- switch (opc & (MO_SIZE | MO_BSWAP)) {
- case MO_UB:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, STC, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STCY, data, base, index, disp);
- }
- break;
-
- case MO_UW | MO_BSWAP:
- tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
- break;
- case MO_UW:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, STH, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STHY, data, base, index, disp);
- }
- break;
-
- case MO_UL | MO_BSWAP:
- tcg_out_insn(s, RXY, STRV, data, base, index, disp);
- break;
- case MO_UL:
- if (disp >= 0 && disp < 0x1000) {
- tcg_out_insn(s, RX, ST, data, base, index, disp);
- } else {
- tcg_out_insn(s, RXY, STY, data, base, index, disp);
- }
- break;
-
- case MO_Q | MO_BSWAP:
- tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
- break;
- case MO_Q:
- tcg_out_insn(s, RXY, STG, data, base, index, disp);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.c.inc"
-
-/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
-QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
-
-/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
- addend into R2. Returns a register with the santitized guest address. */
-static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
- int mem_index, bool is_ld)
-{
- unsigned s_bits = opc & MO_SIZE;
- unsigned a_bits = get_alignment_bits(opc);
- unsigned s_mask = (1 << s_bits) - 1;
- unsigned a_mask = (1 << a_bits) - 1;
- int fast_off = TLB_MASK_TABLE_OFS(mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- int ofs, a_off;
- uint64_t tlb_mask;
-
- tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off);
- tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off);
-
- /* For aligned accesses, we check the first byte and include the alignment
- bits within the address. For unaligned access, we check that we don't
- cross pages using the address of the last byte of the access. */
- a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
- tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) {
- tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
- } else {
- tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
- tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
- }
-
- if (is_ld) {
- ofs = offsetof(CPUTLBEntry, addr_read);
- } else {
- ofs = offsetof(CPUTLBEntry, addr_write);
- }
- if (TARGET_LONG_BITS == 32) {
- tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
- } else {
- tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
- }
-
- tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE,
- offsetof(CPUTLBEntry, addend));
-
- if (TARGET_LONG_BITS == 32) {
- tgen_ext32u(s, TCG_REG_R3, addr_reg);
- return TCG_REG_R3;
- }
- return addr_reg;
-}
-
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
- TCGReg data, TCGReg addr,
- tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
-{
- TCGLabelQemuLdst *label = new_ldst_label(s);
-
- label->is_ld = is_ld;
- label->oi = oi;
- label->datalo_reg = data;
- label->addrlo_reg = addr;
- label->raddr = tcg_splitwx_to_rx(raddr);
- label->label_ptr[0] = label_ptr;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg addr_reg = lb->addrlo_reg;
- TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
-
- if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
- (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
- }
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
- tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
-
- tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
- return true;
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
-{
- TCGReg addr_reg = lb->addrlo_reg;
- TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
-
- if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
- (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
- return false;
- }
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
- if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
- }
- switch (opc & MO_SIZE) {
- case MO_UB:
- tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- case MO_UW:
- tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- case MO_UL:
- tgen_ext32u(s, TCG_REG_R4, data_reg);
- break;
- case MO_Q:
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
- break;
- default:
- tcg_abort();
- }
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
- return true;
-}
-#else
-static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
- TCGReg *index_reg, tcg_target_long *disp)
-{
- if (TARGET_LONG_BITS == 32) {
- tgen_ext32u(s, TCG_TMP0, *addr_reg);
- *addr_reg = TCG_TMP0;
- }
- if (guest_base < 0x80000) {
- *index_reg = TCG_REG_NONE;
- *disp = guest_base;
- } else {
- *index_reg = TCG_GUEST_BASE_REG;
- *disp = 0;
- }
-}
-#endif /* CONFIG_SOFTMMU */
-
-static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
- TCGReg base_reg;
-
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
-
- tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
- label_ptr = s->code_ptr;
- s->code_ptr += 1;
-
- tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
- add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
-#else
- TCGReg index_reg;
- tcg_target_long disp;
-
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
- tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
-#endif
-}
-
-static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
-#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
- tcg_insn_unit *label_ptr;
- TCGReg base_reg;
-
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
-
- tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
- label_ptr = s->code_ptr;
- s->code_ptr += 1;
-
- tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
- add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
-#else
- TCGReg index_reg;
- tcg_target_long disp;
-
- tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
- tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
-#endif
-}
-
-# define OP_32_64(x) \
- case glue(glue(INDEX_op_,x),_i32): \
- case glue(glue(INDEX_op_,x),_i64)
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
-{
- S390Opcode op, op2;
- TCGArg a0, a1, a2;
-
- switch (opc) {
- case INDEX_op_exit_tb:
- /* Reuse the zeroing that exists for goto_ptr. */
- a0 = args[0];
- if (a0 == 0) {
- tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
- tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
- }
- break;
-
- case INDEX_op_goto_tb:
- a0 = args[0];
- if (s->tb_jmp_insn_offset) {
- /*
- * branch displacement must be aligned for atomic patching;
- * see if we need to add extra nop before branch
- */
- if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
- tcg_out16(s, NOP);
- }
- tcg_debug_assert(!USE_REG_TB);
- tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- s->code_ptr += 2;
- } else {
- /* load address stored at s->tb_jmp_target_addr + a0 */
- tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
- tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0));
- /* and go there */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
- }
- set_jmp_reset_offset(s, a0);
-
- /* For the unlinked path of goto_tb, we need to reset
- TCG_REG_TB to the beginning of this TB. */
- if (USE_REG_TB) {
- int ofs = -tcg_current_code_size(s);
- /* All TB are restricted to 64KiB by unwind info. */
- tcg_debug_assert(ofs == sextract64(ofs, 0, 20));
- tcg_out_insn(s, RXY, LAY, TCG_REG_TB,
- TCG_REG_TB, TCG_REG_NONE, ofs);
- }
- break;
-
- case INDEX_op_goto_ptr:
- a0 = args[0];
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
- }
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
- break;
-
- OP_32_64(ld8u):
- /* ??? LLC (RXY format) is only present with the extended-immediate
- facility, whereas LLGC is always present. */
- tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(ld8s):
- /* ??? LB is no smaller than LGB, so no point to using it. */
- tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(ld16u):
- /* ??? LLH (RXY format) is only present with the extended-immediate
- facility, whereas LLGH is always present. */
- tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_ld16s_i32:
- tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_ld_i32:
- tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
-
- OP_32_64(st8):
- tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- OP_32_64(st16):
- tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
- TCG_REG_NONE, args[2]);
- break;
-
- case INDEX_op_st_i32:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_add_i32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (const_args[2]) {
- do_addi_32:
- if (a0 == a1) {
- if (a2 == (int16_t)a2) {
- tcg_out_insn(s, RI, AHI, a0, a2);
- break;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- tcg_out_insn(s, RIL, AFI, a0, a2);
- break;
- }
- }
- tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, AR, a0, a2);
- } else {
- tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
- }
- break;
- case INDEX_op_sub_i32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (const_args[2]) {
- a2 = -a2;
- goto do_addi_32;
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, SR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, SRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_and_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_andi(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, NR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, NRK, a0, a1, a2);
- }
- break;
- case INDEX_op_or_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_ori(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, OR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, ORK, a0, a1, a2);
- }
- break;
- case INDEX_op_xor_i32:
- a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
- tgen_xori(s, TCG_TYPE_I32, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RR, XR, args[0], args[2]);
- } else {
- tcg_out_insn(s, RRF, XRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_neg_i32:
- tcg_out_insn(s, RR, LCR, args[0], args[1]);
- break;
-
- case INDEX_op_mul_i32:
- if (const_args[2]) {
- if ((int32_t)args[2] == (int16_t)args[2]) {
- tcg_out_insn(s, RI, MHI, args[0], args[2]);
- } else {
- tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
- }
- } else {
- tcg_out_insn(s, RRE, MSR, args[0], args[2]);
- }
- break;
-
- case INDEX_op_div2_i32:
- tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_divu2_i32:
- tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
- break;
-
- case INDEX_op_shl_i32:
- op = RS_SLL;
- op2 = RSY_SLLK;
- do_shift32:
- a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
- if (a0 == a1) {
- if (const_args[2]) {
- tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
- } else {
- tcg_out_sh32(s, op, a0, a2, 0);
- }
- } else {
- /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
- if (const_args[2]) {
- tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
- } else {
- tcg_out_sh64(s, op2, a0, a1, a2, 0);
- }
- }
- break;
- case INDEX_op_shr_i32:
- op = RS_SRL;
- op2 = RSY_SRLK;
- goto do_shift32;
- case INDEX_op_sar_i32:
- op = RS_SRA;
- op2 = RSY_SRAK;
- goto do_shift32;
-
- case INDEX_op_rotl_i32:
- /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_rotr_i32:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLL, args[0], args[1],
- TCG_REG_NONE, (32 - args[2]) & 31);
- } else {
- tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
- tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
- }
- break;
-
- case INDEX_op_ext8s_i32:
- tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i32:
- tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext8u_i32:
- tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i32:
- tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
- break;
-
- case INDEX_op_bswap16_i32:
- a0 = args[0], a1 = args[1], a2 = args[2];
- tcg_out_insn(s, RRE, LRVR, a0, a1);
- if (a2 & TCG_BSWAP_OS) {
- tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16);
- } else {
- tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16);
- }
- break;
- case INDEX_op_bswap16_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- tcg_out_insn(s, RRE, LRVGR, a0, a1);
- if (a2 & TCG_BSWAP_OS) {
- tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48);
- } else {
- tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48);
- }
- break;
-
- case INDEX_op_bswap32_i32:
- tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
- break;
- case INDEX_op_bswap32_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- tcg_out_insn(s, RRE, LRVR, a0, a1);
- if (a2 & TCG_BSWAP_OS) {
- tgen_ext32s(s, a0, a0);
- } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
- tgen_ext32u(s, a0, a0);
- }
- break;
-
- case INDEX_op_add2_i32:
- if (const_args[4]) {
- tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RR, ALR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
- break;
- case INDEX_op_sub2_i32:
- if (const_args[4]) {
- tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RR, SLR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
- break;
-
- case INDEX_op_br:
- tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
- break;
-
- case INDEX_op_brcond_i32:
- tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
- args[1], const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i32:
- tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_movcond_i32:
- tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
- args[2], const_args[2], args[3], const_args[3]);
- break;
-
- case INDEX_op_qemu_ld_i32:
- /* ??? Technically we can use a non-extending instruction. */
- case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args[0], args[1], args[2]);
- break;
- case INDEX_op_qemu_st_i32:
- case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_ld16s_i64:
- tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld32u_i64:
- tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld32s_i64:
- tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
- break;
- case INDEX_op_ld_i64:
- tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_st32_i64:
- tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_add_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- do_addi_64:
- if (a0 == a1) {
- if (a2 == (int16_t)a2) {
- tcg_out_insn(s, RI, AGHI, a0, a2);
- break;
- }
- if (s390_facilities & FACILITY_EXT_IMM) {
- if (a2 == (int32_t)a2) {
- tcg_out_insn(s, RIL, AGFI, a0, a2);
- break;
- } else if (a2 == (uint32_t)a2) {
- tcg_out_insn(s, RIL, ALGFI, a0, a2);
- break;
- } else if (-a2 == (uint32_t)-a2) {
- tcg_out_insn(s, RIL, SLGFI, a0, -a2);
- break;
- }
- }
- }
- tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, AGR, a0, a2);
- } else {
- tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
- }
- break;
- case INDEX_op_sub_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- a2 = -a2;
- goto do_addi_64;
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, SGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_and_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, NGR, args[0], args[2]);
- } else {
- tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
- }
- break;
- case INDEX_op_or_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_ori(s, TCG_TYPE_I64, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, OGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
- }
- break;
- case INDEX_op_xor_i64:
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[2]) {
- tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
- tgen_xori(s, TCG_TYPE_I64, a0, a2);
- } else if (a0 == a1) {
- tcg_out_insn(s, RRE, XGR, a0, a2);
- } else {
- tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
- }
- break;
-
- case INDEX_op_neg_i64:
- tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
- break;
- case INDEX_op_bswap64_i64:
- tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
- break;
-
- case INDEX_op_mul_i64:
- if (const_args[2]) {
- if (args[2] == (int16_t)args[2]) {
- tcg_out_insn(s, RI, MGHI, args[0], args[2]);
- } else {
- tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
- }
- } else {
- tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
- }
- break;
-
- case INDEX_op_div2_i64:
- /* ??? We get an unnecessary sign-extension of the dividend
- into R3 with this definition, but as we do in fact always
- produce both quotient and remainder using INDEX_op_div_i64
- instead requires jumping through even more hoops. */
- tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_divu2_i64:
- tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
- break;
- case INDEX_op_mulu2_i64:
- tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
- break;
-
- case INDEX_op_shl_i64:
- op = RSY_SLLG;
- do_shift64:
- if (const_args[2]) {
- tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_shr_i64:
- op = RSY_SRLG;
- goto do_shift64;
- case INDEX_op_sar_i64:
- op = RSY_SRAG;
- goto do_shift64;
-
- case INDEX_op_rotl_i64:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
- TCG_REG_NONE, args[2]);
- } else {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
- }
- break;
- case INDEX_op_rotr_i64:
- if (const_args[2]) {
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
- TCG_REG_NONE, (64 - args[2]) & 63);
- } else {
- /* We can use the smaller 32-bit negate because only the
- low 6 bits are examined for the rotate. */
- tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
- tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
- }
- break;
-
- case INDEX_op_ext8s_i64:
- tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i64:
- tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext_i32_i64:
- case INDEX_op_ext32s_i64:
- tgen_ext32s(s, args[0], args[1]);
- break;
- case INDEX_op_ext8u_i64:
- tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i64:
- tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_extu_i32_i64:
- case INDEX_op_ext32u_i64:
- tgen_ext32u(s, args[0], args[1]);
- break;
-
- case INDEX_op_add2_i64:
- if (const_args[4]) {
- if ((int64_t)args[4] >= 0) {
- tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
- }
- } else {
- tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
- break;
- case INDEX_op_sub2_i64:
- if (const_args[4]) {
- if ((int64_t)args[4] >= 0) {
- tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
- } else {
- tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
- }
- } else {
- tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
- }
- tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
- break;
-
- case INDEX_op_brcond_i64:
- tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
- args[1], const_args[1], arg_label(args[3]));
- break;
- case INDEX_op_setcond_i64:
- tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
- args[2], const_args[2]);
- break;
- case INDEX_op_movcond_i64:
- tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
- args[2], const_args[2], args[3], const_args[3]);
- break;
-
- OP_32_64(deposit):
- a0 = args[0], a1 = args[1], a2 = args[2];
- if (const_args[1]) {
- tgen_deposit(s, a0, a2, args[3], args[4], 1);
- } else {
- /* Since we can't support "0Z" as a constraint, we allow a1 in
- any register. Fix things up as if a matching constraint. */
- if (a0 != a1) {
- TCGType type = (opc == INDEX_op_deposit_i64);
- if (a0 == a2) {
- tcg_out_mov(s, type, TCG_TMP0, a2);
- a2 = TCG_TMP0;
- }
- tcg_out_mov(s, type, a0, a1);
- }
- tgen_deposit(s, a0, a2, args[3], args[4], 0);
- }
- break;
-
- OP_32_64(extract):
- tgen_extract(s, args[0], args[1], args[2], args[3]);
- break;
-
- case INDEX_op_clz_i64:
- tgen_clz(s, args[0], args[1], args[2], const_args[2]);
- break;
-
- case INDEX_op_mb:
- /* The host memory model is quite strong, we simply need to
- serialize the instruction stream. */
- if (args[0] & TCG_MO_ST_LD) {
- tcg_out_insn(s, RR, BCR,
- s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
- }
- break;
-
- case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_mov_i64:
- case INDEX_op_call: /* Always emitted via tcg_out_call. */
- default:
- tcg_abort();
- }
-}
-
-static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
-{
- switch (op) {
- case INDEX_op_goto_ptr:
- return C_O0_I1(r);
-
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- case INDEX_op_ld8s_i32:
- case INDEX_op_ld8s_i64:
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- case INDEX_op_ld16s_i32:
- case INDEX_op_ld16s_i64:
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- case INDEX_op_ld32s_i64:
- case INDEX_op_ld_i64:
- return C_O1_I1(r, r);
-
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
- return C_O0_I2(r, r);
-
- case INDEX_op_add_i32:
- case INDEX_op_add_i64:
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- case INDEX_op_clz_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return C_O1_I2(r, r, ri);
-
- case INDEX_op_sub_i32:
- case INDEX_op_sub_i64:
- case INDEX_op_and_i32:
- case INDEX_op_and_i64:
- case INDEX_op_or_i32:
- case INDEX_op_or_i64:
- case INDEX_op_xor_i32:
- case INDEX_op_xor_i64:
- return (s390_facilities & FACILITY_DISTINCT_OPS
- ? C_O1_I2(r, r, ri)
- : C_O1_I2(r, 0, ri));
-
- case INDEX_op_mul_i32:
- /* If we have the general-instruction-extensions, then we have
- MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
- have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
- return (s390_facilities & FACILITY_GEN_INST_EXT
- ? C_O1_I2(r, 0, ri)
- : C_O1_I2(r, 0, rI));
-
- case INDEX_op_mul_i64:
- return (s390_facilities & FACILITY_GEN_INST_EXT
- ? C_O1_I2(r, 0, rJ)
- : C_O1_I2(r, 0, rI));
-
- case INDEX_op_shl_i32:
- case INDEX_op_shr_i32:
- case INDEX_op_sar_i32:
- return (s390_facilities & FACILITY_DISTINCT_OPS
- ? C_O1_I2(r, r, ri)
- : C_O1_I2(r, 0, ri));
-
- case INDEX_op_brcond_i32:
- case INDEX_op_brcond_i64:
- return C_O0_I2(r, ri);
-
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap32_i64:
- case INDEX_op_bswap64_i64:
- case INDEX_op_neg_i32:
- case INDEX_op_neg_i64:
- case INDEX_op_ext8s_i32:
- case INDEX_op_ext8s_i64:
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- case INDEX_op_ext16s_i32:
- case INDEX_op_ext16s_i64:
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- case INDEX_op_ext32s_i64:
- case INDEX_op_ext32u_i64:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_extract_i32:
- case INDEX_op_extract_i64:
- return C_O1_I1(r, r);
-
- case INDEX_op_qemu_ld_i32:
- case INDEX_op_qemu_ld_i64:
- return C_O1_I1(r, L);
- case INDEX_op_qemu_st_i64:
- case INDEX_op_qemu_st_i32:
- return C_O0_I2(L, L);
-
- case INDEX_op_deposit_i32:
- case INDEX_op_deposit_i64:
- return C_O1_I2(r, rZ, r);
-
- case INDEX_op_movcond_i32:
- case INDEX_op_movcond_i64:
- return (s390_facilities & FACILITY_LOAD_ON_COND2
- ? C_O1_I4(r, r, ri, rI, 0)
- : C_O1_I4(r, r, ri, r, 0));
-
- case INDEX_op_div2_i32:
- case INDEX_op_div2_i64:
- case INDEX_op_divu2_i32:
- case INDEX_op_divu2_i64:
- return C_O2_I3(b, a, 0, 1, r);
-
- case INDEX_op_mulu2_i64:
- return C_O2_I2(b, a, 0, r);
-
- case INDEX_op_add2_i32:
- case INDEX_op_sub2_i32:
- return (s390_facilities & FACILITY_EXT_IMM
- ? C_O2_I4(r, r, 0, 1, ri, r)
- : C_O2_I4(r, r, 0, 1, r, r));
-
- case INDEX_op_add2_i64:
- case INDEX_op_sub2_i64:
- return (s390_facilities & FACILITY_EXT_IMM
- ? C_O2_I4(r, r, 0, 1, rA, r)
- : C_O2_I4(r, r, 0, 1, r, r));
-
- default:
- g_assert_not_reached();
- }
-}
-
-static void query_s390_facilities(void)
-{
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
-
- /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
- is present on all 64-bit systems, but let's check for it anyway. */
- if (hwcap & HWCAP_S390_STFLE) {
- register int r0 __asm__("0");
- register void *r1 __asm__("1");
-
- /* stfle 0(%r1) */
- r1 = &s390_facilities;
- asm volatile(".word 0xb2b0,0x1000"
- : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
- }
-}
-
-static void tcg_target_init(TCGContext *s)
-{
- query_s390_facilities();
-
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
-
- tcg_target_call_clobber_regs = 0;
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
- /* The r6 register is technically call-saved, but it's also a parameter
- register, so it can get killed by setup for the qemu_st helper. */
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
- /* The return register can be considered call-clobbered. */
- tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
-
- s->reserved_regs = 0;
- tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
- /* XXX many insns can't be used with R0, so we better avoid it for now */
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
- if (USE_REG_TB) {
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
- }
-}
-
-#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
- + TCG_STATIC_CALL_ARGS_SIZE \
- + CPU_TEMP_BUF_NLONGS * sizeof(long)))
-
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- /* stmg %r6,%r15,48(%r15) (save registers) */
- tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
-
- /* aghi %r15,-frame_size */
- tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
-
- tcg_set_frame(s, TCG_REG_CALL_STACK,
- TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
-
-#ifndef CONFIG_SOFTMMU
- if (guest_base >= 0x80000) {
- tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
- tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
- }
-#endif
-
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- if (USE_REG_TB) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,
- tcg_target_call_iarg_regs[1]);
- }
-
- /* br %r3 (go to TB) */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
-
- /*
- * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
- * and fall through to the rest of the epilogue.
- */
- tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
-
- /* TB epilogue */
- tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
-
- /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
- tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
- FRAME_SIZE + 48);
-
- /* br %r14 (return) */
- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
-}
-
-static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-{
- memset(p, 0x07, count * sizeof(tcg_insn_unit));
-}
-
-typedef struct {
- DebugFrameHeader h;
- uint8_t fde_def_cfa[4];
- uint8_t fde_reg_ofs[18];
-} DebugFrame;
-
-/* We're expecting a 2 byte uleb128 encoded value. */
-QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-
-#define ELF_HOST_MACHINE EM_S390
-
-static const DebugFrame debug_frame = {
- .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
- .h.cie.id = -1,
- .h.cie.version = 1,
- .h.cie.code_align = 1,
- .h.cie.data_align = 8, /* sleb128 8 */
- .h.cie.return_column = TCG_REG_R14,
-
- /* Total FDE size does not include the "len" member. */
- .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
-
- .fde_def_cfa = {
- 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
- (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
- (FRAME_SIZE >> 7)
- },
- .fde_reg_ofs = {
- 0x86, 6, /* DW_CFA_offset, %r6, 48 */
- 0x87, 7, /* DW_CFA_offset, %r7, 56 */
- 0x88, 8, /* DW_CFA_offset, %r8, 64 */
- 0x89, 9, /* DW_CFA_offset, %r92, 72 */
- 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
- 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
- 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
- 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
- 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
- }
-};
-
-void tcg_register_jit(const void *buf, size_t buf_size)
-{
- tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
-}
+++ /dev/null
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef S390_TCG_TARGET_H
-#define S390_TCG_TARGET_H
-
-#define TCG_TARGET_INSN_UNIT_SIZE 2
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
-
-/* We have a +- 4GB range on the branches; leave some slop. */
-#define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB)
-
-typedef enum TCGReg {
- TCG_REG_R0 = 0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
- TCG_REG_R4,
- TCG_REG_R5,
- TCG_REG_R6,
- TCG_REG_R7,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15
-} TCGReg;
-
-#define TCG_TARGET_NB_REGS 16
-
-/* A list of relevant facilities used by this translator. Some of these
- are required for proper operation, and these are checked at startup. */
-
-#define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2))
-#define FACILITY_LONG_DISP (1ULL << (63 - 18))
-#define FACILITY_EXT_IMM (1ULL << (63 - 21))
-#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
-#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
-#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
-#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
-#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53))
-
-extern uint64_t s390_facilities;
-
-/* optional instructions */
-#define TCG_TARGET_HAS_div2_i32 1
-#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_ext8s_i32 1
-#define TCG_TARGET_HAS_ext16s_i32 1
-#define TCG_TARGET_HAS_ext8u_i32 1
-#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_bswap16_i32 1
-#define TCG_TARGET_HAS_bswap32_i32 1
-#define TCG_TARGET_HAS_not_i32 0
-#define TCG_TARGET_HAS_neg_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_orc_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
-#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
-#define TCG_TARGET_HAS_ctpop_i32 0
-#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
-#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
-#define TCG_TARGET_HAS_sextract_i32 0
-#define TCG_TARGET_HAS_extract2_i32 0
-#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_add2_i32 1
-#define TCG_TARGET_HAS_sub2_i32 1
-#define TCG_TARGET_HAS_mulu2_i32 0
-#define TCG_TARGET_HAS_muls2_i32 0
-#define TCG_TARGET_HAS_muluh_i32 0
-#define TCG_TARGET_HAS_mulsh_i32 0
-#define TCG_TARGET_HAS_extrl_i64_i32 0
-#define TCG_TARGET_HAS_extrh_i64_i32 0
-#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT)
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
-#define TCG_TARGET_HAS_div2_i64 1
-#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_ext8s_i64 1
-#define TCG_TARGET_HAS_ext16s_i64 1
-#define TCG_TARGET_HAS_ext32s_i64 1
-#define TCG_TARGET_HAS_ext8u_i64 1
-#define TCG_TARGET_HAS_ext16u_i64 1
-#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_bswap16_i64 1
-#define TCG_TARGET_HAS_bswap32_i64 1
-#define TCG_TARGET_HAS_bswap64_i64 1
-#define TCG_TARGET_HAS_not_i64 0
-#define TCG_TARGET_HAS_neg_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
-#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM)
-#define TCG_TARGET_HAS_ctz_i64 0
-#define TCG_TARGET_HAS_ctpop_i64 0
-#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
-#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
-#define TCG_TARGET_HAS_sextract_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
-#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_add2_i64 1
-#define TCG_TARGET_HAS_sub2_i64 1
-#define TCG_TARGET_HAS_mulu2_i64 1
-#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
-
-/* used for function call generation */
-#define TCG_REG_CALL_STACK TCG_REG_R15
-#define TCG_TARGET_STACK_ALIGN 8
-#define TCG_TARGET_CALL_STACK_OFFSET 160
-
-#define TCG_TARGET_EXTEND_ARGS 1
-#define TCG_TARGET_HAS_MEMORY_BSWAP 1
-
-#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
-enum {
- TCG_AREG0 = TCG_REG_R10,
-};
-
-static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- uintptr_t jmp_rw, uintptr_t addr)
-{
- /* patch the branch destination */
- intptr_t disp = addr - (jmp_rx - 2);
- qatomic_set((int32_t *)jmp_rw, disp / 2);
- /* no need to flush icache explicitly */
-}
-
-#ifdef CONFIG_SOFTMMU
-#define TCG_TARGET_NEED_LDST_LABELS
-#endif
-#define TCG_TARGET_NEED_POOL_LABELS
-
-#endif
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(v, r)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I1(v, r)
+C_O1_I1(v, v)
+C_O1_I1(v, vr)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I2(v, v, r)
+C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define S390 target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+REGS('v', ALL_VECTOR_REGS)
+/*
+ * A (single) even/odd pair for division.
+ * TODO: Add something to the register allocator to allow
+ * this kind of regno+1 pairing to be done more generally.
+ */
+REGS('a', 1u << TCG_REG_R2)
+REGS('b', 1u << TCG_REG_R3)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('A', TCG_CT_CONST_S33)
+CONST('I', TCG_CT_CONST_S16)
+CONST('J', TCG_CT_CONST_S32)
+CONST('Z', TCG_CT_CONST_ZERO)
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
+ * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
+ * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* We only support generating code for 64-bit mode. */
+#if TCG_TARGET_REG_BITS != 64
+#error "unsupported code generation mode"
+#endif
+
+#include "../tcg-pool.c.inc"
+#include "elf.h"
+
+/* ??? The translation blocks produced by TCG are generally small enough to
+ be entirely reachable with a 16-bit displacement. Leaving the option for
+ a 32-bit displacement here Just In Case. */
+#define USE_LONG_BRANCHES 0
+
+#define TCG_CT_CONST_S16 0x100
+#define TCG_CT_CONST_S32 0x200
+#define TCG_CT_CONST_S33 0x400
+#define TCG_CT_CONST_ZERO 0x800
+
+#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
+#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
+
+/*
+ * For softmmu, we need to avoid conflicts with the first 3
+ * argument registers to perform the tlb lookup, and to call
+ * the helper function.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3)
+#else
+#define SOFTMMU_RESERVE_REGS 0
+#endif
+
+
+/* Several places within the instruction set 0 means "no register"
+ rather than TCG_REG_R0. */
+#define TCG_REG_NONE 0
+
+/* A scratch register that may be be used throughout the backend. */
+#define TCG_TMP0 TCG_REG_R1
+
+/* A scratch register that holds a pointer to the beginning of the TB.
+ We don't need this when we have pc-relative loads with the general
+ instructions extension facility. */
+#define TCG_REG_TB TCG_REG_R12
+#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT))
+
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_R13
+#endif
+
+/* All of the following instructions are prefixed with their instruction
+ format, and are defined as 8- or 16-bit quantities, even when the two
+ halves of the 16-bit quantity may appear 32 bits apart in the insn.
+ This makes it easy to copy the values from the tables in Appendix B. */
+typedef enum S390Opcode {
+ RIL_AFI = 0xc209,
+ RIL_AGFI = 0xc208,
+ RIL_ALFI = 0xc20b,
+ RIL_ALGFI = 0xc20a,
+ RIL_BRASL = 0xc005,
+ RIL_BRCL = 0xc004,
+ RIL_CFI = 0xc20d,
+ RIL_CGFI = 0xc20c,
+ RIL_CLFI = 0xc20f,
+ RIL_CLGFI = 0xc20e,
+ RIL_CLRL = 0xc60f,
+ RIL_CLGRL = 0xc60a,
+ RIL_CRL = 0xc60d,
+ RIL_CGRL = 0xc608,
+ RIL_IIHF = 0xc008,
+ RIL_IILF = 0xc009,
+ RIL_LARL = 0xc000,
+ RIL_LGFI = 0xc001,
+ RIL_LGRL = 0xc408,
+ RIL_LLIHF = 0xc00e,
+ RIL_LLILF = 0xc00f,
+ RIL_LRL = 0xc40d,
+ RIL_MSFI = 0xc201,
+ RIL_MSGFI = 0xc200,
+ RIL_NIHF = 0xc00a,
+ RIL_NILF = 0xc00b,
+ RIL_OIHF = 0xc00c,
+ RIL_OILF = 0xc00d,
+ RIL_SLFI = 0xc205,
+ RIL_SLGFI = 0xc204,
+ RIL_XIHF = 0xc006,
+ RIL_XILF = 0xc007,
+
+ RI_AGHI = 0xa70b,
+ RI_AHI = 0xa70a,
+ RI_BRC = 0xa704,
+ RI_CHI = 0xa70e,
+ RI_CGHI = 0xa70f,
+ RI_IIHH = 0xa500,
+ RI_IIHL = 0xa501,
+ RI_IILH = 0xa502,
+ RI_IILL = 0xa503,
+ RI_LGHI = 0xa709,
+ RI_LLIHH = 0xa50c,
+ RI_LLIHL = 0xa50d,
+ RI_LLILH = 0xa50e,
+ RI_LLILL = 0xa50f,
+ RI_MGHI = 0xa70d,
+ RI_MHI = 0xa70c,
+ RI_NIHH = 0xa504,
+ RI_NIHL = 0xa505,
+ RI_NILH = 0xa506,
+ RI_NILL = 0xa507,
+ RI_OIHH = 0xa508,
+ RI_OIHL = 0xa509,
+ RI_OILH = 0xa50a,
+ RI_OILL = 0xa50b,
+
+ RIE_CGIJ = 0xec7c,
+ RIE_CGRJ = 0xec64,
+ RIE_CIJ = 0xec7e,
+ RIE_CLGRJ = 0xec65,
+ RIE_CLIJ = 0xec7f,
+ RIE_CLGIJ = 0xec7d,
+ RIE_CLRJ = 0xec77,
+ RIE_CRJ = 0xec76,
+ RIE_LOCGHI = 0xec46,
+ RIE_RISBG = 0xec55,
+
+ RRE_AGR = 0xb908,
+ RRE_ALGR = 0xb90a,
+ RRE_ALCR = 0xb998,
+ RRE_ALCGR = 0xb988,
+ RRE_CGR = 0xb920,
+ RRE_CLGR = 0xb921,
+ RRE_DLGR = 0xb987,
+ RRE_DLR = 0xb997,
+ RRE_DSGFR = 0xb91d,
+ RRE_DSGR = 0xb90d,
+ RRE_FLOGR = 0xb983,
+ RRE_LGBR = 0xb906,
+ RRE_LCGR = 0xb903,
+ RRE_LGFR = 0xb914,
+ RRE_LGHR = 0xb907,
+ RRE_LGR = 0xb904,
+ RRE_LLGCR = 0xb984,
+ RRE_LLGFR = 0xb916,
+ RRE_LLGHR = 0xb985,
+ RRE_LRVR = 0xb91f,
+ RRE_LRVGR = 0xb90f,
+ RRE_LTGR = 0xb902,
+ RRE_MLGR = 0xb986,
+ RRE_MSGR = 0xb90c,
+ RRE_MSR = 0xb252,
+ RRE_NGR = 0xb980,
+ RRE_OGR = 0xb981,
+ RRE_SGR = 0xb909,
+ RRE_SLGR = 0xb90b,
+ RRE_SLBR = 0xb999,
+ RRE_SLBGR = 0xb989,
+ RRE_XGR = 0xb982,
+
+ RRF_LOCR = 0xb9f2,
+ RRF_LOCGR = 0xb9e2,
+ RRF_NRK = 0xb9f4,
+ RRF_NGRK = 0xb9e4,
+ RRF_ORK = 0xb9f6,
+ RRF_OGRK = 0xb9e6,
+ RRF_SRK = 0xb9f9,
+ RRF_SGRK = 0xb9e9,
+ RRF_SLRK = 0xb9fb,
+ RRF_SLGRK = 0xb9eb,
+ RRF_XRK = 0xb9f7,
+ RRF_XGRK = 0xb9e7,
+
+ RR_AR = 0x1a,
+ RR_ALR = 0x1e,
+ RR_BASR = 0x0d,
+ RR_BCR = 0x07,
+ RR_CLR = 0x15,
+ RR_CR = 0x19,
+ RR_DR = 0x1d,
+ RR_LCR = 0x13,
+ RR_LR = 0x18,
+ RR_LTR = 0x12,
+ RR_NR = 0x14,
+ RR_OR = 0x16,
+ RR_SR = 0x1b,
+ RR_SLR = 0x1f,
+ RR_XR = 0x17,
+
+ RSY_RLL = 0xeb1d,
+ RSY_RLLG = 0xeb1c,
+ RSY_SLLG = 0xeb0d,
+ RSY_SLLK = 0xebdf,
+ RSY_SRAG = 0xeb0a,
+ RSY_SRAK = 0xebdc,
+ RSY_SRLG = 0xeb0c,
+ RSY_SRLK = 0xebde,
+
+ RS_SLL = 0x89,
+ RS_SRA = 0x8a,
+ RS_SRL = 0x88,
+
+ RXY_AG = 0xe308,
+ RXY_AY = 0xe35a,
+ RXY_CG = 0xe320,
+ RXY_CLG = 0xe321,
+ RXY_CLY = 0xe355,
+ RXY_CY = 0xe359,
+ RXY_LAY = 0xe371,
+ RXY_LB = 0xe376,
+ RXY_LG = 0xe304,
+ RXY_LGB = 0xe377,
+ RXY_LGF = 0xe314,
+ RXY_LGH = 0xe315,
+ RXY_LHY = 0xe378,
+ RXY_LLGC = 0xe390,
+ RXY_LLGF = 0xe316,
+ RXY_LLGH = 0xe391,
+ RXY_LMG = 0xeb04,
+ RXY_LRV = 0xe31e,
+ RXY_LRVG = 0xe30f,
+ RXY_LRVH = 0xe31f,
+ RXY_LY = 0xe358,
+ RXY_NG = 0xe380,
+ RXY_OG = 0xe381,
+ RXY_STCY = 0xe372,
+ RXY_STG = 0xe324,
+ RXY_STHY = 0xe370,
+ RXY_STMG = 0xeb24,
+ RXY_STRV = 0xe33e,
+ RXY_STRVG = 0xe32f,
+ RXY_STRVH = 0xe33f,
+ RXY_STY = 0xe350,
+ RXY_XG = 0xe382,
+
+ RX_A = 0x5a,
+ RX_C = 0x59,
+ RX_L = 0x58,
+ RX_LA = 0x41,
+ RX_LH = 0x48,
+ RX_ST = 0x50,
+ RX_STC = 0x42,
+ RX_STH = 0x40,
+
+ VRIa_VGBM = 0xe744,
+ VRIa_VREPI = 0xe745,
+ VRIb_VGM = 0xe746,
+ VRIc_VREP = 0xe74d,
+
+ VRRa_VLC = 0xe7de,
+ VRRa_VLP = 0xe7df,
+ VRRa_VLR = 0xe756,
+ VRRc_VA = 0xe7f3,
+ VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
+ VRRc_VCH = 0xe7fb, /* " */
+ VRRc_VCHL = 0xe7f9, /* " */
+ VRRc_VERLLV = 0xe773,
+ VRRc_VESLV = 0xe770,
+ VRRc_VESRAV = 0xe77a,
+ VRRc_VESRLV = 0xe778,
+ VRRc_VML = 0xe7a2,
+ VRRc_VMN = 0xe7fe,
+ VRRc_VMNL = 0xe7fc,
+ VRRc_VMX = 0xe7ff,
+ VRRc_VMXL = 0xe7fd,
+ VRRc_VN = 0xe768,
+ VRRc_VNC = 0xe769,
+ VRRc_VNO = 0xe76b,
+ VRRc_VO = 0xe76a,
+ VRRc_VOC = 0xe76f,
+ VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */
+ VRRc_VS = 0xe7f7,
+ VRRa_VUPH = 0xe7d7,
+ VRRa_VUPL = 0xe7d6,
+ VRRc_VX = 0xe76d,
+ VRRe_VSEL = 0xe78d,
+ VRRf_VLVGP = 0xe762,
+
+ VRSa_VERLL = 0xe733,
+ VRSa_VESL = 0xe730,
+ VRSa_VESRA = 0xe73a,
+ VRSa_VESRL = 0xe738,
+ VRSb_VLVG = 0xe722,
+ VRSc_VLGV = 0xe721,
+
+ VRX_VL = 0xe706,
+ VRX_VLLEZ = 0xe704,
+ VRX_VLREP = 0xe705,
+ VRX_VST = 0xe70e,
+ VRX_VSTEF = 0xe70b,
+ VRX_VSTEG = 0xe70a,
+
+ NOP = 0x0707,
+} S390Opcode;
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
+ "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
+ "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
+ "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
+};
+#endif
+
+/* Since R6 is a potential argument register, choose it last of the
+ call-saved registers. Likewise prefer the call-clobbered registers
+ in reverse order to maximize the chance of avoiding the arguments. */
+static const int tcg_target_reg_alloc_order[] = {
+ /* Call saved registers. */
+ TCG_REG_R13,
+ TCG_REG_R12,
+ TCG_REG_R11,
+ TCG_REG_R10,
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_R7,
+ TCG_REG_R6,
+ /* Call clobbered registers. */
+ TCG_REG_R14,
+ TCG_REG_R0,
+ TCG_REG_R1,
+ /* Argument registers, in reverse order of allocation. */
+ TCG_REG_R5,
+ TCG_REG_R4,
+ TCG_REG_R3,
+ TCG_REG_R2,
+
+ /* V8-V15 are call saved, and omitted. */
+ TCG_REG_V0,
+ TCG_REG_V1,
+ TCG_REG_V2,
+ TCG_REG_V3,
+ TCG_REG_V4,
+ TCG_REG_V5,
+ TCG_REG_V6,
+ TCG_REG_V7,
+ TCG_REG_V16,
+ TCG_REG_V17,
+ TCG_REG_V18,
+ TCG_REG_V19,
+ TCG_REG_V20,
+ TCG_REG_V21,
+ TCG_REG_V22,
+ TCG_REG_V23,
+ TCG_REG_V24,
+ TCG_REG_V25,
+ TCG_REG_V26,
+ TCG_REG_V27,
+ TCG_REG_V28,
+ TCG_REG_V29,
+ TCG_REG_V30,
+ TCG_REG_V31,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_R2,
+ TCG_REG_R3,
+ TCG_REG_R4,
+ TCG_REG_R5,
+ TCG_REG_R6,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_R2,
+};
+
+#define S390_CC_EQ 8
+#define S390_CC_LT 4
+#define S390_CC_GT 2
+#define S390_CC_OV 1
+#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
+#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
+#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
+#define S390_CC_NEVER 0
+#define S390_CC_ALWAYS 15
+
+/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
+static const uint8_t tcg_cond_to_s390_cond[] = {
+ [TCG_COND_EQ] = S390_CC_EQ,
+ [TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_LT] = S390_CC_LT,
+ [TCG_COND_LE] = S390_CC_LE,
+ [TCG_COND_GT] = S390_CC_GT,
+ [TCG_COND_GE] = S390_CC_GE,
+ [TCG_COND_LTU] = S390_CC_LT,
+ [TCG_COND_LEU] = S390_CC_LE,
+ [TCG_COND_GTU] = S390_CC_GT,
+ [TCG_COND_GEU] = S390_CC_GE,
+};
+
+/* Condition codes that result from a LOAD AND TEST. Here, we have no
+ unsigned instruction variation, however since the test is vs zero we
+ can re-map the outcomes appropriately. */
+static const uint8_t tcg_cond_to_ltr_cond[] = {
+ [TCG_COND_EQ] = S390_CC_EQ,
+ [TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_LT] = S390_CC_LT,
+ [TCG_COND_LE] = S390_CC_LE,
+ [TCG_COND_GT] = S390_CC_GT,
+ [TCG_COND_GE] = S390_CC_GE,
+ [TCG_COND_LTU] = S390_CC_NEVER,
+ [TCG_COND_LEU] = S390_CC_EQ,
+ [TCG_COND_GTU] = S390_CC_NE,
+ [TCG_COND_GEU] = S390_CC_ALWAYS,
+};
+
+#ifdef CONFIG_SOFTMMU
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+ [MO_LEUW] = helper_le_lduw_mmu,
+ [MO_LESW] = helper_le_ldsw_mmu,
+ [MO_LEUL] = helper_le_ldul_mmu,
+ [MO_LESL] = helper_le_ldsl_mmu,
+ [MO_LEQ] = helper_le_ldq_mmu,
+ [MO_BEUW] = helper_be_lduw_mmu,
+ [MO_BESW] = helper_be_ldsw_mmu,
+ [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_BESL] = helper_be_ldsl_mmu,
+ [MO_BEQ] = helper_be_ldq_mmu,
+};
+
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
+ [MO_UB] = helper_ret_stb_mmu,
+ [MO_LEUW] = helper_le_stw_mmu,
+ [MO_LEUL] = helper_le_stl_mmu,
+ [MO_LEQ] = helper_le_stq_mmu,
+ [MO_BEUW] = helper_be_stw_mmu,
+ [MO_BEUL] = helper_be_stl_mmu,
+ [MO_BEQ] = helper_be_stq_mmu,
+};
+#endif
+
+static const tcg_insn_unit *tb_ret_addr;
+uint64_t s390_facilities[3];
+
+static inline bool is_general_reg(TCGReg r)
+{
+ return r <= TCG_REG_R15;
+}
+
+static inline bool is_vector_reg(TCGReg r)
+{
+ return r >= TCG_REG_V0 && r <= TCG_REG_V31;
+}
+
+static bool patch_reloc(tcg_insn_unit *src_rw, int type,
+ intptr_t value, intptr_t addend)
+{
+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+ intptr_t pcrel2;
+ uint32_t old;
+
+ value += addend;
+ pcrel2 = (tcg_insn_unit *)value - src_rx;
+
+ switch (type) {
+ case R_390_PC16DBL:
+ if (pcrel2 == (int16_t)pcrel2) {
+ tcg_patch16(src_rw, pcrel2);
+ return true;
+ }
+ break;
+ case R_390_PC32DBL:
+ if (pcrel2 == (int32_t)pcrel2) {
+ tcg_patch32(src_rw, pcrel2);
+ return true;
+ }
+ break;
+ case R_390_20:
+ if (value == sextract64(value, 0, 20)) {
+ old = *(uint32_t *)src_rw & 0xf00000ff;
+ old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
+ tcg_patch32(src_rw, old);
+ return true;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
+}
+
+/* Test if a constant matches the constraint. */
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+{
+ if (ct & TCG_CT_CONST) {
+ return 1;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ /* The following are mutually exclusive. */
+ if (ct & TCG_CT_CONST_S16) {
+ return val == (int16_t)val;
+ } else if (ct & TCG_CT_CONST_S32) {
+ return val == (int32_t)val;
+ } else if (ct & TCG_CT_CONST_S33) {
+ return val >= -0xffffffffll && val <= 0xffffffffll;
+ } else if (ct & TCG_CT_CONST_ZERO) {
+ return val == 0;
+ }
+
+ return 0;
+}
+
+/* Emit instructions according to the given instruction format. */
+
+static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
+{
+ tcg_out16(s, (op << 8) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
+ TCGReg r1, TCGReg r2)
+{
+ tcg_out32(s, (op << 16) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
+ TCGReg r1, TCGReg r2, int m3)
+{
+ tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
+{
+ tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
+}
+
+static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
+ int i2, int m3)
+{
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
+ tcg_out32(s, (i2 << 16) | (op & 0xff));
+}
+
+static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
+{
+ tcg_out16(s, op | (r1 << 4));
+ tcg_out32(s, i2);
+}
+
+static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
+ TCGReg b2, TCGReg r3, int disp)
+{
+ tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
+ | (disp & 0xfff));
+}
+
+static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
+ TCGReg b2, TCGReg r3, int disp)
+{
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
+ tcg_out32(s, (op & 0xff) | (b2 << 28)
+ | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
+}
+
+#define tcg_out_insn_RX tcg_out_insn_RS
+#define tcg_out_insn_RXY tcg_out_insn_RSY
+
+static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
+{
+ /*
+ * Shift bit 4 of each regno to its corresponding bit of RXB.
+ * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4
+ * is the left-shift of the 4th operand.
+ */
+ return ((v1 & 0x10) << (4 + 3))
+ | ((v2 & 0x10) << (4 + 2))
+ | ((v3 & 0x10) << (4 + 1))
+ | ((v4 & 0x10) << (4 + 0));
+}
+
+static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op,
+ TCGReg v1, uint16_t i2, int m3)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
+ tcg_out16(s, i2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
+}
+
+static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op,
+ TCGReg v1, uint8_t i2, uint8_t i3, int m4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
+ tcg_out16(s, (i2 << 8) | (i3 & 0xff));
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op,
+ TCGReg v1, uint16_t i2, TCGReg v3, int m4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
+ tcg_out16(s, i2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, int m3)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_vector_reg(v2));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
+ tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
+}
+
+static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, TCGReg v3, int m4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_vector_reg(v2));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
+ tcg_out16(s, v3 << 12);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_vector_reg(v2));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_debug_assert(is_vector_reg(v4));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
+ tcg_out16(s, v3 << 12);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12));
+}
+
+static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg r2, TCGReg r3)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_general_reg(r2));
+ tcg_debug_assert(is_general_reg(r3));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2);
+ tcg_out16(s, r3 << 12);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
+}
+
+static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
+ intptr_t d2, TCGReg b2, TCGReg v3, int m4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(is_general_reg(b2));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
+ tcg_out16(s, b2 << 12 | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
+ intptr_t d2, TCGReg b2, TCGReg r3, int m4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(is_general_reg(b2));
+ tcg_debug_assert(is_general_reg(r3));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3);
+ tcg_out16(s, b2 << 12 | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
+ intptr_t d2, TCGReg b2, TCGReg v3, int m4)
+{
+ tcg_debug_assert(is_general_reg(r1));
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(is_general_reg(b2));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf));
+ tcg_out16(s, b2 << 12 | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
+}
+
+static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
+ TCGReg b2, TCGReg x2, intptr_t d2, int m3)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
+ tcg_debug_assert(is_general_reg(x2));
+ tcg_debug_assert(is_general_reg(b2));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2);
+ tcg_out16(s, (b2 << 12) | d2);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
+}
+
+/* Emit an opcode with "type-checking" of the format. */
+#define tcg_out_insn(S, FMT, OP, ...) \
+ glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
+
+
+/* emit 64-bit shifts */
+static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
+ TCGReg src, TCGReg sh_reg, int sh_imm)
+{
+ tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
+}
+
+/* emit 32-bit shifts */
+static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
+ TCGReg sh_reg, int sh_imm)
+{
+ tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
+}
+
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
+{
+ if (src == dst) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (likely(is_general_reg(dst) && is_general_reg(src))) {
+ tcg_out_insn(s, RR, LR, dst, src);
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_I64:
+ if (likely(is_general_reg(dst))) {
+ if (likely(is_general_reg(src))) {
+ tcg_out_insn(s, RRE, LGR, dst, src);
+ } else {
+ tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
+ }
+ break;
+ } else if (is_general_reg(src)) {
+ tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_out_insn(s, VRRa, VLR, dst, src, 0);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static const S390Opcode lli_insns[4] = {
+ RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
+};
+
+static bool maybe_out_small_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long sval)
+{
+ tcg_target_ulong uval = sval;
+ int i;
+
+ if (type == TCG_TYPE_I32) {
+ uval = (uint32_t)sval;
+ sval = (int32_t)sval;
+ }
+
+ /* Try all 32-bit insns that can load it in one go. */
+ if (sval >= -0x8000 && sval < 0x8000) {
+ tcg_out_insn(s, RI, LGHI, ret, sval);
+ return true;
+ }
+
+ for (i = 0; i < 4; i++) {
+ tcg_target_long mask = 0xffffull << i*16;
+ if ((uval & mask) == uval) {
+ tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/* load a register with an immediate value */
+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long sval, bool in_prologue)
+{
+ tcg_target_ulong uval;
+
+ /* Try all 32-bit insns that can load it in one go. */
+ if (maybe_out_small_movi(s, type, ret, sval)) {
+ return;
+ }
+
+ uval = sval;
+ if (type == TCG_TYPE_I32) {
+ uval = (uint32_t)sval;
+ sval = (int32_t)sval;
+ }
+
+ /* Try all 48-bit insns that can load it in one go. */
+ if (HAVE_FACILITY(EXT_IMM)) {
+ if (sval == (int32_t)sval) {
+ tcg_out_insn(s, RIL, LGFI, ret, sval);
+ return;
+ }
+ if (uval <= 0xffffffff) {
+ tcg_out_insn(s, RIL, LLILF, ret, uval);
+ return;
+ }
+ if ((uval & 0xffffffff) == 0) {
+ tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
+ return;
+ }
+ }
+
+ /* Try for PC-relative address load. For odd addresses,
+ attempt to use an offset from the start of the TB. */
+ if ((sval & 1) == 0) {
+ ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
+ if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, LARL, ret, off);
+ return;
+ }
+ } else if (USE_REG_TB && !in_prologue) {
+ ptrdiff_t off = tcg_tbrel_diff(s, (void *)sval);
+ if (off == sextract64(off, 0, 20)) {
+ /* This is certain to be an address within TB, and therefore
+ OFF will be negative; don't try RX_LA. */
+ tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
+ return;
+ }
+ }
+
+ /* A 32-bit unsigned value can be loaded in 2 insns. And given
+ that LLILL, LLIHL, LLILF above did not succeed, we know that
+ both insns are required. */
+ if (uval <= 0xffffffff) {
+ tcg_out_insn(s, RI, LLILL, ret, uval);
+ tcg_out_insn(s, RI, IILH, ret, uval >> 16);
+ return;
+ }
+
+ /* Otherwise, stuff it in the constant pool. */
+ if (HAVE_FACILITY(GEN_INST_EXT)) {
+ tcg_out_insn(s, RIL, LGRL, ret, 0);
+ new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
+ } else if (USE_REG_TB && !in_prologue) {
+ tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
+ tcg_tbrel_diff(s, NULL));
+ } else {
+ TCGReg base = ret ? ret : TCG_TMP0;
+ tcg_out_insn(s, RIL, LARL, base, 0);
+ new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
+ tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
+ }
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long sval)
+{
+ tcg_out_movi_int(s, type, ret, sval, false);
+}
+
+/* Emit a load/store type instruction. Inputs are:
+ DATA: The register to be loaded or stored.
+ BASE+OFS: The effective address.
+ OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
+ OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
+
+static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
+ TCGReg data, TCGReg base, TCGReg index,
+ tcg_target_long ofs)
+{
+ if (ofs < -0x80000 || ofs >= 0x80000) {
+ /* Combine the low 20 bits of the offset with the actual load insn;
+ the high 44 bits must come from an immediate load. */
+ tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
+ ofs = low;
+
+ /* If we were already given an index register, add it in. */
+ if (index != TCG_REG_NONE) {
+ tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
+ }
+ index = TCG_TMP0;
+ }
+
+ if (opc_rx && ofs >= 0 && ofs < 0x1000) {
+ tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
+ } else {
+ tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
+ }
+}
+
+static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx,
+ TCGReg data, TCGReg base, TCGReg index,
+ tcg_target_long ofs, int m3)
+{
+ if (ofs < 0 || ofs >= 0x1000) {
+ if (ofs >= -0x80000 && ofs < 0x80000) {
+ tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs);
+ base = TCG_TMP0;
+ index = TCG_REG_NONE;
+ ofs = 0;
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs);
+ if (index != TCG_REG_NONE) {
+ tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
+ }
+ index = TCG_TMP0;
+ ofs = 0;
+ }
+ }
+ tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3);
+}
+
+/* load data without address translation or endianness conversion */
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, intptr_t ofs)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (likely(is_general_reg(data))) {
+ tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
+ break;
+ }
+ tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32);
+ break;
+
+ case TCG_TYPE_I64:
+ if (likely(is_general_reg(data))) {
+ tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_V64:
+ tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64);
+ break;
+
+ case TCG_TYPE_V128:
+ /* Hint quadword aligned. */
+ tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
+ TCGReg base, intptr_t ofs)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (likely(is_general_reg(data))) {
+ tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
+ } else {
+ tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1);
+ }
+ break;
+
+ case TCG_TYPE_I64:
+ if (likely(is_general_reg(data))) {
+ tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
+ break;
+ }
+ /* fallthru */
+
+ case TCG_TYPE_V64:
+ tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0);
+ break;
+
+ case TCG_TYPE_V128:
+ /* Hint quadword aligned. */
+ tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+ TCGReg base, intptr_t ofs)
+{
+ return false;
+}
+
+/* load data from an absolute host address */
+static void tcg_out_ld_abs(TCGContext *s, TCGType type,
+ TCGReg dest, const void *abs)
+{
+ intptr_t addr = (intptr_t)abs;
+
+ if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) {
+ ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
+ if (disp == (int32_t)disp) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RIL, LRL, dest, disp);
+ } else {
+ tcg_out_insn(s, RIL, LGRL, dest, disp);
+ }
+ return;
+ }
+ }
+ if (USE_REG_TB) {
+ ptrdiff_t disp = tcg_tbrel_diff(s, abs);
+ if (disp == sextract64(disp, 0, 20)) {
+ tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
+ return;
+ }
+ }
+
+ tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
+ tcg_out_ld(s, type, dest, dest, addr & 0xffff);
+}
+
+static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
+ int msb, int lsb, int ofs, int z)
+{
+ /* Format RIE-f */
+ tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
+ tcg_out16(s, (msb << 8) | (z << 7) | lsb);
+ tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
+}
+
+static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (HAVE_FACILITY(EXT_IMM)) {
+ tcg_out_insn(s, RRE, LGBR, dest, src);
+ return;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ if (dest == src) {
+ tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
+ }
+ tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
+ tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
+ }
+}
+
+static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (HAVE_FACILITY(EXT_IMM)) {
+ tcg_out_insn(s, RRE, LLGCR, dest, src);
+ return;
+ }
+
+ if (dest == src) {
+ tcg_out_movi(s, type, TCG_TMP0, 0xff);
+ src = TCG_TMP0;
+ } else {
+ tcg_out_movi(s, type, dest, 0xff);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, src);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, src);
+ }
+}
+
+static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (HAVE_FACILITY(EXT_IMM)) {
+ tcg_out_insn(s, RRE, LGHR, dest, src);
+ return;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ if (dest == src) {
+ tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
+ }
+ tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
+ tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
+ }
+}
+
+static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
+{
+ if (HAVE_FACILITY(EXT_IMM)) {
+ tcg_out_insn(s, RRE, LLGHR, dest, src);
+ return;
+ }
+
+ if (dest == src) {
+ tcg_out_movi(s, type, TCG_TMP0, 0xffff);
+ src = TCG_TMP0;
+ } else {
+ tcg_out_movi(s, type, dest, 0xffff);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, src);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, src);
+ }
+}
+
+static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_insn(s, RRE, LGFR, dest, src);
+}
+
+static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
+{
+ tcg_out_insn(s, RRE, LLGFR, dest, src);
+}
+
+/* Accept bit patterns like these:
+ 0....01....1
+ 1....10....0
+ 1..10..01..1
+ 0..01..10..0
+ Copied from gcc sources. */
+static inline bool risbg_mask(uint64_t c)
+{
+ uint64_t lsb;
+ /* We don't change the number of transitions by inverting,
+ so make sure we start with the LSB zero. */
+ if (c & 1) {
+ c = ~c;
+ }
+ /* Reject all zeros or all ones. */
+ if (c == 0) {
+ return false;
+ }
+ /* Find the first transition. */
+ lsb = c & -c;
+ /* Invert to look for a second transition. */
+ c = ~c;
+ /* Erase the first transition. */
+ c &= -lsb;
+ /* Find the second transition, if any. */
+ lsb = c & -c;
+ /* Match if all the bits are 1's, or if c is zero. */
+ return c == -lsb;
+}
+
+static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
+{
+ int msb, lsb;
+ if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
+ /* Achieve wraparound by swapping msb and lsb. */
+ msb = 64 - ctz64(~val);
+ lsb = clz64(~val) - 1;
+ } else {
+ msb = clz64(val);
+ lsb = 63 - ctz64(val);
+ }
+ tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
+}
+
+static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ static const S390Opcode ni_insns[4] = {
+ RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
+ };
+ static const S390Opcode nif_insns[2] = {
+ RIL_NILF, RIL_NIHF
+ };
+ uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
+ int i;
+
+ /* Look for the zero-extensions. */
+ if ((val & valid) == 0xffffffff) {
+ tgen_ext32u(s, dest, dest);
+ return;
+ }
+ if (HAVE_FACILITY(EXT_IMM)) {
+ if ((val & valid) == 0xff) {
+ tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
+ return;
+ }
+ if ((val & valid) == 0xffff) {
+ tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
+ return;
+ }
+ }
+
+ /* Try all 32-bit insns that can perform it in one go. */
+ for (i = 0; i < 4; i++) {
+ tcg_target_ulong mask = ~(0xffffull << i*16);
+ if (((val | ~valid) & mask) == mask) {
+ tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
+ return;
+ }
+ }
+
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (HAVE_FACILITY(EXT_IMM)) {
+ for (i = 0; i < 2; i++) {
+ tcg_target_ulong mask = ~(0xffffffffull << i*32);
+ if (((val | ~valid) & mask) == mask) {
+ tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
+ return;
+ }
+ }
+ }
+ if (HAVE_FACILITY(GEN_INST_EXT) && risbg_mask(val)) {
+ tgen_andi_risbg(s, dest, dest, val);
+ return;
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (USE_REG_TB) {
+ if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
+ tcg_tbrel_diff(s, NULL));
+ return;
+ }
+ } else {
+ tcg_out_movi(s, type, TCG_TMP0, val);
+ }
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
+ }
+}
+
+static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ static const S390Opcode oi_insns[4] = {
+ RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
+ };
+ static const S390Opcode oif_insns[2] = {
+ RIL_OILF, RIL_OIHF
+ };
+
+ int i;
+
+ /* Look for no-op. */
+ if (unlikely(val == 0)) {
+ return;
+ }
+
+ /* Try all 32-bit insns that can perform it in one go. */
+ for (i = 0; i < 4; i++) {
+ tcg_target_ulong mask = (0xffffull << i*16);
+ if ((val & mask) != 0 && (val & ~mask) == 0) {
+ tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
+ return;
+ }
+ }
+
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (HAVE_FACILITY(EXT_IMM)) {
+ for (i = 0; i < 2; i++) {
+ tcg_target_ulong mask = (0xffffffffull << i*32);
+ if ((val & mask) != 0 && (val & ~mask) == 0) {
+ tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
+ return;
+ }
+ }
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
+ }
+ } else if (USE_REG_TB) {
+ tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,
+ tcg_tbrel_diff(s, NULL));
+ } else {
+ /* Perform the OR via sequential modifications to the high and
+ low parts. Do this via recursion to handle 16-bit vs 32-bit
+ masks in each half. */
+ tcg_debug_assert(HAVE_FACILITY(EXT_IMM));
+ tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
+ tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
+ }
+}
+
+static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
+{
+ /* Try all 48-bit insns that can perform it in one go. */
+ if (HAVE_FACILITY(EXT_IMM)) {
+ if ((val & 0xffffffff00000000ull) == 0) {
+ tcg_out_insn(s, RIL, XILF, dest, val);
+ return;
+ }
+ if ((val & 0x00000000ffffffffull) == 0) {
+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
+ return;
+ }
+ }
+
+ /* Use the constant pool if USE_REG_TB, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, XR, dest, TCG_TMP0);
+ } else {
+ tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
+ }
+ } else if (USE_REG_TB) {
+ tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,
+ tcg_tbrel_diff(s, NULL));
+ } else {
+ /* Perform the xor by parts. */
+ tcg_debug_assert(HAVE_FACILITY(EXT_IMM));
+ if (val & 0xffffffff) {
+ tcg_out_insn(s, RIL, XILF, dest, val);
+ }
+ if (val > 0xffffffff) {
+ tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
+ }
+ }
+}
+
+static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
+ TCGArg c2, bool c2const, bool need_carry)
+{
+ bool is_unsigned = is_unsigned_cond(c);
+ S390Opcode op;
+
+ if (c2const) {
+ if (c2 == 0) {
+ if (!(is_unsigned && need_carry)) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RR, LTR, r1, r1);
+ } else {
+ tcg_out_insn(s, RRE, LTGR, r1, r1);
+ }
+ return tcg_cond_to_ltr_cond[c];
+ }
+ }
+
+ if (!is_unsigned && c2 == (int16_t)c2) {
+ op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);
+ tcg_out_insn_RI(s, op, r1, c2);
+ goto exit;
+ }
+
+ if (HAVE_FACILITY(EXT_IMM)) {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RIL_CLFI : RIL_CFI);
+ tcg_out_insn_RIL(s, op, r1, c2);
+ goto exit;
+ } else if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) {
+ op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
+ tcg_out_insn_RIL(s, op, r1, c2);
+ goto exit;
+ }
+ }
+
+ /* Use the constant pool, but not for small constants. */
+ if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {
+ c2 = TCG_TMP0;
+ /* fall through to reg-reg */
+ } else if (USE_REG_TB) {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RXY_CLY : RXY_CY);
+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2,
+ 4 - tcg_tbrel_diff(s, NULL));
+ } else {
+ op = (is_unsigned ? RXY_CLG : RXY_CG);
+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);
+ new_pool_label(s, c2, R_390_20, s->code_ptr - 2,
+ tcg_tbrel_diff(s, NULL));
+ }
+ goto exit;
+ } else {
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RIL_CLRL : RIL_CRL);
+ tcg_out_insn_RIL(s, op, r1, 0);
+ new_pool_label(s, (uint32_t)c2, R_390_PC32DBL,
+ s->code_ptr - 2, 2 + 4);
+ } else {
+ op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);
+ tcg_out_insn_RIL(s, op, r1, 0);
+ new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);
+ }
+ goto exit;
+ }
+ }
+
+ if (type == TCG_TYPE_I32) {
+ op = (is_unsigned ? RR_CLR : RR_CR);
+ tcg_out_insn_RR(s, op, r1, c2);
+ } else {
+ op = (is_unsigned ? RRE_CLGR : RRE_CGR);
+ tcg_out_insn_RRE(s, op, r1, c2);
+ }
+
+ exit:
+ return tcg_cond_to_s390_cond[c];
+}
+
+static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
+ TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
+{
+ int cc;
+ bool have_loc;
+
+ /* With LOC2, we can always emit the minimum 3 insns. */
+ if (HAVE_FACILITY(LOAD_ON_COND2)) {
+ /* Emit: d = 0, d = (cc ? 1 : d). */
+ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+ tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
+ return;
+ }
+
+ have_loc = HAVE_FACILITY(LOAD_ON_COND);
+
+ /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
+ restart:
+ switch (cond) {
+ case TCG_COND_NE:
+ /* X != 0 is X > 0. */
+ if (c2const && c2 == 0) {
+ cond = TCG_COND_GTU;
+ } else {
+ break;
+ }
+ /* fallthru */
+
+ case TCG_COND_GTU:
+ case TCG_COND_GT:
+ /* The result of a compare has CC=2 for GT and CC=3 unused.
+ ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
+ tgen_cmp(s, type, cond, c1, c2, c2const, true);
+ tcg_out_movi(s, type, dest, 0);
+ tcg_out_insn(s, RRE, ALCGR, dest, dest);
+ return;
+
+ case TCG_COND_EQ:
+ /* X == 0 is X <= 0. */
+ if (c2const && c2 == 0) {
+ cond = TCG_COND_LEU;
+ } else {
+ break;
+ }
+ /* fallthru */
+
+ case TCG_COND_LEU:
+ case TCG_COND_LE:
+ /* As above, but we're looking for borrow, or !carry.
+ The second insn computes d - d - borrow, or -1 for true
+ and 0 for false. So we must mask to 1 bit afterward. */
+ tgen_cmp(s, type, cond, c1, c2, c2const, true);
+ tcg_out_insn(s, RRE, SLBGR, dest, dest);
+ tgen_andi(s, type, dest, 1);
+ return;
+
+ case TCG_COND_GEU:
+ case TCG_COND_LTU:
+ case TCG_COND_LT:
+ case TCG_COND_GE:
+ /* Swap operands so that we can use LEU/GTU/GT/LE. */
+ if (c2const) {
+ if (have_loc) {
+ break;
+ }
+ tcg_out_movi(s, type, TCG_TMP0, c2);
+ c2 = c1;
+ c2const = 0;
+ c1 = TCG_TMP0;
+ } else {
+ TCGReg t = c1;
+ c1 = c2;
+ c2 = t;
+ }
+ cond = tcg_swap_cond(cond);
+ goto restart;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
+ if (have_loc) {
+ /* Emit: d = 0, t = 1, d = (cc ? t : d). */
+ tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
+ tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
+ } else {
+ /* Emit: d = 1; if (cc) goto over; d = 0; over: */
+ tcg_out_movi(s, type, dest, 1);
+ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+ tcg_out_movi(s, type, dest, 0);
+ }
+}
+
+static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
+ TCGReg c1, TCGArg c2, int c2const,
+ TCGArg v3, int v3const)
+{
+ int cc;
+ if (HAVE_FACILITY(LOAD_ON_COND)) {
+ cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
+ if (v3const) {
+ tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
+ } else {
+ tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
+ }
+ } else {
+ c = tcg_invert_cond(c);
+ cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
+
+ /* Emit: if (cc) goto over; dest = r3; over: */
+ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
+ tcg_out_insn(s, RRE, LGR, dest, v3);
+ }
+}
+
+static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
+ TCGArg a2, int a2const)
+{
+ /* Since this sets both R and R+1, we have no choice but to store the
+ result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
+ QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
+ tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
+
+ if (a2const && a2 == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
+ } else {
+ if (a2const) {
+ tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
+ }
+ if (HAVE_FACILITY(LOAD_ON_COND)) {
+ /* Emit: if (one bit found) dest = r0. */
+ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
+ } else {
+ /* Emit: if (no one bit found) goto over; dest = r0; over: */
+ tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
+ tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
+ }
+ }
+}
+
+static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
+ int ofs, int len, int z)
+{
+ int lsb = (63 - ofs);
+ int msb = lsb - (len - 1);
+ tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
+}
+
+static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
+ int ofs, int len)
+{
+ tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
+}
+
+static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest)
+{
+ ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
+ if (off == (int16_t)off) {
+ tcg_out_insn(s, RI, BRC, cc, off);
+ } else if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, BRCL, cc, off);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
+ tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
+ }
+}
+
+static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
+{
+ if (l->has_value) {
+ tgen_gotoi(s, cc, l->u.value_ptr);
+ } else if (USE_LONG_BRANCHES) {
+ tcg_out16(s, RIL_BRCL | (cc << 4));
+ tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2);
+ s->code_ptr += 2;
+ } else {
+ tcg_out16(s, RI_BRC | (cc << 4));
+ tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
+ s->code_ptr += 1;
+ }
+}
+
+static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
+ TCGReg r1, TCGReg r2, TCGLabel *l)
+{
+ tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
+ tcg_out16(s, 0);
+ tcg_out16(s, cc << 12 | (opc & 0xff));
+}
+
+static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
+ TCGReg r1, int i2, TCGLabel *l)
+{
+ tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
+ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
+ tcg_out16(s, 0);
+ tcg_out16(s, (i2 << 8) | (opc & 0xff));
+}
+
+static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
+ TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
+{
+ int cc;
+
+ if (HAVE_FACILITY(GEN_INST_EXT)) {
+ bool is_unsigned = is_unsigned_cond(c);
+ bool in_range;
+ S390Opcode opc;
+
+ cc = tcg_cond_to_s390_cond[c];
+
+ if (!c2const) {
+ opc = (type == TCG_TYPE_I32
+ ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
+ : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
+ tgen_compare_branch(s, opc, cc, r1, c2, l);
+ return;
+ }
+
+ /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
+ If the immediate we've been given does not fit that range, we'll
+ fall back to separate compare and branch instructions using the
+ larger comparison range afforded by COMPARE IMMEDIATE. */
+ if (type == TCG_TYPE_I32) {
+ if (is_unsigned) {
+ opc = RIE_CLIJ;
+ in_range = (uint32_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIE_CIJ;
+ in_range = (int32_t)c2 == (int8_t)c2;
+ }
+ } else {
+ if (is_unsigned) {
+ opc = RIE_CLGIJ;
+ in_range = (uint64_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIE_CGIJ;
+ in_range = (int64_t)c2 == (int8_t)c2;
+ }
+ }
+ if (in_range) {
+ tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
+ return;
+ }
+ }
+
+ cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
+ tgen_branch(s, cc, l);
+}
+
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest)
+{
+ ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
+ if (off == (int32_t)off) {
+ tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
+ tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
+ }
+}
+
+static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
+ TCGReg base, TCGReg index, int disp)
+{
+ switch (opc & (MO_SSIZE | MO_BSWAP)) {
+ case MO_UB:
+ tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
+ break;
+ case MO_SB:
+ tcg_out_insn(s, RXY, LGB, data, base, index, disp);
+ break;
+
+ case MO_UW | MO_BSWAP:
+ /* swapped unsigned halfword load with upper bits zeroed */
+ tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
+ tgen_ext16u(s, TCG_TYPE_I64, data, data);
+ break;
+ case MO_UW:
+ tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
+ break;
+
+ case MO_SW | MO_BSWAP:
+ /* swapped sign-extended halfword load */
+ tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
+ tgen_ext16s(s, TCG_TYPE_I64, data, data);
+ break;
+ case MO_SW:
+ tcg_out_insn(s, RXY, LGH, data, base, index, disp);
+ break;
+
+ case MO_UL | MO_BSWAP:
+ /* swapped unsigned int load with upper bits zeroed */
+ tcg_out_insn(s, RXY, LRV, data, base, index, disp);
+ tgen_ext32u(s, data, data);
+ break;
+ case MO_UL:
+ tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
+ break;
+
+ case MO_SL | MO_BSWAP:
+ /* swapped sign-extended int load */
+ tcg_out_insn(s, RXY, LRV, data, base, index, disp);
+ tgen_ext32s(s, data, data);
+ break;
+ case MO_SL:
+ tcg_out_insn(s, RXY, LGF, data, base, index, disp);
+ break;
+
+ case MO_Q | MO_BSWAP:
+ tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
+ break;
+ case MO_Q:
+ tcg_out_insn(s, RXY, LG, data, base, index, disp);
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
+ TCGReg base, TCGReg index, int disp)
+{
+ switch (opc & (MO_SIZE | MO_BSWAP)) {
+ case MO_UB:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, STC, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STCY, data, base, index, disp);
+ }
+ break;
+
+ case MO_UW | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
+ break;
+ case MO_UW:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, STH, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STHY, data, base, index, disp);
+ }
+ break;
+
+ case MO_UL | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRV, data, base, index, disp);
+ break;
+ case MO_UL:
+ if (disp >= 0 && disp < 0x1000) {
+ tcg_out_insn(s, RX, ST, data, base, index, disp);
+ } else {
+ tcg_out_insn(s, RXY, STY, data, base, index, disp);
+ }
+ break;
+
+ case MO_Q | MO_BSWAP:
+ tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
+ break;
+ case MO_Q:
+ tcg_out_insn(s, RXY, STG, data, base, index, disp);
+ break;
+
+ default:
+ tcg_abort();
+ }
+}
+
+#if defined(CONFIG_SOFTMMU)
+#include "../tcg-ldst.c.inc"
+
+/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
+QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
+
+/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
+ addend into R2. Returns a register with the santitized guest address. */
+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
+ int mem_index, bool is_ld)
+{
+ unsigned s_bits = opc & MO_SIZE;
+ unsigned a_bits = get_alignment_bits(opc);
+ unsigned s_mask = (1 << s_bits) - 1;
+ unsigned a_mask = (1 << a_bits) - 1;
+ int fast_off = TLB_MASK_TABLE_OFS(mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ int ofs, a_off;
+ uint64_t tlb_mask;
+
+ tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off);
+ tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_off);
+
+ /* For aligned accesses, we check the first byte and include the alignment
+ bits within the address. For unaligned access, we check that we don't
+ cross pages using the address of the last byte of the access. */
+ a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
+ tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
+ if (HAVE_FACILITY(GEN_INST_EXT) && a_off == 0) {
+ tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
+ } else {
+ tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
+ tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
+ }
+
+ if (is_ld) {
+ ofs = offsetof(CPUTLBEntry, addr_read);
+ } else {
+ ofs = offsetof(CPUTLBEntry, addr_write);
+ }
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
+ } else {
+ tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs);
+ }
+
+ tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE,
+ offsetof(CPUTLBEntry, addend));
+
+ if (TARGET_LONG_BITS == 32) {
+ tgen_ext32u(s, TCG_REG_R3, addr_reg);
+ return TCG_REG_R3;
+ }
+ return addr_reg;
+}
+
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
+ TCGReg data, TCGReg addr,
+ tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
+{
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->oi = oi;
+ label->datalo_reg = data;
+ label->addrlo_reg = addr;
+ label->raddr = tcg_splitwx_to_rx(raddr);
+ label->label_ptr[0] = label_ptr;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg addr_reg = lb->addrlo_reg;
+ TCGReg data_reg = lb->datalo_reg;
+ MemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
+ (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
+ }
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
+ tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+ tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
+
+ tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
+ return true;
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
+{
+ TCGReg addr_reg = lb->addrlo_reg;
+ TCGReg data_reg = lb->datalo_reg;
+ MemOpIdx oi = lb->oi;
+ MemOp opc = get_memop(oi);
+
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
+ (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
+ }
+ switch (opc & MO_SIZE) {
+ case MO_UB:
+ tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ case MO_UW:
+ tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ case MO_UL:
+ tgen_ext32u(s, TCG_REG_R4, data_reg);
+ break;
+ case MO_Q:
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
+ break;
+ default:
+ tcg_abort();
+ }
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
+ tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+
+ tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
+ return true;
+}
+#else
+static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
+ TCGReg *index_reg, tcg_target_long *disp)
+{
+ if (TARGET_LONG_BITS == 32) {
+ tgen_ext32u(s, TCG_TMP0, *addr_reg);
+ *addr_reg = TCG_TMP0;
+ }
+ if (guest_base < 0x80000) {
+ *index_reg = TCG_REG_NONE;
+ *disp = guest_base;
+ } else {
+ *index_reg = TCG_GUEST_BASE_REG;
+ *disp = 0;
+ }
+}
+#endif /* CONFIG_SOFTMMU */
+
+static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
+ MemOpIdx oi)
+{
+ MemOp opc = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+ TCGReg base_reg;
+
+ base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
+
+ tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
+ label_ptr = s->code_ptr;
+ s->code_ptr += 1;
+
+ tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
+
+ add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
+#else
+ TCGReg index_reg;
+ tcg_target_long disp;
+
+ tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
+ tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
+#endif
+}
+
+static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
+ MemOpIdx oi)
+{
+ MemOp opc = get_memop(oi);
+#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
+ tcg_insn_unit *label_ptr;
+ TCGReg base_reg;
+
+ base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
+
+ tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
+ label_ptr = s->code_ptr;
+ s->code_ptr += 1;
+
+ tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
+
+ add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
+#else
+ TCGReg index_reg;
+ tcg_target_long disp;
+
+ tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
+ tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
+#endif
+}
+
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_,x),_i32): \
+ case glue(glue(INDEX_op_,x),_i64)
+
+static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
+{
+ S390Opcode op, op2;
+ TCGArg a0, a1, a2;
+
+ switch (opc) {
+ case INDEX_op_exit_tb:
+ /* Reuse the zeroing that exists for goto_ptr. */
+ a0 = args[0];
+ if (a0 == 0) {
+ tgen_gotoi(s, S390_CC_ALWAYS, tcg_code_gen_epilogue);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
+ tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
+ }
+ break;
+
+ case INDEX_op_goto_tb:
+ a0 = args[0];
+ if (s->tb_jmp_insn_offset) {
+ /*
+ * branch displacement must be aligned for atomic patching;
+ * see if we need to add extra nop before branch
+ */
+ if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
+ tcg_out16(s, NOP);
+ }
+ tcg_debug_assert(!USE_REG_TB);
+ tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+ s->code_ptr += 2;
+ } else {
+ /* load address stored at s->tb_jmp_target_addr + a0 */
+ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
+ tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0));
+ /* and go there */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
+ }
+ set_jmp_reset_offset(s, a0);
+
+ /* For the unlinked path of goto_tb, we need to reset
+ TCG_REG_TB to the beginning of this TB. */
+ if (USE_REG_TB) {
+ int ofs = -tcg_current_code_size(s);
+ /* All TB are restricted to 64KiB by unwind info. */
+ tcg_debug_assert(ofs == sextract64(ofs, 0, 20));
+ tcg_out_insn(s, RXY, LAY, TCG_REG_TB,
+ TCG_REG_TB, TCG_REG_NONE, ofs);
+ }
+ break;
+
+ case INDEX_op_goto_ptr:
+ a0 = args[0];
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
+ }
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
+ break;
+
+ OP_32_64(ld8u):
+ /* ??? LLC (RXY format) is only present with the extended-immediate
+ facility, whereas LLGC is always present. */
+ tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(ld8s):
+ /* ??? LB is no smaller than LGB, so no point to using it. */
+ tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(ld16u):
+ /* ??? LLH (RXY format) is only present with the extended-immediate
+ facility, whereas LLGH is always present. */
+ tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_ld16s_i32:
+ tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_ld_i32:
+ tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+
+ OP_32_64(st8):
+ tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ break;
+
+ OP_32_64(st16):
+ tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ break;
+
+ case INDEX_op_st_i32:
+ tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_add_i32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (const_args[2]) {
+ do_addi_32:
+ if (a0 == a1) {
+ if (a2 == (int16_t)a2) {
+ tcg_out_insn(s, RI, AHI, a0, a2);
+ break;
+ }
+ if (HAVE_FACILITY(EXT_IMM)) {
+ tcg_out_insn(s, RIL, AFI, a0, a2);
+ break;
+ }
+ }
+ tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, AR, a0, a2);
+ } else {
+ tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
+ }
+ break;
+ case INDEX_op_sub_i32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_32;
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, SR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, SRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_andi(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, NR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, NRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_or_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_ori(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, OR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, ORK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_xor_i32:
+ a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
+ tgen_xori(s, TCG_TYPE_I32, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RR, XR, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RRF, XRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_neg_i32:
+ tcg_out_insn(s, RR, LCR, args[0], args[1]);
+ break;
+
+ case INDEX_op_mul_i32:
+ if (const_args[2]) {
+ if ((int32_t)args[2] == (int16_t)args[2]) {
+ tcg_out_insn(s, RI, MHI, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, MSR, args[0], args[2]);
+ }
+ break;
+
+ case INDEX_op_div2_i32:
+ tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_divu2_i32:
+ tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
+ break;
+
+ case INDEX_op_shl_i32:
+ op = RS_SLL;
+ op2 = RSY_SLLK;
+ do_shift32:
+ a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
+ if (a0 == a1) {
+ if (const_args[2]) {
+ tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
+ } else {
+ tcg_out_sh32(s, op, a0, a2, 0);
+ }
+ } else {
+ /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
+ if (const_args[2]) {
+ tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
+ } else {
+ tcg_out_sh64(s, op2, a0, a1, a2, 0);
+ }
+ }
+ break;
+ case INDEX_op_shr_i32:
+ op = RS_SRL;
+ op2 = RSY_SRLK;
+ goto do_shift32;
+ case INDEX_op_sar_i32:
+ op = RS_SRA;
+ op2 = RSY_SRAK;
+ goto do_shift32;
+
+ case INDEX_op_rotl_i32:
+ /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_rotr_i32:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1],
+ TCG_REG_NONE, (32 - args[2]) & 31);
+ } else {
+ tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
+ tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
+ }
+ break;
+
+ case INDEX_op_ext8s_i32:
+ tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i32:
+ tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext8u_i32:
+ tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i32:
+ tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
+ break;
+
+ case INDEX_op_bswap16_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16);
+ }
+ break;
+ case INDEX_op_bswap16_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVGR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48);
+ } else {
+ tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48);
+ }
+ break;
+
+ case INDEX_op_bswap32_i32:
+ tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+ break;
+ case INDEX_op_bswap32_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tgen_ext32s(s, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tgen_ext32u(s, a0, a0);
+ }
+ break;
+
+ case INDEX_op_add2_i32:
+ if (const_args[4]) {
+ tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RR, ALR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
+ break;
+ case INDEX_op_sub2_i32:
+ if (const_args[4]) {
+ tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RR, SLR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
+ break;
+
+ case INDEX_op_br:
+ tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
+ break;
+
+ case INDEX_op_brcond_i32:
+ tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
+ args[1], const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i32:
+ tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_movcond_i32:
+ tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
+
+ case INDEX_op_qemu_ld_i32:
+ /* ??? Technically we can use a non-extending instruction. */
+ case INDEX_op_qemu_ld_i64:
+ tcg_out_qemu_ld(s, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_qemu_st_i32:
+ case INDEX_op_qemu_st_i64:
+ tcg_out_qemu_st(s, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_ld16s_i64:
+ tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld32u_i64:
+ tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld32s_i64:
+ tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_st32_i64:
+ tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+
+ case INDEX_op_add_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ do_addi_64:
+ if (a0 == a1) {
+ if (a2 == (int16_t)a2) {
+ tcg_out_insn(s, RI, AGHI, a0, a2);
+ break;
+ }
+ if (HAVE_FACILITY(EXT_IMM)) {
+ if (a2 == (int32_t)a2) {
+ tcg_out_insn(s, RIL, AGFI, a0, a2);
+ break;
+ } else if (a2 == (uint32_t)a2) {
+ tcg_out_insn(s, RIL, ALGFI, a0, a2);
+ break;
+ } else if (-a2 == (uint32_t)-a2) {
+ tcg_out_insn(s, RIL, SLGFI, a0, -a2);
+ break;
+ }
+ }
+ }
+ tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, AGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
+ }
+ break;
+ case INDEX_op_sub_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ a2 = -a2;
+ goto do_addi_64;
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, SGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, NGR, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_or_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_ori(s, TCG_TYPE_I64, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, OGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
+ }
+ break;
+ case INDEX_op_xor_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
+ tgen_xori(s, TCG_TYPE_I64, a0, a2);
+ } else if (a0 == a1) {
+ tcg_out_insn(s, RRE, XGR, a0, a2);
+ } else {
+ tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_neg_i64:
+ tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
+ break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
+ break;
+
+ case INDEX_op_mul_i64:
+ if (const_args[2]) {
+ if (args[2] == (int16_t)args[2]) {
+ tcg_out_insn(s, RI, MGHI, args[0], args[2]);
+ } else {
+ tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
+ }
+ break;
+
+ case INDEX_op_div2_i64:
+ /* ??? We get an unnecessary sign-extension of the dividend
+ into R3 with this definition, but as we do in fact always
+ produce both quotient and remainder using INDEX_op_div_i64
+ instead requires jumping through even more hoops. */
+ tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_divu2_i64:
+ tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
+ break;
+ case INDEX_op_mulu2_i64:
+ tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
+ break;
+
+ case INDEX_op_shl_i64:
+ op = RSY_SLLG;
+ do_shift64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_shr_i64:
+ op = RSY_SRLG;
+ goto do_shift64;
+ case INDEX_op_sar_i64:
+ op = RSY_SRAG;
+ goto do_shift64;
+
+ case INDEX_op_rotl_i64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
+ TCG_REG_NONE, args[2]);
+ } else {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
+ }
+ break;
+ case INDEX_op_rotr_i64:
+ if (const_args[2]) {
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
+ TCG_REG_NONE, (64 - args[2]) & 63);
+ } else {
+ /* We can use the smaller 32-bit negate because only the
+ low 6 bits are examined for the rotate. */
+ tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
+ tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
+ }
+ break;
+
+ case INDEX_op_ext8s_i64:
+ tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext16s_i64:
+ tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_ext32s_i64:
+ tgen_ext32s(s, args[0], args[1]);
+ break;
+ case INDEX_op_ext8u_i64:
+ tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ext16u_i64:
+ tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_ext32u_i64:
+ tgen_ext32u(s, args[0], args[1]);
+ break;
+
+ case INDEX_op_add2_i64:
+ if (const_args[4]) {
+ if ((int64_t)args[4] >= 0) {
+ tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
+ break;
+ case INDEX_op_sub2_i64:
+ if (const_args[4]) {
+ if ((int64_t)args[4] >= 0) {
+ tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
+ } else {
+ tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
+ }
+ } else {
+ tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
+ }
+ tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
+ break;
+
+ case INDEX_op_brcond_i64:
+ tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
+ args[1], const_args[1], arg_label(args[3]));
+ break;
+ case INDEX_op_setcond_i64:
+ tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
+ args[2], const_args[2]);
+ break;
+ case INDEX_op_movcond_i64:
+ tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
+ args[2], const_args[2], args[3], const_args[3]);
+ break;
+
+ OP_32_64(deposit):
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[1]) {
+ tgen_deposit(s, a0, a2, args[3], args[4], 1);
+ } else {
+ /* Since we can't support "0Z" as a constraint, we allow a1 in
+ any register. Fix things up as if a matching constraint. */
+ if (a0 != a1) {
+ TCGType type = (opc == INDEX_op_deposit_i64);
+ if (a0 == a2) {
+ tcg_out_mov(s, type, TCG_TMP0, a2);
+ a2 = TCG_TMP0;
+ }
+ tcg_out_mov(s, type, a0, a1);
+ }
+ tgen_deposit(s, a0, a2, args[3], args[4], 0);
+ }
+ break;
+
+ OP_32_64(extract):
+ tgen_extract(s, args[0], args[1], args[2], args[3]);
+ break;
+
+ case INDEX_op_clz_i64:
+ tgen_clz(s, args[0], args[1], args[2], const_args[2]);
+ break;
+
+ case INDEX_op_mb:
+ /* The host memory model is quite strong, we simply need to
+ serialize the instruction stream. */
+ if (args[0] & TCG_MO_ST_LD) {
+ tcg_out_insn(s, RR, BCR, HAVE_FACILITY(FAST_BCR_SER) ? 14 : 15, 0);
+ }
+ break;
+
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
+ case INDEX_op_call: /* Always emitted via tcg_out_call. */
+ default:
+ tcg_abort();
+ }
+}
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg src)
+{
+ if (is_general_reg(src)) {
+ /* Replicate general register into two MO_64. */
+ tcg_out_insn(s, VRRf, VLVGP, dst, src, src);
+ if (vece == MO_64) {
+ return true;
+ }
+ }
+
+ /*
+ * Recall that the "standard" integer, within a vector, is the
+ * rightmost element of the leftmost doubleword, a-la VLLEZ.
+ */
+ tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece);
+ return true;
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg base, intptr_t offset)
+{
+ tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece);
+ return true;
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, int64_t val)
+{
+ int i, mask, msb, lsb;
+
+ /* Look for int16_t elements. */
+ if (vece <= MO_16 ||
+ (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) {
+ tcg_out_insn(s, VRIa, VREPI, dst, val, vece);
+ return;
+ }
+
+ /* Look for bit masks. */
+ if (vece == MO_32) {
+ if (risbg_mask((int32_t)val)) {
+ /* Handle wraparound by swapping msb and lsb. */
+ if ((val & 0x80000001u) == 0x80000001u) {
+ msb = 32 - ctz32(~val);
+ lsb = clz32(~val) - 1;
+ } else {
+ msb = clz32(val);
+ lsb = 31 - ctz32(val);
+ }
+ tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
+ return;
+ }
+ } else {
+ if (risbg_mask(val)) {
+ /* Handle wraparound by swapping msb and lsb. */
+ if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
+ /* Handle wraparound by swapping msb and lsb. */
+ msb = 64 - ctz64(~val);
+ lsb = clz64(~val) - 1;
+ } else {
+ msb = clz64(val);
+ lsb = 63 - ctz64(val);
+ }
+ tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
+ return;
+ }
+ }
+
+ /* Look for all bytes 0x00 or 0xff. */
+ for (i = mask = 0; i < 8; i++) {
+ uint8_t byte = val >> (i * 8);
+ if (byte == 0xff) {
+ mask |= 1 << i;
+ } else if (byte != 0) {
+ break;
+ }
+ }
+ if (i == 8) {
+ tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0);
+ return;
+ }
+
+ /* Otherwise, stuff it in the constant pool. */
+ tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0);
+ new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2);
+ tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64);
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ TCGType type = vecl + TCG_TYPE_V64;
+ TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ break;
+
+ case INDEX_op_abs_vec:
+ tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
+ break;
+ case INDEX_op_neg_vec:
+ tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
+ break;
+ case INDEX_op_not_vec:
+ tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
+ break;
+
+ case INDEX_op_add_vec:
+ tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
+ break;
+ case INDEX_op_sub_vec:
+ tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece);
+ break;
+ case INDEX_op_and_vec:
+ tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
+ break;
+ case INDEX_op_andc_vec:
+ tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
+ break;
+ case INDEX_op_mul_vec:
+ tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece);
+ break;
+ case INDEX_op_or_vec:
+ tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
+ break;
+ case INDEX_op_orc_vec:
+ tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
+ break;
+ case INDEX_op_xor_vec:
+ tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
+ break;
+
+ case INDEX_op_shli_vec:
+ tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
+ break;
+ case INDEX_op_shri_vec:
+ tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece);
+ break;
+ case INDEX_op_sari_vec:
+ tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece);
+ break;
+ case INDEX_op_rotli_vec:
+ tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece);
+ break;
+ case INDEX_op_shls_vec:
+ tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece);
+ break;
+ case INDEX_op_shrs_vec:
+ tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece);
+ break;
+ case INDEX_op_sars_vec:
+ tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece);
+ break;
+ case INDEX_op_rotls_vec:
+ tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece);
+ break;
+ case INDEX_op_shlv_vec:
+ tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece);
+ break;
+ case INDEX_op_shrv_vec:
+ tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece);
+ break;
+ case INDEX_op_sarv_vec:
+ tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece);
+ break;
+ case INDEX_op_rotlv_vec:
+ tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
+ break;
+
+ case INDEX_op_smin_vec:
+ tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece);
+ break;
+ case INDEX_op_smax_vec:
+ tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece);
+ break;
+ case INDEX_op_umin_vec:
+ tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece);
+ break;
+ case INDEX_op_umax_vec:
+ tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
+ break;
+
+ case INDEX_op_bitsel_vec:
+ tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+ break;
+
+ case INDEX_op_cmp_vec:
+ switch ((TCGCond)args[3]) {
+ case TCG_COND_EQ:
+ tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece);
+ break;
+ case TCG_COND_GT:
+ tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_s390_vuph_vec:
+ tcg_out_insn(s, VRRa, VUPH, a0, a1, vece);
+ break;
+ case INDEX_op_s390_vupl_vec:
+ tcg_out_insn(s, VRRa, VUPL, a0, a1, vece);
+ break;
+ case INDEX_op_s390_vpks_vec:
+ tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece);
+ break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_abs_vec:
+ case INDEX_op_add_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_bitsel_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_rotli_vec:
+ case INDEX_op_rotls_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_sars_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shls_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_shrs_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_xor_vec:
+ return 1;
+ case INDEX_op_cmp_vec:
+ case INDEX_op_cmpsel_vec:
+ case INDEX_op_rotrv_vec:
+ return -1;
+ case INDEX_op_mul_vec:
+ return vece < MO_64;
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ return vece < MO_64 ? -1 : 0;
+ default:
+ return 0;
+ }
+}
+
+static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ bool need_swap = false, need_inv = false;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ break;
+ case TCG_COND_NE:
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ need_inv = true;
+ break;
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ need_swap = true;
+ break;
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ need_swap = need_inv = true;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (need_inv) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (need_swap) {
+ TCGv_vec t1;
+ t1 = v1, v1 = v2, v2 = t1;
+ cond = tcg_swap_cond(cond);
+ }
+
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
+
+ return need_inv;
+}
+
+static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+}
+
+static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec c1, TCGv_vec c2,
+ TCGv_vec v3, TCGv_vec v4, TCGCond cond)
+{
+ TCGv_vec t = tcg_temp_new_vec(type);
+
+ if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
+ /* Invert the sense of the compare by swapping arguments. */
+ tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
+ } else {
+ tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
+ }
+ tcg_temp_free_vec(t);
+}
+
+static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
+{
+ TCGv_vec h1 = tcg_temp_new_vec(type);
+ TCGv_vec h2 = tcg_temp_new_vec(type);
+ TCGv_vec l1 = tcg_temp_new_vec(type);
+ TCGv_vec l2 = tcg_temp_new_vec(type);
+
+ tcg_debug_assert (vece < MO_64);
+
+ /* Unpack with sign-extension. */
+ vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
+ tcgv_vec_arg(h1), tcgv_vec_arg(v1));
+ vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
+ tcgv_vec_arg(h2), tcgv_vec_arg(v2));
+
+ vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
+ tcgv_vec_arg(l1), tcgv_vec_arg(v1));
+ vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
+ tcgv_vec_arg(l2), tcgv_vec_arg(v2));
+
+ /* Arithmetic on a wider element size. */
+ vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1),
+ tcgv_vec_arg(h1), tcgv_vec_arg(h2));
+ vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1),
+ tcgv_vec_arg(l1), tcgv_vec_arg(l2));
+
+ /* Pack with saturation. */
+ vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1,
+ tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1));
+
+ tcg_temp_free_vec(h1);
+ tcg_temp_free_vec(h2);
+ tcg_temp_free_vec(l1);
+ tcg_temp_free_vec(l2);
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGv_vec v0, v1, v2, v3, v4, t0;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+
+ switch (opc) {
+ case INDEX_op_cmp_vec:
+ expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
+ break;
+
+ case INDEX_op_cmpsel_vec:
+ v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
+ break;
+
+ case INDEX_op_rotrv_vec:
+ t0 = tcg_temp_new_vec(type);
+ tcg_gen_neg_vec(vece, t0, v2);
+ tcg_gen_rotlv_vec(vece, v0, v1, t0);
+ tcg_temp_free_vec(t0);
+ break;
+
+ case INDEX_op_ssadd_vec:
+ expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec);
+ break;
+ case INDEX_op_sssub_vec:
+ expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ va_end(va);
+}
+
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+{
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return C_O0_I1(r);
+
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ return C_O1_I1(r, r);
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return C_O0_I2(r, r);
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
+
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ return (HAVE_FACILITY(DISTINCT_OPS)
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
+
+ case INDEX_op_mul_i32:
+ /* If we have the general-instruction-extensions, then we have
+ MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
+ have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
+ return (HAVE_FACILITY(GEN_INST_EXT)
+ ? C_O1_I2(r, 0, ri)
+ : C_O1_I2(r, 0, rI));
+
+ case INDEX_op_mul_i64:
+ return (HAVE_FACILITY(GEN_INST_EXT)
+ ? C_O1_I2(r, 0, rJ)
+ : C_O1_I2(r, 0, rI));
+
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ return (HAVE_FACILITY(DISTINCT_OPS)
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return C_O0_I2(r, ri);
+
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
+ return C_O1_I1(r, r);
+
+ case INDEX_op_qemu_ld_i32:
+ case INDEX_op_qemu_ld_i64:
+ return C_O1_I1(r, L);
+ case INDEX_op_qemu_st_i64:
+ case INDEX_op_qemu_st_i32:
+ return C_O0_I2(L, L);
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return C_O1_I2(r, rZ, r);
+
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return (HAVE_FACILITY(LOAD_ON_COND2)
+ ? C_O1_I4(r, r, ri, rI, 0)
+ : C_O1_I4(r, r, ri, r, 0));
+
+ case INDEX_op_div2_i32:
+ case INDEX_op_div2_i64:
+ case INDEX_op_divu2_i32:
+ case INDEX_op_divu2_i64:
+ return C_O2_I3(b, a, 0, 1, r);
+
+ case INDEX_op_mulu2_i64:
+ return C_O2_I2(b, a, 0, r);
+
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return (HAVE_FACILITY(EXT_IMM)
+ ? C_O2_I4(r, r, 0, 1, ri, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
+
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i64:
+ return (HAVE_FACILITY(EXT_IMM)
+ ? C_O2_I4(r, r, 0, 1, rA, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
+
+ case INDEX_op_st_vec:
+ return C_O0_I2(v, r);
+ case INDEX_op_ld_vec:
+ case INDEX_op_dupm_vec:
+ return C_O1_I1(v, r);
+ case INDEX_op_dup_vec:
+ return C_O1_I1(v, vr);
+ case INDEX_op_abs_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ case INDEX_op_rotli_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_s390_vuph_vec:
+ case INDEX_op_s390_vupl_vec:
+ return C_O1_I1(v, v);
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ case INDEX_op_s390_vpks_vec:
+ return C_O1_I2(v, v, v);
+ case INDEX_op_rotls_vec:
+ case INDEX_op_shls_vec:
+ case INDEX_op_shrs_vec:
+ case INDEX_op_sars_vec:
+ return C_O1_I2(v, v, r);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(v, v, v, v);
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/*
+ * Mainline glibc added HWCAP_S390_VX before it was kernel abi.
+ * Some distros have fixed this up locally, others have not.
+ */
+#ifndef HWCAP_S390_VXRS
+#define HWCAP_S390_VXRS 2048
+#endif
+
+static void query_s390_facilities(void)
+{
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+
+ /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
+ is present on all 64-bit systems, but let's check for it anyway. */
+ if (hwcap & HWCAP_S390_STFLE) {
+ register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1;
+ register void *r1 __asm__("1") = s390_facilities;
+
+ /* stfle 0(%r1) */
+ asm volatile(".word 0xb2b0,0x1000"
+ : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc");
+ }
+
+ /*
+ * Use of vector registers requires os support beyond the facility bit.
+ * If the kernel does not advertise support, disable the facility bits.
+ * There is nothing else we currently care about in the 3rd word, so
+ * disable VECTOR with one store.
+ */
+ if (!(hwcap & HWCAP_S390_VXRS)) {
+ s390_facilities[2] = 0;
+ }
+}
+
+static void tcg_target_init(TCGContext *s)
+{
+ query_s390_facilities();
+
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
+ if (HAVE_FACILITY(VECTOR)) {
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
+ }
+
+ tcg_target_call_clobber_regs = 0;
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
+ /* The r6 register is technically call-saved, but it's also a parameter
+ register, so it can get killed by setup for the qemu_st helper. */
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
+ /* The return register can be considered call-clobbered. */
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
+
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
+
+ s->reserved_regs = 0;
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
+ /* XXX many insns can't be used with R0, so we better avoid it for now */
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
+ if (USE_REG_TB) {
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
+ }
+}
+
+#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long)))
+
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+ /* stmg %r6,%r15,48(%r15) (save registers) */
+ tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
+
+ /* aghi %r15,-frame_size */
+ tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
+
+ tcg_set_frame(s, TCG_REG_CALL_STACK,
+ TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
+ CPU_TEMP_BUF_NLONGS * sizeof(long));
+
+#ifndef CONFIG_SOFTMMU
+ if (guest_base >= 0x80000) {
+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+ if (USE_REG_TB) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,
+ tcg_target_call_iarg_regs[1]);
+ }
+
+ /* br %r3 (go to TB) */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
+
+ /*
+ * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
+ * and fall through to the rest of the epilogue.
+ */
+ tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
+
+ /* TB epilogue */
+ tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
+
+ /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
+ tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
+ FRAME_SIZE + 48);
+
+ /* br %r14 (return) */
+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
+}
+
+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
+{
+ memset(p, 0x07, count * sizeof(tcg_insn_unit));
+}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[18];
+} DebugFrame;
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+#define ELF_HOST_MACHINE EM_S390
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = 8, /* sleb128 8 */
+ .h.cie.return_column = TCG_REG_R14,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x86, 6, /* DW_CFA_offset, %r6, 48 */
+ 0x87, 7, /* DW_CFA_offset, %r7, 56 */
+ 0x88, 8, /* DW_CFA_offset, %r8, 64 */
+ 0x89, 9, /* DW_CFA_offset, %r92, 72 */
+ 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
+ 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
+ 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
+ 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
+ 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
+ }
+};
+
+void tcg_register_jit(const void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
--- /dev/null
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef S390_TCG_TARGET_H
+#define S390_TCG_TARGET_H
+
+#define TCG_TARGET_INSN_UNIT_SIZE 2
+#define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
+
+/* We have a +- 4GB range on the branches; leave some slop. */
+#define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB)
+
+typedef enum TCGReg {
+ TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
+ TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
+ TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
+ TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
+
+ TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
+ TCG_AREG0 = TCG_REG_R10,
+ TCG_REG_CALL_STACK = TCG_REG_R15
+} TCGReg;
+
+#define TCG_TARGET_NB_REGS 64
+
+/* A list of relevant facilities used by this translator. Some of these
+ are required for proper operation, and these are checked at startup. */
+
+#define FACILITY_ZARCH_ACTIVE 2
+#define FACILITY_LONG_DISP 18
+#define FACILITY_EXT_IMM 21
+#define FACILITY_GEN_INST_EXT 34
+#define FACILITY_LOAD_ON_COND 45
+#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
+#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
+#define FACILITY_LOAD_ON_COND2 53
+#define FACILITY_VECTOR 129
+#define FACILITY_VECTOR_ENH1 135
+
+extern uint64_t s390_facilities[3];
+
+#define HAVE_FACILITY(X) \
+ ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
+
+/* optional instructions */
+#define TCG_TARGET_HAS_div2_i32 1
+#define TCG_TARGET_HAS_rot_i32 1
+#define TCG_TARGET_HAS_ext8s_i32 1
+#define TCG_TARGET_HAS_ext16s_i32 1
+#define TCG_TARGET_HAS_ext8u_i32 1
+#define TCG_TARGET_HAS_ext16u_i32 1
+#define TCG_TARGET_HAS_bswap16_i32 1
+#define TCG_TARGET_HAS_bswap32_i32 1
+#define TCG_TARGET_HAS_not_i32 0
+#define TCG_TARGET_HAS_neg_i32 1
+#define TCG_TARGET_HAS_andc_i32 0
+#define TCG_TARGET_HAS_orc_i32 0
+#define TCG_TARGET_HAS_eqv_i32 0
+#define TCG_TARGET_HAS_nand_i32 0
+#define TCG_TARGET_HAS_nor_i32 0
+#define TCG_TARGET_HAS_clz_i32 0
+#define TCG_TARGET_HAS_ctz_i32 0
+#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT)
+#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT)
+#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
+#define TCG_TARGET_HAS_mulu2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muluh_i32 0
+#define TCG_TARGET_HAS_mulsh_i32 0
+#define TCG_TARGET_HAS_extrl_i64_i32 0
+#define TCG_TARGET_HAS_extrh_i64_i32 0
+#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT)
+#define TCG_TARGET_HAS_qemu_st8_i32 0
+
+#define TCG_TARGET_HAS_div2_i64 1
+#define TCG_TARGET_HAS_rot_i64 1
+#define TCG_TARGET_HAS_ext8s_i64 1
+#define TCG_TARGET_HAS_ext16s_i64 1
+#define TCG_TARGET_HAS_ext32s_i64 1
+#define TCG_TARGET_HAS_ext8u_i64 1
+#define TCG_TARGET_HAS_ext16u_i64 1
+#define TCG_TARGET_HAS_ext32u_i64 1
+#define TCG_TARGET_HAS_bswap16_i64 1
+#define TCG_TARGET_HAS_bswap32_i64 1
+#define TCG_TARGET_HAS_bswap64_i64 1
+#define TCG_TARGET_HAS_not_i64 0
+#define TCG_TARGET_HAS_neg_i64 1
+#define TCG_TARGET_HAS_andc_i64 0
+#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_nand_i64 0
+#define TCG_TARGET_HAS_nor_i64 0
+#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM)
+#define TCG_TARGET_HAS_ctz_i64 0
+#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT)
+#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT)
+#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
+#define TCG_TARGET_HAS_add2_i64 1
+#define TCG_TARGET_HAS_sub2_i64 1
+#define TCG_TARGET_HAS_mulu2_i64 1
+#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muluh_i64 0
+#define TCG_TARGET_HAS_mulsh_i64 0
+
+#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR)
+#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_not_vec 1
+#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_abs_vec 1
+#define TCG_TARGET_HAS_roti_vec 1
+#define TCG_TARGET_HAS_rots_vec 1
+#define TCG_TARGET_HAS_rotv_vec 1
+#define TCG_TARGET_HAS_shi_vec 1
+#define TCG_TARGET_HAS_shs_vec 1
+#define TCG_TARGET_HAS_shv_vec 1
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
+#define TCG_TARGET_HAS_bitsel_vec 1
+#define TCG_TARGET_HAS_cmpsel_vec 0
+
+/* used for function call generation */
+#define TCG_TARGET_STACK_ALIGN 8
+#define TCG_TARGET_CALL_STACK_OFFSET 160
+
+#define TCG_TARGET_EXTEND_ARGS 1
+#define TCG_TARGET_HAS_MEMORY_BSWAP 1
+
+#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
+static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
+ uintptr_t jmp_rw, uintptr_t addr)
+{
+ /* patch the branch destination */
+ intptr_t disp = addr - (jmp_rx - 2);
+ qatomic_set((int32_t *)jmp_rw, disp / 2);
+ /* no need to flush icache explicitly */
+}
+
+#ifdef CONFIG_SOFTMMU
+#define TCG_TARGET_NEED_LDST_LABELS
+#endif
+#define TCG_TARGET_NEED_POOL_LABELS
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2021 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion. These will be
+ * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
+DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC)
+DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC)
+DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC)
}
#ifdef CONFIG_SOFTMMU
-static const tcg_insn_unit *qemu_ld_trampoline[16];
-static const tcg_insn_unit *qemu_st_trampoline[16];
+static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1];
+static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1];
static void emit_extend(TCGContext *s, TCGReg r, int op)
{
static void build_trampolines(TCGContext *s)
{
- static void * const qemu_ld_helpers[16] = {
+ static void * const qemu_ld_helpers[] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_BEUL] = helper_be_ldul_mmu,
[MO_BEQ] = helper_be_ldq_mmu,
};
- static void * const qemu_st_helpers[16] = {
+ static void * const qemu_st_helpers[] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
int i;
TCGReg ra;
- for (i = 0; i < 16; ++i) {
+ for (i = 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) {
if (qemu_ld_helpers[i] == NULL) {
continue;
}
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
}
- for (i = 0; i < 16; ++i) {
+ for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) {
if (qemu_st_helpers[i] == NULL) {
continue;
}
}
#endif /* CONFIG_SOFTMMU */
-static const int qemu_ld_opc[16] = {
+static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = {
[MO_UB] = LDUB,
[MO_SB] = LDSB,
[MO_LEQ] = LDX_LE,
};
-static const int qemu_st_opc[16] = {
+static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = STB,
[MO_BEUW] = STH,
};
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi, bool is_64)
+ MemOpIdx oi, bool is_64)
{
MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
typedef struct TCGLabelQemuLdst {
bool is_ld; /* qemu_ld: true, qemu_st: false */
- TCGMemOpIdx oi;
+ MemOpIdx oi;
TCGType type; /* result type of a load */
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
continue;
}
break;
+ case INDEX_op_usadd_vec:
+ if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) ||
+ tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) {
+ continue;
+ }
+ break;
+ case INDEX_op_ussub_vec:
+ if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) ||
+ tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) {
+ continue;
+ }
+ break;
case INDEX_op_cmpsel_vec:
case INDEX_op_smin_vec:
case INDEX_op_smax_vec:
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec);
+ if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) {
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+
+ /* usadd(a, b) = min(a, ~b) + b */
+ tcg_gen_not_vec(vece, t, b);
+ tcg_gen_umin_vec(vece, t, t, a);
+ tcg_gen_add_vec(vece, r, t, b);
+
+ tcg_temp_free_vec(t);
+ tcg_swap_vecop_list(hold_list);
+ }
}
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec);
+ if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) {
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+
+ /* ussub(a, b) = max(a, b) - b */
+ tcg_gen_umax_vec(vece, t, a, b);
+ tcg_gen_sub_vec(vece, r, t, b);
+
+ tcg_temp_free_vec(t);
+ tcg_swap_vecop_list(hold_list);
+ }
}
static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a,
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "trace-tcg.h"
-#include "trace/mem.h"
#include "exec/plugin-gen.h"
/* Reduce the number of ifdefs below. This assumes that all uses of
}
break;
case MO_64:
- if (!is64) {
- tcg_abort();
+ if (is64) {
+ op &= ~MO_SIGN;
+ break;
}
- break;
+ /* fall through */
+ default:
+ g_assert_not_reached();
}
if (st) {
op &= ~MO_SIGN;
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
MemOp memop, TCGArg idx)
{
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ MemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
tcg_gen_op3i_i32(opc, val, addr, oi);
#else
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
MemOp memop, TCGArg idx)
{
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ MemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
return vaddr;
}
-static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
+static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi,
+ enum qemu_plugin_mem_rw rw)
{
#ifdef CONFIG_PLUGIN
if (tcg_ctx->plugin_insn != NULL) {
+ qemu_plugin_meminfo_t info = make_plugin_meminfo(oi, rw);
plugin_gen_empty_mem_callback(vaddr, info);
tcg_temp_free(vaddr);
}
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
- uint16_t info = trace_mem_get_info(memop, idx, 0);
+ MemOpIdx oi;
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ oi = make_memop_idx(memop, idx);
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i32 swap = NULL;
- uint16_t info = trace_mem_get_info(memop, idx, 1);
+ MemOpIdx oi;
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ oi = make_memop_idx(memop, idx);
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
swap = tcg_temp_new_i32();
} else {
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
}
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
if (swap) {
tcg_temp_free_i32(swap);
void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
- uint16_t info;
+ MemOpIdx oi;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 1, 0);
- info = trace_mem_get_info(memop, idx, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ oi = make_memop_idx(memop, idx);
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
if ((orig_memop ^ memop) & MO_BSWAP) {
int flags = (orig_memop & MO_SIGN
void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i64 swap = NULL;
- uint16_t info;
+ MemOpIdx oi;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 1, 1);
- info = trace_mem_get_info(memop, idx, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ oi = make_memop_idx(memop, idx);
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
swap = tcg_temp_new_i64();
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
if (swap) {
tcg_temp_free_i64(swap);
# define WITH_ATOMIC64(X)
#endif
-static void * const table_cmpxchg[16] = {
+static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_8] = gen_helper_atomic_cmpxchgb,
[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
tcg_temp_free_i32(t1);
} else {
gen_atomic_cx_i32 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
} else if ((memop & MO_SIZE) == MO_64) {
#ifdef CONFIG_ATOMIC64
gen_atomic_cx_i64 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
TCGArg idx, MemOp memop, void * const table[])
{
gen_atomic_op_i32 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
memop = tcg_canonicalize_memop(memop, 0, 0);
if ((memop & MO_SIZE) == MO_64) {
#ifdef CONFIG_ATOMIC64
gen_atomic_op_i64 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
}
#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \
-static void * const table_##NAME[16] = { \
+static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] = { \
[MO_8] = gen_helper_atomic_##NAME##b, \
[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
{
- TCGMemOpIdx oi = op->args[k++];
+ MemOpIdx oi = op->args[k++];
MemOp op = get_memop(oi);
unsigned ix = get_mmuidx(oi);
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
* l = label or pointer
- * m = immediate (TCGMemOpIdx)
+ * m = immediate (MemOpIdx)
* n = immediate (call return length)
* r = register
* s = signed ldst offset
}
static void tci_args_rrm(uint32_t insn, TCGReg *r0,
- TCGReg *r1, TCGMemOpIdx *m2)
+ TCGReg *r1, MemOpIdx *m2)
{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
}
static void tci_args_rrrm(uint32_t insn,
- TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
}
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
- TCGMemOpIdx oi, const void *tb_ptr)
+ MemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
uintptr_t ra = (uintptr_t)tb_ptr;
}
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
- TCGMemOpIdx oi, const void *tb_ptr)
+ MemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
uintptr_t ra = (uintptr_t)tb_ptr;
uint32_t tmp32;
uint64_t tmp64;
uint64_t T1, T2;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
int32_t ofs;
void *ptr;
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
uint8_t pos, len;
void *ptr;
DOCKER_PARTIAL_IMAGES += debian-sh4-cross debian-sparc64-cross
DOCKER_PARTIAL_IMAGES += debian-tricore-cross
DOCKER_PARTIAL_IMAGES += debian-xtensa-cross
-DOCKER_PARTIAL_IMAGES += fedora-i386-cross fedora-cris-cross
+DOCKER_PARTIAL_IMAGES += fedora-cris-cross
# Rules for building linux-user powered images
#
-FROM registry.fedoraproject.org/fedora:33
+FROM registry.fedoraproject.org/fedora:34
+
ENV PACKAGES \
bzip2 \
ccache \
glibc-static.i686 \
gnutls-devel.i686 \
nettle-devel.i686 \
+ pcre-devel.i686 \
perl-Test-Harness \
pixman-devel.i686 \
+ sysprof-capture-devel.i686 \
zlib-devel.i686
-ENV QEMU_CONFIGURE_OPTS --extra-cflags=-m32 --disable-vhost-user
-ENV PKG_CONFIG_PATH /usr/lib/pkgconfig
+ENV QEMU_CONFIGURE_OPTS --cpu=i386 --disable-vhost-user
+ENV PKG_CONFIG_LIBDIR /usr/lib/pkgconfig
-RUN dnf install -y $PACKAGES
+RUN dnf update -y && dnf install -y $PACKAGES
RUN rpm -q $PACKAGES | sort > /packages.txt
test_env = environment()
-test_env.set('PYTHONPATH', meson.source_root() / 'scripts')
+test_env.set('PYTHONPATH', meson.project_source_root() / 'scripts')
test_env.set('PYTHONIOENCODING', 'utf-8')
schemas = [
# clutter up the build dir with the cache.
command: [SPHINX_ARGS,
'-b', 'text', '-E',
- '-c', meson.source_root() / 'docs',
+ '-c', meson.project_source_root() / 'docs',
'-D', 'master_doc=doc-good',
meson.current_source_dir(),
meson.current_build_dir()])
import iotests
from iotests import qemu_img_create, qemu_io, file_path, log
-sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python'))
-
from qemu.machine import QEMUMachine
iotests.script_initialize(supported_fmts=['qcow2'])
# Todo notes are fine, but fixme's or xxx's should probably just be
# fixed (in tests, at least)
env = os.environ.copy()
- qemu_module_path = os.path.join(os.path.dirname(__file__),
- '..', '..', 'python')
- try:
- env['PYTHONPATH'] += os.pathsep + qemu_module_path
- except KeyError:
- env['PYTHONPATH'] = qemu_module_path
subprocess.run(('pylint-3', '--score=n', '--notes=FIXME,XXX', *files),
env=env, check=False)
print('=== mypy ===')
sys.stdout.flush()
- # We have to call mypy separately for each file. Otherwise, it
- # will interpret all given files as belonging together (i.e., they
- # may not both define the same classes, etc.; most notably, they
- # must not both define the __main__ module).
env['MYPYPATH'] = env['PYTHONPATH']
- for filename in files:
- p = subprocess.run(('mypy',
- '--warn-unused-configs',
- '--disallow-subclassing-any',
- '--disallow-any-generics',
- '--disallow-incomplete-defs',
- '--disallow-untyped-decorators',
- '--no-implicit-optional',
- '--warn-redundant-casts',
- '--warn-unused-ignores',
- '--no-implicit-reexport',
- '--namespace-packages',
- filename),
- env=env,
- check=False,
- stdout=subprocess.PIPE,
- stderr=subprocess.STDOUT,
- universal_newlines=True)
-
- if p.returncode != 0:
- print(p.stdout)
+ p = subprocess.run(('mypy',
+ '--warn-unused-configs',
+ '--disallow-subclassing-any',
+ '--disallow-any-generics',
+ '--disallow-incomplete-defs',
+ '--disallow-untyped-decorators',
+ '--no-implicit-optional',
+ '--warn-redundant-casts',
+ '--warn-unused-ignores',
+ '--no-implicit-reexport',
+ '--namespace-packages',
+ '--scripts-are-modules',
+ *files),
+ env=env,
+ check=False,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT,
+ universal_newlines=True)
+
+ if p.returncode != 0:
+ print(p.stdout)
for linter in ('pylint-3', 'mypy'):
import re
from typing import Dict, List, Optional
+from qemu.machine import machine
+
import iotests
-# Import qemu after iotests.py has amended sys.path
-# pylint: disable=wrong-import-order
-from qemu.machine import machine
BlockBitmapMapping = List[Dict[str, object]]
from contextlib import contextmanager
-# pylint: disable=import-error, wrong-import-position
-sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python'))
from qemu.machine import qtest
from qemu.qmp import QMPMessage
too-many-public-methods,
# pylint warns about Optional[] etc. as unsubscriptable in 3.9
unsubscriptable-object,
+ # pylint's static analysis causes false positivies for file_path();
+ # If we really care to make it statically knowable, we'll use mypy.
+ unbalanced-tuple-unpacking,
# Sometimes we need to disable a newly introduced pylint warning.
# Doing so should not produce a warning in older versions of pylint.
bad-option-value,
# These are temporary, and should be removed:
missing-docstring,
too-many-return-statements,
- too-many-statements
+ too-many-statements,
+ consider-using-f-string,
[FORMAT]
SAMPLE_IMG_DIR
OUTPUT_DIR
"""
- self.pythonpath = os.getenv('PYTHONPATH')
- if self.pythonpath:
- self.pythonpath = self.source_iotests + os.pathsep + \
- self.pythonpath
- else:
- self.pythonpath = self.source_iotests
+
+ # Path where qemu goodies live in this source tree.
+ qemu_srctree_path = Path(__file__, '../../../python').resolve()
+
+ self.pythonpath = os.pathsep.join(filter(None, (
+ self.source_iotests,
+ str(qemu_srctree_path),
+ os.getenv('PYTHONPATH'),
+ )))
self.test_dir = os.getenv('TEST_DIR',
os.path.join(os.getcwd(), 'scratch'))
diff=file_diff(str(f_reference), str(f_bad)))
if f_notrun.exists():
- return TestResult(status='not run',
- description=f_notrun.read_text().strip())
+ return TestResult(
+ status='not run',
+ description=f_notrun.read_text(encoding='utf-8').strip())
casenotrun = ''
if f_casenotrun.exists():
- casenotrun = f_casenotrun.read_text()
+ casenotrun = f_casenotrun.read_text(encoding='utf-8')
diff = file_diff(str(f_reference), str(f_bad))
if diff:
iotests.script_initialize(
supported_fmts=['qcow2', 'qcow', 'qed', 'vmdk', 'vhdx', 'raw'],
supported_platforms=['linux'],
+ required_fmts=['copy-before-write'],
)
patterns = [('0x5d', '0', '64k'),
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-import os
import itertools
import operator
+import os
import re
+
import iotests
from iotests import qemu_img, qemu_img_create, Timeout
setattr(klass, 'test_' + method + suffix, lambda self: mc(self))
-for cmb in list(itertools.product((True, False), repeat=5)):
- name = ('_' if cmb[0] else '_not_') + 'persistent_'
- name += ('_' if cmb[1] else '_not_') + 'migbitmap_'
- name += '_online' if cmb[2] else '_offline'
- name += '_shared' if cmb[3] else '_nonshared'
- if cmb[4]:
- name += '__pre_shutdown'
-
- inject_test_case(TestDirtyBitmapMigration, name, 'do_test_migration',
- *list(cmb))
-
-for cmb in list(itertools.product((True, False), repeat=2)):
- name = ('_' if cmb[0] else '_not_') + 'persistent_'
- name += ('_' if cmb[1] else '_not_') + 'migbitmap'
-
- inject_test_case(TestDirtyBitmapMigration, name,
- 'do_test_migration_resume_source', *list(cmb))
-
-
class TestDirtyBitmapBackingMigration(iotests.QMPTestCase):
def setUp(self):
qemu_img_create('-f', iotests.imgfmt, base_a, size)
self.assert_qmp(result, 'return', {})
+def main() -> None:
+ for cmb in list(itertools.product((True, False), repeat=5)):
+ name = ('_' if cmb[0] else '_not_') + 'persistent_'
+ name += ('_' if cmb[1] else '_not_') + 'migbitmap_'
+ name += '_online' if cmb[2] else '_offline'
+ name += '_shared' if cmb[3] else '_nonshared'
+ if cmb[4]:
+ name += '__pre_shutdown'
+
+ inject_test_case(TestDirtyBitmapMigration, name, 'do_test_migration',
+ *list(cmb))
+
+ for cmb in list(itertools.product((True, False), repeat=2)):
+ name = ('_' if cmb[0] else '_not_') + 'persistent_'
+ name += ('_' if cmb[1] else '_not_') + 'migbitmap'
+
+ inject_test_case(TestDirtyBitmapMigration, name,
+ 'do_test_migration_resume_source', *list(cmb))
+
+ iotests.main(
+ supported_fmts=['qcow2'],
+ supported_protocols=['file']
+ )
+
+
if __name__ == '__main__':
- iotests.main(supported_fmts=['qcow2'],
- supported_protocols=['file'])
+ main()
#
import os
+
+from qemu import qmp
+from qemu.machine import machine
+
import iotests
from iotests import qemu_img
-# Import qemu after iotests.py has amended sys.path
-# pylint: disable=wrong-import-order
-import qemu
-
image_size = 1 * 1024 * 1024
source = os.path.join(iotests.test_dir, 'source.img')
def tearDown(self):
try:
self.vm.shutdown()
- except qemu.machine.machine.AbnormalShutdown:
+ except machine.AbnormalShutdown:
pass
if self.vm_b is not None:
self.vm_b.launch()
print('ERROR: VM B launched successfully, this should not have '
'happened')
- except qemu.qmp.QMPConnectError:
+ except qmp.QMPConnectError:
assert 'Is another process using the image' in self.vm_b.get_log()
result = self.vm.qmp('block-job-cancel',
qtest_env.set('QTEST_QEMU_IMG', './qemu-img')
test_deps += [qemu_img]
endif
- qtest_env.set('G_TEST_DBUS_DAEMON', meson.source_root() / 'tests/dbus-vmstate-daemon.sh')
+ qtest_env.set('G_TEST_DBUS_DAEMON', meson.project_source_root() / 'tests/dbus-vmstate-daemon.sh')
qtest_env.set('QTEST_QEMU_BINARY', './qemu-system-' + target_base)
if have_tools and have_vhost_user_blk_server
qtest_env.set('QTEST_QEMU_STORAGE_DAEMON_BINARY', './storage-daemon/qemu-storage-daemon')
$(CC) -static -mv67 -nostdlib $^ -o $@
HEX_TESTS = first
+HEX_TESTS += hex_sigsegv
HEX_TESTS += misc
HEX_TESTS += preg_alias
HEX_TESTS += dual_stores
--- /dev/null
+/*
+ * Copyright(c) 2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Test the VLIW semantics of two stores in a packet
+ *
+ * When a packet has 2 stores, either both commit or neither commit.
+ * We test this with a packet that does stores to both NULL and a global
+ * variable, "should_not_change". After the SIGSEGV is caught, we check
+ * that the "should_not_change" value is the same.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <setjmp.h>
+#include <signal.h>
+
+typedef unsigned char uint8_t;
+
+int err;
+int segv_caught;
+
+#define SHOULD_NOT_CHANGE_VAL 5
+int should_not_change = SHOULD_NOT_CHANGE_VAL;
+
+#define BUF_SIZE 300
+unsigned char buf[BUF_SIZE];
+
+
+static void __check(const char *filename, int line, int x, int expect)
+{
+ if (x != expect) {
+ printf("ERROR %s:%d - %d != %d\n",
+ filename, line, x, expect);
+ err++;
+ }
+}
+
+#define check(x, expect) __check(__FILE__, __LINE__, (x), (expect))
+
+static void __chk_error(const char *filename, int line, int ret)
+{
+ if (ret < 0) {
+ printf("ERROR %s:%d - %d\n", filename, line, ret);
+ err++;
+ }
+}
+
+#define chk_error(ret) __chk_error(__FILE__, __LINE__, (ret))
+
+jmp_buf jmp_env;
+
+static void sig_segv(int sig, siginfo_t *info, void *puc)
+{
+ check(sig, SIGSEGV);
+ segv_caught = 1;
+ longjmp(jmp_env, 1);
+}
+
+int main()
+{
+ struct sigaction act;
+
+ /* SIGSEGV test */
+ act.sa_sigaction = sig_segv;
+ sigemptyset(&act.sa_mask);
+ act.sa_flags = SA_SIGINFO;
+ chk_error(sigaction(SIGSEGV, &act, NULL));
+ if (setjmp(jmp_env) == 0) {
+ asm volatile("r18 = ##should_not_change\n\t"
+ "r19 = #0\n\t"
+ "{\n\t"
+ " memw(r18) = #7\n\t"
+ " memw(r19) = #0\n\t"
+ "}\n\t"
+ : : : "r18", "r19", "memory");
+ }
+
+ act.sa_handler = SIG_DFL;
+ sigemptyset(&act.sa_mask);
+ act.sa_flags = 0;
+ chk_error(sigaction(SIGSEGV, &act, NULL));
+
+ check(segv_caught, 1);
+ check(should_not_change, SHOULD_NOT_CHANGE_VAL);
+
+ puts(err ? "FAIL" : "PASS");
+ return err ? EXIT_FAILURE : EXIT_SUCCESS;
+}
'test-keyval': [testqapi],
'test-logging': [],
'test-uuid': [],
- 'ptimer-test': ['ptimer-test-stubs.c', meson.source_root() / 'hw/core/ptimer.c'],
+ 'ptimer-test': ['ptimer-test-stubs.c', meson.project_source_root() / 'hw/core/ptimer.c'],
'test-qapi-util': [],
}
# tcg/tcg-op.c
# @vaddr: Access' virtual address.
-# @info : Access' information (see below).
+# @memopidx: Access' information (see below).
#
# Start virtual memory access (before any potential access violation).
-#
# Does not include memory accesses performed by devices.
#
-# Access information can be parsed as:
-#
-# struct mem_info {
-# uint8_t size_shift : 4; /* interpreted as "1 << size_shift" bytes */
-# bool sign_extend: 1; /* sign-extended */
-# uint8_t endianness : 1; /* 0: little, 1: big */
-# bool store : 1; /* whether it is a store operation */
-# pad : 1;
-# uint8_t mmuidx : 4; /* mmuidx (softmmu only) */
-# };
-#
# Mode: user, softmmu
# Targets: TCG(all)
-vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d"
+vcpu tcg guest_ld_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
+vcpu tcg guest_st_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
+vcpu tcg guest_rmw_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
# include/user/syscall-trace.h
+++ /dev/null
-/*
- * Helper functions for guest memory tracing
- *
- * Copyright (C) 2016 Lluís Vilanova <vilanova@ac.upc.edu>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef TRACE__MEM_H
-#define TRACE__MEM_H
-
-#include "tcg/tcg.h"
-
-#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */
-#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */
-#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */
-#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */
-#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */
-
-/**
- * trace_mem_build_info:
- *
- * Return a value for the 'info' argument in guest memory access traces.
- */
-static inline uint16_t trace_mem_build_info(int size_shift, bool sign_extend,
- MemOp endianness, bool store,
- unsigned int mmu_idx)
-{
- uint16_t res;
-
- res = size_shift & TRACE_MEM_SZ_SHIFT_MASK;
- if (sign_extend) {
- res |= TRACE_MEM_SE;
- }
- if (endianness == MO_BE) {
- res |= TRACE_MEM_BE;
- }
- if (store) {
- res |= TRACE_MEM_ST;
- }
-#ifdef CONFIG_SOFTMMU
- res |= mmu_idx << TRACE_MEM_MMU_SHIFT;
-#endif
- return res;
-}
-
-
-/**
- * trace_mem_get_info:
- *
- * Return a value for the 'info' argument in guest memory access traces.
- */
-static inline uint16_t trace_mem_get_info(MemOp op,
- unsigned int mmu_idx,
- bool store)
-{
- return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),
- op & MO_BSWAP, store,
- mmu_idx);
-}
-
-#endif /* TRACE__MEM_H */
trace_events_files = []
dtrace = find_program('dtrace', required: 'CONFIG_TRACE_DTRACE' in config_host)
foreach dir : [ '.' ] + trace_events_subdirs
- trace_events_file = meson.source_root() / dir / 'trace-events'
+ trace_events_file = meson.project_source_root() / dir / 'trace-events'
trace_events_files += [ trace_events_file ]
group_name = dir == '.' ? 'root' : dir.underscorify()
group = '--group=' + group_name
]
gen = custom_target(d[0],
output: d[0],
- input: meson.source_root() / 'trace-events',
+ input: meson.project_source_root() / 'trace-events',
command: [ tracetool, '--group=root', '--format=@0@'.format(d[1]), '@INPUT@', '@OUTPUT@' ],
depend_files: tracetool_depends)
specific_ss.add(when: 'CONFIG_TCG', if_true: gen)
projects / mirror_qemu.git / commitdiff