Merge tag 'pull-hex-20221216-1' of https://github.com/quic/qemu into staging

1)
Performance improvement
Add pkt and insn to DisasContext
Many functions need information from all 3 structures, so merge
them together.

2)
Bug fix
Fix predicated assignment to .tmp and .cur

3)
Performance improvement
Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These functions will not be handled by idef-parser

4-11)
The final 8 patches improve change-of-flow handling.

Currently, we set the PC to a new address before exiting a TB.  The
ultimate goal is to use direct block chaining.  However, several steps
are needed along the way.

4)
When a packet has more than one change-of-flow (COF) instruction, only
the first one taken is considered.  The runtime bookkeeping is only
needed when there is more than one COF instruction in a packet.

5, 6)
Remove PC and next_PC from the runtime state and always use a
translation-time constant.  Note that next_PC is used by call instructions
to set LR and by conditional COF instructions to set the fall-through
address.

7, 8, 9)
Add helper overrides for COF instructions.  In particular, we must
distinguish those that use a PC-relative address for the destination.
These are candidates for direct block chaining later.

10)
Use direct block chaining for packets that have a single PC-relative
COF instruction.  Instead of generating the code while processing the
instruction, we record the effect in DisasContext and generate the code
during gen_end_tb.

11)
Use direct block chaining for tight loops.  We look for TBs that end
with an endloop0 that will branch back to the TB start address.

12-21)
Instruction definition parser (idef-parser) from rev.ng
Parses the instruction semantics and generates TCG

# gpg: Signature made Fri 16 Dec 2022 20:41:53 GMT
# gpg:                using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5  9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20221216-1' of https://github.com/quic/qemu: (21 commits)
  target/hexagon: import additional tests
  target/hexagon: call idef-parser functions
  target/hexagon: import parser for idef-parser
  target/hexagon: import lexer for idef-parser
  target/hexagon: prepare input for the idef-parser
  target/hexagon: introduce new helper functions
  target/hexagon: make helper functions non-static
  target/hexagon: make slot number an unsigned
  target/hexagon: import README for idef-parser
  target/hexagon: update MAINTAINERS for idef-parser
  Hexagon (target/hexagon) Use direct block chaining for tight loops
  Hexagon (target/hexagon) Use direct block chaining for direct jump/branch
  Hexagon (target/hexagon) Add overrides for various forms of jump
  Hexagon (target/hexagon) Add overrides for compound compare and jump
  Hexagon (target/hexagon) Add overrides for direct call instructions
  Hexagon (target/hexagon) Remove next_PC from runtime state
  Hexagon (target/hexagon) Remove PC from the runtime state
  Hexagon (target/hexagon) Only use branch_taken when packet has multi cof
  Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
  Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --combined target/hexagon/cpu.h
index 794a0453fd40d89118b7d486722c9f8e3a9e863c,1d89e11a1a3740f8c3182a74553e686ada7da4c8..34c0ae0a672cc2bf8418b434ccb965d26551f332
--- 1/target/hexagon/cpu.h
--- 2/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@@ -25,6 -25,7 +25,7 @@@
  #include "mmvec/mmvec.h"
  #include "qom/object.h"
  #include "hw/core/cpu.h"
+ #include "hw/registerfields.h"
  
  #define NUM_PREGS 4
  #define TOTAL_PER_THREAD_REGS 64
@@@ -78,7 -79,6 +79,6 @@@ typedef struct CPUArchState 
      target_ulong gpr[TOTAL_PER_THREAD_REGS];
      target_ulong pred[NUM_PREGS];
      target_ulong branch_taken;
-     target_ulong next_PC;
  
      /* For comparing with LLDB on target - see adjust_stack_ptrs function */
      target_ulong last_pc_dumped;
@@@ -137,7 -137,7 +137,7 @@@ typedef struct HexagonCPUClass 
      CPUClass parent_class;
      /*< public >*/
      DeviceRealize parent_realize;
 -    DeviceReset parent_reset;
 +    ResettablePhases parent_phases;
  } HexagonCPUClass;
  
  struct ArchCPU {
@@@ -153,16 -153,18 +153,18 @@@
  
  #include "cpu_bits.h"
  
+ FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
+ 
  static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,
                                          target_ulong *cs_base, uint32_t *flags)
  {
+     uint32_t hex_flags = 0;
      *pc = env->gpr[HEX_REG_PC];
      *cs_base = 0;
- #ifdef CONFIG_USER_ONLY
-     *flags = 0;
- #else
- #error System mode not supported on Hexagon yet
- #endif
+     if (*pc == env->gpr[HEX_REG_SA0]) {
+         hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
+     }
+     *flags = hex_flags;
  }
  
  static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)