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# gpg: Signature made Mon 13 Nov 2023 21:39:31 EST
# gpg: using RSA key
EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full]
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* tag 'net-pull-request' of https://github.com/jasowang/qemu:
igb: Add Function Level Reset to PF and VF
igb: Add a VF reset handler
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
GlobalProperty hw_compat_8_1[] = {
{ TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" },
{ "ramfb", "x-migrate", "off" },
- { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }
+ { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" },
+ { "igb", "x-pcie-flr-init", "off" },
};
const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1);
uint32_t ioaddr;
IGBCore core;
+ bool has_flr;
};
#define IGB_CAP_SRIOV_OFFSET (0x160)
trace_igb_write_config(addr, val, len);
pci_default_write_config(dev, addr, val, len);
+ if (s->has_flr) {
+ pcie_cap_flr_write_config(dev, addr, val, len);
+ }
if (range_covers_byte(addr, len, PCI_COMMAND) &&
(dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
igb_core_write(&s->core, addr, val, size);
}
+void igb_vf_reset(void *opaque, uint16_t vfn)
+{
+ IGBState *s = opaque;
+ igb_core_vf_reset(&s->core, vfn);
+}
+
static bool
igb_io_get_reg_index(IGBState *s, uint32_t *idx)
{
}
/* PCIe extended capabilities (in order) */
+ if (s->has_flr) {
+ pcie_cap_flr_init(pci_dev);
+ }
+
if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) {
hw_error("Failed to initialize AER capability");
}
static Property igb_properties[] = {
DEFINE_NIC_PROPERTIES(IGBState, conf),
+ DEFINE_PROP_BOOL("x-pcie-flr-init", IGBState, has_flr, true),
DEFINE_PROP_END_OF_LIST(),
};
uint64_t igb_mmio_read(void *opaque, hwaddr addr, unsigned size);
void igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
+void igb_vf_reset(void *opaque, uint16_t vfn);
#endif
}
}
-static void igb_vf_reset(IGBCore *core, uint16_t vfn)
+void igb_core_vf_reset(IGBCore *core, uint16_t vfn)
{
uint16_t qn0 = vfn;
uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
+ trace_igb_core_vf_reset(vfn);
+
/* disable Rx and Tx for the VF*/
core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
if (val & E1000_CTRL_RST) {
vfn = (index - PVTCTRL0) / 0x40;
- igb_vf_reset(core, vfn);
+ igb_core_vf_reset(core, vfn);
}
}
void
igb_core_pci_uninit(IGBCore *core);
+void
+igb_core_vf_reset(IGBCore *core, uint16_t vfn);
+
bool
igb_can_receive(IGBCore *core);
{
trace_igbvf_write_config(addr, val, len);
pci_default_write_config(dev, addr, val, len);
+ if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)),
+ "x-pcie-flr-init", &error_abort)) {
+ pcie_cap_flr_write_config(dev, addr, val, len);
+ }
}
static uint64_t igbvf_mmio_read(void *opaque, hwaddr addr, unsigned size)
hw_error("Failed to initialize PCIe capability");
}
+ if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)),
+ "x-pcie-flr-init", &error_abort)) {
+ pcie_cap_flr_init(dev);
+ }
+
if (pcie_aer_init(dev, 1, 0x100, 0x40, errp) < 0) {
hw_error("Failed to initialize AER capability");
}
pcie_ari_init(dev, 0x150);
}
+static void igbvf_qdev_reset_hold(Object *obj)
+{
+ PCIDevice *vf = PCI_DEVICE(obj);
+
+ igb_vf_reset(pcie_sriov_get_pf(vf), pcie_sriov_vf_number(vf));
+}
+
static void igbvf_pci_uninit(PCIDevice *dev)
{
IgbVfState *s = IGBVF(dev);
{
DeviceClass *dc = DEVICE_CLASS(class);
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
+ ResettableClass *rc = RESETTABLE_CLASS(class);
c->realize = igbvf_pci_realize;
c->exit = igbvf_pci_uninit;
c->revision = 1;
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
+ rc->phases.hold = igbvf_qdev_reset_hold;
+
dc->desc = "Intel 82576 Virtual Function";
dc->user_creatable = false;
igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED"
igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x"
igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED"
+igb_core_vf_reset(uint16_t vfn) "VF%d"
igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d"