ancestor = ancestor.strip()
+log = subprocess.check_output(["git", "log", "--format=%H %s",
+ ancestor + "..."],
+ universal_newlines=True)
+
subprocess.check_call(["git", "remote", "rm", "check-patch"])
+if log == "":
+ print("\nNo commits since %s, skipping checks\n" % ancestor)
+ sys.exit(0)
+
errors = False
print("\nChecking all commits since %s...\n" % ancestor)
image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:latest
before_script:
- JOBS=$(expr $(nproc) + 1)
+ - sed -i s,git.qemu.org/git,gitlab.com/qemu-project, .gitmodules
script:
- mkdir build
- cd build
+++ /dev/null
-This file documents changes for QEMU releases 0.12 and earlier.
-For changelog information for later releases, see
-https://wiki.qemu.org/ChangeLog or look at the git history for
-more detailed information.
-
-
-version 0.12.0:
-
- - Update to SeaBIOS 0.5.0
- - e1000: fix device link status in Linux (Anthony Liguori)
- - monitor: fix QMP for balloon command (Luiz Capitulino)
- - QMP: Return an empty dict by default (Luiz Capitulino)
- - QMP: Only handle converted commands (Luiz Capitulino)
- - pci: support PCI based option rom loading (Gerd Hoffman/Anthony Liguori)
- - Fix backcompat for hotplug of SCSI controllers (Daniel P. Berrange)
- - fdc: fix migration from 0.11 (Juan Quintela)
- - vmware-vga: fix segv on cursor resize. (Dave Airlie)
- - vmware-vga: various fixes (Dave Airlie/Anthony Liguori)
- - qdev: improve property error reporting. (Gerd Hoffmann)
- - fix vga names in default_list (Gerd Hoffmann)
- - usb-host: check mon before using it. (Gerd Hoffmann)
- - usb-net: use qdev for -usbdevice (Gerd Hoffmann)
- - monitor: Catch printing to non-existent monitor (Luiz Capitulino)
- - Avoid permanently disabled QEMU monitor when UNIX migration fails (Daniel P. Berrange)
- - Fix loading of ELF multiboot kernels (Kevin Wolf)
- - qemu-io: Fix memory leak (Kevin Wolf)
- - Fix thinko in linuxboot.S (Paolo Bonzini)
- - target-i386: Fix evaluation of DR7 register (Jan Kiszka)
- - vnc: hextile: do not generate ForegroundSpecified and SubrectsColoured tiles (Anthony Liguori)
- - S390: Bail out without KVM (Alexander Graf)
- - S390: Don't tell guest we're updating config space (Alexander Graf)
- - target-s390: Fail on unknown instructions (Alexander Graf)
- - osdep: Fix runtime failure on older Linux kernels (Andre Przywara)
- - Fix a make -j race (Juergen Lock)
- - target-alpha: Fix generic ctz64. (Richard Henderson)
- - s390: Fix buggy assignment (Stefan Weil)
- - target-mips: fix user-mode emulation startup (Nathan Froyd)
- - target-i386: Update CPUID feature set for TCG (Andre Przywara)
- - s390: fix build on 32 bit host (Michael S. Tsirkin)
-
-version 0.12.0-rc2:
-
- - v2: properly save kvm system time msr registers (Glauber Costa)
- - convert more monitor commands to qmp (Luiz Capitulino)
- - vnc: fix capslock tracking logic. (Gerd Hoffmann)
- - QemuOpts: allow larger option values. (Gerd Hoffmann)
- - scsi: fix drive hotplug. (Gerd Hoffmann)
- - pci: don't hw_error() when no slot is available. (Gerd Hoffmann)
- - pci: don't abort() when trying to hotplug with acpi off. (Gerd Hoffmann)
- - allow default devices to be implemented in config file (Gerd Hoffman)
- - vc: colorize chardev title line with blue background. (Gerd Hoffmann)
- - chardev: make chardevs specified in config file work. (Gerd Hoffmann)
- - qdev: also match bus name for global properties (Gerd Hoffmann)
- - qdev: add command line option to set global defaults for properties. (Gerd Hoffmann)
- - kvm: x86: Save/restore exception_index (Jan Kiszka)
- - qdev: Replace device names containing whitespace (Markus Armbruster)
- - fix rtc-td-hack on host without high-res timers (Gleb Natapov)
- - virtio: verify features on load (Michael S. Tsirkin)
- - vmware_vga: add rom file so that it boots. (Dave Airlie)
- - Do not abort on qemu_malloc(0) in production builds (Anthony Liguori)
- - Fix ARM userspace strex implementation. (Paul Brook)
- - qemu: delete rule target on error (Michael S. Tsirkin)
- - QMP: add human-readable description to error response (Markus Armbruster)
- - convert more monitor commands to QError (Markus Armbruster)
- - monitor: Fix double-prompt after "change vnc passwd BLA" (Markus Armbruster)
- - monitor: do_cont(): Don't ask for passwords (Luiz Capitulino)
- - monitor: Introduce 'block_passwd' command (Luiz Capitulino)
- - pci: interrupt disable bit support (Michael S. Tsirkin)
- - pci: interrupt status bit implementation (Michael S. Tsirkin)
- - pci: prepare irq code for interrupt state (Michael S. Tsirkin)
- - msix: function mask support (Michael S. Tsirkin)
- - msix: macro rename for function mask support (Michael S. Tsirkin)
- - cpuid: Fix multicore setup on Intel (Andre Przywara)
- - kvm: x86: Fix initial kvm_has_msr_star (Jan Kiszka)
- - Update OpenBIOS images to r640 (Aurelien Jarno)
-
-version 0.10.2:
-
- - fix savevm/loadvm (Anthony Liguori)
- - live migration: fix dirty tracking windows (Glauber Costa)
- - live migration: improve error propagation (Glauber Costa)
- - qcow2: fix image creation for > ~2TB images (Chris Wright)
- - hotplug: fix error handling for if= parameter (Eduardo Habkost)
- - qcow2: fix data corruption (Nolan Leake)
- - virtio: fix guest oops with 2.6.25 kernels (Rusty Russell)
- - SH4: add support for -kernel (Takashi Yoshii, Aurelien Jarno)
- - hotplug: fix closing of char devices (Jan Kiszka)
- - hotplug: remove incorrect check for device name (Eduardo Habkost)
- - enable -k on win32 (Herve Poussineau)
- - configure: use LANG=C for grep (Andreas Faerber)
- - fix VGA regression (malc)
-
-version 0.10.1:
-
- - virtio-net: check right return size on sg list (Alex Williamson)
- - Make qemu_announce_self handle holes (live migration after hotplug)
- (Marcelo Tosatti)
- - Revert r6804-r6808 (qcow2 allocation info). This series of changes added
- a high cost to startup for large qcow2 images (Anthony Liguori)
- - qemu-img: fix help message (Aurelien Jarno)
- - Fix build for non-default installs of SDL (Anthony Liguori)
- - Fix race condition in env->interrupt_request. When using TCG and a dynticks
- host timer, this condition could cause TCG to get stuck in an infinite
- loop (Aurelien Jarno)
- - Fix reading encrypted hard disk passwords during early startup (Jan Kiszka)
- - Fix encrypted disk reporting in 'info block' (Jan Kiszka)
- - Fix console size with tiny displays (MusicPal) (Jan Kiszka)
- - Improve error handling in bdrv_open2 (Jan Kiszka)
- - Avoid leaking data in mux'ed character devices (Jan Kiszka)
- - Fix initial character device reset (no banner in monitor) (Jan Kiszka)
- - Fix cpuid KVM crash on i386 host (Lubomir Rintel)
- - Fix SLES10sp2 installation by adding ISTAT1 register to LSI SCSI emulation
- (Ryan Harper)
-
-version 0.10.0:
-
- - TCG support (No longer requires GCC 3.x)
- - Kernel Virtual Machine acceleration support
- - BSD userspace emulation
- - Bluetooth emulation and host passthrough support
- - GDB XML register description support
- - Intel e1000 emulation
- - HPET emulation
- - VirtIO paravirtual device support
- - Marvell 88w8618 / MusicPal emulation
- - Nokia N-series tablet emulation / OMAP2 processor emulation
- - PCI hotplug support
- - Live migration and new save/restore formats
- - Curses display support
- - qemu-nbd utility to mount supported block formats
- - Altivec support in PPC emulation and new firmware (OpenBIOS)
- - Multiple VNC clients are now supported
- - TLS encryption is now supported in VNC
- - MIPS Magnum R4000 machine (Hervé Poussineau)
- - Braille support (Samuel Thibault)
- - Freecom MusicPal system emulation (Jan Kiszka)
- - OMAP242x and Nokia N800, N810 machines (Andrzej Zaborowski)
- - EsounD audio driver (Frederick Reeve)
- - Gravis Ultrasound GF1 sound card (Tibor "TS" Schütz)
- - Many, many, bug fixes and new features
-
-version 0.9.1:
-
- - TFTP booting from host directory (Anthony Liguori, Erwan Velu)
- - Tap device emulation for Solaris (Sittichai Palanisong)
- - Monitor multiplexing to several I/O channels (Jason Wessel)
- - ds1225y nvram support (Herve Poussineau)
- - CPU model selection support (J. Mayer, Paul Brook, Herve Poussineau)
- - Several Sparc fixes (Aurelien Jarno, Blue Swirl, Robert Reif)
- - MIPS 64-bit FPU support (Thiemo Seufer)
- - Xscale PDA emulation (Andrzej Zaborowski)
- - ColdFire system emulation (Paul Brook)
- - Improved SH4 support (Magnus Damm)
- - MIPS64 support (Aurelien Jarno, Thiemo Seufer)
- - Preliminary Alpha guest support (J. Mayer)
- - Read-only support for Parallels disk images (Alex Beregszaszi)
- - SVM (x86 virtualization) support (Alexander Graf)
- - CRIS emulation (Edgar E. Iglesias)
- - SPARC32PLUS execution support (Blue Swirl)
- - MIPS mipssim pseudo machine (Thiemo Seufer)
- - Strace for Linux userland emulation (Stuart Anderson, Thayne Harbaugh)
- - OMAP310 MPU emulation plus Palm T|E machine (Andrzej Zaborowski)
- - ARM v6, v7, NEON SIMD and SMP emulation (Paul Brook/CodeSourcery)
- - Gumstix boards: connex and verdex emulation (Thorsten Zitterell)
- - Intel mainstone II board emulation (Armin Kuster)
- - VMware SVGA II graphics card support (Andrzej Zaborowski)
-
-version 0.9.0:
-
- - Support for relative paths in backing files for disk images
- - Async file I/O API
- - New qcow2 disk image format
- - Support of multiple VM snapshots
- - Linux: specific host CDROM and floppy support
- - SMM support
- - Moved PCI init, MP table init and ACPI table init to Bochs BIOS
- - Support for MIPS32 Release 2 instruction set (Thiemo Seufer)
- - MIPS Malta system emulation (Aurelien Jarno, Stefan Weil)
- - Darwin userspace emulation (Pierre d'Herbemont)
- - m68k user support (Paul Brook)
- - several x86 and x86_64 emulation fixes
- - Mouse relative offset VNC extension (Anthony Liguori)
- - PXE boot support (Anthony Liguori)
- - '-daemonize' option (Anthony Liguori)
-
-version 0.8.2:
-
- - ACPI support
- - PC VGA BIOS fixes
- - switch to OpenBios for SPARC targets (Blue Swirl)
- - VNC server fixes
- - MIPS FPU support (Marius Groeger)
- - Solaris/SPARC host support (Juergen Keil)
- - PPC breakpoints and single stepping (Jason Wessel)
- - USB updates (Paul Brook)
- - UDP/TCP/telnet character devices (Jason Wessel)
- - Windows sparse file support (Frediano Ziglio)
- - RTL8139 NIC TCP segmentation offloading (Igor Kovalenko)
- - PCNET NIC support (Antony T Curtis)
- - Support for variable frequency host CPUs
- - Workaround for win32 SMP hosts
- - Support for AMD Flash memories (Jocelyn Mayer)
- - Audio capture to WAV files support (malc)
-
-version 0.8.1:
-
- - USB tablet support (Brad Campbell, Anthony Liguori)
- - win32 host serial support (Kazu)
- - PC speaker support (Joachim Henke)
- - IDE LBA48 support (Jens Axboe)
- - SSE3 support
- - Solaris port (Juergen Keil)
- - Preliminary SH4 target (Samuel Tardieu)
- - VNC server (Anthony Liguori)
- - slirp fixes (Ed Swierk et al.)
- - USB fixes
- - ARM Versatile Platform Baseboard emulation (Paul Brook)
-
-version 0.8.0:
-
- - ARM system emulation: Arm Integrator/CP board with an arm1026ej-s
- cpu (Paul Brook)
- - SMP support
- - Mac OS X cocoa improvements (Mike Kronenberg)
- - Mac OS X CoreAudio driver (Mike Kronenberg)
- - DirectSound driver (malc)
- - ALSA audio driver (malc)
- - new audio options: '-soundhw' and '-audio-help' (malc)
- - ES1370 PCI audio device (malc)
- - Initial USB support
- - Linux host serial port access
- - Linux host low level parallel port access
- - New network emulation code supporting VLANs.
- - MIPS and MIPSel User Linux emulation
- - MIPS fixes to boot Linux (Daniel Jacobowitz)
- - NX bit support
- - Initial SPARC SMP support (Blue Swirl)
- - Major overhaul of the virtual FAT driver for read/write support
- (Johannes Schindelin)
-
-version 0.7.2:
-
- - x86_64 fixes (Win2000 and Linux 2.6 boot in 32 bit)
- - merge self modifying code handling in dirty ram page mechanism.
- - MIPS fixes (Ralf Baechle)
- - better user net performances
-
-version 0.7.1:
-
- - read-only Virtual FAT support (Johannes Schindelin)
- - Windows 2000 install disk full hack (original idea from Vladimir
- N. Oleynik)
- - VMDK disk image creation (Filip Navara)
- - SPARC64 progress (Blue Swirl)
- - initial MIPS support (Jocelyn mayer)
- - MIPS improvements (Ralf Baechle)
- - 64 bit fixes in user networking (initial patch by Gwenole Beauchesne)
- - IOAPIC support (Filip Navara)
-
-version 0.7.0:
-
- - better BIOS translation and HDD geometry auto-detection
- - user mode networking bug fix
- - undocumented FPU ops support
- - Cirrus VGA: support for 1280x1024x[8,15,16] modes
- - 'pidfile' option
- - .dmg disk image format support (Johannes Schindelin)
- - keymaps support (initial patch by Johannes Schindelin)
- - big endian ARM support (Lennert Buytenhek)
- - added generic 64 bit target support
- - x86_64 target support
- - initial APIC support
- - MMX/SSE/SSE2/PNI support
- - PC parallel port support (Mark Jonckheere)
- - initial SPARC64 support (Blue Swirl)
- - SPARC target boots Linux (Blue Swirl)
- - armv5te user mode support (Paul Brook)
- - ARM VFP support (Paul Brook)
- - ARM "Angel" semihosting syscalls (Paul Brook)
- - user mode gdb stub support (Paul Brook)
- - Samba 3 support
- - initial Cocoa support (Pierre d'Herbemont)
- - generic FPU emulation code
- - Virtual PC read-only disk image support (Alex Beregszaszi)
-
-version 0.6.1:
-
- - Mac OS X port (Pierre d'Herbemont)
- - Virtual console support
- - Better monitor line edition
- - New block device layer
- - New 'qcow' growable disk image support with AES encryption and
- transparent decompression
- - VMware 3 and 4 read-only disk image support (untested)
- - Support for up to 4 serial ports
- - TFTP server support (Magnus Damm)
- - Port redirection support in user mode networking
- - Support for not executable data sections
- - Compressed loop disk image support (Johannes Schindelin)
- - Level triggered IRQ fix (aka NE2000 PCI performance fix) (Steve
- Wormley)
- - Fixed Fedora Core 2 problems (now you can run qemu without any
- LD_ASSUME_KERNEL tricks on FC2)
- - DHCP fix for Windows (accept DHCPREQUEST alone)
- - SPARC system emulation (Blue Swirl)
- - Automatic Samba configuration for host file access from Windows.
- - '-loadvm' and '-full-screen' options
- - ne2000 savevm support (Johannes Schindelin)
- - Ctrl-Alt is now the default grab key. Ctrl-Alt-[0-9] switches to
- the virtual consoles.
- - BIOS floppy fix for NT4 (Mike Nordell, Derek Fawcus, Volker Ruppert)
- - Floppy fixes for NT4 and NT5 (Mike Nordell)
- - NT4 IDE fixes (Ben Pfaf, Mike Nordell)
- - SDL Audio support and SB16 fixes (malc)
- - ENTER instruction bug fix (initial patch by Stefan Kisdaroczi)
- - VGA font change fix
- - VGA read-only CRTC register fix
-
-version 0.6.0:
-
- - minimalist FPU exception support (NetBSD FPU probe fix)
- - cr0.ET fix (Win95 boot)
- - *BSD port (Markus Niemisto)
- - I/O access fix (signaled by Mark Jonckheere)
- - IDE drives serial number fix (Mike Nordell)
- - int13 CDROM BIOS fix (aka Solaris x86 install CD fix)
- - int15, ah=86 BIOS fix (aka Solaris x86 hardware probe hang up fix)
- - BSR/BSF "undefined behaviour" fix
- - vmdk2raw: convert VMware disk images to raw images
- - PCI support
- - NE2K PCI support
- - dummy VGA PCI support
- - VGA font selection fix (Daniel Serpell)
- - PIC reset fix (Hidemi KAWAI)
- - PIC spurious irq support (aka Solaris install bug)
- - added '-localtime' option
- - Cirrus CL-GD54xx VGA support (initial patch by Makoto Suzuki (suzu))
- - APM and system shutdown support
- - Fixed system reset
- - Support for other PC BIOSes
- - Initial PowerMac hardware emulation
- - PowerMac/PREP OpenFirmware compatible BIOS (Jocelyn Mayer)
- - initial IDE BMDMA support (needed for Darwin x86)
- - Set the default memory size for PC emulation to 128 MB
-
-version 0.5.5:
-
- - SDL full screen support (initial patch by malc)
- - VGA support on PowerPC PREP
- - VBE fixes (Matthew Mastracci)
- - PIT fixes (aka Win98 hardware probe and "VGA slowness" bug)
- - IDE master only fixes (aka Win98 CD-ROM probe bug)
- - ARM load/store half word fix (Ulrich Hecht)
- - FDC fixes for Win98
-
-version 0.5.4:
-
- - qemu-fast fixes
- - BIOS area protection fix (aka EMM386.EXE fix) (Mike Nordell)
- - keyboard/mouse fix (Mike Nordell)
- - IDE fixes (Linux did not recognized slave drivers)
- - VM86 EIP masking fix (aka NT5 install fix) (Mike Nordell)
- - QEMU can now boot a PowerPC Linux kernel (Jocelyn Mayer)
- - User mode network stack
- - imul imm8 fix + 0x82 opcode support (Hidemi KAWAI)
- - precise self modifying code (aka BeOS install bug)
-
-version 0.5.3:
-
- - added Bochs VESA VBE support
- - VGA memory map mode 3 access fix (OS/2 install fix)
- - IDE fixes (Jens Axboe)
- - CPU interrupt fixes
- - fixed various TLB invalidation cases (NT install)
- - fixed cr0.WP semantics (XP install)
- - direct chaining support for SPARC and PowerPC (faster)
- - ARM NWFPE support (initial patch by Ulrich Hecht)
- - added specific x86 to x86 translator (close to native performance
- in qemu-i386 and qemu-fast)
- - shm syscalls support (Paul McKerras)
- - added accurate CR0.MP/ME/TS emulation
- - fixed DMA memory write access (Win95 boot floppy fix)
- - graphical x86 linux loader
- - command line monitor
- - generic removable device support
- - support of CD-ROM change
- - multiple network interface support
- - initial x86-64 host support (Gwenole Beauchesne)
- - lret to outer privilege fix (OS/2 install fix)
- - task switch fixes (SkyOS boot)
- - VM save/restore commands
- - new timer API
- - more precise RTC emulation (periodic timers + time updates)
- - Win32 port (initial patch by Kazu)
-
-version 0.5.2:
-
- - improved soft MMU speed (assembly functions and specializing)
- - improved multitasking speed by avoiding flushing TBs when
- switching tasks
- - improved qemu-fast speed
- - improved self modifying code handling (big performance gain in
- softmmu mode).
- - fixed IO checking
- - fixed CD-ROM detection (win98 install CD)
- - fixed addseg real mode bug (GRUB boot fix)
- - added ROM memory support (win98 boot)
- - fixed 'call Ev' in case of paging exception
- - updated the script 'qemu-binfmt-conf.sh' to use QEMU automagically
- when launching executables for the supported target CPUs.
- - PowerPC system emulation update (Jocelyn Mayer)
- - PC floppy emulation and DMA fixes (Jocelyn Mayer)
- - polled mode for PIC (Jocelyn Mayer)
- - fixed PTE dirty bit handling
- - fixed xadd same reg bug
- - fixed cmpxchg exception safeness
- - access to virtual memory in gdb stub
- - task gate and NT flag fixes
- - eflags optimisation fix for string operations
-
-version 0.5.1:
-
- - float access fixes when using soft mmu
- - PC emulation support on PowerPC
- - A20 support
- - IDE CD-ROM emulation
- - ARM fixes (Ulrich Hecht)
- - SB16 emulation (malc)
- - IRET and INT fixes in VM86 mode with IOPL=3
- - Port I/Os use TSS io map
- - Full task switching/task gate support
- - added verr, verw, arpl, fcmovxx
- - PowerPC target support (Jocelyn Mayer)
- - Major SPARC target fixes (dynamically linked programs begin to work)
-
-version 0.5.0:
-
- - full hardware level VGA emulation
- - graphical display with SDL
- - added PS/2 mouse and keyboard emulation
- - popw (%esp) fix
- - mov to/from segment data width fix
- - added real mode support
- - added Bochs BIOS and LGPL'ed VGA BIOS loader in qemu
- - m68k host port (Richard Zidlicky)
- - partial soft MMU support for memory mapped I/Os
- - multi-target build
- - fixed: no error code in hardware interrupts
- - fixed: pop ss, mov ss, x and sti disable hardware irqs for the next insn
- - correct single stepping through string operations
- - preliminary SPARC target support (Thomas M. Ogrisegg)
- - tun-fd option (Rusty Russell)
- - automatic IDE geometry detection
- - renamed 'vl' to qemu[-fast] and user qemu to qemu-{cpu}.
- - added man page
- - added full soft mmu mode to launch unpatched OSes.
-
-version 0.4.3:
-
- - x86 exception fix in case of nop instruction.
- - gcc 3.2.2 bug workaround (RedHat 9 fix)
- - sparc and Alpha host fixes
- - many ARM target fixes: 'ls' and 'bash' can be launched.
-
-version 0.4.2:
-
- - many exception handling fixes (can compile a Linux kernel inside vl)
- - IDE emulation support
- - initial GDB stub support
- - deferred update support for disk images (Rusty Russell)
- - accept User Mode Linux Copy On Write disk images
- - SMP kernels can at least be booted
-
-version 0.4.1:
-
- - more accurate timer support in vl.
- - more reliable NE2000 probe in vl.
- - added 2.5.66 kernel in vl-test.
- - added VLTMPDIR environment variable in vl.
-
-version 0.4:
-
- - initial support for ring 0 x86 processor emulation
- - fixed signal handling for correct dosemu DPMI emulation
- - fast x86 MMU emulation with mmap()
- - fixed popl (%esp) case
- - Linux kernel can be executed by QEMU with the 'vl' command.
-
-version 0.3:
-
- - initial support for ARM emulation
- - added fnsave, frstor, fnstenv, fldenv FPU instructions
- - added FPU register save in signal emulation
- - initial ARM port
- - Sparc and Alpha ports work on the regression test
- - generic ioctl number conversion
- - fixed ioctl type conversion
-
-version 0.2:
-
- - PowerPC disassembly and ELF symbols output (Rusty Russell)
- - flock support (Rusty Russell)
- - ugetrlimit support (Rusty Russell)
- - fstat64 fix (Rusty Russell)
- - initial Alpha port (Falk Hueffner)
- - initial IA64 port (Matt Wilson)
- - initial Sparc and Sparc64 port (David S. Miller)
- - added HLT instruction
- - LRET instruction fix.
- - added GPF generation for I/Os.
- - added INT3 and TF flag support.
- - SHL instruction C flag fix.
- - mmap emulation for host page size > 4KB
- - self-modifying code support
- - better VM86 support (dosemu works on non trivial programs)
- - precise exception support (EIP is computed correctly in most cases)
- - more precise LDT/GDT/IDT emulation
- - faster segment load in vm86 mode
- - direct chaining of basic blocks (faster emulation)
-
-version 0.1.6:
-
- - automatic library search system. QEMU can now work with unpatched
- ELF dynamic loader and libc (Rusty Russell).
- - ISO C warning fixes (Alistair Strachan)
- - first self-virtualizable version (works only as long as the
- translation cache is not flushed)
- - RH9 fixes
-
-version 0.1.5:
-
- - ppc64 support + personality() patch (Rusty Russell)
- - first Alpha CPU patches (Falk Hueffner)
- - removed bfd.h dependency
- - fixed shrd, shld, idivl and divl on PowerPC.
- - fixed buggy glibc PowerPC rint() function (test-i386 passes now on PowerPC).
-
-version 0.1.4:
-
- - more accurate VM86 emulation (can launch small DOS 16 bit
- executables in wine).
- - fixed push/pop fs/gs
- - added iret instruction.
- - added times() syscall and SIOCATMARK ioctl.
-
-version 0.1.3:
-
- - S390 support (Ulrich Weigand)
- - glibc 2.3.x compile fix (Ulrich Weigand)
- - socketcall endian fix (Ulrich Weigand)
- - struct sockaddr endian fix (Ulrich Weigand)
- - sendmsg/recvmsg endian fix (Ulrich Weigand)
- - execve endian fix (Ulrich Weigand)
- - fdset endian fix (Ulrich Weigand)
- - partial setsockopt syscall support (Ulrich Weigand)
- - more accurate pushf/popf emulation
- - first partial vm86() syscall support (can be used with runcom example).
- - added bound, cmpxchg8b, cpuid instructions
- - added 16 bit addressing support/override for string operations
- - poll() fix
-
-version 0.1.2:
-
- - compile fixes
- - xlat instruction
- - xchg instruction memory lock
- - added simple vm86 example (not working with QEMU yet). The 54 byte
- DOS executable 'pi_10.com' program was released by Bertram
- Felgenhauer (more information at http://www.boo.net/~jasonp/pipage.html).
-
-version 0.1.1:
-
- - glibc 2.2 compilation fixes
- - added -s and -L options
- - binary distribution of x86 glibc and wine
- - big endian fixes in ELF loader and getdents.
-
-version 0.1:
-
- - initial public release.
S: Supported
F: hw/*/npcm7xx*
F: include/hw/*/npcm7xx*
+F: tests/qtest/npcm7xx*
F: pc-bios/npcm7xx_bootrom.bin
F: roms/vbootrom
# 4. Rules to bridge to other makefiles
ifneq ($(NINJA),)
-NINJAFLAGS = $(if $V,-v,) \
+MAKE.n = $(findstring n,$(firstword $(MAKEFLAGS)))
+MAKE.k = $(findstring k,$(firstword $(MAKEFLAGS)))
+MAKE.q = $(findstring q,$(firstword $(MAKEFLAGS)))
+MAKE.nq = $(if $(word 2, $(MAKE.n) $(MAKE.q)),nq)
+NINJAFLAGS = $(if $V,-v) $(if $(MAKE.n), -n) $(if $(MAKE.k), -k0) \
$(filter-out -j, $(lastword -j1 $(filter -l% -j%, $(MAKEFLAGS)))) \
- $(subst -k, -k0, $(filter -n -k,$(MAKEFLAGS)))
ninja-cmd-goals = $(or $(MAKECMDGOALS), all)
ninja-cmd-goals += $(foreach t, $(.tests), $(.test.deps.$t))
# --output-sync line.
run-ninja: config-host.mak
ifneq ($(filter $(ninja-targets), $(ninja-cmd-goals)),)
- +@$(NINJA) $(NINJAFLAGS) $(sort $(filter $(ninja-targets), $(ninja-cmd-goals))) | cat
+ +$(quiet-@)$(if $(MAKE.nq),@:, $(NINJA) \
+ $(NINJAFLAGS) $(sort $(filter $(ninja-targets), $(ninja-cmd-goals))) | cat)
endif
endif
rm -f linux-headers/asm
rm -Rf .sdk
-find-src-path = find "$(SRC_PATH)/" -path "$(SRC_PATH)/meson" -prune -o -name "*.[chsS]"
+find-src-path = find "$(SRC_PATH)/" -path "$(SRC_PATH)/meson" -prune -o \( -name "*.[chsS]" -o -name "*.[ch].inc" \)
.PHONY: ctags
ctags:
* `<https://qemu.org/Contribute/ReportABug>`_
+ChangeLog
+=========
+
+For version history and release notes, please visit
+`<https://wiki.qemu.org/ChangeLog/>`_ or look at the git history for
+more detailed information.
+
+
Contact
=======
tb_destroy(tb);
}
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
+ "cpu_io_recompile: rewound execution of TB to "
+ TARGET_FMT_lx "\n", tb->pc);
+
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
* the first in the TB) then we end up generating a whole new TB and
* repeating the fault, which is horribly inefficient.
{
}
+void cpu_remove_sync(CPUState *cpu)
+{
+}
+
void qemu_init_vcpu(CPUState *cpu)
{
}
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
}
QLIST_INIT(&bs->aio_notifiers);
bdrv_drained_end(bs);
+
+ /*
+ * If we're still inside some bdrv_drain_all_begin()/end() sections, end
+ * them now since this BDS won't exist anymore when bdrv_drain_all_end()
+ * gets called.
+ */
+ if (bs->quiesce_counter) {
+ bdrv_drain_all_end_quiesce(bs);
+ }
}
void bdrv_close_all(void)
}
}
+void bdrv_drain_all_end_quiesce(BlockDriverState *bs)
+{
+ int drained_end_counter = 0;
+
+ g_assert(bs->quiesce_counter > 0);
+ g_assert(!bs->refcnt);
+
+ while (bs->quiesce_counter) {
+ bdrv_do_drained_end(bs, false, NULL, true, &drained_end_counter);
+ }
+ BDRV_POLL_WHILE(bs, qatomic_read(&drained_end_counter) > 0);
+}
+
void bdrv_drain_all_end(void)
{
BlockDriverState *bs = NULL;
if (ret & (BDRV_BLOCK_DATA | BDRV_BLOCK_ZERO)) {
ret |= BDRV_BLOCK_ALLOCATED;
- } else if (want_zero && bs->drv->supports_backing) {
+ } else if (bs->drv->supports_backing) {
BlockDriverState *cow_bs = bdrv_cow_bs(bs);
- if (cow_bs) {
+ if (!cow_bs) {
+ ret |= BDRV_BLOCK_ZERO;
+ } else if (want_zero) {
int64_t size2 = bdrv_getlength(cow_bs);
if (size2 >= 0 && offset >= size2) {
ret |= BDRV_BLOCK_ZERO;
}
- } else {
- ret |= BDRV_BLOCK_ZERO;
}
}
offset, bytes, pnum, map, file);
}
+/*
+ * Check @bs (and its backing chain) to see if the range defined
+ * by @offset and @bytes is known to read as zeroes.
+ * Return 1 if that is the case, 0 otherwise and -errno on error.
+ * This test is meant to be fast rather than accurate so returning 0
+ * does not guarantee non-zero data.
+ */
+int coroutine_fn bdrv_co_is_zero_fast(BlockDriverState *bs, int64_t offset,
+ int64_t bytes)
+{
+ int ret;
+ int64_t pnum = bytes;
+
+ if (!bytes) {
+ return 1;
+ }
+
+ ret = bdrv_common_block_status_above(bs, NULL, false, false, offset,
+ bytes, &pnum, NULL, NULL);
+
+ if (ret < 0) {
+ return ret;
+ }
+
+ return (pnum == bytes) && (ret & BDRV_BLOCK_ZERO);
+}
+
int coroutine_fn bdrv_is_allocated(BlockDriverState *bs, int64_t offset,
int64_t bytes, int64_t *pnum)
{
return false;
}
-static bool is_unallocated(BlockDriverState *bs, int64_t offset, int64_t bytes)
-{
- int64_t nr;
- return !bytes ||
- (!bdrv_is_allocated_above(bs, NULL, false, offset, bytes, &nr) &&
- nr == bytes);
-}
-
-static bool is_zero_cow(BlockDriverState *bs, QCowL2Meta *m)
+/*
+ * Return 1 if the COW regions read as zeroes, 0 if not, < 0 on error.
+ * Note that returning 0 does not guarantee non-zero data.
+ */
+static int is_zero_cow(BlockDriverState *bs, QCowL2Meta *m)
{
/*
* This check is designed for optimization shortcut so it must be
* efficient.
- * Instead of is_zero(), use is_unallocated() as it is faster (but not
- * as accurate and can result in false negatives).
+ * Instead of is_zero(), use bdrv_co_is_zero_fast() as it is
+ * faster (but not as accurate and can result in false negatives).
*/
- return is_unallocated(bs, m->offset + m->cow_start.offset,
- m->cow_start.nb_bytes) &&
- is_unallocated(bs, m->offset + m->cow_end.offset,
- m->cow_end.nb_bytes);
+ int ret = bdrv_co_is_zero_fast(bs, m->offset + m->cow_start.offset,
+ m->cow_start.nb_bytes);
+ if (ret <= 0) {
+ return ret;
+ }
+
+ return bdrv_co_is_zero_fast(bs, m->offset + m->cow_end.offset,
+ m->cow_end.nb_bytes);
}
static int handle_alloc_space(BlockDriverState *bs, QCowL2Meta *l2meta)
continue;
}
- if (!is_zero_cow(bs, m)) {
+ ret = is_zero_cow(bs, m);
+ if (ret < 0) {
+ return ret;
+ } else if (ret == 0) {
continue;
}
if (fill_header(&header, &ps, &vs, KdDebuggerDataBlock, kdbg,
KdVersionBlock, qemu_elf.state_nr)) {
err = 1;
- goto out_pdb;
+ goto out_kdbg;
}
if (fill_context(kdbg, &vs, &qemu_elf)) {
err = 1;
- goto out_pdb;
+ goto out_kdbg;
}
if (write_dump(&ps, &header, argv[2])) {
nieklinnenbank@gmail.com
devnexen@gmail.com
pauldzim@gmail.com
+ani@anisinha.ca
+sundeep.lkml@gmail.com
+mrolnik@gmail.com
+huth@tuxfamily.org
+jhogan@kernel.org
+atar4qemu@gmail.com
* DDR4 memory controller (dummy interface indicating memory training is done)
* OTP controllers (no protection features)
* Flash Interface Unit (FIU; no protection features)
+ * Random Number Generator (RNG)
+ * USB host (USBH)
+ * GPIO controller
Missing devices
---------------
- * GPIO controller
* LPC/eSPI host-to-BMC interface, including
* Keyboard and mouse controller interface (KBCI)
* eSPI slave interface
* Ethernet controllers (GMAC and EMC)
- * USB host (USBH)
* USB device (USBD)
* SMBus controller (SMBF)
* Peripheral SPI controller (PSPI)
* Analog to Digital Converter (ADC)
* SD/MMC host
- * Random Number Generator (RNG)
* PECI interface
* Pulse Width Modulation (PWM)
* Tachometer
allocated target image depending on the host support for getting allocation
information.
+.. option:: -r
+
+ Rate limit for the convert process
+
.. option:: --salvage
Try to ignore I/O errors when reading. Unless in quiet mode (``-q``), errors
state after (the attempt at) repairing it. That is, a successful ``-r all``
will yield the exit code 0, independently of the image state before.
-.. option:: commit [--object OBJECTDEF] [--image-opts] [-q] [-f FMT] [-t CACHE] [-b BASE] [-d] [-p] FILENAME
+.. option:: commit [--object OBJECTDEF] [--image-opts] [-q] [-f FMT] [-t CACHE] [-b BASE] [-r RATE_LIMIT] [-d] [-p] FILENAME
Commit the changes recorded in *FILENAME* in its base image or backing file.
If the backing file is smaller than the snapshot, then the backing file will be
garbage data when read. For this reason, ``-b`` implies ``-d`` (so that
the top image stays valid).
+ The rate limit for the commit process is specified by ``-r``.
+
.. option:: compare [--object OBJECTDEF] [--image-opts] [-f FMT] [-F FMT] [-T SRC_CACHE] [-p] [-q] [-s] [-U] FILENAME1 FILENAME2
Check if two images have the same content. You can compare images with
4
Error on reading data
-.. option:: convert [--object OBJECTDEF] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f FMT] [-t CACHE] [-T SRC_CACHE] [-O OUTPUT_FMT] [-B BACKING_FILE] [-o OPTIONS] [-l SNAPSHOT_PARAM] [-S SPARSE_SIZE] [-m NUM_COROUTINES] [-W] FILENAME [FILENAME2 [...]] OUTPUT_FILENAME
+.. option:: convert [--object OBJECTDEF] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f FMT] [-t CACHE] [-T SRC_CACHE] [-O OUTPUT_FMT] [-B BACKING_FILE] [-o OPTIONS] [-l SNAPSHOT_PARAM] [-S SPARSE_SIZE] [-r RATE_LIMIT] [-m NUM_COROUTINES] [-W] FILENAME [FILENAME2 [...]] OUTPUT_FILENAME
Convert the disk image *FILENAME* or a snapshot *SNAPSHOT_PARAM*
to disk image *OUTPUT_FILENAME* using format *OUTPUT_FMT*. It can
select PL031 # RTC
select PL061 # GPIO
select USB_EHCI_SYSBUS
+ select WDT_SBSA
config SABRELITE
bool
/* DWC2 */
object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB);
+ /* CPRMAN clock manager */
+ object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN);
+
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
OBJECT(&s->gpu_bus_mr));
}
return;
}
+ /* CPRMAN clock manager */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) {
+ return;
+ }
+ memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0));
+ qdev_connect_clock_in(DEVICE(&s->uart0), "clk",
+ qdev_get_clock_out(DEVICE(&s->cprman), "uart-out"));
+
memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
- create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
- create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
+ create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
-struct BCM283XInfo {
+typedef struct BCM283XClass {
+ /*< private >*/
+ DeviceClass parent_class;
+ /*< public >*/
const char *name;
const char *cpu_type;
+ unsigned core_count;
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
-};
+} BCM283XClass;
-static const BCM283XInfo bcm283x_socs[] = {
- {
- .name = TYPE_BCM2836,
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"),
- .peri_base = 0x3f000000,
- .ctrl_base = 0x40000000,
- .clusterid = 0xf,
- },
-#ifdef TARGET_AARCH64
- {
- .name = TYPE_BCM2837,
- .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"),
- .peri_base = 0x3f000000,
- .ctrl_base = 0x40000000,
- .clusterid = 0x0,
- },
-#endif
-};
+#define BCM283X_CLASS(klass) \
+ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+#define BCM283X_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+
+static Property bcm2836_enabled_cores_property =
+ DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
static void bcm2836_init(Object *obj)
{
BCM283XState *s = BCM283X(obj);
BCM283XClass *bc = BCM283X_GET_CLASS(obj);
- const BCM283XInfo *info = bc->info;
int n;
- for (n = 0; n < BCM283X_NCPUS; n++) {
+ for (n = 0; n < bc->core_count; n++) {
object_initialize_child(obj, "cpu[*]", &s->cpu[n].core,
- info->cpu_type);
+ bc->cpu_type);
+ }
+ if (bc->core_count > 1) {
+ qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property);
+ qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count);
}
- object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL);
+ if (bc->ctrl_base) {
+ object_initialize_child(obj, "control", &s->control,
+ TYPE_BCM2836_CONTROL);
+ }
object_initialize_child(obj, "peripherals", &s->peripherals,
TYPE_BCM2835_PERIPHERALS);
"vcram-size");
}
-static void bcm2836_realize(DeviceState *dev, Error **errp)
+static bool bcm283x_common_realize(DeviceState *dev, Error **errp)
{
BCM283XState *s = BCM283X(dev);
BCM283XClass *bc = BCM283X_GET_CLASS(dev);
- const BCM283XInfo *info = bc->info;
Object *obj;
- int n;
/* common peripherals from bcm2835 */
object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) {
- return;
+ return false;
}
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals),
"sd-bus");
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0,
- info->peri_base, 1);
+ bc->peri_base, 1);
+ return true;
+}
+
+static void bcm2835_realize(DeviceState *dev, Error **errp)
+{
+ BCM283XState *s = BCM283X(dev);
+
+ if (!bcm283x_common_realize(dev, errp)) {
+ return;
+ }
+
+ if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) {
+ return;
+ }
+
+ /* Connect irq/fiq outputs from the interrupt controller. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1,
+ qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ));
+}
+
+static void bcm2836_realize(DeviceState *dev, Error **errp)
+{
+ BCM283XState *s = BCM283X(dev);
+ BCM283XClass *bc = BCM283X_GET_CLASS(dev);
+ int n;
+
+ if (!bcm283x_common_realize(dev, errp)) {
+ return;
+ }
/* bcm2836 interrupt controller (and mailboxes, etc.) */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0,
qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0));
for (n = 0; n < BCM283X_NCPUS; n++) {
/* TODO: this should be converted to a property of ARM_CPU */
- s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n;
+ s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
/* set periphbase/CBAR value for CPU-local registers */
if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
- info->peri_base, errp)) {
+ bc->peri_base, errp)) {
return;
}
}
}
-static Property bcm2836_props[] = {
- DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus,
- BCM283X_NCPUS),
- DEFINE_PROP_END_OF_LIST()
-};
-
static void bcm283x_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- BCM283XClass *bc = BCM283X_CLASS(oc);
- bc->info = data;
- dc->realize = bcm2836_realize;
- device_class_set_props(dc, bcm2836_props);
/* Reason: Must be wired up in code (see raspi_init() function) */
dc->user_creatable = false;
}
-static const TypeInfo bcm283x_type_info = {
- .name = TYPE_BCM283X,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(BCM283XState),
- .instance_init = bcm2836_init,
- .class_size = sizeof(BCM283XClass),
- .abstract = true,
+static void bcm2835_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
+ bc->core_count = 1;
+ bc->peri_base = 0x20000000;
+ dc->realize = bcm2835_realize;
+};
+
+static void bcm2836_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ bc->core_count = BCM283X_NCPUS;
+ bc->peri_base = 0x3f000000;
+ bc->ctrl_base = 0x40000000;
+ bc->clusterid = 0xf;
+ dc->realize = bcm2836_realize;
};
-static void bcm2836_register_types(void)
+#ifdef TARGET_AARCH64
+static void bcm2837_class_init(ObjectClass *oc, void *data)
{
- int i;
-
- type_register_static(&bcm283x_type_info);
- for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) {
- TypeInfo ti = {
- .name = bcm283x_socs[i].name,
- .parent = TYPE_BCM283X,
- .class_init = bcm283x_class_init,
- .class_data = (void *) &bcm283x_socs[i],
- };
- type_register(&ti);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ BCM283XClass *bc = BCM283X_CLASS(oc);
+
+ bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
+ bc->core_count = BCM283X_NCPUS;
+ bc->peri_base = 0x3f000000;
+ bc->ctrl_base = 0x40000000;
+ bc->clusterid = 0x0;
+ dc->realize = bcm2836_realize;
+};
+#endif
+
+static const TypeInfo bcm283x_types[] = {
+ {
+ .name = TYPE_BCM2835,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2835_class_init,
+ }, {
+ .name = TYPE_BCM2836,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2836_class_init,
+#ifdef TARGET_AARCH64
+ }, {
+ .name = TYPE_BCM2837,
+ .parent = TYPE_BCM283X,
+ .class_init = bcm2837_class_init,
+#endif
+ }, {
+ .name = TYPE_BCM283X,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(BCM283XState),
+ .instance_init = bcm2836_init,
+ .class_size = sizeof(BCM283XClass),
+ .class_init = bcm283x_class_init,
+ .abstract = true,
}
-}
+};
-type_init(bcm2836_register_types)
+DEFINE_TYPES(bcm283x_types)
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x30, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
+ /* fallthrough */
case 3:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x20, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
+ /* fallthrough */
case 2:
address_space_stl_notdirty(&address_space_memory,
SMP_BOOT_REG + 0x10, 0,
#define NPCM7XX_GCR_BA (0xf0800000)
#define NPCM7XX_CLK_BA (0xf0801000)
#define NPCM7XX_MC_BA (0xf0824000)
+#define NPCM7XX_RNG_BA (0xf000b000)
+
+/* USB Host modules */
+#define NPCM7XX_EHCI_BA (0xf0806000)
+#define NPCM7XX_OHCI_BA (0xf0807000)
/* Internal AHB SRAM */
#define NPCM7XX_RAM3_BA (0xc0008000)
NPCM7XX_TIMER12_IRQ,
NPCM7XX_TIMER13_IRQ,
NPCM7XX_TIMER14_IRQ,
+ NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
+ NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
+ NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
+ NPCM7XX_EHCI_IRQ = 61,
+ NPCM7XX_OHCI_IRQ = 62,
+ NPCM7XX_GPIO0_IRQ = 116,
+ NPCM7XX_GPIO1_IRQ,
+ NPCM7XX_GPIO2_IRQ,
+ NPCM7XX_GPIO3_IRQ,
+ NPCM7XX_GPIO4_IRQ,
+ NPCM7XX_GPIO5_IRQ,
+ NPCM7XX_GPIO6_IRQ,
+ NPCM7XX_GPIO7_IRQ,
};
/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
0xb8000000, /* CS3 */
};
+static const struct {
+ hwaddr regs_addr;
+ uint32_t unconnected_pins;
+ uint32_t reset_pu;
+ uint32_t reset_pd;
+ uint32_t reset_osrc;
+ uint32_t reset_odsc;
+} npcm7xx_gpio[] = {
+ {
+ .regs_addr = 0xf0010000,
+ .reset_pu = 0xff03ffff,
+ .reset_pd = 0x00fc0000,
+ }, {
+ .regs_addr = 0xf0011000,
+ .unconnected_pins = 0x0000001e,
+ .reset_pu = 0xfefffe07,
+ .reset_pd = 0x010001e0,
+ }, {
+ .regs_addr = 0xf0012000,
+ .reset_pu = 0x780fffff,
+ .reset_pd = 0x07f00000,
+ .reset_odsc = 0x00700000,
+ }, {
+ .regs_addr = 0xf0013000,
+ .reset_pu = 0x00fc0000,
+ .reset_pd = 0xff000000,
+ }, {
+ .regs_addr = 0xf0014000,
+ .reset_pu = 0xffffffff,
+ }, {
+ .regs_addr = 0xf0015000,
+ .reset_pu = 0xbf83f801,
+ .reset_pd = 0x007c0000,
+ .reset_osrc = 0x000000f1,
+ .reset_odsc = 0x3f9f80f1,
+ }, {
+ .regs_addr = 0xf0016000,
+ .reset_pu = 0xfc00f801,
+ .reset_pd = 0x000007fe,
+ .reset_odsc = 0x00000800,
+ }, {
+ .regs_addr = 0xf0017000,
+ .unconnected_pins = 0xffffff00,
+ .reset_pu = 0x0000007f,
+ .reset_osrc = 0x0000007f,
+ .reset_odsc = 0x0000007f,
+ },
+};
+
static const struct {
const char *name;
hwaddr regs_addr;
object_initialize_child(obj, "otp2", &s->fuse_array,
TYPE_NPCM7XX_FUSE_ARRAY);
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
+ object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
}
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
+ object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
+ }
+
+ object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
+ object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
+
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
qemu_irq irq = npcm7xx_irq(s, first_irq + j);
sysbus_connect_irq(sbd, j, irq);
}
+
+ /* IRQ for watchdogs */
+ sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
+ npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
+ /* GPIO that connects clk module with watchdog */
+ qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
+ NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
+ qdev_get_gpio_in_named(DEVICE(&s->clk),
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
}
/* UART0..3 (16550 compatible) */
serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
+ /* Random Number Generator. Cannot fail. */
+ sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
+
+ /* GPIO modules. Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
+ Object *obj = OBJECT(&s->gpio[i]);
+
+ object_property_set_uint(obj, "reset-pullup",
+ npcm7xx_gpio[i].reset_pu, &error_abort);
+ object_property_set_uint(obj, "reset-pulldown",
+ npcm7xx_gpio[i].reset_pd, &error_abort);
+ object_property_set_uint(obj, "reset-osrc",
+ npcm7xx_gpio[i].reset_osrc, &error_abort);
+ object_property_set_uint(obj, "reset-odsc",
+ npcm7xx_gpio[i].reset_odsc, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
+ npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
+ }
+
+ /* USB Host */
+ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
+ &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
+ npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
+
+ object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
+ &error_abort);
+ object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
+ npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
+
/*
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
* specified, but this is a programming error.
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
- create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB);
create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
- create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
- create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
FIELD(REV_CODE, STYLE, 23, 1);
typedef enum RaspiProcessorId {
+ PROCESSOR_ID_BCM2835 = 0,
PROCESSOR_ID_BCM2836 = 1,
PROCESSOR_ID_BCM2837 = 2,
} RaspiProcessorId;
const char *type;
int cores_count;
} soc_property[] = {
+ [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1},
[PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
[PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
};
mc->default_ram_id = "ram";
};
+static void raspi0_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x920092; /* Revision 1.2 */
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
+static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x900021; /* Revision 1.1 */
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
};
#ifdef TARGET_AARCH64
+static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+ rmc->board_rev = 0x9020e0; /* Revision 1.0 */
+ raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
static const TypeInfo raspi_machine_types[] = {
{
+ .name = MACHINE_TYPE_NAME("raspi0"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi0_machine_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("raspi1ap"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi1ap_machine_class_init,
+ }, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
#ifdef TARGET_AARCH64
+ }, {
+ .name = MACHINE_TYPE_NAME("raspi3ap"),
+ .parent = TYPE_RASPI_MACHINE,
+ .class_init = raspi3ap_machine_class_init,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
#include "hw/qdev-properties.h"
#include "hw/usb.h"
#include "hw/char/pl011.h"
+#include "hw/watchdog/sbsa_gwdt.h"
#include "net/net.h"
#include "qom/object.h"
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
SBSA_SECURE_EC,
+ SBSA_GWDT,
+ SBSA_GWDT_REFRESH,
+ SBSA_GWDT_CONTROL,
SBSA_SMMU,
SBSA_UART,
SBSA_RTC,
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
+ [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
+ [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
[SBSA_UART] = { 0x60000000, 0x00001000 },
[SBSA_RTC] = { 0x60010000, 0x00001000 },
[SBSA_GPIO] = { 0x60020000, 0x00001000 },
[SBSA_AHCI] = 10,
[SBSA_EHCI] = 11,
[SBSA_SMMU] = 12, /* ... to 15 */
+ [SBSA_GWDT] = 16,
};
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
}
+static void create_wdt(const SBSAMachineState *sms)
+{
+ hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
+ hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
+ DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
+ int irq = sbsa_ref_irqmap[SBSA_GWDT];
+
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, rbase);
+ sysbus_mmio_map(s, 1, cbase);
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
+}
+
static DeviceState *gpio_key_dev;
static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
{
create_rtc(sms);
+ create_wdt(sms);
+
create_gpio(sms);
create_ahci(sms);
.name = "smmuv3",
.version_id = 1,
.minimum_version_id = 1,
+ .priority = MIG_PRI_IOMMU,
.fields = (VMStateField[]) {
VMSTATE_UINT32(features, SMMUv3State),
VMSTATE_UINT8(sid_size, SMMUv3State),
smmuv3_decode_cd(uint32_t oas) "oas=%d"
smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
-smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
+smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
MachineState *ms = MACHINE(hotplug_dev);
bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
- Error *local_err = NULL;
- pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err);
- if (local_err) {
- goto out;
- }
+ pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
if (is_nvdimm) {
nvdimm_plug(ms->nvdimms_state);
hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
dev, &error_abort);
-
-out:
- error_propagate(errp, local_err);
}
static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
mc->desc = "Xilinx Versal Virtual development board";
mc->init = versal_virt_init;
+ mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
mc->no_cdrom = true;
#include "hw/char/pl011.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
+#include "hw/qdev-clock.h"
#include "migration/vmstate.h"
#include "chardev/char-fe.h"
#include "qemu/log.h"
s->read_trigger = 1;
}
+static unsigned int pl011_get_baudrate(const PL011State *s)
+{
+ uint64_t clk;
+
+ if (s->fbrd == 0) {
+ return 0;
+ }
+
+ clk = clock_get_hz(s->clk);
+ return (clk / ((s->ibrd << 6) + s->fbrd)) << 2;
+}
+
+static void pl011_trace_baudrate_change(const PL011State *s)
+{
+ trace_pl011_baudrate_change(pl011_get_baudrate(s),
+ clock_get_hz(s->clk),
+ s->ibrd, s->fbrd);
+}
+
static void pl011_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
break;
case 9: /* UARTIBRD */
s->ibrd = value;
+ pl011_trace_baudrate_change(s);
break;
case 10: /* UARTFBRD */
s->fbrd = value;
+ pl011_trace_baudrate_change(s);
break;
case 11: /* UARTLCR_H */
/* Reset the FIFO state on FIFO enable or disable */
pl011_put_fifo(opaque, 0x400);
}
+static void pl011_clock_update(void *opaque)
+{
+ PL011State *s = PL011(opaque);
+
+ pl011_trace_baudrate_change(s);
+}
+
static const MemoryRegionOps pl011_ops = {
.read = pl011_read,
.write = pl011_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static const VMStateDescription vmstate_pl011_clock = {
+ .name = "pl011/clock",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CLOCK(clk, PL011State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_pl011 = {
.name = "pl011",
.version_id = 2,
VMSTATE_INT32(read_count, PL011State),
VMSTATE_INT32(read_trigger, PL011State),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_pl011_clock,
+ NULL
}
};
sysbus_init_irq(sbd, &s->irq[i]);
}
+ s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s);
+
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d"
pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d"
pl011_put_fifo_full(void) "FIFO now full, RXFF set"
+pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
# cmsdk-apb-uart.c
cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
if (clk->period == period) {
return false;
}
- trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
- CLOCK_PERIOD_TO_NS(period));
+ trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period),
+ CLOCK_PERIOD_TO_HZ(period));
clk->period = period;
return true;
if (child->period != clk->period) {
child->period = clk->period;
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
- CLOCK_PERIOD_TO_NS(clk->period),
+ CLOCK_PERIOD_TO_HZ(clk->period),
call_callbacks);
if (call_callbacks && child->callback) {
child->callback(child->callback_opaque);
}
if (delta == 0) {
+ if (s->enabled == 0) {
+ /* trigger callback disabled the timer already */
+ return;
+ }
if (!qtest_enabled()) {
fprintf(stderr, "Timer with delta zero, disabling\n");
}
# clock.c
clock_set_source(const char *clk, const char *src) "'%s', src='%s'"
clock_disconnect(const char *clk) "'%s'"
-clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=%"PRIu64"->%"PRIu64
+clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"Hz->%"PRIu64"Hz"
clock_propagate(const char *clk) "'%s'"
-clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s', src='%s', ns=%"PRIu64", cb=%d"
+clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s', src='%s', val=%"PRIu64"Hz cb=%d"
.read = tcx_stip_readl,
.write = tcx_stip_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static const MemoryRegionOps tcx_rstip_ops = {
.read = tcx_stip_readl,
.write = tcx_rstip_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
.read = tcx_blit_readl,
.write = tcx_rblit_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
+ .impl = {
.min_access_size = 4,
.max_access_size = 4,
},
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
static void tcx_invalidate_cursor_position(TCXState *s)
static void sparc32_espdma_device_init(Object *obj)
{
DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
+ ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"espdma-mmio", DMA_SIZE);
+
+ object_initialize_child(obj, "esp", &es->esp, TYPE_ESP);
}
static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
{
- DeviceState *d;
- SysBusESPState *sysbus;
- ESPState *esp;
-
- d = qdev_new(TYPE_ESP);
- object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
- sysbus = ESP(d);
- esp = &sysbus->esp;
+ ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
+ SysBusESPState *sysbus = ESP(&es->esp);
+ ESPState *esp = &sysbus->esp;
+
esp->dma_memory_read = espdma_memory_read;
esp->dma_memory_write = espdma_memory_write;
esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2;
esp->dma_enabled = 1;
- sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
}
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
static void sparc32_ledma_device_init(Object *obj)
{
DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
+ LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"ledma-mmio", DMA_SIZE);
+
+ object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
}
static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
{
- DeviceState *d;
- NICInfo *nd = &nd_table[0];
+ LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
+ SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
- /* FIXME use qdev NIC properties instead of nd_table[] */
- qemu_check_nic_model(nd, TYPE_LANCE);
-
- d = qdev_new(TYPE_LANCE);
- object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
- qdev_set_nic_properties(d, nd);
- object_property_set_link(OBJECT(d), "dma", OBJECT(dev), &error_abort);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
+ object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
}
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
return;
}
- espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE);
+ espdma = DEVICE(&s->espdma);
object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
- object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp);
memory_region_add_subregion(&s->dmamem, 0x0,
sysbus_mmio_get_region(sbd, 0));
- ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE);
+ ledma = DEVICE(&s->ledma);
object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
- object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance);
memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
sysbus_init_mmio(sbd, &s->dmamem);
+
+ object_initialize_child(obj, "espdma", &s->espdma,
+ TYPE_SPARC32_ESPDMA_DEVICE);
+ object_initialize_child(obj, "ledma", &s->ledma,
+ TYPE_SPARC32_LEDMA_DEVICE);
}
static void sparc32_dma_class_init(ObjectClass *klass, void *data)
softmmu_ss.add(when: 'CONFIG_ZAURUS', if_true: files('zaurus.c'))
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_gpio.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
--- /dev/null
+/*
+ * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/gpio/npcm7xx_gpio.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+/* 32-bit register indices. */
+enum NPCM7xxGPIORegister {
+ NPCM7XX_GPIO_TLOCK1,
+ NPCM7XX_GPIO_DIN,
+ NPCM7XX_GPIO_POL,
+ NPCM7XX_GPIO_DOUT,
+ NPCM7XX_GPIO_OE,
+ NPCM7XX_GPIO_OTYP,
+ NPCM7XX_GPIO_MP,
+ NPCM7XX_GPIO_PU,
+ NPCM7XX_GPIO_PD,
+ NPCM7XX_GPIO_DBNC,
+ NPCM7XX_GPIO_EVTYP,
+ NPCM7XX_GPIO_EVBE,
+ NPCM7XX_GPIO_OBL0,
+ NPCM7XX_GPIO_OBL1,
+ NPCM7XX_GPIO_OBL2,
+ NPCM7XX_GPIO_OBL3,
+ NPCM7XX_GPIO_EVEN,
+ NPCM7XX_GPIO_EVENS,
+ NPCM7XX_GPIO_EVENC,
+ NPCM7XX_GPIO_EVST,
+ NPCM7XX_GPIO_SPLCK,
+ NPCM7XX_GPIO_MPLCK,
+ NPCM7XX_GPIO_IEM,
+ NPCM7XX_GPIO_OSRC,
+ NPCM7XX_GPIO_ODSC,
+ NPCM7XX_GPIO_DOS = 0x68 / sizeof(uint32_t),
+ NPCM7XX_GPIO_DOC,
+ NPCM7XX_GPIO_OES,
+ NPCM7XX_GPIO_OEC,
+ NPCM7XX_GPIO_TLOCK2 = 0x7c / sizeof(uint32_t),
+ NPCM7XX_GPIO_REGS_END,
+};
+
+#define NPCM7XX_GPIO_REGS_SIZE (4 * KiB)
+
+#define NPCM7XX_GPIO_LOCK_MAGIC1 (0xc0defa73)
+#define NPCM7XX_GPIO_LOCK_MAGIC2 (0xc0de1248)
+
+static void npcm7xx_gpio_update_events(NPCM7xxGPIOState *s, uint32_t din_diff)
+{
+ uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];
+
+ /* Trigger on high level */
+ s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];
+ /* Trigger on both edges */
+ s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]
+ & s->regs[NPCM7XX_GPIO_EVBE]);
+ /* Trigger on rising edge */
+ s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new
+ & s->regs[NPCM7XX_GPIO_EVTYP]);
+
+ trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,
+ s->regs[NPCM7XX_GPIO_EVST],
+ s->regs[NPCM7XX_GPIO_EVEN]);
+ qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]
+ & s->regs[NPCM7XX_GPIO_EVEN]));
+}
+
+static void npcm7xx_gpio_update_pins(NPCM7xxGPIOState *s, uint32_t diff)
+{
+ uint32_t drive_en;
+ uint32_t drive_lvl;
+ uint32_t not_driven;
+ uint32_t undefined;
+ uint32_t pin_diff;
+ uint32_t din_old;
+
+ /* Calculate level of each pin driven by GPIO controller. */
+ drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];
+ /* If OTYP=1, only drive low (open drain) */
+ drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]
+ & drive_lvl);
+ /*
+ * If a pin is driven to opposite levels by the GPIO controller and the
+ * external driver, the result is undefined.
+ */
+ undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);
+ if (undefined) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: pins have multiple drivers: 0x%" PRIx32 "\n",
+ DEVICE(s)->canonical_path, undefined);
+ }
+
+ not_driven = ~(drive_en | s->ext_driven);
+ pin_diff = s->pin_level;
+
+ /* Set pins to externally driven level. */
+ s->pin_level = s->ext_level & s->ext_driven;
+ /* Set internally driven pins, ignoring any conflicts. */
+ s->pin_level |= drive_lvl & drive_en;
+ /* Pull up undriven pins with internal pull-up enabled. */
+ s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];
+ /* Pins not driven, pulled up or pulled down are undefined */
+ undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]
+ | s->regs[NPCM7XX_GPIO_PD]);
+
+ /* If any pins changed state, update the outgoing GPIOs. */
+ pin_diff ^= s->pin_level;
+ pin_diff |= undefined & diff;
+ if (pin_diff) {
+ int i;
+
+ for (i = 0; i < NPCM7XX_GPIO_NR_PINS; i++) {
+ uint32_t mask = BIT(i);
+ if (pin_diff & mask) {
+ int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);
+ trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,
+ i, level);
+ qemu_set_irq(s->output[i], level);
+ }
+ }
+ }
+
+ /* Calculate new value of DIN after masking and polarity setting. */
+ din_old = s->regs[NPCM7XX_GPIO_DIN];
+ s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])
+ ^ s->regs[NPCM7XX_GPIO_POL]);
+
+ /* See if any new events triggered because of all this. */
+ npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);
+}
+
+static bool npcm7xx_gpio_is_locked(NPCM7xxGPIOState *s)
+{
+ return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;
+}
+
+static uint64_t npcm7xx_gpio_regs_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ hwaddr reg = addr / sizeof(uint32_t);
+ NPCM7xxGPIOState *s = opaque;
+ uint64_t value = 0;
+
+ switch (reg) {
+ case NPCM7XX_GPIO_TLOCK1 ... NPCM7XX_GPIO_EVEN:
+ case NPCM7XX_GPIO_EVST ... NPCM7XX_GPIO_ODSC:
+ value = s->regs[reg];
+ break;
+
+ case NPCM7XX_GPIO_EVENS ... NPCM7XX_GPIO_EVENC:
+ case NPCM7XX_GPIO_DOS ... NPCM7XX_GPIO_TLOCK2:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: read from write-only register 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, addr);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, addr);
+ break;
+ }
+
+ trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);
+
+ return value;
+}
+
+static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ hwaddr reg = addr / sizeof(uint32_t);
+ NPCM7xxGPIOState *s = opaque;
+ uint32_t value = v;
+ uint32_t diff;
+
+ trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);
+
+ if (npcm7xx_gpio_is_locked(s)) {
+ switch (reg) {
+ case NPCM7XX_GPIO_TLOCK1:
+ if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&
+ value == NPCM7XX_GPIO_LOCK_MAGIC1) {
+ s->regs[NPCM7XX_GPIO_TLOCK1] = 0;
+ s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
+ }
+ break;
+
+ case NPCM7XX_GPIO_TLOCK2:
+ s->regs[reg] = value;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to locked register @ 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, addr);
+ break;
+ }
+
+ return;
+ }
+
+ diff = s->regs[reg] ^ value;
+
+ switch (reg) {
+ case NPCM7XX_GPIO_TLOCK1:
+ case NPCM7XX_GPIO_TLOCK2:
+ s->regs[NPCM7XX_GPIO_TLOCK1] = 1;
+ s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
+ break;
+
+ case NPCM7XX_GPIO_DIN:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, addr);
+ break;
+
+ case NPCM7XX_GPIO_POL:
+ case NPCM7XX_GPIO_DOUT:
+ case NPCM7XX_GPIO_OE:
+ case NPCM7XX_GPIO_OTYP:
+ case NPCM7XX_GPIO_PU:
+ case NPCM7XX_GPIO_PD:
+ case NPCM7XX_GPIO_IEM:
+ s->regs[reg] = value;
+ npcm7xx_gpio_update_pins(s, diff);
+ break;
+
+ case NPCM7XX_GPIO_DOS:
+ s->regs[NPCM7XX_GPIO_DOUT] |= value;
+ npcm7xx_gpio_update_pins(s, value);
+ break;
+ case NPCM7XX_GPIO_DOC:
+ s->regs[NPCM7XX_GPIO_DOUT] &= ~value;
+ npcm7xx_gpio_update_pins(s, value);
+ break;
+ case NPCM7XX_GPIO_OES:
+ s->regs[NPCM7XX_GPIO_OE] |= value;
+ npcm7xx_gpio_update_pins(s, value);
+ break;
+ case NPCM7XX_GPIO_OEC:
+ s->regs[NPCM7XX_GPIO_OE] &= ~value;
+ npcm7xx_gpio_update_pins(s, value);
+ break;
+
+ case NPCM7XX_GPIO_EVTYP:
+ case NPCM7XX_GPIO_EVBE:
+ case NPCM7XX_GPIO_EVEN:
+ s->regs[reg] = value;
+ npcm7xx_gpio_update_events(s, 0);
+ break;
+
+ case NPCM7XX_GPIO_EVENS:
+ s->regs[NPCM7XX_GPIO_EVEN] |= value;
+ npcm7xx_gpio_update_events(s, 0);
+ break;
+ case NPCM7XX_GPIO_EVENC:
+ s->regs[NPCM7XX_GPIO_EVEN] &= ~value;
+ npcm7xx_gpio_update_events(s, 0);
+ break;
+
+ case NPCM7XX_GPIO_EVST:
+ s->regs[reg] &= ~value;
+ npcm7xx_gpio_update_events(s, 0);
+ break;
+
+ case NPCM7XX_GPIO_MP:
+ case NPCM7XX_GPIO_DBNC:
+ case NPCM7XX_GPIO_OSRC:
+ case NPCM7XX_GPIO_ODSC:
+ /* Nothing to do; just store the value. */
+ s->regs[reg] = value;
+ break;
+
+ case NPCM7XX_GPIO_OBL0:
+ case NPCM7XX_GPIO_OBL1:
+ case NPCM7XX_GPIO_OBL2:
+ case NPCM7XX_GPIO_OBL3:
+ s->regs[reg] = value;
+ qemu_log_mask(LOG_UNIMP, "%s: Blinking is not implemented\n",
+ __func__);
+ break;
+
+ case NPCM7XX_GPIO_SPLCK:
+ case NPCM7XX_GPIO_MPLCK:
+ qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",
+ __func__);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, addr);
+ break;
+ }
+}
+
+static const MemoryRegionOps npcm7xx_gpio_regs_ops = {
+ .read = npcm7xx_gpio_regs_read,
+ .write = npcm7xx_gpio_regs_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_gpio_set_input(void *opaque, int line, int level)
+{
+ NPCM7xxGPIOState *s = opaque;
+
+ trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);
+
+ g_assert(line >= 0 && line < NPCM7XX_GPIO_NR_PINS);
+
+ s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);
+ s->ext_level = deposit32(s->ext_level, line, 1, level > 0);
+
+ npcm7xx_gpio_update_pins(s, BIT(line));
+}
+
+static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;
+ s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;
+ s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;
+ s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
+}
+
+static void npcm7xx_gpio_hold_reset(Object *obj)
+{
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
+
+ npcm7xx_gpio_update_pins(s, -1);
+}
+
+static void npcm7xx_gpio_init(Object *obj)
+{
+ NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
+ DeviceState *dev = DEVICE(obj);
+
+ memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,
+ "regs", NPCM7XX_GPIO_REGS_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+ qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
+ qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
+}
+
+static const VMStateDescription vmstate_npcm7xx_gpio = {
+ .name = "npcm7xx-gpio",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(pin_level, NPCM7xxGPIOState),
+ VMSTATE_UINT32(ext_level, NPCM7xxGPIOState),
+ VMSTATE_UINT32(ext_driven, NPCM7xxGPIOState),
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxGPIOState, NPCM7XX_GPIO_NR_REGS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static Property npcm7xx_gpio_properties[] = {
+ /* Bit n set => pin n has pullup enabled by default. */
+ DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
+ /* Bit n set => pin n has pulldown enabled by default. */
+ DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
+ /* Bit n set => pin n has high slew rate by default. */
+ DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
+ /* Bit n set => pin n has high drive strength by default. */
+ DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *reset = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
+
+ dc->desc = "NPCM7xx GPIO Controller";
+ dc->vmsd = &vmstate_npcm7xx_gpio;
+ reset->phases.enter = npcm7xx_gpio_enter_reset;
+ reset->phases.hold = npcm7xx_gpio_hold_reset;
+ device_class_set_props(dc, npcm7xx_gpio_properties);
+}
+
+static const TypeInfo npcm7xx_gpio_types[] = {
+ {
+ .name = TYPE_NPCM7XX_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxGPIOState),
+ .class_init = npcm7xx_gpio_class_init,
+ .instance_init = npcm7xx_gpio_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_gpio_types);
# See docs/devel/tracing.txt for syntax documentation.
+# npcm7xx_gpio.c
+npcm7xx_gpio_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_gpio_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_gpio_set_input(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
+npcm7xx_gpio_set_output(const char *id, int32_t line, int32_t level) "%s line: %" PRIi32 " level: %" PRIi32
+npcm7xx_gpio_update_events(const char *id, uint32_t evst, uint32_t even) "%s evst: 0x%08" PRIx32 " even: 0x%08" PRIx32
+
# nrf51_gpio.c
nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
static void pc_memory_plug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
- Error *local_err = NULL;
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
MachineState *ms = MACHINE(hotplug_dev);
bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
- pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
- if (local_err) {
- goto out;
- }
+ pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
if (is_nvdimm) {
nvdimm_plug(ms->nvdimms_state);
}
hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
-out:
- error_propagate(errp, local_err);
}
static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
/* Cancel PIO callback, reset registers/signature, etc */
ide_reset(s);
- if (s->drive_kind == IDE_CD) {
- /* ATAPI drives do not set READY or SEEK */
- s->status = 0x00;
- }
+ /* perform diagnostic */
+ cmd_exec_dev_diagnostic(s, WIN_DIAGNOSE);
}
static void ide_bus_perform_srst(void *opaque)
s = &bus->ifs[i];
ide_perform_srst(s);
}
+
+ bus->cmd &= ~IDE_CTRL_RESET;
}
void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val)
/* Device0 and Device1 each have their own control register,
* but QEMU models it as just one register in the controller. */
- if ((bus->cmd & IDE_CTRL_RESET) &&
- !(val & IDE_CTRL_RESET)) {
- /* SRST triggers on falling edge */
+ if (!(bus->cmd & IDE_CTRL_RESET) && (val & IDE_CTRL_RESET)) {
for (i = 0; i < 2; i++) {
s = &bus->ifs[i];
s->status |= BUSY_STAT;
errp);
}
-void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine, Error **errp)
+void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine)
{
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
MemoryRegion *vmstate_mr = ddc->get_vmstate_memory_region(dimm,
--- /dev/null
+/*
+ * BCM2835 CPRMAN clock manager
+ *
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * This peripheral is roughly divided into 3 main parts:
+ * - the PLLs
+ * - the PLL channels
+ * - the clock muxes
+ *
+ * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
+ * channels. Those channel are then connected to the clock muxes. Each mux has
+ * multiples sources (usually the xosc, some of the PLL channels and some "test
+ * debug" clocks). A mux is configured to select a given source through its
+ * control register. Each mux has one output clock that also goes out of the
+ * CPRMAN. This output clock usually connects to another peripheral in the SoC
+ * (so a given mux is dedicated to a peripheral).
+ *
+ * At each level (PLL, channel and mux), the clock can be altered through
+ * dividers (and multipliers in case of the PLLs), and can be disabled (in this
+ * case, the next levels see no clock).
+ *
+ * This can be sum-up as follows (this is an example and not the actual BCM2835
+ * clock tree):
+ *
+ * /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
+ * | |->[PLL channel] muxes takes [mux]
+ * | \->[PLL channel] inputs from [mux]
+ * | some channels [mux]
+ * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
+ * | \->[PLL channel] ...-->[mux]
+ * | [mux]
+ * \-->[PLL]--->[PLL channel] [mux]
+ *
+ * The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
+ * tree configuration.
+ *
+ * The CPRMAN exposes clock outputs with the name of the clock mux suffixed
+ * with "-out" (e.g. "uart-out", "h264-out", ...).
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_cprman_internals.h"
+#include "trace.h"
+
+/* PLL */
+
+static void pll_reset(DeviceState *dev)
+{
+ CprmanPllState *s = CPRMAN_PLL(dev);
+ const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
+
+ *s->reg_cm = info->cm;
+ *s->reg_a2w_ctrl = info->a2w_ctrl;
+ memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
+ *s->reg_a2w_frac = info->a2w_frac;
+}
+
+static bool pll_is_locked(const CprmanPllState *pll)
+{
+ return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
+ && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST);
+}
+
+static void pll_update(CprmanPllState *pll)
+{
+ uint64_t freq, ndiv, fdiv, pdiv;
+
+ if (!pll_is_locked(pll)) {
+ clock_update(pll->out, 0);
+ return;
+ }
+
+ pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV);
+
+ if (!pdiv) {
+ clock_update(pll->out, 0);
+ return;
+ }
+
+ ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV);
+ fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC);
+
+ if (pll->reg_a2w_ana[1] & pll->prediv_mask) {
+ /* The prescaler doubles the parent frequency */
+ ndiv *= 2;
+ fdiv *= 2;
+ }
+
+ /*
+ * We have a multiplier with an integer part (ndiv) and a fractional part
+ * (fdiv), and a divider (pdiv).
+ */
+ freq = clock_get_hz(pll->xosc_in) *
+ ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv);
+ freq /= pdiv;
+ freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH;
+
+ clock_update_hz(pll->out, freq);
+}
+
+static void pll_xosc_update(void *opaque)
+{
+ pll_update(CPRMAN_PLL(opaque));
+}
+
+static void pll_init(Object *obj)
+{
+ CprmanPllState *s = CPRMAN_PLL(obj);
+
+ s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, s);
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
+}
+
+static const VMStateDescription pll_vmstate = {
+ .name = TYPE_CPRMAN_PLL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CLOCK(xosc_in, CprmanPllState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pll_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = pll_reset;
+ dc->vmsd = &pll_vmstate;
+}
+
+static const TypeInfo cprman_pll_info = {
+ .name = TYPE_CPRMAN_PLL,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(CprmanPllState),
+ .class_init = pll_class_init,
+ .instance_init = pll_init,
+};
+
+
+/* PLL channel */
+
+static void pll_channel_reset(DeviceState *dev)
+{
+ CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev);
+ const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id];
+
+ *s->reg_a2w_ctrl = info->a2w_ctrl;
+}
+
+static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
+{
+ /*
+ * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
+ * not set it when enabling the channel, but does clear it when disabling
+ * it.
+ */
+ return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
+ && !(*channel->reg_cm & channel->hold_mask);
+}
+
+static void pll_channel_update(CprmanPllChannelState *channel)
+{
+ uint64_t freq, div;
+
+ if (!pll_channel_is_enabled(channel)) {
+ clock_update(channel->out, 0);
+ return;
+ }
+
+ div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
+
+ if (!div) {
+ /*
+ * It seems that when the divider value is 0, it is considered as
+ * being maximum by the hardware (see the Linux driver).
+ */
+ div = R_A2W_PLLx_CHANNELy_DIV_MASK;
+ }
+
+ /* Some channels have an additional fixed divider */
+ freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
+
+ clock_update_hz(channel->out, freq);
+}
+
+/* Update a PLL and all its channels */
+static void pll_update_all_channels(BCM2835CprmanState *s,
+ CprmanPllState *pll)
+{
+ size_t i;
+
+ pll_update(pll);
+
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
+ CprmanPllChannelState *channel = &s->channels[i];
+ if (channel->parent == pll->id) {
+ pll_channel_update(channel);
+ }
+ }
+}
+
+static void pll_channel_pll_in_update(void *opaque)
+{
+ pll_channel_update(CPRMAN_PLL_CHANNEL(opaque));
+}
+
+static void pll_channel_init(Object *obj)
+{
+ CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj);
+
+ s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in",
+ pll_channel_pll_in_update, s);
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
+}
+
+static const VMStateDescription pll_channel_vmstate = {
+ .name = TYPE_CPRMAN_PLL_CHANNEL,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CLOCK(pll_in, CprmanPllChannelState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pll_channel_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = pll_channel_reset;
+ dc->vmsd = &pll_channel_vmstate;
+}
+
+static const TypeInfo cprman_pll_channel_info = {
+ .name = TYPE_CPRMAN_PLL_CHANNEL,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(CprmanPllChannelState),
+ .class_init = pll_channel_class_init,
+ .instance_init = pll_channel_init,
+};
+
+
+/* clock mux */
+
+static bool clock_mux_is_enabled(CprmanClockMuxState *mux)
+{
+ return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE);
+}
+
+static void clock_mux_update(CprmanClockMuxState *mux)
+{
+ uint64_t freq;
+ uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC);
+ bool enabled = clock_mux_is_enabled(mux);
+
+ *mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled);
+
+ if (!enabled) {
+ clock_update(mux->out, 0);
+ return;
+ }
+
+ freq = clock_get_hz(mux->srcs[src]);
+
+ if (mux->int_bits == 0 && mux->frac_bits == 0) {
+ clock_update_hz(mux->out, freq);
+ return;
+ }
+
+ /*
+ * The divider has an integer and a fractional part. The size of each part
+ * varies with the muxes (int_bits and frac_bits). Both parts are
+ * concatenated, with the integer part always starting at bit 12.
+ *
+ * 31 12 11 0
+ * ------------------------------
+ * CM_DIV | | int | frac | |
+ * ------------------------------
+ * <-----> <------>
+ * int_bits frac_bits
+ */
+ div = extract32(*mux->reg_div,
+ R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits,
+ mux->int_bits + mux->frac_bits);
+
+ if (!div) {
+ clock_update(mux->out, 0);
+ return;
+ }
+
+ freq = muldiv64(freq, 1 << mux->frac_bits, div);
+
+ clock_update_hz(mux->out, freq);
+}
+
+static void clock_mux_src_update(void *opaque)
+{
+ CprmanClockMuxState **backref = opaque;
+ CprmanClockMuxState *s = *backref;
+ CprmanClockMuxSource src = backref - s->backref;
+
+ if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) {
+ return;
+ }
+
+ clock_mux_update(s);
+}
+
+static void clock_mux_reset(DeviceState *dev)
+{
+ CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev);
+ const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id];
+
+ *clock->reg_ctl = info->cm_ctl;
+ *clock->reg_div = info->cm_div;
+}
+
+static void clock_mux_init(Object *obj)
+{
+ CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
+ char *name = g_strdup_printf("srcs[%zu]", i);
+ s->backref[i] = s;
+ s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
+ clock_mux_src_update,
+ &s->backref[i]);
+ g_free(name);
+ }
+
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
+}
+
+static const VMStateDescription clock_mux_vmstate = {
+ .name = TYPE_CPRMAN_CLOCK_MUX,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState,
+ CPRMAN_NUM_CLOCK_MUX_SRC),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void clock_mux_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = clock_mux_reset;
+ dc->vmsd = &clock_mux_vmstate;
+}
+
+static const TypeInfo cprman_clock_mux_info = {
+ .name = TYPE_CPRMAN_CLOCK_MUX,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(CprmanClockMuxState),
+ .class_init = clock_mux_class_init,
+ .instance_init = clock_mux_init,
+};
+
+
+/* DSI0HSCK mux */
+
+static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
+{
+ bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
+ Clock *src = src_is_plld ? s->plld_in : s->plla_in;
+
+ clock_update(s->out, clock_get(src));
+}
+
+static void dsi0hsck_mux_in_update(void *opaque)
+{
+ dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
+}
+
+static void dsi0hsck_mux_init(Object *obj)
+{
+ CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj);
+ DeviceState *dev = DEVICE(obj);
+
+ s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s);
+ s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s);
+ s->out = qdev_init_clock_out(DEVICE(s), "out");
+}
+
+static const VMStateDescription dsi0hsck_mux_vmstate = {
+ .name = TYPE_CPRMAN_DSI0HSCK_MUX,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
+ VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &dsi0hsck_mux_vmstate;
+}
+
+static const TypeInfo cprman_dsi0hsck_mux_info = {
+ .name = TYPE_CPRMAN_DSI0HSCK_MUX,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(CprmanDsi0HsckMuxState),
+ .class_init = dsi0hsck_mux_class_init,
+ .instance_init = dsi0hsck_mux_init,
+};
+
+
+/* CPRMAN "top level" model */
+
+static uint32_t get_cm_lock(const BCM2835CprmanState *s)
+{
+ static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = {
+ [CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT,
+ [CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT,
+ [CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT,
+ [CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT,
+ [CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT,
+ };
+
+ uint32_t r = 0;
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
+ r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i];
+ }
+
+ return r;
+}
+
+static uint64_t cprman_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ BCM2835CprmanState *s = CPRMAN(opaque);
+ uint64_t r = 0;
+ size_t idx = offset / sizeof(uint32_t);
+
+ switch (idx) {
+ case R_CM_LOCK:
+ r = get_cm_lock(s);
+ break;
+
+ default:
+ r = s->regs[idx];
+ }
+
+ trace_bcm2835_cprman_read(offset, r);
+ return r;
+}
+
+static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s,
+ size_t idx)
+{
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
+ if (PLL_INIT_INFO[i].cm_offset == idx) {
+ pll_update_all_channels(s, &s->plls[i]);
+ return;
+ }
+ }
+}
+
+static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
+{
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
+ if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) {
+ pll_channel_update(&s->channels[i]);
+ return;
+ }
+ }
+}
+
+static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx)
+{
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
+ if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) ||
+ (CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) {
+ /* matches CM_CTL or CM_DIV mux register */
+ clock_mux_update(&s->clock_muxes[i]);
+ return;
+ }
+ }
+}
+
+#define CASE_PLL_A2W_REGS(pll_) \
+ case R_A2W_ ## pll_ ## _CTRL: \
+ case R_A2W_ ## pll_ ## _ANA0: \
+ case R_A2W_ ## pll_ ## _ANA1: \
+ case R_A2W_ ## pll_ ## _ANA2: \
+ case R_A2W_ ## pll_ ## _ANA3: \
+ case R_A2W_ ## pll_ ## _FRAC
+
+static void cprman_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ BCM2835CprmanState *s = CPRMAN(opaque);
+ size_t idx = offset / sizeof(uint32_t);
+
+ if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) {
+ trace_bcm2835_cprman_write_invalid_magic(offset, value);
+ return;
+ }
+
+ value &= ~R_CPRMAN_PASSWORD_MASK;
+
+ trace_bcm2835_cprman_write(offset, value);
+ s->regs[idx] = value;
+
+ switch (idx) {
+ case R_CM_PLLA ... R_CM_PLLH:
+ case R_CM_PLLB:
+ /*
+ * A given CM_PLLx register is shared by both the PLL and the channels
+ * of this PLL.
+ */
+ update_pll_and_channels_from_cm(s, idx);
+ break;
+
+ CASE_PLL_A2W_REGS(PLLA) :
+ pll_update(&s->plls[CPRMAN_PLLA]);
+ break;
+
+ CASE_PLL_A2W_REGS(PLLC) :
+ pll_update(&s->plls[CPRMAN_PLLC]);
+ break;
+
+ CASE_PLL_A2W_REGS(PLLD) :
+ pll_update(&s->plls[CPRMAN_PLLD]);
+ break;
+
+ CASE_PLL_A2W_REGS(PLLH) :
+ pll_update(&s->plls[CPRMAN_PLLH]);
+ break;
+
+ CASE_PLL_A2W_REGS(PLLB) :
+ pll_update(&s->plls[CPRMAN_PLLB]);
+ break;
+
+ case R_A2W_PLLA_DSI0:
+ case R_A2W_PLLA_CORE:
+ case R_A2W_PLLA_PER:
+ case R_A2W_PLLA_CCP2:
+ case R_A2W_PLLC_CORE2:
+ case R_A2W_PLLC_CORE1:
+ case R_A2W_PLLC_PER:
+ case R_A2W_PLLC_CORE0:
+ case R_A2W_PLLD_DSI0:
+ case R_A2W_PLLD_CORE:
+ case R_A2W_PLLD_PER:
+ case R_A2W_PLLD_DSI1:
+ case R_A2W_PLLH_AUX:
+ case R_A2W_PLLH_RCAL:
+ case R_A2W_PLLH_PIX:
+ case R_A2W_PLLB_ARM:
+ update_channel_from_a2w(s, idx);
+ break;
+
+ case R_CM_GNRICCTL ... R_CM_SMIDIV:
+ case R_CM_TCNTCNT ... R_CM_VECDIV:
+ case R_CM_PULSECTL ... R_CM_PULSEDIV:
+ case R_CM_SDCCTL ... R_CM_ARMCTL:
+ case R_CM_AVEOCTL ... R_CM_EMMCDIV:
+ case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
+ update_mux_from_cm(s, idx);
+ break;
+
+ case R_CM_DSI0HSCK:
+ dsi0hsck_mux_update(&s->dsi0hsck_mux);
+ break;
+ }
+}
+
+#undef CASE_PLL_A2W_REGS
+
+static const MemoryRegionOps cprman_ops = {
+ .read = cprman_read,
+ .write = cprman_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ /*
+ * Although this hasn't been checked against real hardware, nor the
+ * information can be found in a datasheet, it seems reasonable because
+ * of the "PASSWORD" magic value found in every registers.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+ .impl = {
+ .max_access_size = 4,
+ },
+};
+
+static void cprman_reset(DeviceState *dev)
+{
+ BCM2835CprmanState *s = CPRMAN(dev);
+ size_t i;
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
+ device_cold_reset(DEVICE(&s->plls[i]));
+ }
+
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
+ device_cold_reset(DEVICE(&s->channels[i]));
+ }
+
+ device_cold_reset(DEVICE(&s->dsi0hsck_mux));
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
+ device_cold_reset(DEVICE(&s->clock_muxes[i]));
+ }
+
+ clock_update_hz(s->xosc, s->xosc_freq);
+}
+
+static void cprman_init(Object *obj)
+{
+ BCM2835CprmanState *s = CPRMAN(obj);
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
+ object_initialize_child(obj, PLL_INIT_INFO[i].name,
+ &s->plls[i], TYPE_CPRMAN_PLL);
+ set_pll_init_info(s, &s->plls[i], i);
+ }
+
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
+ object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name,
+ &s->channels[i],
+ TYPE_CPRMAN_PLL_CHANNEL);
+ set_pll_channel_init_info(s, &s->channels[i], i);
+ }
+
+ object_initialize_child(obj, "dsi0hsck-mux",
+ &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
+ s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK];
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
+ char *alias;
+
+ object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
+ &s->clock_muxes[i],
+ TYPE_CPRMAN_CLOCK_MUX);
+ set_clock_mux_init_info(s, &s->clock_muxes[i], i);
+
+ /* Expose muxes output as CPRMAN outputs */
+ alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
+ qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
+ g_free(alias);
+ }
+
+ s->xosc = clock_new(obj, "xosc");
+ s->gnd = clock_new(obj, "gnd");
+
+ clock_set(s->gnd, 0);
+
+ memory_region_init_io(&s->iomem, obj, &cprman_ops,
+ s, "bcm2835-cprman", 0x2000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static void connect_mux_sources(BCM2835CprmanState *s,
+ CprmanClockMuxState *mux,
+ const CprmanPllChannel *clk_mapping)
+{
+ size_t i;
+ Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out;
+ Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out;
+
+ /* For sources from 0 to 3. Source 4 to 9 are mux specific */
+ Clock * const CLK_SRC_MAPPING[] = {
+ [CPRMAN_CLOCK_SRC_GND] = s->gnd,
+ [CPRMAN_CLOCK_SRC_XOSC] = s->xosc,
+ [CPRMAN_CLOCK_SRC_TD0] = td0,
+ [CPRMAN_CLOCK_SRC_TD1] = td1,
+ };
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
+ CprmanPllChannel mapping = clk_mapping[i];
+ Clock *src;
+
+ if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
+ src = s->gnd;
+ } else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
+ src = s->dsi0hsck_mux.out;
+ } else if (i < CPRMAN_CLOCK_SRC_PLLA) {
+ src = CLK_SRC_MAPPING[i];
+ } else {
+ src = s->channels[mapping].out;
+ }
+
+ clock_set_source(mux->srcs[i], src);
+ }
+}
+
+static void cprman_realize(DeviceState *dev, Error **errp)
+{
+ BCM2835CprmanState *s = CPRMAN(dev);
+ size_t i;
+
+ for (i = 0; i < CPRMAN_NUM_PLL; i++) {
+ CprmanPllState *pll = &s->plls[i];
+
+ clock_set_source(pll->xosc_in, s->xosc);
+
+ if (!qdev_realize(DEVICE(pll), NULL, errp)) {
+ return;
+ }
+ }
+
+ for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
+ CprmanPllChannelState *channel = &s->channels[i];
+ CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent;
+ Clock *parent_clk = s->plls[parent].out;
+
+ clock_set_source(channel->pll_in, parent_clk);
+
+ if (!qdev_realize(DEVICE(channel), NULL, errp)) {
+ return;
+ }
+ }
+
+ clock_set_source(s->dsi0hsck_mux.plla_in,
+ s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
+ clock_set_source(s->dsi0hsck_mux.plld_in,
+ s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
+
+ if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
+ return;
+ }
+
+ for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
+ CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
+
+ connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
+
+ if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
+ return;
+ }
+ }
+}
+
+static const VMStateDescription cprman_vmstate = {
+ .name = TYPE_BCM2835_CPRMAN,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property cprman_properties[] = {
+ DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void cprman_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = cprman_realize;
+ dc->reset = cprman_reset;
+ dc->vmsd = &cprman_vmstate;
+ device_class_set_props(dc, cprman_properties);
+}
+
+static const TypeInfo cprman_info = {
+ .name = TYPE_BCM2835_CPRMAN,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835CprmanState),
+ .class_init = cprman_class_init,
+ .instance_init = cprman_init,
+};
+
+static void cprman_register_types(void)
+{
+ type_register_static(&cprman_info);
+ type_register_static(&cprman_pll_info);
+ type_register_static(&cprman_pll_channel_info);
+ type_register_static(&cprman_clock_mux_info);
+ type_register_static(&cprman_dsi0hsck_mux_info);
+}
+
+type_init(cprman_register_types);
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
'npcm7xx_clk.c',
'npcm7xx_gcr.c',
+ 'npcm7xx_rng.c',
))
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
'omap_clk.c',
'bcm2835_property.c',
'bcm2835_rng.c',
'bcm2835_thermal.c',
+ 'bcm2835_cprman.c',
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
#include "qemu/osdep.h"
#include "hw/misc/npcm7xx_clk.h"
+#include "hw/timer/npcm7xx_timer.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/timer.h"
#include "qemu/units.h"
#include "trace.h"
+#include "sysemu/watchdog.h"
#define PLLCON_LOKI BIT(31)
#define PLLCON_LOKS BIT(30)
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
};
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
+
+/* The number of watchdogs that can trigger a reset. */
+#define NPCM7XX_NR_WATCHDOGS (3)
+
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
s->regs[reg] = value;
}
+/* Perform reset action triggered by a watchdog */
+static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
+ int level)
+{
+ NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
+ uint32_t rcr;
+
+ g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
+ rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];
+ if (rcr & NPCM7XX_CLK_WDRCR_CA9C) {
+ watchdog_perform_action();
+ } else {
+ qemu_log_mask(LOG_UNIMP,
+ "%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
+ __func__, rcr);
+ }
+}
+
static const struct MemoryRegionOps npcm7xx_clk_ops = {
.read = npcm7xx_clk_read,
.write = npcm7xx_clk_write,
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
TYPE_NPCM7XX_CLK, 4 * KiB);
sysbus_init_mmio(&s->parent, &s->iomem);
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
}
static const VMStateDescription vmstate_npcm7xx_clk = {
--- /dev/null
+/*
+ * Nuvoton NPCM7xx Random Number Generator.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/misc/npcm7xx_rng.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/guest-random.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+#define NPCM7XX_RNG_REGS_SIZE (4 * KiB)
+
+#define NPCM7XX_RNGCS (0x00)
+#define NPCM7XX_RNGCS_CLKP(rv) extract32(rv, 2, 4)
+#define NPCM7XX_RNGCS_DVALID BIT(1)
+#define NPCM7XX_RNGCS_RNGE BIT(0)
+
+#define NPCM7XX_RNGD (0x04)
+#define NPCM7XX_RNGMODE (0x08)
+#define NPCM7XX_RNGMODE_NORMAL (0x02)
+
+static bool npcm7xx_rng_is_enabled(NPCM7xxRNGState *s)
+{
+ return (s->rngcs & NPCM7XX_RNGCS_RNGE) &&
+ (s->rngmode == NPCM7XX_RNGMODE_NORMAL);
+}
+
+static uint64_t npcm7xx_rng_read(void *opaque, hwaddr offset, unsigned size)
+{
+ NPCM7xxRNGState *s = opaque;
+ uint64_t value = 0;
+
+ switch (offset) {
+ case NPCM7XX_RNGCS:
+ /*
+ * If the RNG is enabled, but we don't have any valid random data, try
+ * obtaining some and update the DVALID bit accordingly.
+ */
+ if (!npcm7xx_rng_is_enabled(s)) {
+ s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
+ } else if (!(s->rngcs & NPCM7XX_RNGCS_DVALID)) {
+ uint8_t byte = 0;
+
+ if (qemu_guest_getrandom(&byte, sizeof(byte), NULL) == 0) {
+ s->rngd = byte;
+ s->rngcs |= NPCM7XX_RNGCS_DVALID;
+ }
+ }
+ value = s->rngcs;
+ break;
+ case NPCM7XX_RNGD:
+ if (npcm7xx_rng_is_enabled(s) && s->rngcs & NPCM7XX_RNGCS_DVALID) {
+ s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
+ value = s->rngd;
+ s->rngd = 0;
+ }
+ break;
+ case NPCM7XX_RNGMODE:
+ value = s->rngmode;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, offset);
+ break;
+ }
+
+ trace_npcm7xx_rng_read(offset, value, size);
+
+ return value;
+}
+
+static void npcm7xx_rng_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ NPCM7xxRNGState *s = opaque;
+
+ trace_npcm7xx_rng_write(offset, value, size);
+
+ switch (offset) {
+ case NPCM7XX_RNGCS:
+ s->rngcs &= NPCM7XX_RNGCS_DVALID;
+ s->rngcs |= value & ~NPCM7XX_RNGCS_DVALID;
+ break;
+ case NPCM7XX_RNGD:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, offset);
+ break;
+ case NPCM7XX_RNGMODE:
+ s->rngmode = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
+ DEVICE(s)->canonical_path, offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps npcm7xx_rng_ops = {
+ .read = npcm7xx_rng_read,
+ .write = npcm7xx_rng_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_rng_enter_reset(Object *obj, ResetType type)
+{
+ NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
+
+ s->rngcs = 0;
+ s->rngd = 0;
+ s->rngmode = 0;
+}
+
+static void npcm7xx_rng_init(Object *obj)
+{
+ NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
+
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
+ NPCM7XX_RNG_REGS_SIZE);
+ sysbus_init_mmio(&s->parent, &s->iomem);
+}
+
+static const VMStateDescription vmstate_npcm7xx_rng = {
+ .name = "npcm7xx-rng",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(rngcs, NPCM7xxRNGState),
+ VMSTATE_UINT8(rngd, NPCM7xxRNGState),
+ VMSTATE_UINT8(rngmode, NPCM7xxRNGState),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static void npcm7xx_rng_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Random Number Generator";
+ dc->vmsd = &vmstate_npcm7xx_rng;
+ rc->phases.enter = npcm7xx_rng_enter_reset;
+}
+
+static const TypeInfo npcm7xx_rng_types[] = {
+ {
+ .name = TYPE_NPCM7XX_RNG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxRNGState),
+ .class_init = npcm7xx_rng_class_init,
+ .instance_init = npcm7xx_rng_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_rng_types);
npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+# npcm7xx_rng.c
+npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
+npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
+
# stm32f4xx_syscfg.c
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
# pca9552.c
pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
pca955x_gpio_change(const char *description, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u -> %u"
+
+# bcm2835_cprman.c
+bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
+bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
+bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 " value:0x%" PRIx64
SpaprVioDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
SpaprVioVlan *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
unsigned total_len;
- uint8_t *lbuf, *p;
+ uint8_t *p;
+ g_autofree uint8_t *lbuf = NULL;
int i, nbufs;
int ret;
return H_RESOURCE;
}
- lbuf = alloca(total_len);
+ lbuf = g_malloc(total_len);
p = lbuf;
for (i = 0; i < nbufs; i++) {
ret = spapr_vio_dma_read(sdev, VLAN_BD_ADDR(bufs[i]),
/*
* Chipset docs:
* PBM: "UltraSPARC IIi User's Manual",
- * http://www.sun.com/processors/manuals/805-0087.pdf
+ * https://web.archive.org/web/20030403110020/http://www.sun.com/processors/manuals/805-0087.pdf
*/
#define PBM_PCI_IMR_MASK 0x7fffffff
trace_sabre_config_write(addr, val);
- switch (addr & 0xffff) {
+ switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */
/* XXX: not implemented yet */
break;
hwaddr addr, unsigned size)
{
SabreState *s = opaque;
- uint32_t val;
+ uint32_t val = 0;
- switch (addr & 0xffff) {
+ switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */
- val = 0;
/* XXX: not implemented yet */
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {
val = s->pci_irq_map[(addr & 0x3f) >> 3];
- } else {
- val = 0;
}
break;
case 0x1000 ... 0x107f: /* OBIO interrupt control */
if (addr & 4) {
val = s->obio_irq_map[(addr & 0xff) >> 3];
- } else {
- val = 0;
}
break;
case 0x1080 ... 0x108f: /* PCI bus error */
if (addr & 4) {
val = s->pci_err_irq_map[(addr & 0xf) >> 3];
- } else {
- val = 0;
}
break;
case 0x2000 ... 0x202f: /* PCI control */
case 0xf020 ... 0xf027: /* Reset control */
if (addr & 4) {
val = s->reset_control;
- } else {
- val = 0;
}
break;
case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
case 0xf000 ... 0xf01f: /* FFB config, memory control */
/* we don't care */
default:
- val = 0;
break;
}
trace_sabre_config_read(addr, val);
{
SabreState *s = SABRE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
- SysBusDevice *sbd = SYS_BUS_DEVICE(s);
PCIDevice *pci_dev;
- /* sabre_config */
- sysbus_mmio_map(sbd, 0, s->special_base);
- /* PCI configuration space */
- sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
- /* pci_ioport */
- sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
-
memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
memory_region_add_subregion(get_system_memory(), s->mem_base,
&s->pci_mmio);
pci_sabre_set_irq, pci_sabre_map_irq, s,
&s->pci_mmio,
&s->pci_ioport,
- 0, 32, TYPE_PCI_BUS);
+ 0, 0x40, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
close_htab_fd(spapr);
}
-void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
- Error **errp)
+int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp)
{
+ ERRP_GUARD();
long rc;
/* Clean up any HPT info from a previous boot */
if (rc == -EOPNOTSUPP) {
error_setg(errp, "HPT not supported in nested guests");
- return;
+ return -EOPNOTSUPP;
}
if (rc < 0) {
/* kernel-side HPT needed, but couldn't allocate one */
- error_setg_errno(errp, errno,
- "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
+ error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d",
shift);
- /* This is almost certainly fatal, but if the caller really
- * wants to carry on with shift == 0, it's welcome to try */
+ error_append_hint(errp, "Try smaller maxmem?\n");
+ return -errno;
} else if (rc > 0) {
/* kernel-side HPT allocated */
if (rc != shift) {
error_setg(errp,
- "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
+ "Requested order %d HPT, but kernel allocated order %ld",
shift, rc);
+ error_append_hint(errp, "Try smaller maxmem?\n");
+ return -ENOSPC;
}
spapr->htab_shift = shift;
if (!spapr->htab) {
error_setg_errno(errp, errno,
"Could not allocate HPT of order %d", shift);
- return;
+ return -ENOMEM;
}
memset(spapr->htab, 0, size);
/* We're setting up a hash table, so that means we're not radix */
spapr->patb_entry = 0;
spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
+ return 0;
}
void spapr_setup_hpt(SpaprMachineState *spapr)
}
if (section_hdr) {
+ int ret;
+
/* First section gives the htab size */
- spapr_reallocate_hpt(spapr, section_hdr, &local_err);
- if (local_err) {
+ ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err);
+ if (ret < 0) {
error_report_err(local_err);
- return -EINVAL;
+ return ret;
}
return 0;
}
assert(fd >= 0);
- rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
+ rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid,
+ &local_err);
if (rc < 0) {
+ error_report_err(local_err);
return rc;
}
}
return rma_size;
}
+static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr)
+{
+ MachineState *machine = MACHINE(spapr);
+ int i;
+
+ for (i = 0; i < machine->ram_slots; i++) {
+ spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i);
+ }
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void spapr_machine_init(MachineState *machine)
{
return 0;
}
-static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
+static bool spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
bool dedicated_hp_event_source, Error **errp)
{
SpaprDrc *drc;
addr / SPAPR_MEMORY_BLOCK_SIZE);
spapr_drc_detach(drc);
}
- return;
+ return false;
}
if (!hotplugged) {
spapr_drc_reset(drc);
nr_lmbs);
}
}
+ return true;
}
static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
- Error *local_err = NULL;
SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
PCDIMMDevice *dimm = PC_DIMM(dev);
- uint64_t size, addr, slot;
+ uint64_t size, addr;
+ int64_t slot;
bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
- pc_dimm_plug(dimm, MACHINE(ms), &local_err);
- if (local_err) {
- goto out;
- }
+ pc_dimm_plug(dimm, MACHINE(ms));
if (!is_nvdimm) {
addr = object_property_get_uint(OBJECT(dimm),
- PC_DIMM_ADDR_PROP, &local_err);
- if (local_err) {
+ PC_DIMM_ADDR_PROP, &error_abort);
+ if (!spapr_add_lmbs(dev, addr, size,
+ spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), errp)) {
goto out_unplug;
}
- spapr_add_lmbs(dev, addr, size,
- spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
- &local_err);
} else {
- slot = object_property_get_uint(OBJECT(dimm),
- PC_DIMM_SLOT_PROP, &local_err);
- if (local_err) {
+ slot = object_property_get_int(OBJECT(dimm),
+ PC_DIMM_SLOT_PROP, &error_abort);
+ /* We should have valid slot number at this point */
+ g_assert(slot >= 0);
+ if (!spapr_add_nvdimm(dev, slot, errp)) {
goto out_unplug;
}
- spapr_add_nvdimm(dev, slot, &local_err);
- }
-
- if (local_err) {
- goto out_unplug;
}
return;
out_unplug:
pc_dimm_unplug(dimm, MACHINE(ms));
-out:
- error_propagate(errp, local_err);
}
static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
uint64_t addr_start, addr;
int i;
- addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
- &error_abort);
+ addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
+ &error_abort);
addr = addr_start;
for (i = 0; i < nr_lmbs; i++) {
DeviceState *dev, Error **errp)
{
SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
- Error *local_err = NULL;
PCDIMMDevice *dimm = PC_DIMM(dev);
uint32_t nr_lmbs;
uint64_t size, addr_start, addr;
nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
- &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
- return;
- }
+ &error_abort);
/*
* An existing pending dimm state for this DIMM means that there is an
vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
}
spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
- cpu_remove_sync(CPU(cpu));
- object_unparent(OBJECT(cpu));
+ qdev_unrealize(DEVICE(cpu));
}
/*
spapr_cpu_core_reset(opaque);
}
+static void spapr_delete_vcpu(PowerPCCPU *cpu)
+{
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+
+ cpu->machine_data = NULL;
+ g_free(spapr_cpu);
+ object_unparent(OBJECT(cpu));
+}
+
static void spapr_cpu_core_unrealize(DeviceState *dev)
{
SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(dev);
int i;
- qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
-
for (i = 0; i < cc->nr_threads; i++) {
- spapr_unrealize_vcpu(sc->threads[i], sc);
+ if (sc->threads[i]) {
+ /*
+ * Since this we can get here from the error path of
+ * spapr_cpu_core_realize(), make sure we only unrealize
+ * vCPUs that have already been realized.
+ */
+ if (object_property_get_bool(OBJECT(sc->threads[i]), "realized",
+ &error_abort)) {
+ spapr_unrealize_vcpu(sc->threads[i], sc);
+ }
+ spapr_delete_vcpu(sc->threads[i]);
+ }
}
g_free(sc->threads);
+ qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
}
static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
kvmppc_set_papr(cpu);
if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
- cpu_remove_sync(CPU(cpu));
+ qdev_unrealize(DEVICE(cpu));
return false;
}
return NULL;
}
-static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
-{
- SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
-
- cpu->machine_data = NULL;
- g_free(spapr_cpu);
- object_unparent(OBJECT(cpu));
-}
-
static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
TYPE_SPAPR_MACHINE);
SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(OBJECT(dev));
- int i, j;
+ int i;
if (!spapr) {
error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
return;
}
- sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
+ qemu_register_reset(spapr_cpu_core_reset_handler, sc);
+ sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
sc->threads[i] = spapr_create_vcpu(sc, i, errp);
- if (!sc->threads[i]) {
- goto err;
- }
- }
-
- for (j = 0; j < cc->nr_threads; j++) {
- if (!spapr_realize_vcpu(sc->threads[j], spapr, sc, errp)) {
- goto err_unrealize;
+ if (!sc->threads[i] ||
+ !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) {
+ spapr_cpu_core_unrealize(dev);
+ return;
}
}
-
- qemu_register_reset(spapr_cpu_core_reset_handler, sc);
- return;
-
-err_unrealize:
- while (--j >= 0) {
- spapr_unrealize_vcpu(sc->threads[j], sc);
- }
-err:
- while (--i >= 0) {
- spapr_delete_vcpu(sc->threads[i], sc);
- }
- g_free(sc->threads);
}
static Property spapr_cpu_core_properties[] = {
dk->realize = realize;
dk->unrealize = unrealize;
/*
- * Reason: it crashes FIXME find and document the real reason
+ * Reason: DR connector needs to be wired to either the machine or to a
+ * PHB in spapr_dr_connector_new().
*/
dk->user_creatable = false;
}
target_ulong args,
uint32_t nret, target_ulong rets)
{
+ int i;
if (nargs != 4 || nret != 1) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
+
+ for (i = 0; i < EVENT_CLASS_MAX; i++) {
+ if (rtas_event_log_contains(EVENT_CLASS_MASK(i))) {
+ const SpaprEventSource *source =
+ spapr_event_sources_get_source(spapr->event_sources, i);
+
+ g_assert(source->enabled);
+ qemu_irq_pulse(spapr_qirq(spapr, source->irq));
+ }
+ }
+
rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
}
}
-void spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp)
+bool spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp)
{
SpaprDrc *drc;
bool hotplugged = spapr_drc_hotplugged(dev);
g_assert(drc);
if (!spapr_drc_attach(drc, dev, errp)) {
- return;
+ return false;
}
if (hotplugged) {
spapr_hotplug_req_add_by_index(drc);
}
+ return true;
}
-void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr)
-{
- MachineState *machine = MACHINE(spapr);
- int i;
-
- for (i = 0; i < machine->ram_slots; i++) {
- spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i);
- }
-}
-
-
static int spapr_dt_nvdimm(SpaprMachineState *spapr, void *fdt,
int parent_offset, NVDIMMDevice *nvdimm)
{
static void *sparc32_dma_init(hwaddr dma_base,
hwaddr esp_base, qemu_irq espdma_irq,
- hwaddr le_base, qemu_irq ledma_irq)
+ hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
{
DeviceState *dma;
ESPDMADeviceState *espdma;
SysBusPCNetState *lance;
dma = qdev_new(TYPE_SPARC32_DMA);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
-
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "espdma"));
sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
- sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
- scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "ledma"));
lance = SYSBUS_PCNET(object_resolve_path_component(
OBJECT(ledma), "lance"));
+ qdev_set_nic_properties(DEVICE(lance), nd);
+
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
+ scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
+
sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
return dma;
unsigned int max_cpus = machine->smp.max_cpus;
Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
TYPE_MEMORY_BACKEND, NULL);
+ NICInfo *nd = &nd_table[0];
if (machine->ram_size > hwdef->max_mem) {
error_report("Too much memory for this machine: %" PRId64 ","
hwdef->iommu_pad_base, hwdef->iommu_pad_len);
}
+ qemu_check_nic_model(nd, TYPE_LANCE);
sparc32_dma_init(hwdef->dma_base,
hwdef->esp_base, slavio_irq[18],
- hwdef->le_base, slavio_irq[16]);
+ hwdef->le_base, slavio_irq[16], nd);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
machine->initrd_filename,
machine->ram_size, &initrd_size);
- nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
+ nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
machine->boot_order, machine->ram_size, kernel_size,
graphic_width, graphic_height, graphic_depth,
hwdef->nvram_machine_id, "Sun4m");
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
+ /* sabre_config */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
+ /* PCI configuration space */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
+ /* pci_ioport */
+ sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
+
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
}
}
-static void systick_reload(SysTickState *s, int reset)
-{
- /* The Cortex-M3 Devices Generic User Guide says that "When the
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
- * SYST RVR register and then counts down". So, we need to check the
- * ENABLE bit before reloading the value.
- */
- trace_systick_reload();
-
- if ((s->control & SYSTICK_ENABLE) == 0) {
- return;
- }
-
- if (reset) {
- s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- }
- s->tick += (s->reload + 1) * systick_scale(s);
- timer_mod(s->timer, s->tick);
-}
-
static void systick_timer_tick(void *opaque)
{
SysTickState *s = (SysTickState *)opaque;
/* Tell the NVIC to pend the SysTick exception */
qemu_irq_pulse(s->irq);
}
- if (s->reload == 0) {
- s->control &= ~SYSTICK_ENABLE;
- } else {
- systick_reload(s, 0);
+ if (ptimer_get_limit(s->ptimer) == 0) {
+ /*
+ * Timer expiry with SYST_RVR zero disables the timer
+ * (but doesn't clear SYST_CSR.ENABLE)
+ */
+ ptimer_stop(s->ptimer);
}
}
s->control &= ~SYSTICK_COUNTFLAG;
break;
case 0x4: /* SysTick Reload Value. */
- val = s->reload;
+ val = ptimer_get_limit(s->ptimer);
break;
case 0x8: /* SysTick Current Value. */
- {
- int64_t t;
-
- if ((s->control & SYSTICK_ENABLE) == 0) {
- val = 0;
- break;
- }
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- if (t >= s->tick) {
- val = 0;
- break;
- }
- val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
- /* The interrupt in triggered when the timer reaches zero.
- However the counter is not reloaded until the next clock
- tick. This is a hack to return zero during the first tick. */
- if (val > s->reload) {
- val = 0;
- }
+ val = ptimer_get_count(s->ptimer);
break;
- }
case 0xc: /* SysTick Calibration Value. */
val = 10000;
break;
switch (addr) {
case 0x0: /* SysTick Control and Status. */
{
- uint32_t oldval = s->control;
+ uint32_t oldval;
+ ptimer_transaction_begin(s->ptimer);
+ oldval = s->control;
s->control &= 0xfffffff8;
s->control |= value & 7;
+
if ((oldval ^ value) & SYSTICK_ENABLE) {
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (value & SYSTICK_ENABLE) {
- if (s->tick) {
- s->tick += now;
- timer_mod(s->timer, s->tick);
- } else {
- systick_reload(s, 1);
- }
+ /*
+ * Always reload the period in case board code has
+ * changed system_clock_scale. If we ever replace that
+ * global with a more sensible API then we might be able
+ * to set the period only when it actually changes.
+ */
+ ptimer_set_period(s->ptimer, systick_scale(s));
+ ptimer_run(s->ptimer, 0);
} else {
- timer_del(s->timer);
- s->tick -= now;
- if (s->tick < 0) {
- s->tick = 0;
- }
+ ptimer_stop(s->ptimer);
}
} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
- /* This is a hack. Force the timer to be reloaded
- when the reference clock is changed. */
- systick_reload(s, 1);
+ ptimer_set_period(s->ptimer, systick_scale(s));
}
+ ptimer_transaction_commit(s->ptimer);
break;
}
case 0x4: /* SysTick Reload Value. */
- s->reload = value;
+ ptimer_transaction_begin(s->ptimer);
+ ptimer_set_limit(s->ptimer, value & 0xffffff, 0);
+ ptimer_transaction_commit(s->ptimer);
break;
- case 0x8: /* SysTick Current Value. Writes reload the timer. */
- systick_reload(s, 1);
+ case 0x8: /* SysTick Current Value. */
+ /*
+ * Writing any value clears SYST_CVR to zero and clears
+ * SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR
+ * on the next clock edge unless SYST_RVR is zero.
+ */
+ ptimer_transaction_begin(s->ptimer);
+ if (ptimer_get_limit(s->ptimer) == 0) {
+ ptimer_stop(s->ptimer);
+ }
+ ptimer_set_count(s->ptimer, 0);
s->control &= ~SYSTICK_COUNTFLAG;
+ ptimer_transaction_commit(s->ptimer);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
*/
assert(system_clock_scale != 0);
+ ptimer_transaction_begin(s->ptimer);
s->control = 0;
- s->reload = 0;
- s->tick = 0;
- timer_del(s->timer);
+ ptimer_stop(s->ptimer);
+ ptimer_set_count(s->ptimer, 0);
+ ptimer_set_limit(s->ptimer, 0, 0);
+ ptimer_set_period(s->ptimer, systick_scale(s));
+ ptimer_transaction_commit(s->ptimer);
}
static void systick_instance_init(Object *obj)
static void systick_realize(DeviceState *dev, Error **errp)
{
SysTickState *s = SYSTICK(dev);
- s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
+ s->ptimer = ptimer_init(systick_timer_tick, s,
+ PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
}
static const VMStateDescription vmstate_systick = {
.name = "armv7m_systick",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, SysTickState),
- VMSTATE_UINT32(reload, SysTickState),
VMSTATE_INT64(tick, SysTickState),
- VMSTATE_TIMER_PTR(timer, SysTickState),
+ VMSTATE_PTIMER(ptimer, SysTickState),
VMSTATE_END_OF_LIST()
}
};
#include "qemu/osdep.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/timer/npcm7xx_timer.h"
#include "migration/vmstate.h"
#define NPCM7XX_TCSR_PRESCALE_START 0
#define NPCM7XX_TCSR_PRESCALE_LEN 8
+#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
+#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
+#define NPCM7XX_WTCR_WTE BIT(7)
+#define NPCM7XX_WTCR_WTIE BIT(6)
+#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
+#define NPCM7XX_WTCR_WTIF BIT(3)
+#define NPCM7XX_WTCR_WTRF BIT(2)
+#define NPCM7XX_WTCR_WTRE BIT(1)
+#define NPCM7XX_WTCR_WTR BIT(0)
+
+/*
+ * The number of clock cycles between interrupt and reset in watchdog, used
+ * by the software to handle the interrupt before system is reset.
+ */
+#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
+
+/* Start or resume the timer. */
+static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
+{
+ int64_t now;
+
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ t->expires_ns = now + t->remaining_ns;
+ timer_mod(&t->qtimer, t->expires_ns);
+}
+
+/* Stop counting. Record the time remaining so we can continue later. */
+static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
+{
+ int64_t now;
+
+ timer_del(&t->qtimer);
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ t->remaining_ns = t->expires_ns - now;
+}
+
+/* Delete the timer and reset it to default state. */
+static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
+{
+ timer_del(&t->qtimer);
+ t->expires_ns = 0;
+ t->remaining_ns = 0;
+}
+
/*
* Returns the index of timer in the tc->timer array. This can be used to
* locate the registers that belong to this timer.
return count;
}
+static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
+{
+ switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
+ case 0:
+ return 1;
+ case 1:
+ return 256;
+ case 2:
+ return 2048;
+ case 3:
+ return 65536;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
+ int64_t cycles)
+{
+ uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
+ int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+
+ /*
+ * The reset function always clears the current timer. The caller of the
+ * this needs to decide whether to start the watchdog timer based on
+ * specific flag in WTCR.
+ */
+ npcm7xx_timer_clear(&t->base_timer);
+
+ ns *= prescaler;
+ t->base_timer.remaining_ns = ns;
+}
+
+static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
+{
+ int64_t cycles = 1;
+ uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
+
+ g_assert(s <= 3);
+
+ cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
+ cycles <<= 2 * s;
+
+ npcm7xx_watchdog_timer_reset_cycles(t, cycles);
+}
+
/*
* Raise the interrupt line if there's a pending interrupt and interrupts are
* enabled for this timer. If not, lower it.
trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
}
-/* Start or resume the timer. */
-static void npcm7xx_timer_start(NPCM7xxTimer *t)
-{
- int64_t now;
-
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- t->expires_ns = now + t->remaining_ns;
- timer_mod(&t->qtimer, t->expires_ns);
-}
-
/*
* Called when the counter reaches zero. Sets the interrupt flag, and either
* restarts or disables the timer.
tc->tisr |= BIT(index);
if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
if (t->tcsr & NPCM7XX_TCSR_CEN) {
- npcm7xx_timer_start(t);
+ npcm7xx_timer_start(&t->base_timer);
}
} else {
t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
npcm7xx_timer_check_interrupt(t);
}
-/* Stop counting. Record the time remaining so we can continue later. */
-static void npcm7xx_timer_pause(NPCM7xxTimer *t)
-{
- int64_t now;
-
- timer_del(&t->qtimer);
- now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- t->remaining_ns = t->expires_ns - now;
- if (t->remaining_ns <= 0) {
- npcm7xx_timer_reached_zero(t);
- }
-}
/*
* Restart the timer from its initial value. If the timer was enabled and stays
*/
static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
{
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
- npcm7xx_timer_start(t);
+ npcm7xx_timer_start(&t->base_timer);
}
}
if (t->tcsr & NPCM7XX_TCSR_CEN) {
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
+ return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
}
- return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
+ return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
}
static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
/* Recalculate time remaining based on the current TDR value. */
- t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
+ t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
- npcm7xx_timer_start(t);
+ npcm7xx_timer_start(&t->base_timer);
}
}
if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
if (new_tcsr & NPCM7XX_TCSR_CEN) {
t->tcsr |= NPCM7XX_TCSR_CACT;
- npcm7xx_timer_start(t);
+ npcm7xx_timer_start(&t->base_timer);
} else {
t->tcsr &= ~NPCM7XX_TCSR_CACT;
- npcm7xx_timer_pause(t);
+ npcm7xx_timer_pause(&t->base_timer);
+ if (t->base_timer.remaining_ns <= 0) {
+ npcm7xx_timer_reached_zero(t);
+ }
}
}
}
if (value & (1U << i)) {
npcm7xx_timer_check_interrupt(&s->timer[i]);
}
+
}
}
+static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
+{
+ uint32_t old_wtcr = t->wtcr;
+
+ /*
+ * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
+ * unchanged.
+ */
+ if (new_wtcr & NPCM7XX_WTCR_WTIF) {
+ new_wtcr &= ~NPCM7XX_WTCR_WTIF;
+ } else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
+ new_wtcr |= NPCM7XX_WTCR_WTIF;
+ }
+ if (new_wtcr & NPCM7XX_WTCR_WTRF) {
+ new_wtcr &= ~NPCM7XX_WTCR_WTRF;
+ } else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
+ new_wtcr |= NPCM7XX_WTCR_WTRF;
+ }
+
+ t->wtcr = new_wtcr;
+
+ if (new_wtcr & NPCM7XX_WTCR_WTR) {
+ t->wtcr &= ~NPCM7XX_WTCR_WTR;
+ npcm7xx_watchdog_timer_reset(t);
+ if (new_wtcr & NPCM7XX_WTCR_WTE) {
+ npcm7xx_timer_start(&t->base_timer);
+ }
+ } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
+ if (new_wtcr & NPCM7XX_WTCR_WTE) {
+ npcm7xx_timer_start(&t->base_timer);
+ } else {
+ npcm7xx_timer_pause(&t->base_timer);
+ }
+ }
+
+}
+
static hwaddr npcm7xx_tcsr_index(hwaddr reg)
{
switch (reg) {
break;
case NPCM7XX_TIMER_WTCR:
- value = s->wtcr;
+ value = s->watchdog_timer.wtcr;
break;
default:
return;
case NPCM7XX_TIMER_WTCR:
- qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
- __func__, value);
+ npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
return;
}
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
NPCM7xxTimer *t = &s->timer[i];
- timer_del(&t->qtimer);
- t->expires_ns = 0;
- t->remaining_ns = 0;
+ npcm7xx_timer_clear(&t->base_timer);
t->tcsr = 0x00000005;
t->ticr = 0x00000000;
}
s->tisr = 0x00000000;
- s->wtcr = 0x00000400;
+ /*
+ * Set WTCLK to 1(default) and reset all flags except WTRF.
+ * WTRF is not reset during a core domain reset.
+ */
+ s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
+ NPCM7XX_WTCR_WTRF);
+}
+
+static void npcm7xx_watchdog_timer_expired(void *opaque)
+{
+ NPCM7xxWatchdogTimer *t = opaque;
+
+ if (t->wtcr & NPCM7XX_WTCR_WTE) {
+ if (t->wtcr & NPCM7XX_WTCR_WTIF) {
+ if (t->wtcr & NPCM7XX_WTCR_WTRE) {
+ t->wtcr |= NPCM7XX_WTCR_WTRF;
+ /* send reset signal to CLK module*/
+ qemu_irq_raise(t->reset_signal);
+ }
+ } else {
+ t->wtcr |= NPCM7XX_WTCR_WTIF;
+ if (t->wtcr & NPCM7XX_WTCR_WTIE) {
+ /* send interrupt */
+ qemu_irq_raise(t->irq);
+ }
+ npcm7xx_watchdog_timer_reset_cycles(t,
+ NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
+ npcm7xx_timer_start(&t->base_timer);
+ }
+ }
}
static void npcm7xx_timer_hold_reset(Object *obj)
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
qemu_irq_lower(s->timer[i].irq);
}
+ qemu_irq_lower(s->watchdog_timer.irq);
}
static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
SysBusDevice *sbd = &s->parent;
int i;
+ NPCM7xxWatchdogTimer *w;
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
NPCM7xxTimer *t = &s->timer[i];
t->ctrl = s;
- timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
+ timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
+ npcm7xx_timer_expired, t);
sysbus_init_irq(sbd, &t->irq);
}
+ w = &s->watchdog_timer;
+ w->ctrl = s;
+ timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
+ npcm7xx_watchdog_timer_expired, w);
+ sysbus_init_irq(sbd, &w->irq);
+
memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
TYPE_NPCM7XX_TIMER, 4 * KiB);
sysbus_init_mmio(sbd, &s->iomem);
+ qdev_init_gpio_out_named(dev, &w->reset_signal,
+ NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
}
-static const VMStateDescription vmstate_npcm7xx_timer = {
- .name = "npcm7xx-timer",
+static const VMStateDescription vmstate_npcm7xx_base_timer = {
+ .name = "npcm7xx-base-timer",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
- VMSTATE_TIMER(qtimer, NPCM7xxTimer),
- VMSTATE_INT64(expires_ns, NPCM7xxTimer),
- VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
+ VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
+ VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
+ VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static const VMStateDescription vmstate_npcm7xx_timer = {
+ .name = "npcm7xx-timer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
+ 0, vmstate_npcm7xx_base_timer,
+ NPCM7xxBaseTimer),
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
VMSTATE_UINT32(ticr, NPCM7xxTimer),
VMSTATE_END_OF_LIST(),
},
};
-static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
- .name = "npcm7xx-timer-ctrl",
+static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
+ .name = "npcm7xx-watchdog-timer",
.version_id = 0,
.minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
+ 0, vmstate_npcm7xx_base_timer,
+ NPCM7xxBaseTimer),
+ VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
+ .name = "npcm7xx-timer-ctrl",
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
- VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
NPCM7xxTimer),
+ VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
+ 0, vmstate_npcm7xx_watchdog_timer,
+ NPCM7xxWatchdogTimer),
VMSTATE_END_OF_LIST(),
},
};
.class_init = ehci_aw_h3_class_init,
};
+static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
+{
+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ sec->capsbase = 0x0;
+ sec->opregbase = 0x10;
+ sec->portscbase = 0x44;
+ sec->portnr = 1;
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_npcm7xx_type_info = {
+ .name = TYPE_NPCM7XX_EHCI,
+ .parent = TYPE_SYS_BUS_EHCI,
+ .class_init = ehci_npcm7xx_class_init,
+};
+
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
type_register_static(&ehci_platform_type_info);
type_register_static(&ehci_exynos4210_type_info);
type_register_static(&ehci_aw_h3_type_info);
+ type_register_static(&ehci_npcm7xx_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
type_register_static(&ehci_fusbh200_type_info);
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
+#define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb"
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
config WDT_IMX2
bool
+
+config WDT_SBSA
+ bool
softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c'))
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c'))
softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c'))
+softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c'))
--- /dev/null
+/*
+ * Generic watchdog device model for SBSA
+ *
+ * The watchdog device has been implemented as revision 1 variant of
+ * the ARM SBSA specification v6.0
+ * (https://developer.arm.com/documentation/den0029/d?lang=en)
+ *
+ * Copyright Linaro.org 2020
+ *
+ * Authors:
+ * Shashi Mallela <shashi.mallela@linaro.org>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/reset.h"
+#include "sysemu/watchdog.h"
+#include "hw/watchdog/sbsa_gwdt.h"
+#include "qemu/timer.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+
+static WatchdogTimerModel model = {
+ .wdt_name = TYPE_WDT_SBSA,
+ .wdt_description = "SBSA-compliant generic watchdog device",
+};
+
+static const VMStateDescription vmstate_sbsa_gwdt = {
+ .name = "sbsa-gwdt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_TIMER_PTR(timer, SBSA_GWDTState),
+ VMSTATE_UINT32(wcs, SBSA_GWDTState),
+ VMSTATE_UINT32(worl, SBSA_GWDTState),
+ VMSTATE_UINT32(woru, SBSA_GWDTState),
+ VMSTATE_UINT32(wcvl, SBSA_GWDTState),
+ VMSTATE_UINT32(wcvu, SBSA_GWDTState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef enum WdtRefreshType {
+ EXPLICIT_REFRESH = 0,
+ TIMEOUT_REFRESH = 1,
+} WdtRefreshType;
+
+static uint64_t sbsa_gwdt_rread(void *opaque, hwaddr addr, unsigned int size)
+{
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
+ uint32_t ret = 0;
+
+ switch (addr) {
+ case SBSA_GWDT_WRR:
+ /* watch refresh read has no effect and returns 0 */
+ ret = 0;
+ break;
+ case SBSA_GWDT_W_IIDR:
+ ret = s->id;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame read :"
+ " 0x%x\n", (int)addr);
+ }
+ return ret;
+}
+
+static uint64_t sbsa_gwdt_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
+ uint32_t ret = 0;
+
+ switch (addr) {
+ case SBSA_GWDT_WCS:
+ ret = s->wcs;
+ break;
+ case SBSA_GWDT_WOR:
+ ret = s->worl;
+ break;
+ case SBSA_GWDT_WORU:
+ ret = s->woru;
+ break;
+ case SBSA_GWDT_WCV:
+ ret = s->wcvl;
+ break;
+ case SBSA_GWDT_WCVU:
+ ret = s->wcvu;
+ break;
+ case SBSA_GWDT_W_IIDR:
+ ret = s->id;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame read :"
+ " 0x%x\n", (int)addr);
+ }
+ return ret;
+}
+
+static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
+{
+ uint64_t timeout = 0;
+
+ timer_del(s->timer);
+
+ if (s->wcs & SBSA_GWDT_WCS_EN) {
+ /*
+ * Extract the upper 16 bits from woru & 32 bits from worl
+ * registers to construct the 48 bit offset value
+ */
+ timeout = s->woru;
+ timeout <<= 32;
+ timeout |= s->worl;
+ timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
+ timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
+ (!(s->wcs & SBSA_GWDT_WCS_WS0)))) {
+ /* store the current timeout value into compare registers */
+ s->wcvu = timeout >> 32;
+ s->wcvl = timeout;
+ }
+ timer_mod(s->timer, timeout);
+ }
+}
+
+static void sbsa_gwdt_rwrite(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size) {
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
+
+ if (offset == SBSA_GWDT_WRR) {
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
+
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame write :"
+ " 0x%x\n", (int)offset);
+ }
+}
+
+static void sbsa_gwdt_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size) {
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
+
+ switch (offset) {
+ case SBSA_GWDT_WCS:
+ s->wcs = data & SBSA_GWDT_WCS_EN;
+ qemu_set_irq(s->irq, 0);
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
+ break;
+
+ case SBSA_GWDT_WOR:
+ s->worl = data;
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
+ qemu_set_irq(s->irq, 0);
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
+ break;
+
+ case SBSA_GWDT_WORU:
+ s->woru = data & SBSA_GWDT_WOR_MASK;
+ s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
+ qemu_set_irq(s->irq, 0);
+ sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
+ break;
+
+ case SBSA_GWDT_WCV:
+ s->wcvl = data;
+ break;
+
+ case SBSA_GWDT_WCVU:
+ s->wcvu = data;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame write :"
+ " 0x%x\n", (int)offset);
+ }
+ return;
+}
+
+static void wdt_sbsa_gwdt_reset(DeviceState *dev)
+{
+ SBSA_GWDTState *s = SBSA_GWDT(dev);
+
+ timer_del(s->timer);
+
+ s->wcs = 0;
+ s->wcvl = 0;
+ s->wcvu = 0;
+ s->worl = 0;
+ s->woru = 0;
+ s->id = SBSA_GWDT_ID;
+}
+
+static void sbsa_gwdt_timer_sysinterrupt(void *opaque)
+{
+ SBSA_GWDTState *s = SBSA_GWDT(opaque);
+
+ if (!(s->wcs & SBSA_GWDT_WCS_WS0)) {
+ s->wcs |= SBSA_GWDT_WCS_WS0;
+ sbsa_gwdt_update_timer(s, TIMEOUT_REFRESH);
+ qemu_set_irq(s->irq, 1);
+ } else {
+ s->wcs |= SBSA_GWDT_WCS_WS1;
+ qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
+ /*
+ * Reset the watchdog only if the guest gets notified about
+ * expiry. watchdog_perform_action() may temporarily relinquish
+ * the BQL; reset before triggering the action to avoid races with
+ * sbsa_gwdt instructions.
+ */
+ switch (get_watchdog_action()) {
+ case WATCHDOG_ACTION_DEBUG:
+ case WATCHDOG_ACTION_NONE:
+ case WATCHDOG_ACTION_PAUSE:
+ break;
+ default:
+ wdt_sbsa_gwdt_reset(DEVICE(s));
+ }
+ watchdog_perform_action();
+ }
+}
+
+static const MemoryRegionOps sbsa_gwdt_rops = {
+ .read = sbsa_gwdt_rread,
+ .write = sbsa_gwdt_rwrite,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static const MemoryRegionOps sbsa_gwdt_ops = {
+ .read = sbsa_gwdt_read,
+ .write = sbsa_gwdt_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
+{
+ SBSA_GWDTState *s = SBSA_GWDT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&s->rmmio, OBJECT(dev),
+ &sbsa_gwdt_rops, s,
+ "sbsa_gwdt.refresh",
+ SBSA_GWDT_RMMIO_SIZE);
+
+ memory_region_init_io(&s->cmmio, OBJECT(dev),
+ &sbsa_gwdt_ops, s,
+ "sbsa_gwdt.control",
+ SBSA_GWDT_CMMIO_SIZE);
+
+ sysbus_init_mmio(sbd, &s->rmmio);
+ sysbus_init_mmio(sbd, &s->cmmio);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sbsa_gwdt_timer_sysinterrupt,
+ dev);
+}
+
+static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = wdt_sbsa_gwdt_realize;
+ dc->reset = wdt_sbsa_gwdt_reset;
+ dc->hotpluggable = false;
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ dc->vmsd = &vmstate_sbsa_gwdt;
+}
+
+static const TypeInfo wdt_sbsa_gwdt_info = {
+ .class_init = wdt_sbsa_gwdt_class_init,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .name = TYPE_WDT_SBSA,
+ .instance_size = sizeof(SBSA_GWDTState),
+};
+
+static void wdt_sbsa_gwdt_register_types(void)
+{
+ watchdog_add_model(&model);
+ type_register_static(&wdt_sbsa_gwdt_info);
+}
+
+type_init(wdt_sbsa_gwdt_register_types)
int bdrv_is_allocated_above(BlockDriverState *top, BlockDriverState *base,
bool include_base, int64_t offset, int64_t bytes,
int64_t *pnum);
+int coroutine_fn bdrv_co_is_zero_fast(BlockDriverState *bs, int64_t offset,
+ int64_t bytes);
bool bdrv_is_read_only(BlockDriverState *bs);
int bdrv_can_set_read_only(BlockDriverState *bs, bool read_only,
*/
void bdrv_drained_end_no_poll(BlockDriverState *bs, int *drained_end_counter);
+/**
+ * End all quiescent sections started by bdrv_drain_all_begin(). This is
+ * only needed when deleting a BDS before bdrv_drain_all_end() is called.
+ */
+void bdrv_drain_all_end_quiesce(BlockDriverState *bs);
+
/**
* End a quiescent section started by bdrv_subtree_drained_begin().
*/
#define PT_NOTE 4
#define PT_SHLIB 5
#define PT_PHDR 6
+#define PT_LOOS 0x60000000
+#define PT_HIOS 0x6fffffff
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
+#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
+
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_RTPROC 0x70000001
#define PT_MIPS_OPTIONS 0x70000002
#define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */
+/* Defined note types for GNU systems. */
+
+#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */
+
+/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */
+
+#define GNU_PROPERTY_STACK_SIZE 1
+#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2
+
+#define GNU_PROPERTY_LOPROC 0xc0000000
+#define GNU_PROPERTY_HIPROC 0xdfffffff
+#define GNU_PROPERTY_LOUSER 0xe0000000
+#define GNU_PROPERTY_HIUSER 0xffffffff
+
+#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
+#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0)
+#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1)
+
/*
* Physical entry point into the kernel.
*
/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0020
#endif
+/* Target-specific bits that will be used via page_get_flags(). */
+#define PAGE_TARGET_1 0x0080
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);
#include "hw/misc/bcm2835_mbox.h"
#include "hw/misc/bcm2835_mphi.h"
#include "hw/misc/bcm2835_thermal.h"
+#include "hw/misc/bcm2835_cprman.h"
#include "hw/sd/sdhci.h"
#include "hw/sd/bcm2835_sdhost.h"
#include "hw/gpio/bcm2835_gpio.h"
BCM2835MphiState mphi;
UnimplementedDeviceState txp;
UnimplementedDeviceState armtmr;
- UnimplementedDeviceState cprman;
- UnimplementedDeviceState a2w;
+ UnimplementedDeviceState powermgt;
+ BCM2835CprmanState cprman;
PL011State uart0;
BCM2835AuxState aux;
BCM2835FBState fb;
* them, code using these devices should always handle them via the
* BCM283x base class, so they have no BCM2836(obj) etc macros.
*/
+#define TYPE_BCM2835 "bcm2835"
#define TYPE_BCM2836 "bcm2836"
#define TYPE_BCM2837 "bcm2837"
BCM2835PeripheralState peripherals;
};
-typedef struct BCM283XInfo BCM283XInfo;
-
-struct BCM283XClass {
- DeviceClass parent_class;
- const BCM283XInfo *info;
-};
-
-
#endif /* BCM2836_H */
#include "hw/boards.h"
#include "hw/cpu/a9mpcore.h"
+#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm7xx_rng.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/usb/hcd-ehci.h"
+#include "hw/usb/hcd-ohci.h"
#include "target/arm/cpu.h"
#define NPCM7XX_MAX_NUM_CPUS (2)
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
NPCM7xxMCState mc;
+ NPCM7xxRNGState rng;
+ NPCM7xxGPIOState gpio[8];
+ EHCISysBusState ehci;
+ OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
} NPCM7xxState;
#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
* Doorbells & Mailboxes */
-#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
-#define CM_OFFSET 0x101000 /* Clock Management */
-#define A2W_OFFSET 0x102000 /* Reset controller */
+#define PM_OFFSET 0x100000 /* Power Management */
+#define CPRMAN_OFFSET 0x101000 /* Clock Management */
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
#define RNG_OFFSET 0x104000
#define GPIO_OFFSET 0x200000
int read_trigger;
CharBackend chr;
qemu_irq irq[6];
+ Clock *clk;
const unsigned char *id;
};
VMSTATE_CLOCK_V(field, state, 0)
#define VMSTATE_CLOCK_V(field, state, version) \
VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock)
+#define VMSTATE_ARRAY_CLOCK(field, state, num) \
+ VMSTATE_ARRAY_CLOCK_V(field, state, num, 0)
+#define VMSTATE_ARRAY_CLOCK_V(field, state, num, version) \
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(field, state, num, version, \
+ vmstate_clock, Clock)
/**
* clock_setup_canonical_path:
void cpu_resume(CPUState *cpu);
/**
- * cpu_remove:
- * @cpu: The CPU to remove.
- *
- * Requests the CPU to be removed.
- */
-void cpu_remove(CPUState *cpu);
-
- /**
* cpu_remove_sync:
* @cpu: The CPU to remove.
*
--- /dev/null
+/*
+ * Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef NPCM7XX_GPIO_H
+#define NPCM7XX_GPIO_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/* Number of pins managed by each controller. */
+#define NPCM7XX_GPIO_NR_PINS (32)
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t))
+
+typedef struct NPCM7xxGPIOState {
+ SysBusDevice parent;
+
+ /* Properties to be defined by the SoC */
+ uint32_t reset_pu;
+ uint32_t reset_pd;
+ uint32_t reset_osrc;
+ uint32_t reset_odsc;
+
+ MemoryRegion mmio;
+
+ qemu_irq irq;
+ qemu_irq output[NPCM7XX_GPIO_NR_PINS];
+
+ uint32_t pin_level;
+ uint32_t ext_level;
+ uint32_t ext_driven;
+
+ uint32_t regs[NPCM7XX_GPIO_NR_REGS];
+} NPCM7xxGPIOState;
+
+#define TYPE_NPCM7XX_GPIO "npcm7xx-gpio"
+#define NPCM7XX_GPIO(obj) \
+ OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO)
+
+#endif /* NPCM7XX_GPIO_H */
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,
const uint64_t *legacy_align, Error **errp);
-void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine, Error **errp);
+void pc_dimm_plug(PCDIMMDevice *dimm, MachineState *machine);
void pc_dimm_unplug(PCDIMMDevice *dimm, MachineState *machine);
#endif
--- /dev/null
+/*
+ * BCM2835 CPRMAN clock manager
+ *
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_MISC_CPRMAN_H
+#define HW_MISC_CPRMAN_H
+
+#include "hw/sysbus.h"
+#include "hw/qdev-clock.h"
+
+#define TYPE_BCM2835_CPRMAN "bcm2835-cprman"
+
+typedef struct BCM2835CprmanState BCM2835CprmanState;
+
+DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN,
+ TYPE_BCM2835_CPRMAN)
+
+#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t))
+
+typedef enum CprmanPll {
+ CPRMAN_PLLA = 0,
+ CPRMAN_PLLC,
+ CPRMAN_PLLD,
+ CPRMAN_PLLH,
+ CPRMAN_PLLB,
+
+ CPRMAN_NUM_PLL
+} CprmanPll;
+
+typedef enum CprmanPllChannel {
+ CPRMAN_PLLA_CHANNEL_DSI0 = 0,
+ CPRMAN_PLLA_CHANNEL_CORE,
+ CPRMAN_PLLA_CHANNEL_PER,
+ CPRMAN_PLLA_CHANNEL_CCP2,
+
+ CPRMAN_PLLC_CHANNEL_CORE2,
+ CPRMAN_PLLC_CHANNEL_CORE1,
+ CPRMAN_PLLC_CHANNEL_PER,
+ CPRMAN_PLLC_CHANNEL_CORE0,
+
+ CPRMAN_PLLD_CHANNEL_DSI0,
+ CPRMAN_PLLD_CHANNEL_CORE,
+ CPRMAN_PLLD_CHANNEL_PER,
+ CPRMAN_PLLD_CHANNEL_DSI1,
+
+ CPRMAN_PLLH_CHANNEL_AUX,
+ CPRMAN_PLLH_CHANNEL_RCAL,
+ CPRMAN_PLLH_CHANNEL_PIX,
+
+ CPRMAN_PLLB_CHANNEL_ARM,
+
+ CPRMAN_NUM_PLL_CHANNEL,
+
+ /* Special values used when connecting clock sources to clocks */
+ CPRMAN_CLOCK_SRC_NORMAL = -1,
+ CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
+ CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
+} CprmanPllChannel;
+
+typedef enum CprmanClockMux {
+ CPRMAN_CLOCK_GNRIC,
+ CPRMAN_CLOCK_VPU,
+ CPRMAN_CLOCK_SYS,
+ CPRMAN_CLOCK_PERIA,
+ CPRMAN_CLOCK_PERII,
+ CPRMAN_CLOCK_H264,
+ CPRMAN_CLOCK_ISP,
+ CPRMAN_CLOCK_V3D,
+ CPRMAN_CLOCK_CAM0,
+ CPRMAN_CLOCK_CAM1,
+ CPRMAN_CLOCK_CCP2,
+ CPRMAN_CLOCK_DSI0E,
+ CPRMAN_CLOCK_DSI0P,
+ CPRMAN_CLOCK_DPI,
+ CPRMAN_CLOCK_GP0,
+ CPRMAN_CLOCK_GP1,
+ CPRMAN_CLOCK_GP2,
+ CPRMAN_CLOCK_HSM,
+ CPRMAN_CLOCK_OTP,
+ CPRMAN_CLOCK_PCM,
+ CPRMAN_CLOCK_PWM,
+ CPRMAN_CLOCK_SLIM,
+ CPRMAN_CLOCK_SMI,
+ CPRMAN_CLOCK_TEC,
+ CPRMAN_CLOCK_TD0,
+ CPRMAN_CLOCK_TD1,
+ CPRMAN_CLOCK_TSENS,
+ CPRMAN_CLOCK_TIMER,
+ CPRMAN_CLOCK_UART,
+ CPRMAN_CLOCK_VEC,
+ CPRMAN_CLOCK_PULSE,
+ CPRMAN_CLOCK_SDC,
+ CPRMAN_CLOCK_ARM,
+ CPRMAN_CLOCK_AVEO,
+ CPRMAN_CLOCK_EMMC,
+ CPRMAN_CLOCK_EMMC2,
+
+ CPRMAN_NUM_CLOCK_MUX
+} CprmanClockMux;
+
+typedef enum CprmanClockMuxSource {
+ CPRMAN_CLOCK_SRC_GND = 0,
+ CPRMAN_CLOCK_SRC_XOSC,
+ CPRMAN_CLOCK_SRC_TD0,
+ CPRMAN_CLOCK_SRC_TD1,
+ CPRMAN_CLOCK_SRC_PLLA,
+ CPRMAN_CLOCK_SRC_PLLC,
+ CPRMAN_CLOCK_SRC_PLLD,
+ CPRMAN_CLOCK_SRC_PLLH,
+ CPRMAN_CLOCK_SRC_PLLC_CORE1,
+ CPRMAN_CLOCK_SRC_PLLC_CORE2,
+
+ CPRMAN_NUM_CLOCK_MUX_SRC
+} CprmanClockMuxSource;
+
+typedef struct CprmanPllState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CprmanPll id;
+
+ uint32_t *reg_cm;
+ uint32_t *reg_a2w_ctrl;
+ uint32_t *reg_a2w_ana; /* ANA[0] .. ANA[3] */
+ uint32_t prediv_mask; /* prediv bit in ana[1] */
+ uint32_t *reg_a2w_frac;
+
+ Clock *xosc_in;
+ Clock *out;
+} CprmanPllState;
+
+typedef struct CprmanPllChannelState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CprmanPllChannel id;
+ CprmanPll parent;
+
+ uint32_t *reg_cm;
+ uint32_t hold_mask;
+ uint32_t load_mask;
+ uint32_t *reg_a2w_ctrl;
+ int fixed_divider;
+
+ Clock *pll_in;
+ Clock *out;
+} CprmanPllChannelState;
+
+typedef struct CprmanClockMuxState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CprmanClockMux id;
+
+ uint32_t *reg_ctl;
+ uint32_t *reg_div;
+ int int_bits;
+ int frac_bits;
+
+ Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
+ Clock *out;
+
+ /*
+ * Used by clock srcs update callback to retrieve both the clock and the
+ * source number.
+ */
+ struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
+} CprmanClockMuxState;
+
+typedef struct CprmanDsi0HsckMuxState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CprmanClockMux id;
+
+ uint32_t *reg_cm;
+
+ Clock *plla_in;
+ Clock *plld_in;
+ Clock *out;
+} CprmanDsi0HsckMuxState;
+
+struct BCM2835CprmanState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ CprmanPllState plls[CPRMAN_NUM_PLL];
+ CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
+ CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
+ CprmanDsi0HsckMuxState dsi0hsck_mux;
+
+ uint32_t regs[CPRMAN_NUM_REGS];
+ uint32_t xosc_freq;
+
+ Clock *xosc;
+ Clock *gnd;
+};
+
+#endif
--- /dev/null
+/*
+ * BCM2835 CPRMAN clock manager
+ *
+ * Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_MISC_CPRMAN_INTERNALS_H
+#define HW_MISC_CPRMAN_INTERNALS_H
+
+#include "hw/registerfields.h"
+#include "hw/misc/bcm2835_cprman.h"
+
+#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
+#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
+#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
+#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
+
+DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
+ TYPE_CPRMAN_PLL)
+DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
+ TYPE_CPRMAN_PLL_CHANNEL)
+DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
+ TYPE_CPRMAN_CLOCK_MUX)
+DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
+ TYPE_CPRMAN_DSI0HSCK_MUX)
+
+/* Register map */
+
+/* PLLs */
+REG32(CM_PLLA, 0x104)
+ FIELD(CM_PLLA, LOADDSI0, 0, 1)
+ FIELD(CM_PLLA, HOLDDSI0, 1, 1)
+ FIELD(CM_PLLA, LOADCCP2, 2, 1)
+ FIELD(CM_PLLA, HOLDCCP2, 3, 1)
+ FIELD(CM_PLLA, LOADCORE, 4, 1)
+ FIELD(CM_PLLA, HOLDCORE, 5, 1)
+ FIELD(CM_PLLA, LOADPER, 6, 1)
+ FIELD(CM_PLLA, HOLDPER, 7, 1)
+ FIELD(CM_PLLx, ANARST, 8, 1)
+REG32(CM_PLLC, 0x108)
+ FIELD(CM_PLLC, LOADCORE0, 0, 1)
+ FIELD(CM_PLLC, HOLDCORE0, 1, 1)
+ FIELD(CM_PLLC, LOADCORE1, 2, 1)
+ FIELD(CM_PLLC, HOLDCORE1, 3, 1)
+ FIELD(CM_PLLC, LOADCORE2, 4, 1)
+ FIELD(CM_PLLC, HOLDCORE2, 5, 1)
+ FIELD(CM_PLLC, LOADPER, 6, 1)
+ FIELD(CM_PLLC, HOLDPER, 7, 1)
+REG32(CM_PLLD, 0x10c)
+ FIELD(CM_PLLD, LOADDSI0, 0, 1)
+ FIELD(CM_PLLD, HOLDDSI0, 1, 1)
+ FIELD(CM_PLLD, LOADDSI1, 2, 1)
+ FIELD(CM_PLLD, HOLDDSI1, 3, 1)
+ FIELD(CM_PLLD, LOADCORE, 4, 1)
+ FIELD(CM_PLLD, HOLDCORE, 5, 1)
+ FIELD(CM_PLLD, LOADPER, 6, 1)
+ FIELD(CM_PLLD, HOLDPER, 7, 1)
+REG32(CM_PLLH, 0x110)
+ FIELD(CM_PLLH, LOADPIX, 0, 1)
+ FIELD(CM_PLLH, LOADAUX, 1, 1)
+ FIELD(CM_PLLH, LOADRCAL, 2, 1)
+REG32(CM_PLLB, 0x170)
+ FIELD(CM_PLLB, LOADARM, 0, 1)
+ FIELD(CM_PLLB, HOLDARM, 1, 1)
+
+REG32(A2W_PLLA_CTRL, 0x1100)
+ FIELD(A2W_PLLx_CTRL, NDIV, 0, 10)
+ FIELD(A2W_PLLx_CTRL, PDIV, 12, 3)
+ FIELD(A2W_PLLx_CTRL, PWRDN, 16, 1)
+ FIELD(A2W_PLLx_CTRL, PRST_DISABLE, 17, 1)
+REG32(A2W_PLLC_CTRL, 0x1120)
+REG32(A2W_PLLD_CTRL, 0x1140)
+REG32(A2W_PLLH_CTRL, 0x1160)
+REG32(A2W_PLLB_CTRL, 0x11e0)
+
+REG32(A2W_PLLA_ANA0, 0x1010)
+REG32(A2W_PLLA_ANA1, 0x1014)
+ FIELD(A2W_PLLx_ANA1, FB_PREDIV, 14, 1)
+REG32(A2W_PLLA_ANA2, 0x1018)
+REG32(A2W_PLLA_ANA3, 0x101c)
+
+REG32(A2W_PLLC_ANA0, 0x1030)
+REG32(A2W_PLLC_ANA1, 0x1034)
+REG32(A2W_PLLC_ANA2, 0x1038)
+REG32(A2W_PLLC_ANA3, 0x103c)
+
+REG32(A2W_PLLD_ANA0, 0x1050)
+REG32(A2W_PLLD_ANA1, 0x1054)
+REG32(A2W_PLLD_ANA2, 0x1058)
+REG32(A2W_PLLD_ANA3, 0x105c)
+
+REG32(A2W_PLLH_ANA0, 0x1070)
+REG32(A2W_PLLH_ANA1, 0x1074)
+ FIELD(A2W_PLLH_ANA1, FB_PREDIV, 11, 1)
+REG32(A2W_PLLH_ANA2, 0x1078)
+REG32(A2W_PLLH_ANA3, 0x107c)
+
+REG32(A2W_PLLB_ANA0, 0x10f0)
+REG32(A2W_PLLB_ANA1, 0x10f4)
+REG32(A2W_PLLB_ANA2, 0x10f8)
+REG32(A2W_PLLB_ANA3, 0x10fc)
+
+REG32(A2W_PLLA_FRAC, 0x1200)
+ FIELD(A2W_PLLx_FRAC, FRAC, 0, 20)
+REG32(A2W_PLLC_FRAC, 0x1220)
+REG32(A2W_PLLD_FRAC, 0x1240)
+REG32(A2W_PLLH_FRAC, 0x1260)
+REG32(A2W_PLLB_FRAC, 0x12e0)
+
+/* PLL channels */
+REG32(A2W_PLLA_DSI0, 0x1300)
+ FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8)
+ FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1)
+REG32(A2W_PLLA_CORE, 0x1400)
+REG32(A2W_PLLA_PER, 0x1500)
+REG32(A2W_PLLA_CCP2, 0x1600)
+
+REG32(A2W_PLLC_CORE2, 0x1320)
+REG32(A2W_PLLC_CORE1, 0x1420)
+REG32(A2W_PLLC_PER, 0x1520)
+REG32(A2W_PLLC_CORE0, 0x1620)
+
+REG32(A2W_PLLD_DSI0, 0x1340)
+REG32(A2W_PLLD_CORE, 0x1440)
+REG32(A2W_PLLD_PER, 0x1540)
+REG32(A2W_PLLD_DSI1, 0x1640)
+
+REG32(A2W_PLLH_AUX, 0x1360)
+REG32(A2W_PLLH_RCAL, 0x1460)
+REG32(A2W_PLLH_PIX, 0x1560)
+REG32(A2W_PLLH_STS, 0x1660)
+
+REG32(A2W_PLLB_ARM, 0x13e0)
+
+/* Clock muxes */
+REG32(CM_GNRICCTL, 0x000)
+ FIELD(CM_CLOCKx_CTL, SRC, 0, 4)
+ FIELD(CM_CLOCKx_CTL, ENABLE, 4, 1)
+ FIELD(CM_CLOCKx_CTL, KILL, 5, 1)
+ FIELD(CM_CLOCKx_CTL, GATE, 6, 1)
+ FIELD(CM_CLOCKx_CTL, BUSY, 7, 1)
+ FIELD(CM_CLOCKx_CTL, BUSYD, 8, 1)
+ FIELD(CM_CLOCKx_CTL, MASH, 9, 2)
+ FIELD(CM_CLOCKx_CTL, FLIP, 11, 1)
+REG32(CM_GNRICDIV, 0x004)
+ FIELD(CM_CLOCKx_DIV, FRAC, 0, 12)
+REG32(CM_VPUCTL, 0x008)
+REG32(CM_VPUDIV, 0x00c)
+REG32(CM_SYSCTL, 0x010)
+REG32(CM_SYSDIV, 0x014)
+REG32(CM_PERIACTL, 0x018)
+REG32(CM_PERIADIV, 0x01c)
+REG32(CM_PERIICTL, 0x020)
+REG32(CM_PERIIDIV, 0x024)
+REG32(CM_H264CTL, 0x028)
+REG32(CM_H264DIV, 0x02c)
+REG32(CM_ISPCTL, 0x030)
+REG32(CM_ISPDIV, 0x034)
+REG32(CM_V3DCTL, 0x038)
+REG32(CM_V3DDIV, 0x03c)
+REG32(CM_CAM0CTL, 0x040)
+REG32(CM_CAM0DIV, 0x044)
+REG32(CM_CAM1CTL, 0x048)
+REG32(CM_CAM1DIV, 0x04c)
+REG32(CM_CCP2CTL, 0x050)
+REG32(CM_CCP2DIV, 0x054)
+REG32(CM_DSI0ECTL, 0x058)
+REG32(CM_DSI0EDIV, 0x05c)
+REG32(CM_DSI0PCTL, 0x060)
+REG32(CM_DSI0PDIV, 0x064)
+REG32(CM_DPICTL, 0x068)
+REG32(CM_DPIDIV, 0x06c)
+REG32(CM_GP0CTL, 0x070)
+REG32(CM_GP0DIV, 0x074)
+REG32(CM_GP1CTL, 0x078)
+REG32(CM_GP1DIV, 0x07c)
+REG32(CM_GP2CTL, 0x080)
+REG32(CM_GP2DIV, 0x084)
+REG32(CM_HSMCTL, 0x088)
+REG32(CM_HSMDIV, 0x08c)
+REG32(CM_OTPCTL, 0x090)
+REG32(CM_OTPDIV, 0x094)
+REG32(CM_PCMCTL, 0x098)
+REG32(CM_PCMDIV, 0x09c)
+REG32(CM_PWMCTL, 0x0a0)
+REG32(CM_PWMDIV, 0x0a4)
+REG32(CM_SLIMCTL, 0x0a8)
+REG32(CM_SLIMDIV, 0x0ac)
+REG32(CM_SMICTL, 0x0b0)
+REG32(CM_SMIDIV, 0x0b4)
+REG32(CM_TCNTCTL, 0x0c0)
+REG32(CM_TCNTCNT, 0x0c4)
+REG32(CM_TECCTL, 0x0c8)
+REG32(CM_TECDIV, 0x0cc)
+REG32(CM_TD0CTL, 0x0d0)
+REG32(CM_TD0DIV, 0x0d4)
+REG32(CM_TD1CTL, 0x0d8)
+REG32(CM_TD1DIV, 0x0dc)
+REG32(CM_TSENSCTL, 0x0e0)
+REG32(CM_TSENSDIV, 0x0e4)
+REG32(CM_TIMERCTL, 0x0e8)
+REG32(CM_TIMERDIV, 0x0ec)
+REG32(CM_UARTCTL, 0x0f0)
+REG32(CM_UARTDIV, 0x0f4)
+REG32(CM_VECCTL, 0x0f8)
+REG32(CM_VECDIV, 0x0fc)
+REG32(CM_PULSECTL, 0x190)
+REG32(CM_PULSEDIV, 0x194)
+REG32(CM_SDCCTL, 0x1a8)
+REG32(CM_SDCDIV, 0x1ac)
+REG32(CM_ARMCTL, 0x1b0)
+REG32(CM_AVEOCTL, 0x1b8)
+REG32(CM_AVEODIV, 0x1bc)
+REG32(CM_EMMCCTL, 0x1c0)
+REG32(CM_EMMCDIV, 0x1c4)
+REG32(CM_EMMC2CTL, 0x1d0)
+REG32(CM_EMMC2DIV, 0x1d4)
+
+/* misc registers */
+REG32(CM_LOCK, 0x114)
+ FIELD(CM_LOCK, FLOCKH, 12, 1)
+ FIELD(CM_LOCK, FLOCKD, 11, 1)
+ FIELD(CM_LOCK, FLOCKC, 10, 1)
+ FIELD(CM_LOCK, FLOCKB, 9, 1)
+ FIELD(CM_LOCK, FLOCKA, 8, 1)
+
+REG32(CM_DSI0HSCK, 0x120)
+ FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
+
+/*
+ * This field is common to all registers. Each register write value must match
+ * the CPRMAN_PASSWORD magic value in its 8 MSB.
+ */
+FIELD(CPRMAN, PASSWORD, 24, 8)
+#define CPRMAN_PASSWORD 0x5a
+
+/* PLL init info */
+typedef struct PLLInitInfo {
+ const char *name;
+ size_t cm_offset;
+ size_t a2w_ctrl_offset;
+ size_t a2w_ana_offset;
+ uint32_t prediv_mask; /* Prediv bit in ana[1] */
+ size_t a2w_frac_offset;
+} PLLInitInfo;
+
+#define FILL_PLL_INIT_INFO(pll_) \
+ .cm_offset = R_CM_ ## pll_, \
+ .a2w_ctrl_offset = R_A2W_ ## pll_ ## _CTRL, \
+ .a2w_ana_offset = R_A2W_ ## pll_ ## _ANA0, \
+ .a2w_frac_offset = R_A2W_ ## pll_ ## _FRAC
+
+static const PLLInitInfo PLL_INIT_INFO[] = {
+ [CPRMAN_PLLA] = {
+ .name = "plla",
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
+ FILL_PLL_INIT_INFO(PLLA),
+ },
+ [CPRMAN_PLLC] = {
+ .name = "pllc",
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
+ FILL_PLL_INIT_INFO(PLLC),
+ },
+ [CPRMAN_PLLD] = {
+ .name = "plld",
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
+ FILL_PLL_INIT_INFO(PLLD),
+ },
+ [CPRMAN_PLLH] = {
+ .name = "pllh",
+ .prediv_mask = R_A2W_PLLH_ANA1_FB_PREDIV_MASK,
+ FILL_PLL_INIT_INFO(PLLH),
+ },
+ [CPRMAN_PLLB] = {
+ .name = "pllb",
+ .prediv_mask = R_A2W_PLLx_ANA1_FB_PREDIV_MASK,
+ FILL_PLL_INIT_INFO(PLLB),
+ },
+};
+
+#undef FILL_PLL_CHANNEL_INIT_INFO
+
+static inline void set_pll_init_info(BCM2835CprmanState *s,
+ CprmanPllState *pll,
+ CprmanPll id)
+{
+ pll->id = id;
+ pll->reg_cm = &s->regs[PLL_INIT_INFO[id].cm_offset];
+ pll->reg_a2w_ctrl = &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset];
+ pll->reg_a2w_ana = &s->regs[PLL_INIT_INFO[id].a2w_ana_offset];
+ pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;
+ pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
+}
+
+
+/* PLL channel init info */
+typedef struct PLLChannelInitInfo {
+ const char *name;
+ CprmanPll parent;
+ size_t cm_offset;
+ uint32_t cm_hold_mask;
+ uint32_t cm_load_mask;
+ size_t a2w_ctrl_offset;
+ unsigned int fixed_divider;
+} PLLChannelInitInfo;
+
+#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \
+ .parent = CPRMAN_ ## pll_, \
+ .cm_offset = R_CM_ ## pll_, \
+ .cm_load_mask = R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \
+ .a2w_ctrl_offset = R_A2W_ ## pll_ ## _ ## channel_
+
+#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \
+ FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
+ .cm_hold_mask = R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \
+ .fixed_divider = 1
+
+#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \
+ FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
+ .cm_hold_mask = 0
+
+static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] = {
+ [CPRMAN_PLLA_CHANNEL_DSI0] = {
+ .name = "plla-dsi0",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0),
+ },
+ [CPRMAN_PLLA_CHANNEL_CORE] = {
+ .name = "plla-core",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE),
+ },
+ [CPRMAN_PLLA_CHANNEL_PER] = {
+ .name = "plla-per",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER),
+ },
+ [CPRMAN_PLLA_CHANNEL_CCP2] = {
+ .name = "plla-ccp2",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2),
+ },
+
+ [CPRMAN_PLLC_CHANNEL_CORE2] = {
+ .name = "pllc-core2",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2),
+ },
+ [CPRMAN_PLLC_CHANNEL_CORE1] = {
+ .name = "pllc-core1",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1),
+ },
+ [CPRMAN_PLLC_CHANNEL_PER] = {
+ .name = "pllc-per",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER),
+ },
+ [CPRMAN_PLLC_CHANNEL_CORE0] = {
+ .name = "pllc-core0",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0),
+ },
+
+ [CPRMAN_PLLD_CHANNEL_DSI0] = {
+ .name = "plld-dsi0",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0),
+ },
+ [CPRMAN_PLLD_CHANNEL_CORE] = {
+ .name = "plld-core",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE),
+ },
+ [CPRMAN_PLLD_CHANNEL_PER] = {
+ .name = "plld-per",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER),
+ },
+ [CPRMAN_PLLD_CHANNEL_DSI1] = {
+ .name = "plld-dsi1",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1),
+ },
+
+ [CPRMAN_PLLH_CHANNEL_AUX] = {
+ .name = "pllh-aux",
+ .fixed_divider = 1,
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX),
+ },
+ [CPRMAN_PLLH_CHANNEL_RCAL] = {
+ .name = "pllh-rcal",
+ .fixed_divider = 10,
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL),
+ },
+ [CPRMAN_PLLH_CHANNEL_PIX] = {
+ .name = "pllh-pix",
+ .fixed_divider = 10,
+ FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX),
+ },
+
+ [CPRMAN_PLLB_CHANNEL_ARM] = {
+ .name = "pllb-arm",
+ FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM),
+ },
+};
+
+#undef FILL_PLL_CHANNEL_INIT_INFO_nohold
+#undef FILL_PLL_CHANNEL_INIT_INFO
+#undef FILL_PLL_CHANNEL_INIT_INFO_common
+
+static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
+ CprmanPllChannelState *channel,
+ CprmanPllChannel id)
+{
+ channel->id = id;
+ channel->parent = PLL_CHANNEL_INIT_INFO[id].parent;
+ channel->reg_cm = &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset];
+ channel->hold_mask = PLL_CHANNEL_INIT_INFO[id].cm_hold_mask;
+ channel->load_mask = PLL_CHANNEL_INIT_INFO[id].cm_load_mask;
+ channel->reg_a2w_ctrl = &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_offset];
+ channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
+}
+
+/* Clock mux init info */
+typedef struct ClockMuxInitInfo {
+ const char *name;
+ size_t cm_offset; /* cm_offset[0]->CM_CTL, cm_offset[1]->CM_DIV */
+ int int_bits;
+ int frac_bits;
+
+ CprmanPllChannel src_mapping[CPRMAN_NUM_CLOCK_MUX_SRC];
+} ClockMuxInitInfo;
+
+/*
+ * Each clock mux can have up to 10 sources. Sources 0 to 3 are always the
+ * same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are not
+ * always populated. The following macros catch all those cases.
+ */
+
+/* Unknown mapping. Connect everything to ground */
+#define SRC_MAPPING_INFO_unknown \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* gnd */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* xosc */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 0 */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 1 */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
+ }
+
+/* Only the oscillator and the two test debug clocks */
+#define SRC_MAPPING_INFO_xosc \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ }
+
+/* All the PLL "core" channels */
+#define SRC_MAPPING_INFO_core \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_PLLA_CHANNEL_CORE, \
+ CPRMAN_PLLC_CHANNEL_CORE0, \
+ CPRMAN_PLLD_CHANNEL_CORE, \
+ CPRMAN_PLLH_CHANNEL_AUX, \
+ CPRMAN_PLLC_CHANNEL_CORE1, \
+ CPRMAN_PLLC_CHANNEL_CORE2, \
+ }
+
+/* All the PLL "per" channels */
+#define SRC_MAPPING_INFO_periph \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_PLLA_CHANNEL_PER, \
+ CPRMAN_PLLC_CHANNEL_PER, \
+ CPRMAN_PLLD_CHANNEL_PER, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ }
+
+/*
+ * The DSI0 channels. This one got an intermediate mux between the PLL channels
+ * and the clock input.
+ */
+#define SRC_MAPPING_INFO_dsi0 \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_DSI0HSCK, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ }
+
+/* The DSI1 channel */
+#define SRC_MAPPING_INFO_dsi1 \
+ .src_mapping = { \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_CLOCK_SRC_NORMAL, \
+ CPRMAN_PLLD_CHANNEL_DSI1, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ CPRMAN_CLOCK_SRC_FORCE_GROUND, \
+ }
+
+#define FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) \
+ SRC_MAPPING_INFO_ ## kind_
+
+#define FILL_CLOCK_MUX_INIT_INFO(clock_, kind_) \
+ .cm_offset = R_CM_ ## clock_ ## CTL, \
+ FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_)
+
+static ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
+ [CPRMAN_CLOCK_GNRIC] = {
+ .name = "gnric",
+ FILL_CLOCK_MUX_INIT_INFO(GNRIC, unknown),
+ },
+ [CPRMAN_CLOCK_VPU] = {
+ .name = "vpu",
+ .int_bits = 12,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(VPU, core),
+ },
+ [CPRMAN_CLOCK_SYS] = {
+ .name = "sys",
+ FILL_CLOCK_MUX_INIT_INFO(SYS, unknown),
+ },
+ [CPRMAN_CLOCK_PERIA] = {
+ .name = "peria",
+ FILL_CLOCK_MUX_INIT_INFO(PERIA, unknown),
+ },
+ [CPRMAN_CLOCK_PERII] = {
+ .name = "perii",
+ FILL_CLOCK_MUX_INIT_INFO(PERII, unknown),
+ },
+ [CPRMAN_CLOCK_H264] = {
+ .name = "h264",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(H264, core),
+ },
+ [CPRMAN_CLOCK_ISP] = {
+ .name = "isp",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(ISP, core),
+ },
+ [CPRMAN_CLOCK_V3D] = {
+ .name = "v3d",
+ FILL_CLOCK_MUX_INIT_INFO(V3D, core),
+ },
+ [CPRMAN_CLOCK_CAM0] = {
+ .name = "cam0",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(CAM0, periph),
+ },
+ [CPRMAN_CLOCK_CAM1] = {
+ .name = "cam1",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(CAM1, periph),
+ },
+ [CPRMAN_CLOCK_CCP2] = {
+ .name = "ccp2",
+ FILL_CLOCK_MUX_INIT_INFO(CCP2, unknown),
+ },
+ [CPRMAN_CLOCK_DSI0E] = {
+ .name = "dsi0e",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0),
+ },
+ [CPRMAN_CLOCK_DSI0P] = {
+ .name = "dsi0p",
+ .int_bits = 0,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0),
+ },
+ [CPRMAN_CLOCK_DPI] = {
+ .name = "dpi",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(DPI, periph),
+ },
+ [CPRMAN_CLOCK_GP0] = {
+ .name = "gp0",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(GP0, periph),
+ },
+ [CPRMAN_CLOCK_GP1] = {
+ .name = "gp1",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(GP1, periph),
+ },
+ [CPRMAN_CLOCK_GP2] = {
+ .name = "gp2",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(GP2, periph),
+ },
+ [CPRMAN_CLOCK_HSM] = {
+ .name = "hsm",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(HSM, periph),
+ },
+ [CPRMAN_CLOCK_OTP] = {
+ .name = "otp",
+ .int_bits = 4,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(OTP, xosc),
+ },
+ [CPRMAN_CLOCK_PCM] = {
+ .name = "pcm",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(PCM, periph),
+ },
+ [CPRMAN_CLOCK_PWM] = {
+ .name = "pwm",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(PWM, periph),
+ },
+ [CPRMAN_CLOCK_SLIM] = {
+ .name = "slim",
+ .int_bits = 12,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(SLIM, periph),
+ },
+ [CPRMAN_CLOCK_SMI] = {
+ .name = "smi",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(SMI, periph),
+ },
+ [CPRMAN_CLOCK_TEC] = {
+ .name = "tec",
+ .int_bits = 6,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(TEC, xosc),
+ },
+ [CPRMAN_CLOCK_TD0] = {
+ .name = "td0",
+ FILL_CLOCK_MUX_INIT_INFO(TD0, unknown),
+ },
+ [CPRMAN_CLOCK_TD1] = {
+ .name = "td1",
+ FILL_CLOCK_MUX_INIT_INFO(TD1, unknown),
+ },
+ [CPRMAN_CLOCK_TSENS] = {
+ .name = "tsens",
+ .int_bits = 5,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(TSENS, xosc),
+ },
+ [CPRMAN_CLOCK_TIMER] = {
+ .name = "timer",
+ .int_bits = 6,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(TIMER, xosc),
+ },
+ [CPRMAN_CLOCK_UART] = {
+ .name = "uart",
+ .int_bits = 10,
+ .frac_bits = 12,
+ FILL_CLOCK_MUX_INIT_INFO(UART, periph),
+ },
+ [CPRMAN_CLOCK_VEC] = {
+ .name = "vec",
+ .int_bits = 4,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(VEC, periph),
+ },
+ [CPRMAN_CLOCK_PULSE] = {
+ .name = "pulse",
+ FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc),
+ },
+ [CPRMAN_CLOCK_SDC] = {
+ .name = "sdram",
+ .int_bits = 6,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(SDC, core),
+ },
+ [CPRMAN_CLOCK_ARM] = {
+ .name = "arm",
+ FILL_CLOCK_MUX_INIT_INFO(ARM, unknown),
+ },
+ [CPRMAN_CLOCK_AVEO] = {
+ .name = "aveo",
+ .int_bits = 4,
+ .frac_bits = 0,
+ FILL_CLOCK_MUX_INIT_INFO(AVEO, periph),
+ },
+ [CPRMAN_CLOCK_EMMC] = {
+ .name = "emmc",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(EMMC, periph),
+ },
+ [CPRMAN_CLOCK_EMMC2] = {
+ .name = "emmc2",
+ .int_bits = 4,
+ .frac_bits = 8,
+ FILL_CLOCK_MUX_INIT_INFO(EMMC2, unknown),
+ },
+};
+
+#undef FILL_CLOCK_MUX_INIT_INFO
+#undef FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO
+#undef SRC_MAPPING_INFO_dsi1
+#undef SRC_MAPPING_INFO_dsi0
+#undef SRC_MAPPING_INFO_periph
+#undef SRC_MAPPING_INFO_core
+#undef SRC_MAPPING_INFO_xosc
+#undef SRC_MAPPING_INFO_unknown
+
+static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
+ CprmanClockMuxState *mux,
+ CprmanClockMux id)
+{
+ mux->id = id;
+ mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset];
+ mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];
+ mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;
+ mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
+}
+
+
+/*
+ * Object reset info
+ * Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using the
+ * clk debugfs interface in Linux.
+ */
+typedef struct PLLResetInfo {
+ uint32_t cm;
+ uint32_t a2w_ctrl;
+ uint32_t a2w_ana[4];
+ uint32_t a2w_frac;
+} PLLResetInfo;
+
+static const PLLResetInfo PLL_RESET_INFO[] = {
+ [CPRMAN_PLLA] = {
+ .cm = 0x0000008a,
+ .a2w_ctrl = 0x0002103a,
+ .a2w_frac = 0x00098000,
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
+ },
+
+ [CPRMAN_PLLC] = {
+ .cm = 0x00000228,
+ .a2w_ctrl = 0x0002103e,
+ .a2w_frac = 0x00080000,
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
+ },
+
+ [CPRMAN_PLLD] = {
+ .cm = 0x0000020a,
+ .a2w_ctrl = 0x00021034,
+ .a2w_frac = 0x00015556,
+ .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
+ },
+
+ [CPRMAN_PLLH] = {
+ .cm = 0x00000000,
+ .a2w_ctrl = 0x0002102d,
+ .a2w_frac = 0x00000000,
+ .a2w_ana = { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 }
+ },
+
+ [CPRMAN_PLLB] = {
+ /* unknown */
+ .cm = 0x00000000,
+ .a2w_ctrl = 0x00000000,
+ .a2w_frac = 0x00000000,
+ .a2w_ana = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
+ }
+};
+
+typedef struct PLLChannelResetInfo {
+ /*
+ * Even though a PLL channel has a CM register, it shares it with its
+ * parent PLL. The parent already takes care of the reset value.
+ */
+ uint32_t a2w_ctrl;
+} PLLChannelResetInfo;
+
+static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] = {
+ [CPRMAN_PLLA_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
+ [CPRMAN_PLLA_CHANNEL_CORE] = { .a2w_ctrl = 0x00000003 },
+ [CPRMAN_PLLA_CHANNEL_PER] = { .a2w_ctrl = 0x00000000 }, /* unknown */
+ [CPRMAN_PLLA_CHANNEL_CCP2] = { .a2w_ctrl = 0x00000100 },
+
+ [CPRMAN_PLLC_CHANNEL_CORE2] = { .a2w_ctrl = 0x00000100 },
+ [CPRMAN_PLLC_CHANNEL_CORE1] = { .a2w_ctrl = 0x00000100 },
+ [CPRMAN_PLLC_CHANNEL_PER] = { .a2w_ctrl = 0x00000002 },
+ [CPRMAN_PLLC_CHANNEL_CORE0] = { .a2w_ctrl = 0x00000002 },
+
+ [CPRMAN_PLLD_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
+ [CPRMAN_PLLD_CHANNEL_CORE] = { .a2w_ctrl = 0x00000004 },
+ [CPRMAN_PLLD_CHANNEL_PER] = { .a2w_ctrl = 0x00000004 },
+ [CPRMAN_PLLD_CHANNEL_DSI1] = { .a2w_ctrl = 0x00000100 },
+
+ [CPRMAN_PLLH_CHANNEL_AUX] = { .a2w_ctrl = 0x00000004 },
+ [CPRMAN_PLLH_CHANNEL_RCAL] = { .a2w_ctrl = 0x00000000 },
+ [CPRMAN_PLLH_CHANNEL_PIX] = { .a2w_ctrl = 0x00000000 },
+
+ [CPRMAN_PLLB_CHANNEL_ARM] = { .a2w_ctrl = 0x00000000 }, /* unknown */
+};
+
+typedef struct ClockMuxResetInfo {
+ uint32_t cm_ctl;
+ uint32_t cm_div;
+} ClockMuxResetInfo;
+
+static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] = {
+ [CPRMAN_CLOCK_GNRIC] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_VPU] = {
+ .cm_ctl = 0x00000245,
+ .cm_div = 0x00003000,
+ },
+
+ [CPRMAN_CLOCK_SYS] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_PERIA] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_PERII] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_H264] = {
+ .cm_ctl = 0x00000244,
+ .cm_div = 0x00003000,
+ },
+
+ [CPRMAN_CLOCK_ISP] = {
+ .cm_ctl = 0x00000244,
+ .cm_div = 0x00003000,
+ },
+
+ [CPRMAN_CLOCK_V3D] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_CAM0] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_CAM1] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_CCP2] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_DSI0E] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_DSI0P] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_DPI] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_GP0] = {
+ .cm_ctl = 0x00000200,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_GP1] = {
+ .cm_ctl = 0x00000096,
+ .cm_div = 0x00014000,
+ },
+
+ [CPRMAN_CLOCK_GP2] = {
+ .cm_ctl = 0x00000291,
+ .cm_div = 0x00249f00,
+ },
+
+ [CPRMAN_CLOCK_HSM] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_OTP] = {
+ .cm_ctl = 0x00000091,
+ .cm_div = 0x00004000,
+ },
+
+ [CPRMAN_CLOCK_PCM] = {
+ .cm_ctl = 0x00000200,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_PWM] = {
+ .cm_ctl = 0x00000200,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_SLIM] = {
+ .cm_ctl = 0x00000200,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_SMI] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_TEC] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_TD0] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_TD1] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_TSENS] = {
+ .cm_ctl = 0x00000091,
+ .cm_div = 0x0000a000,
+ },
+
+ [CPRMAN_CLOCK_TIMER] = {
+ .cm_ctl = 0x00000291,
+ .cm_div = 0x00013333,
+ },
+
+ [CPRMAN_CLOCK_UART] = {
+ .cm_ctl = 0x00000296,
+ .cm_div = 0x0000a6ab,
+ },
+
+ [CPRMAN_CLOCK_VEC] = {
+ .cm_ctl = 0x00000097,
+ .cm_div = 0x00002000,
+ },
+
+ [CPRMAN_CLOCK_PULSE] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_SDC] = {
+ .cm_ctl = 0x00004006,
+ .cm_div = 0x00003000,
+ },
+
+ [CPRMAN_CLOCK_ARM] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+
+ [CPRMAN_CLOCK_AVEO] = {
+ .cm_ctl = 0x00000000,
+ .cm_div = 0x00000000,
+ },
+
+ [CPRMAN_CLOCK_EMMC] = {
+ .cm_ctl = 0x00000295,
+ .cm_div = 0x00006000,
+ },
+
+ [CPRMAN_CLOCK_EMMC2] = {
+ .cm_ctl = 0, /* unknown */
+ .cm_div = 0
+ },
+};
+
+#endif
*/
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
+#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
+
typedef struct NPCM7xxCLKState {
SysBusDevice parent;
--- /dev/null
+/*
+ * Nuvoton NPCM7xx Random Number Generator.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_RNG_H
+#define NPCM7XX_RNG_H
+
+#include "hw/sysbus.h"
+
+typedef struct NPCM7xxRNGState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint8_t rngcs;
+ uint8_t rngd;
+ uint8_t rngmode;
+} NPCM7xxRNGState;
+
+#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
+#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
+
+#endif /* NPCM7XX_RNG_H */
void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
uint32_t count, uint32_t index);
int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
-void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
- Error **errp);
+int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp);
void spapr_clear_pending_events(SpaprMachineState *spapr);
void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
int spapr_max_server_number(SpaprMachineState *spapr);
void spapr_dt_persistent_memory(SpaprMachineState *spapr, void *fdt);
bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
uint64_t size, Error **errp);
-void spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp);
-void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr);
+bool spapr_add_nvdimm(DeviceState *dev, uint64_t slot, Error **errp);
#endif
/**
* DeviceState:
* @realized: Indicates whether the device has been fully constructed.
- * When accessed outsize big qemu lock, must be accessed with
- * atomic_load_acquire()
+ * When accessed outside big qemu lock, must be accessed with
+ * qatomic_load_acquire()
* @reset: ResettableState for the device; handled by Resettable interface.
*
* This structure should not be accessed directly. We declare it here
struct ESPDMADeviceState {
DMADeviceState parent_obj;
- SysBusESPState *esp;
+ SysBusESPState esp;
};
#define TYPE_SPARC32_LEDMA_DEVICE "sparc32-ledma"
struct LEDMADeviceState {
DMADeviceState parent_obj;
- SysBusPCNetState *lance;
+ SysBusPCNetState lance;
};
#define TYPE_SPARC32_DMA "sparc32-dma"
MemoryRegion dmamem;
MemoryRegion ledma_alias;
- ESPDMADeviceState *espdma;
- LEDMADeviceState *ledma;
+ ESPDMADeviceState espdma;
+ LEDMADeviceState ledma;
};
/* sparc32_dma.c */
#include "hw/sysbus.h"
#include "qom/object.h"
+#include "hw/ptimer.h"
#define TYPE_SYSTICK "armv7m_systick"
uint32_t control;
uint32_t reload;
int64_t tick;
- QEMUTimer *timer;
+ ptimer_state *ptimer;
MemoryRegion iomem;
qemu_irq irq;
};
*/
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
+/* The basic watchdog timer period is 2^14 clock cycles. */
+#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
+
+#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
+
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
/**
- * struct NPCM7xxTimer - Individual timer state.
- * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
+ * watchdog timer use.
* @qtimer: QEMU timer that notifies us on expiration.
* @expires_ns: Absolute virtual expiration time.
* @remaining_ns: Remaining time until expiration if timer is paused.
+ */
+typedef struct NPCM7xxBaseTimer {
+ QEMUTimer qtimer;
+ int64_t expires_ns;
+ int64_t remaining_ns;
+} NPCM7xxBaseTimer;
+
+/**
+ * struct NPCM7xxTimer - Individual timer state.
+ * @ctrl: The timer module that owns this timer.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @base_timer: The basic timer functionality for this timer.
* @tcsr: The Timer Control and Status Register.
* @ticr: The Timer Initial Count Register.
*/
NPCM7xxTimerCtrlState *ctrl;
qemu_irq irq;
- QEMUTimer qtimer;
- int64_t expires_ns;
- int64_t remaining_ns;
+ NPCM7xxBaseTimer base_timer;
uint32_t tcsr;
uint32_t ticr;
} NPCM7xxTimer;
+/**
+ * struct NPCM7xxWatchdogTimer - The watchdog timer state.
+ * @ctrl: The timer module that owns this timer.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @reset_signal: The GPIO used to send a reset signal.
+ * @base_timer: The basic timer functionality for this timer.
+ * @wtcr: The Watchdog Timer Control Register.
+ */
+typedef struct NPCM7xxWatchdogTimer {
+ NPCM7xxTimerCtrlState *ctrl;
+
+ qemu_irq irq;
+ qemu_irq reset_signal;
+ NPCM7xxBaseTimer base_timer;
+
+ uint32_t wtcr;
+} NPCM7xxWatchdogTimer;
+
/**
* struct NPCM7xxTimerCtrlState - Timer Module device state.
* @parent: System bus device.
* @iomem: Memory region through which registers are accessed.
+ * @index: The index of this timer module.
* @tisr: The Timer Interrupt Status Register.
- * @wtcr: The Watchdog Timer Control Register.
* @timer: The five individual timers managed by this module.
+ * @watchdog_timer: The watchdog timer managed by this module.
*/
struct NPCM7xxTimerCtrlState {
SysBusDevice parent;
MemoryRegion iomem;
uint32_t tisr;
- uint32_t wtcr;
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
+ NPCM7xxWatchdogTimer watchdog_timer;
};
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
--- /dev/null
+/*
+ * Copyright (c) 2020 Linaro Limited
+ *
+ * Authors:
+ * Shashi Mallela <shashi.mallela@linaro.org>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at your
+ * option) any later version. See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef WDT_SBSA_GWDT_H
+#define WDT_SBSA_GWDT_H
+
+#include "qemu/bitops.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+#define TYPE_WDT_SBSA "sbsa_gwdt"
+#define SBSA_GWDT(obj) \
+ OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
+#define SBSA_GWDT_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
+#define SBSA_GWDT_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
+
+/* SBSA Generic Watchdog register definitions */
+/* refresh frame */
+#define SBSA_GWDT_WRR 0x000
+
+/* control frame */
+#define SBSA_GWDT_WCS 0x000
+#define SBSA_GWDT_WOR 0x008
+#define SBSA_GWDT_WORU 0x00C
+#define SBSA_GWDT_WCV 0x010
+#define SBSA_GWDT_WCVU 0x014
+
+/* Watchdog Interface Identification Register */
+#define SBSA_GWDT_W_IIDR 0xFCC
+
+/* Watchdog Control and Status Register Bits */
+#define SBSA_GWDT_WCS_EN BIT(0)
+#define SBSA_GWDT_WCS_WS0 BIT(1)
+#define SBSA_GWDT_WCS_WS1 BIT(2)
+
+#define SBSA_GWDT_WOR_MASK 0x0000FFFF
+
+/*
+ * Watchdog Interface Identification Register definition
+ * considering JEP106 code for ARM in Bits [11:0]
+ */
+#define SBSA_GWDT_ID 0x1043B
+
+/* 2 Separate memory regions for each of refresh & control register frames */
+#define SBSA_GWDT_RMMIO_SIZE 0x1000
+#define SBSA_GWDT_CMMIO_SIZE 0x1000
+
+#define SBSA_TIMER_FREQ 62500000 /* Hz */
+
+typedef struct SBSA_GWDTState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion rmmio;
+ MemoryRegion cmmio;
+ qemu_irq irq;
+
+ QEMUTimer *timer;
+
+ uint32_t id;
+ uint32_t wcs;
+ uint32_t worl;
+ uint32_t woru;
+ uint32_t wcvl;
+ uint32_t wcvu;
+} SBSA_GWDTState;
+
+#endif /* WDT_SBSA_GWDT_H */
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
+ * version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
-DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
+DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
-DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
+DEF(brcond2_i32, 0, 4, 2,
+ TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
IMPL(TCG_TARGET_HAS_extrh_i64_i32)
| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
-DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
+DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
#define TCG_MAX_OP_ARGS 16
-/* Bits for TCGOpDef->flags, 8 bits available. */
+/* Bits for TCGOpDef->flags, 8 bits available, all used. */
enum {
/* Instruction exits the translation block. */
TCG_OPF_BB_EXIT = 0x01,
TCG_OPF_NOT_PRESENT = 0x20,
/* Instruction operands are vectors. */
TCG_OPF_VECTOR = 0x40,
+ /* Instruction is a conditional branch. */
+ TCG_OPF_COND_BRANCH = 0x80
};
typedef struct TCGOpDef {
+ offsetof(struct target_rt_frame_record, tramp);
}
env->xregs[0] = usig;
- env->xregs[31] = frame_addr;
env->xregs[29] = frame_addr + fr_ofs;
- env->pc = ka->_sa_handler;
env->xregs[30] = return_addr;
+ env->xregs[31] = frame_addr;
+ env->pc = ka->_sa_handler;
+
+ /* Invoke the signal handler as if by indirect call. */
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
+ env->btype = 2;
+ }
+
if (info) {
tswap_siginfo(&frame->info, info);
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
#include "qemu/guest-random.h"
#include "qemu/units.h"
#include "qemu/selfmap.h"
+#include "qapi/error.h"
#ifdef _ARCH_PPC64
#undef ARCH_DLINFO
#include "elf.h"
+/* We must delay the following stanzas until after "elf.h". */
+#if defined(TARGET_AARCH64)
+
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
+ const uint32_t *data,
+ struct image_info *info,
+ Error **errp)
+{
+ if (pr_type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) {
+ if (pr_datasz != sizeof(uint32_t)) {
+ error_setg(errp, "Ill-formed GNU_PROPERTY_AARCH64_FEATURE_1_AND");
+ return false;
+ }
+ /* We will extract GNU_PROPERTY_AARCH64_FEATURE_1_BTI later. */
+ info->note_flags = *data;
+ }
+ return true;
+}
+#define ARCH_USE_GNU_PROPERTY 1
+
+#else
+
+static bool arch_parse_elf_property(uint32_t pr_type, uint32_t pr_datasz,
+ const uint32_t *data,
+ struct image_info *info,
+ Error **errp)
+{
+ g_assert_not_reached();
+}
+#define ARCH_USE_GNU_PROPERTY 0
+
+#endif
+
struct exec
{
unsigned int a_info; /* Use macros N_MAGIC, etc for access */
"@ 0x%" PRIx64 "\n", (uint64_t)guest_base);
}
+enum {
+ /* The string "GNU\0" as a magic number. */
+ GNU0_MAGIC = const_le32('G' | 'N' << 8 | 'U' << 16),
+ NOTE_DATA_SZ = 1 * KiB,
+ NOTE_NAME_SZ = 4,
+ ELF_GNU_PROPERTY_ALIGN = ELF_CLASS == ELFCLASS32 ? 4 : 8,
+};
+
+/*
+ * Process a single gnu_property entry.
+ * Return false for error.
+ */
+static bool parse_elf_property(const uint32_t *data, int *off, int datasz,
+ struct image_info *info, bool have_prev_type,
+ uint32_t *prev_type, Error **errp)
+{
+ uint32_t pr_type, pr_datasz, step;
+
+ if (*off > datasz || !QEMU_IS_ALIGNED(*off, ELF_GNU_PROPERTY_ALIGN)) {
+ goto error_data;
+ }
+ datasz -= *off;
+ data += *off / sizeof(uint32_t);
+
+ if (datasz < 2 * sizeof(uint32_t)) {
+ goto error_data;
+ }
+ pr_type = data[0];
+ pr_datasz = data[1];
+ data += 2;
+ datasz -= 2 * sizeof(uint32_t);
+ step = ROUND_UP(pr_datasz, ELF_GNU_PROPERTY_ALIGN);
+ if (step > datasz) {
+ goto error_data;
+ }
+
+ /* Properties are supposed to be unique and sorted on pr_type. */
+ if (have_prev_type && pr_type <= *prev_type) {
+ if (pr_type == *prev_type) {
+ error_setg(errp, "Duplicate property in PT_GNU_PROPERTY");
+ } else {
+ error_setg(errp, "Unsorted property in PT_GNU_PROPERTY");
+ }
+ return false;
+ }
+ *prev_type = pr_type;
+
+ if (!arch_parse_elf_property(pr_type, pr_datasz, data, info, errp)) {
+ return false;
+ }
+
+ *off += 2 * sizeof(uint32_t) + step;
+ return true;
+
+ error_data:
+ error_setg(errp, "Ill-formed property in PT_GNU_PROPERTY");
+ return false;
+}
+
+/* Process NT_GNU_PROPERTY_TYPE_0. */
+static bool parse_elf_properties(int image_fd,
+ struct image_info *info,
+ const struct elf_phdr *phdr,
+ char bprm_buf[BPRM_BUF_SIZE],
+ Error **errp)
+{
+ union {
+ struct elf_note nhdr;
+ uint32_t data[NOTE_DATA_SZ / sizeof(uint32_t)];
+ } note;
+
+ int n, off, datasz;
+ bool have_prev_type;
+ uint32_t prev_type;
+
+ /* Unless the arch requires properties, ignore them. */
+ if (!ARCH_USE_GNU_PROPERTY) {
+ return true;
+ }
+
+ /* If the properties are crazy large, that's too bad. */
+ n = phdr->p_filesz;
+ if (n > sizeof(note)) {
+ error_setg(errp, "PT_GNU_PROPERTY too large");
+ return false;
+ }
+ if (n < sizeof(note.nhdr)) {
+ error_setg(errp, "PT_GNU_PROPERTY too small");
+ return false;
+ }
+
+ if (phdr->p_offset + n <= BPRM_BUF_SIZE) {
+ memcpy(¬e, bprm_buf + phdr->p_offset, n);
+ } else {
+ ssize_t len = pread(image_fd, ¬e, n, phdr->p_offset);
+ if (len != n) {
+ error_setg_errno(errp, errno, "Error reading file header");
+ return false;
+ }
+ }
+
+ /*
+ * The contents of a valid PT_GNU_PROPERTY is a sequence
+ * of uint32_t -- swap them all now.
+ */
+#ifdef BSWAP_NEEDED
+ for (int i = 0; i < n / 4; i++) {
+ bswap32s(note.data + i);
+ }
+#endif
+
+ /*
+ * Note that nhdr is 3 words, and that the "name" described by namesz
+ * immediately follows nhdr and is thus at the 4th word. Further, all
+ * of the inputs to the kernel's round_up are multiples of 4.
+ */
+ if (note.nhdr.n_type != NT_GNU_PROPERTY_TYPE_0 ||
+ note.nhdr.n_namesz != NOTE_NAME_SZ ||
+ note.data[3] != GNU0_MAGIC) {
+ error_setg(errp, "Invalid note in PT_GNU_PROPERTY");
+ return false;
+ }
+ off = sizeof(note.nhdr) + NOTE_NAME_SZ;
+
+ datasz = note.nhdr.n_descsz + off;
+ if (datasz > n) {
+ error_setg(errp, "Invalid note size in PT_GNU_PROPERTY");
+ return false;
+ }
+
+ have_prev_type = false;
+ prev_type = 0;
+ while (1) {
+ if (off == datasz) {
+ return true; /* end, exit ok */
+ }
+ if (!parse_elf_property(note.data, &off, datasz, info,
+ have_prev_type, &prev_type, errp)) {
+ return false;
+ }
+ have_prev_type = true;
+ }
+}
+
/* Load an ELF image into the address space.
IMAGE_NAME is the filename of the image, to use in error messages.
struct elfhdr *ehdr = (struct elfhdr *)bprm_buf;
struct elf_phdr *phdr;
abi_ulong load_addr, load_bias, loaddr, hiaddr, error;
- int i, retval;
- const char *errmsg;
+ int i, retval, prot_exec;
+ Error *err = NULL;
/* First of all, some simple consistency checks */
- errmsg = "Invalid ELF image for this architecture";
if (!elf_check_ident(ehdr)) {
+ error_setg(&err, "Invalid ELF image for this architecture");
goto exit_errmsg;
}
bswap_ehdr(ehdr);
if (!elf_check_ehdr(ehdr)) {
+ error_setg(&err, "Invalid ELF image for this architecture");
goto exit_errmsg;
}
mmap_lock();
- /* Find the maximum size of the image and allocate an appropriate
- amount of memory to handle that. */
+ /*
+ * Find the maximum size of the image and allocate an appropriate
+ * amount of memory to handle that. Locate the interpreter, if any.
+ */
loaddr = -1, hiaddr = 0;
info->alignment = 0;
for (i = 0; i < ehdr->e_phnum; ++i) {
- if (phdr[i].p_type == PT_LOAD) {
- abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset;
+ struct elf_phdr *eppnt = phdr + i;
+ if (eppnt->p_type == PT_LOAD) {
+ abi_ulong a = eppnt->p_vaddr - eppnt->p_offset;
if (a < loaddr) {
loaddr = a;
}
- a = phdr[i].p_vaddr + phdr[i].p_memsz;
+ a = eppnt->p_vaddr + eppnt->p_memsz;
if (a > hiaddr) {
hiaddr = a;
}
++info->nsegs;
- info->alignment |= phdr[i].p_align;
+ info->alignment |= eppnt->p_align;
+ } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
+ g_autofree char *interp_name = NULL;
+
+ if (*pinterp_name) {
+ error_setg(&err, "Multiple PT_INTERP entries");
+ goto exit_errmsg;
+ }
+
+ interp_name = g_malloc(eppnt->p_filesz);
+
+ if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
+ memcpy(interp_name, bprm_buf + eppnt->p_offset,
+ eppnt->p_filesz);
+ } else {
+ retval = pread(image_fd, interp_name, eppnt->p_filesz,
+ eppnt->p_offset);
+ if (retval != eppnt->p_filesz) {
+ goto exit_read;
+ }
+ }
+ if (interp_name[eppnt->p_filesz - 1] != 0) {
+ error_setg(&err, "Invalid PT_INTERP entry");
+ goto exit_errmsg;
+ }
+ *pinterp_name = g_steal_pointer(&interp_name);
+ } else if (eppnt->p_type == PT_GNU_PROPERTY) {
+ if (!parse_elf_properties(image_fd, info, eppnt, bprm_buf, &err)) {
+ goto exit_errmsg;
+ }
}
}
(ehdr->e_type == ET_EXEC ? MAP_FIXED : 0),
-1, 0);
if (load_addr == -1) {
- goto exit_perror;
+ goto exit_mmap;
}
load_bias = load_addr - loaddr;
info->brk = 0;
info->elf_flags = ehdr->e_flags;
+ prot_exec = PROT_EXEC;
+#ifdef TARGET_AARCH64
+ /*
+ * If the BTI feature is present, this indicates that the executable
+ * pages of the startup binary should be mapped with PROT_BTI, so that
+ * branch targets are enforced.
+ *
+ * The startup binary is either the interpreter or the static executable.
+ * The interpreter is responsible for all pages of a dynamic executable.
+ *
+ * Elf notes are backward compatible to older cpus.
+ * Do not enable BTI unless it is supported.
+ */
+ if ((info->note_flags & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
+ && (pinterp_name == NULL || *pinterp_name == 0)
+ && cpu_isar_feature(aa64_bti, ARM_CPU(thread_cpu))) {
+ prot_exec |= TARGET_PROT_BTI;
+ }
+#endif
+
for (i = 0; i < ehdr->e_phnum; i++) {
struct elf_phdr *eppnt = phdr + i;
if (eppnt->p_type == PT_LOAD) {
abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len;
int elf_prot = 0;
- if (eppnt->p_flags & PF_R) elf_prot = PROT_READ;
- if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE;
- if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC;
+ if (eppnt->p_flags & PF_R) {
+ elf_prot |= PROT_READ;
+ }
+ if (eppnt->p_flags & PF_W) {
+ elf_prot |= PROT_WRITE;
+ }
+ if (eppnt->p_flags & PF_X) {
+ elf_prot |= prot_exec;
+ }
vaddr = load_bias + eppnt->p_vaddr;
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
image_fd, eppnt->p_offset - vaddr_po);
if (error == -1) {
- goto exit_perror;
+ goto exit_mmap;
}
}
if (vaddr_em > info->brk) {
info->brk = vaddr_em;
}
- } else if (eppnt->p_type == PT_INTERP && pinterp_name) {
- char *interp_name;
-
- if (*pinterp_name) {
- errmsg = "Multiple PT_INTERP entries";
- goto exit_errmsg;
- }
- interp_name = malloc(eppnt->p_filesz);
- if (!interp_name) {
- goto exit_perror;
- }
-
- if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
- memcpy(interp_name, bprm_buf + eppnt->p_offset,
- eppnt->p_filesz);
- } else {
- retval = pread(image_fd, interp_name, eppnt->p_filesz,
- eppnt->p_offset);
- if (retval != eppnt->p_filesz) {
- goto exit_perror;
- }
- }
- if (interp_name[eppnt->p_filesz - 1] != 0) {
- errmsg = "Invalid PT_INTERP entry";
- goto exit_errmsg;
- }
- *pinterp_name = interp_name;
#ifdef TARGET_MIPS
} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
Mips_elf_abiflags_v0 abiflags;
if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
- errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
+ error_setg(&err, "Invalid PT_MIPS_ABIFLAGS entry");
goto exit_errmsg;
}
if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
retval = pread(image_fd, &abiflags, sizeof(Mips_elf_abiflags_v0),
eppnt->p_offset);
if (retval != sizeof(Mips_elf_abiflags_v0)) {
- goto exit_perror;
+ goto exit_read;
}
}
bswap_mips_abiflags(&abiflags);
exit_read:
if (retval >= 0) {
- errmsg = "Incomplete read of file header";
- goto exit_errmsg;
+ error_setg(&err, "Incomplete read of file header");
+ } else {
+ error_setg_errno(&err, errno, "Error reading file header");
}
- exit_perror:
- errmsg = strerror(errno);
+ goto exit_errmsg;
+ exit_mmap:
+ error_setg_errno(&err, errno, "Error mapping file");
+ goto exit_errmsg;
exit_errmsg:
- fprintf(stderr, "%s: %s\n", image_name, errmsg);
+ error_reportf_err(err, "%s: ", image_name);
exit(-1);
}
char bprm_buf[BPRM_BUF_SIZE])
{
int fd, retval;
+ Error *err = NULL;
fd = open(path(filename), O_RDONLY);
if (fd < 0) {
- goto exit_perror;
+ error_setg_file_open(&err, errno, filename);
+ error_report_err(err);
+ exit(-1);
}
retval = read(fd, bprm_buf, BPRM_BUF_SIZE);
if (retval < 0) {
- goto exit_perror;
+ error_setg_errno(&err, errno, "Error reading file header");
+ error_reportf_err(err, "%s: ", filename);
+ exit(-1);
}
+
if (retval < BPRM_BUF_SIZE) {
memset(bprm_buf + retval, 0, BPRM_BUF_SIZE - retval);
}
load_elf_image(filename, fd, info, NULL, bprm_buf);
- return;
-
- exit_perror:
- fprintf(stderr, "%s: %s\n", filename, strerror(errno));
- exit(-1);
}
static int symfind(const void *s0, const void *s1)
if (elf_interpreter) {
info->load_bias = interp_info.load_bias;
info->entry = interp_info.entry;
- free(elf_interpreter);
+ g_free(elf_interpreter);
}
#ifdef USE_ELF_CORE_DUMP
*host_prot = (prot & (PROT_READ | PROT_WRITE))
| (prot & PROT_EXEC ? PROT_READ : 0);
+#ifdef TARGET_AARCH64
+ /*
+ * The PROT_BTI bit is only accepted if the cpu supports the feature.
+ * Since this is the unusual case, don't bother checking unless
+ * the bit has been requested. If set and valid, record the bit
+ * within QEMU's page_flags.
+ */
+ if (prot & TARGET_PROT_BTI) {
+ ARMCPU *cpu = ARM_CPU(thread_cpu);
+ if (cpu_isar_feature(aa64_bti, cpu)) {
+ valid |= TARGET_PROT_BTI;
+ page_flags |= PAGE_BTI;
+ }
+ }
+#endif
+
return prot & ~valid ? 0 : page_flags;
}
abi_ulong interpreter_loadmap_addr;
abi_ulong interpreter_pt_dynamic_addr;
struct image_info *other_info;
+
+ /* For target-specific processing of NT_GNU_PROPERTY_TYPE_0. */
+ uint32_t note_flags;
+
#ifdef TARGET_MIPS
int fp_abi;
int interp_fp_abi;
#define TARGET_PROT_SEM 0x08
#endif
+#ifdef TARGET_AARCH64
+#define TARGET_PROT_BTI 0x10
+#endif
+
/* Common */
#define TARGET_MAP_SHARED 0x01 /* Share changes */
#define TARGET_MAP_PRIVATE 0x02 /* Changes are private */
ERST
DEF("commit", img_commit,
- "commit [--object objectdef] [--image-opts] [-q] [-f fmt] [-t cache] [-b base] [-d] [-p] filename")
+ "commit [--object objectdef] [--image-opts] [-q] [-f fmt] [-t cache] [-b base] [-r rate_limit] [-d] [-p] filename")
SRST
-.. option:: commit [--object OBJECTDEF] [--image-opts] [-q] [-f FMT] [-t CACHE] [-b BASE] [-d] [-p] FILENAME
+.. option:: commit [--object OBJECTDEF] [--image-opts] [-q] [-f FMT] [-t CACHE] [-b BASE] [-r RATE_LIMIT] [-d] [-p] FILENAME
ERST
DEF("compare", img_compare,
ERST
DEF("convert", img_convert,
- "convert [--object objectdef] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f fmt] [-t cache] [-T src_cache] [-O output_fmt] [-B backing_file] [-o options] [-l snapshot_param] [-S sparse_size] [-m num_coroutines] [-W] [--salvage] filename [filename2 [...]] output_filename")
+ "convert [--object objectdef] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f fmt] [-t cache] [-T src_cache] [-O output_fmt] [-B backing_file] [-o options] [-l snapshot_param] [-S sparse_size] [-r rate_limit] [-m num_coroutines] [-W] [--salvage] filename [filename2 [...]] output_filename")
SRST
-.. option:: convert [--object OBJECTDEF] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f FMT] [-t CACHE] [-T SRC_CACHE] [-O OUTPUT_FMT] [-B BACKING_FILE] [-o OPTIONS] [-l SNAPSHOT_PARAM] [-S SPARSE_SIZE] [-m NUM_COROUTINES] [-W] [--salvage] FILENAME [FILENAME2 [...]] OUTPUT_FILENAME
+.. option:: convert [--object OBJECTDEF] [--image-opts] [--target-image-opts] [--target-is-zero] [--bitmaps] [-U] [-C] [-c] [-p] [-q] [-n] [-f FMT] [-t CACHE] [-T SRC_CACHE] [-O OUTPUT_FMT] [-B BACKING_FILE] [-o OPTIONS] [-l SNAPSHOT_PARAM] [-S SPARSE_SIZE] [-r RATE_LIMIT] [-m NUM_COROUTINES] [-W] [--salvage] FILENAME [FILENAME2 [...]] OUTPUT_FILENAME
ERST
DEF("create", img_create,
#include "block/qapi.h"
#include "crypto/init.h"
#include "trace/control.h"
+#include "qemu/throttle.h"
+#include "block/throttle-groups.h"
#define QEMU_IMG_VERSION "qemu-img version " QEMU_FULL_VERSION \
"\n" QEMU_COPYRIGHT "\n"
CommonBlockJobCBInfo cbi;
bool image_opts = false;
AioContext *aio_context;
+ int64_t rate_limit = 0;
fmt = NULL;
cache = BDRV_DEFAULT_CACHE;
{"image-opts", no_argument, 0, OPTION_IMAGE_OPTS},
{0, 0, 0, 0}
};
- c = getopt_long(argc, argv, ":f:ht:b:dpq",
+ c = getopt_long(argc, argv, ":f:ht:b:dpqr:",
long_options, NULL);
if (c == -1) {
break;
case 'q':
quiet = true;
break;
+ case 'r':
+ rate_limit = cvtnum("rate limit", optarg);
+ if (rate_limit < 0) {
+ return 1;
+ }
+ break;
case OPTION_OBJECT: {
QemuOpts *opts;
opts = qemu_opts_parse_noisily(&qemu_object_opts,
aio_context = bdrv_get_aio_context(bs);
aio_context_acquire(aio_context);
- commit_active_start("commit", bs, base_bs, JOB_DEFAULT, 0,
+ commit_active_start("commit", bs, base_bs, JOB_DEFAULT, rate_limit,
BLOCKDEV_ON_ERROR_REPORT, NULL, common_block_job_cb,
&cbi, false, &local_err);
aio_context_release(aio_context);
};
#define MAX_COROUTINES 16
+#define CONVERT_THROTTLE_GROUP "img_convert"
typedef struct ImgConvertState {
BlockBackend **src;
#define MAX_BUF_SECTORS 32768
+static void set_rate_limit(BlockBackend *blk, int64_t rate_limit)
+{
+ ThrottleConfig cfg;
+
+ throttle_config_init(&cfg);
+ cfg.buckets[THROTTLE_BPS_WRITE].avg = rate_limit;
+
+ blk_io_limits_enable(blk, CONVERT_THROTTLE_GROUP);
+ blk_set_io_limits(blk, &cfg);
+}
+
static int img_convert(int argc, char **argv)
{
int c, bs_i, flags, src_flags = 0;
bool force_share = false;
bool explict_min_sparse = false;
bool bitmaps = false;
+ int64_t rate_limit = 0;
ImgConvertState s = (ImgConvertState) {
/* Need at least 4k of zeros for sparse detection */
{"bitmaps", no_argument, 0, OPTION_BITMAPS},
{0, 0, 0, 0}
};
- c = getopt_long(argc, argv, ":hf:O:B:Cco:l:S:pt:T:qnm:WU",
+ c = getopt_long(argc, argv, ":hf:O:B:Cco:l:S:pt:T:qnm:WUr:",
long_options, NULL);
if (c == -1) {
break;
case 'U':
force_share = true;
break;
+ case 'r':
+ rate_limit = cvtnum("rate limit", optarg);
+ if (rate_limit < 0) {
+ goto fail_getopt;
+ }
+ break;
case OPTION_OBJECT: {
QemuOpts *object_opts;
object_opts = qemu_opts_parse_noisily(&qemu_object_opts,
s.cluster_sectors = bdi.cluster_size / BDRV_SECTOR_SIZE;
}
+ if (rate_limit) {
+ set_rate_limit(s.target, rate_limit);
+ }
+
ret = convert_do_copy(&s);
/* Now copy the bitmaps */
close $HASH;
- die "$P: no revisions returned for revlist '$chk_branch'\n"
+ die "$P: no revisions returned for revlist '$ARGV[0]'\n"
unless @patches;
my $i = 1;
#!/usr/bin/env python3
-#
-# QMP command line tool
-#
-# Copyright IBM, Corp. 2011
-#
-# Authors:
-# Anthony Liguori <aliguori@us.ibm.com>
-#
-# This work is licensed under the terms of the GNU GPLv2 or later.
-# See the COPYING file in the top-level directory.
-import sys, os
+import sys
-sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..', 'python'))
-from qemu.qmp import QEMUMonitorProtocol
+print('''This unmaintained and undocumented script was removed in preference
+for qmp-shell. The assumption is that most users are using either
+qmp-shell, socat, or pasting/piping JSON into stdio. The duplication of
+facilities here is unwanted, and the divergence of syntax harmful.''',
+ file=sys.stderr)
-def print_response(rsp, prefix=[]):
- if type(rsp) == list:
- i = 0
- for item in rsp:
- if prefix == []:
- prefix = ['item']
- print_response(item, prefix[:-1] + ['%s[%d]' % (prefix[-1], i)])
- i += 1
- elif type(rsp) == dict:
- for key in rsp.keys():
- print_response(rsp[key], prefix + [key])
- else:
- if len(prefix):
- print('%s: %s' % ('.'.join(prefix), rsp))
- else:
- print('%s' % (rsp))
-
-def main(args):
- path = None
-
- # Use QMP_PATH if it's set
- if 'QMP_PATH' in os.environ:
- path = os.environ['QMP_PATH']
-
- while len(args):
- arg = args[0]
-
- if arg.startswith('--'):
- arg = arg[2:]
- if arg.find('=') == -1:
- value = True
- else:
- arg, value = arg.split('=', 1)
-
- if arg in ['path']:
- if type(value) == str:
- path = value
- elif arg in ['help']:
- os.execlp('man', 'man', 'qmp')
- else:
- print('Unknown argument "%s"' % arg)
-
- args = args[1:]
- else:
- break
-
- if not path:
- print("QMP path isn't set, use --path=qmp-monitor-address or set QMP_PATH")
- return 1
-
- if len(args):
- command, args = args[0], args[1:]
- else:
- print('No command found')
- print('Usage: "qmp [--path=qmp-monitor-address] qmp-cmd arguments"')
- return 1
-
- if command in ['help']:
- os.execlp('man', 'man', 'qmp')
-
- srv = QEMUMonitorProtocol(path)
- srv.connect()
-
- def do_command(srv, cmd, **kwds):
- rsp = srv.cmd(cmd, kwds)
- if 'error' in rsp:
- raise Exception(rsp['error']['desc'])
- return rsp['return']
-
- commands = map(lambda x: x['name'], do_command(srv, 'query-commands'))
-
- srv.close()
-
- if command not in commands:
- fullcmd = 'qmp-%s' % command
- try:
- os.environ['QMP_PATH'] = path
- os.execvp(fullcmd, [fullcmd] + args)
- except OSError as exc:
- if exc.errno == 2:
- print('Command "%s" not found.' % (fullcmd))
- return 1
- raise
- return 0
-
- srv = QEMUMonitorProtocol(path)
- srv.connect()
-
- arguments = {}
- for arg in args:
- if not arg.startswith('--'):
- print('Unknown argument "%s"' % arg)
- return 1
-
- arg = arg[2:]
- if arg.find('=') == -1:
- value = True
- else:
- arg, value = arg.split('=', 1)
-
- if arg in ['help']:
- os.execlp('man', 'man', 'qmp-%s' % command)
- return 1
-
- arguments[arg] = value
-
- rsp = do_command(srv, command, **arguments)
- print_response(rsp)
-
-if __name__ == '__main__':
- sys.exit(main(sys.argv[1:]))
+sys.exit(1)
indent = None
if self._pretty:
indent = 4
- jsobj = json.dumps(qmp, indent=indent)
+ jsobj = json.dumps(qmp, indent=indent, sort_keys=self._pretty)
print(str(jsobj))
def _execute_cmd(self, cmdline):
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
+/*
+ * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
+ */
+#define PAGE_BTI PAGE_TARGET_1
+
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in
*/
static bool is_guarded_page(CPUARMState *env, DisasContext *s)
{
+ uint64_t addr = s->base.pc_first;
#ifdef CONFIG_USER_ONLY
- return false; /* FIXME */
+ return page_get_flags(addr) & PAGE_BTI;
#else
- uint64_t addr = s->base.pc_first;
int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
unsigned int index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
#define FPSCR_OE 6 /* Floating-point overflow exception enable */
-#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
+#define FPSCR_UE 5 /* Floating-point underflow exception enable */
#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
#define FPSCR_XE 3 /* Floating-point inexact exception enable */
#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
/* Internal hardware exception sources */
PPC_INTERRUPT_DECR, /* Decrementer exception */
PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
- PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
+ PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt */
PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
- PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
+ PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
};
}
/*
- * Exception targetting modifiers
+ * Exception targeting modifiers
*
* LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
* This means we will incorrectly execute past the power management
* instruction instead of triggering a reset.
*
- * It generally means a discrepancy between the wakup conditions in the
+ * It generally means a discrepancy between the wakeup conditions in the
* processor has_work implementation and the logic in this function.
*/
cpu_abort(env_cpu(env),
void helper_rfid(CPUPPCState *env)
{
/*
- * The architeture defines a number of rules for which bits can
+ * The architecture defines a number of rules for which bits can
* change but in practice, we handle this in hreg_store_msr()
* which will be called by do_rfi(), so there is no need to filter
* here
/*
- * VSX_ADD_SUB - VSX floating point add/subract
+ * VSX_ADD_SUB - VSX floating point add/subtract
* name - instruction mnemonic
* op - operation (add or sub)
* nels - number of elements (1, 2 or 4)
/*
- * PowerPC interal definitions for qemu.
+ * PowerPC internal definitions for qemu.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
/*
* KVM-HV has transactional memory on POWER8 also without
* the KVM_CAP_PPC_HTM extension, so enable it here
- * instead as long as it's availble to userspace on the
+ * instead as long as it's available to userspace on the
* host.
*/
if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
}
int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
- uint16_t n_valid, uint16_t n_invalid)
+ uint16_t n_valid, uint16_t n_invalid, Error **errp)
{
struct kvm_get_htab_header *buf;
size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
rc = write(fd, buf, chunksize);
if (rc < 0) {
- fprintf(stderr, "Error writing KVM hash table: %s\n",
- strerror(errno));
- return rc;
+ error_setg_errno(errp, errno, "Error writing the KVM hash table");
+ return -errno;
}
if (rc != chunksize) {
/* We should never get a short write on a single chunk */
- fprintf(stderr, "Short write, restoring KVM hash table\n");
- return -1;
+ error_setg(errp, "Short write while restoring the KVM hash table");
+ return -ENOSPC;
}
return 0;
}
int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp);
int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns);
int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
- uint16_t n_valid, uint16_t n_invalid);
+ uint16_t n_valid, uint16_t n_invalid, Error **errp);
void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n);
void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1);
bool kvmppc_has_cap_fixup_hcalls(void);
}
static inline int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
- uint16_t n_valid, uint16_t n_invalid)
+ uint16_t n_valid, uint16_t n_invalid,
+ Error **errp)
{
abort();
}
/*
* If we're operating in compat mode, we should be ok as long as
- * the destination supports the same compatiblity mode.
+ * the destination supports the same compatibility mode.
*
* Otherwise, however, we require that the destination has exactly
* the same CPU model as the source.
/*
* Note on LPCR usage: 970 uses HID4, but our special variant of
* store_spr copies relevant fields into env->spr[SPR_LPCR].
- * Similarily we filter unimplemented bits when storing into LPCR
+ * Similarly we filter unimplemented bits when storing into LPCR
* depending on the MMU version. This code can thus just use the
* LPCR "as-is".
*/
}
/* Compute access rights */
access = pp_check(ctx->key, pp, ctx->nx);
- /* Keep the matching PTE informations */
+ /* Keep the matching PTE information */
ctx->raddr = pte1;
ctx->prot = access;
ret = check_prot(ctx->prot, rw, type);
env->sr[srnum] = value;
/*
* Invalidating 256MB of virtual memory in 4kB pages is way
- * longer than flusing the whole TLB.
+ * longer than flushing the whole TLB.
*/
#if !defined(FLUSH_ALL_TLBS) && 0
{
&spr_read_xer, &spr_write_xer,
&spr_read_xer, &spr_write_xer,
0x00000000);
- /* Branch contol */
+ /* Branch control */
spr_register(env, SPR_LR, "LR",
&spr_read_lr, &spr_write_lr,
&spr_read_lr, &spr_write_lr,
pcc->parent_unrealize(dev);
+ cpu_remove_sync(CPU(cpu));
+
for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
if (cpu->opcodes[i] == &invalid_handler) {
continue;
}
}
}
- goto do_reset_output;
+ /* fall through */
default:
do_default:
- /* Default case: we know nothing about operation (or were unable
- to compute the operation result) so no propagation is done.
- We trash everything if the operation is the end of a basic
- block, otherwise we only trash the output args. "mask" is
- the non-zero bits mask for the first output arg. */
- if (def->flags & TCG_OPF_BB_END) {
- bitmap_zero(temps_used.l, nb_temps);
- } else {
- do_reset_output:
- for (i = 0; i < nb_oargs; i++) {
- reset_temp(op->args[i]);
- /* Save the corresponding known-zero bits mask for the
- first output argument (only one supported so far). */
- if (i == 0) {
- arg_info(op->args[i])->mask = mask;
- }
+ /*
+ * Default case: we know nothing about operation (or were unable
+ * to compute the operation result) so no propagation is done.
+ */
+ for (i = 0; i < nb_oargs; i++) {
+ reset_temp(op->args[i]);
+ /*
+ * Save the corresponding known-zero bits mask for the
+ * first output argument (only one supported so far).
+ */
+ if (i == 0) {
+ arg_info(op->args[i])->mask = mask;
}
}
break;
+
+ case INDEX_op_set_label:
+ /* Trash everything at the start of a new extended bb. */
+ bitmap_zero(temps_used.l, nb_temps);
+ break;
}
/* Eliminate duplicate and redundant fence instructions. */
}
}
+/*
+ * liveness analysis: conditional branch: all temps are dead,
+ * globals and local temps should be synced.
+ */
+static void la_bb_sync(TCGContext *s, int ng, int nt)
+{
+ la_global_sync(s, ng);
+
+ for (int i = ng; i < nt; ++i) {
+ if (s->temps[i].temp_local) {
+ int state = s->temps[i].state;
+ s->temps[i].state = state | TS_MEM;
+ if (state != TS_DEAD) {
+ continue;
+ }
+ } else {
+ s->temps[i].state = TS_DEAD;
+ }
+ la_reset_pref(&s->temps[i]);
+ }
+}
+
/* liveness analysis: sync globals back to memory and kill. */
static void la_global_kill(TCGContext *s, int ng)
{
/* If end of basic block, update. */
if (def->flags & TCG_OPF_BB_EXIT) {
la_func_end(s, nb_globals, nb_temps);
+ } else if (def->flags & TCG_OPF_COND_BRANCH) {
+ la_bb_sync(s, nb_globals, nb_temps);
} else if (def->flags & TCG_OPF_BB_END) {
la_bb_end(s, nb_globals, nb_temps);
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
nb_oargs = def->nb_oargs;
/* Set flags similar to how calls require. */
- if (def->flags & TCG_OPF_BB_END) {
+ if (def->flags & TCG_OPF_COND_BRANCH) {
+ /* Like reading globals: sync_globals */
+ call_flags = TCG_CALL_NO_WRITE_GLOBALS;
+ } else if (def->flags & TCG_OPF_BB_END) {
/* Like writing globals: save_globals */
call_flags = 0;
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
save_globals(s, allocated_regs);
}
+/*
+ * At a conditional branch, we assume all temporaries are dead and
+ * all globals and local temps are synced to their location.
+ */
+static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs)
+{
+ sync_globals(s, allocated_regs);
+
+ for (int i = s->nb_globals; i < s->nb_temps; i++) {
+ TCGTemp *ts = &s->temps[i];
+ /*
+ * The liveness analysis already ensures that temps are dead.
+ * Keep tcg_debug_asserts for safety.
+ */
+ if (ts->temp_local) {
+ tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent);
+ } else {
+ tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
+ }
+ }
+}
+
/*
* Specialized code generation for INDEX_op_movi_*.
*/
}
}
- if (def->flags & TCG_OPF_BB_END) {
+ if (def->flags & TCG_OPF_COND_BRANCH) {
+ tcg_reg_alloc_cbranch(s, i_allocated_regs);
+ } else if (def->flags & TCG_OPF_BB_END) {
tcg_reg_alloc_bb_end(s, i_allocated_regs);
} else {
if (def->flags & TCG_OPF_CALL_CLOBBER) {
from avocado_qemu import BUILD_DIR
from avocado.utils import gdb
from avocado.utils import process
+from avocado.utils.network.ports import find_free_port
from avocado.utils.path import find_command
from boot_linux_console import LinuxKernelTest
STEPS = 10
endian_is_le = True
- def run_vm(self, record, shift, args, replay_path, image_path):
+ def run_vm(self, record, shift, args, replay_path, image_path, port):
logger = logging.getLogger('replay')
vm = self.get_vm()
vm.set_console()
else:
logger.info('replaying the execution...')
mode = 'replay'
- vm.add_args('-s', '-S')
+ vm.add_args('-gdb', 'tcp::%d' % port, '-S')
vm.add_args('-icount', 'shift=%s,rr=%s,rrfile=%s,rrsnapshot=init' %
(shift, mode, replay_path),
'-net', 'none')
process.run(cmd)
replay_path = os.path.join(self.workdir, 'replay.bin')
+ port = find_free_port()
# record the log
- vm = self.run_vm(True, shift, args, replay_path, image_path)
+ vm = self.run_vm(True, shift, args, replay_path, image_path, port)
while self.vm_get_icount(vm) <= self.STEPS:
pass
last_icount = self.vm_get_icount(vm)
logger.info("recorded log with %s+ steps" % last_icount)
# replay and run debug commands
- vm = self.run_vm(False, shift, args, replay_path, image_path)
+ vm = self.run_vm(False, shift, args, replay_path, image_path, port)
logger.info('connecting to gdbstub')
- g = gdb.GDBRemote('127.0.0.1', 1234, False, False)
+ g = gdb.GDBRemote('127.0.0.1', port, False, False)
g.connect()
r = g.cmd(b'qSupported')
if b'qXfer:features:read+' in r:
perl-Test-Harness \
pixman-devel \
python3 \
- SDL-devel \
+ SDL2-devel \
spice-glib-devel \
spice-server-devel \
tar \
RUN dnf -y update
ENV PACKAGES \
- SDL-devel \
+ SDL2-devel \
bzip2 \
bzip2-devel \
dbus-daemon \
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
['prom-env-test', 'boot-serial-test']
-qtests_npcm7xx = ['npcm7xx_timer-test']
+qtests_npcm7xx = \
+ ['npcm7xx_gpio-test',
+ 'npcm7xx_rng-test',
+ 'npcm7xx_timer-test',
+ 'npcm7xx_watchdog_timer-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
--- /dev/null
+/*
+ * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+#define NR_GPIO_DEVICES (8)
+#define GPIO(x) (0xf0010000 + (x) * 0x1000)
+#define GPIO_IRQ(x) (116 + (x))
+
+/* GPIO registers */
+#define GP_N_TLOCK1 0x00
+#define GP_N_DIN 0x04 /* Data IN */
+#define GP_N_POL 0x08 /* Polarity */
+#define GP_N_DOUT 0x0c /* Data OUT */
+#define GP_N_OE 0x10 /* Output Enable */
+#define GP_N_OTYP 0x14
+#define GP_N_MP 0x18
+#define GP_N_PU 0x1c /* Pull-up */
+#define GP_N_PD 0x20 /* Pull-down */
+#define GP_N_DBNC 0x24 /* Debounce */
+#define GP_N_EVTYP 0x28 /* Event Type */
+#define GP_N_EVBE 0x2c /* Event Both Edge */
+#define GP_N_OBL0 0x30
+#define GP_N_OBL1 0x34
+#define GP_N_OBL2 0x38
+#define GP_N_OBL3 0x3c
+#define GP_N_EVEN 0x40 /* Event Enable */
+#define GP_N_EVENS 0x44 /* Event Set (enable) */
+#define GP_N_EVENC 0x48 /* Event Clear (disable) */
+#define GP_N_EVST 0x4c /* Event Status */
+#define GP_N_SPLCK 0x50
+#define GP_N_MPLCK 0x54
+#define GP_N_IEM 0x58 /* Input Enable */
+#define GP_N_OSRC 0x5c
+#define GP_N_ODSC 0x60
+#define GP_N_DOS 0x68 /* Data OUT Set */
+#define GP_N_DOC 0x6c /* Data OUT Clear */
+#define GP_N_OES 0x70 /* Output Enable Set */
+#define GP_N_OEC 0x74 /* Output Enable Clear */
+#define GP_N_TLOCK2 0x7c
+
+static void gpio_unlock(int n)
+{
+ if (readl(GPIO(n) + GP_N_TLOCK1) != 0) {
+ writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248);
+ writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73);
+ }
+}
+
+/* Restore the GPIO controller to a sensible default state. */
+static void gpio_reset(int n)
+{
+ gpio_unlock(0);
+
+ writel(GPIO(n) + GP_N_EVEN, 0x00000000);
+ writel(GPIO(n) + GP_N_EVST, 0xffffffff);
+ writel(GPIO(n) + GP_N_POL, 0x00000000);
+ writel(GPIO(n) + GP_N_DOUT, 0x00000000);
+ writel(GPIO(n) + GP_N_OE, 0x00000000);
+ writel(GPIO(n) + GP_N_OTYP, 0x00000000);
+ writel(GPIO(n) + GP_N_PU, 0xffffffff);
+ writel(GPIO(n) + GP_N_PD, 0x00000000);
+ writel(GPIO(n) + GP_N_IEM, 0xffffffff);
+}
+
+static void test_dout_to_din(void)
+{
+ gpio_reset(0);
+
+ /* When output is enabled, DOUT should be reflected on DIN. */
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ /* PU and PD shouldn't have any impact on DIN. */
+ writel(GPIO(0) + GP_N_PU, 0xffff0000);
+ writel(GPIO(0) + GP_N_PD, 0x0000ffff);
+ writel(GPIO(0) + GP_N_DOUT, 0x12345678);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678);
+}
+
+static void test_pullup_pulldown(void)
+{
+ gpio_reset(0);
+
+ /*
+ * When output is disabled, and PD is the inverse of PU, PU should be
+ * reflected on DIN. If PD is not the inverse of PU, the state of DIN is
+ * undefined, so we don't test that.
+ */
+ writel(GPIO(0) + GP_N_OE, 0x00000000);
+ /* DOUT shouldn't have any impact on DIN. */
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
+ writel(GPIO(0) + GP_N_PU, 0x23456789);
+ writel(GPIO(0) + GP_N_PD, ~0x23456789U);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789);
+}
+
+static void test_output_enable(void)
+{
+ gpio_reset(0);
+
+ /*
+ * With all pins weakly pulled down, and DOUT all-ones, OE should be
+ * reflected on DIN.
+ */
+ writel(GPIO(0) + GP_N_DOUT, 0xffffffff);
+ writel(GPIO(0) + GP_N_PU, 0x00000000);
+ writel(GPIO(0) + GP_N_PD, 0xffffffff);
+ writel(GPIO(0) + GP_N_OE, 0x3456789a);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a);
+
+ writel(GPIO(0) + GP_N_OEC, 0x00030002);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898);
+
+ writel(GPIO(0) + GP_N_OES, 0x0000f001);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3454f899);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3454f899);
+}
+
+static void test_open_drain(void)
+{
+ gpio_reset(0);
+
+ /*
+ * Upper half of DOUT drives a 1 only if the corresponding bit in OTYP is
+ * not set. If OTYP is set, DIN is determined by PU/PD. Lower half of
+ * DOUT always drives a 0 regardless of OTYP; PU/PD have no effect. When
+ * OE is 0, output is determined by PU/PD; OTYP has no effect.
+ */
+ writel(GPIO(0) + GP_N_OTYP, 0x456789ab);
+ writel(GPIO(0) + GP_N_OE, 0xf0f0f0f0);
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
+ writel(GPIO(0) + GP_N_PU, 0xff00ff00);
+ writel(GPIO(0) + GP_N_PD, 0x00ff00ff);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_OTYP), ==, 0x456789ab);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff900f00);
+}
+
+static void test_polarity(void)
+{
+ gpio_reset(0);
+
+ /*
+ * In push-pull mode, DIN should reflect DOUT because the signal is
+ * inverted in both directions.
+ */
+ writel(GPIO(0) + GP_N_OTYP, 0x00000000);
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_DOUT, 0x56789abc);
+ writel(GPIO(0) + GP_N_POL, 0x6789abcd);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_POL), ==, 0x6789abcd);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x56789abc);
+
+ /*
+ * When turning off the drivers, DIN should reflect the inverse of the
+ * pulled-up lines.
+ */
+ writel(GPIO(0) + GP_N_OE, 0x00000000);
+ writel(GPIO(0) + GP_N_POL, 0xffffffff);
+ writel(GPIO(0) + GP_N_PU, 0x789abcde);
+ writel(GPIO(0) + GP_N_PD, ~0x789abcdeU);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, ~0x789abcdeU);
+
+ /*
+ * In open-drain mode, DOUT=1 will appear to drive the pin high (since DIN
+ * is inverted), while DOUT=0 will leave the pin floating.
+ */
+ writel(GPIO(0) + GP_N_OTYP, 0xffffffff);
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_PU, 0xffff0000);
+ writel(GPIO(0) + GP_N_PD, 0x0000ffff);
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff00ffff);
+}
+
+static void test_input_mask(void)
+{
+ gpio_reset(0);
+
+ /* IEM=0 forces the input to zero before polarity inversion. */
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
+ writel(GPIO(0) + GP_N_POL, 0xffff0000);
+ writel(GPIO(0) + GP_N_IEM, 0x87654321);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0xff9a4300);
+}
+
+static void test_temp_lock(void)
+{
+ gpio_reset(0);
+
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
+
+ /* Make sure we're unlocked initially. */
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
+ /* Writing any value to TLOCK1 will lock. */
+ writel(GPIO(0) + GP_N_TLOCK1, 0);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
+ writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
+ /* Now, try to unlock. */
+ gpio_unlock(0);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
+ writel(GPIO(0) + GP_N_DOUT, 0xa9876543);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
+
+ /* Try it again, but write TLOCK2 to lock. */
+ writel(GPIO(0) + GP_N_TLOCK2, 0);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 1);
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0xa9876543);
+ /* Now, try to unlock. */
+ gpio_unlock(0);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_TLOCK1), ==, 0);
+ writel(GPIO(0) + GP_N_DOUT, 0x98765432);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x98765432);
+}
+
+static void test_events_level(void)
+{
+ gpio_reset(0);
+
+ writel(GPIO(0) + GP_N_EVTYP, 0x00000000);
+ writel(GPIO(0) + GP_N_DOUT, 0xba987654);
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
+
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_DOUT, 0x00000000);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba987654);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0x00007654);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0xba980000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0xba980000);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+}
+
+static void test_events_rising_edge(void)
+{
+ gpio_reset(0);
+
+ writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
+ writel(GPIO(0) + GP_N_EVBE, 0x00000000);
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
+
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x0000ff00);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_DOUT, 0x00ff0000);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0x0000f000);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ff0f00);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0x00ff0f00);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+}
+
+static void test_events_both_edges(void)
+{
+ gpio_reset(0);
+
+ writel(GPIO(0) + GP_N_EVTYP, 0xffffffff);
+ writel(GPIO(0) + GP_N_EVBE, 0xffffffff);
+ writel(GPIO(0) + GP_N_DOUT, 0xffff0000);
+ writel(GPIO(0) + GP_N_OE, 0xffffffff);
+ writel(GPIO(0) + GP_N_EVST, 0xffffffff);
+
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_DOUT, 0xff00ff00);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00ffff00);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_DOUT, 0xef00ff08);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ffff08);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0x0000f000);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x10ff0f08);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+ writel(GPIO(0) + GP_N_EVST, 0x10ff0f08);
+ g_assert_cmphex(readl(GPIO(0) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(0)));
+}
+
+static void test_gpion_irq(gconstpointer test_data)
+{
+ intptr_t n = (intptr_t)test_data;
+
+ gpio_reset(n);
+
+ writel(GPIO(n) + GP_N_EVTYP, 0x00000000);
+ writel(GPIO(n) + GP_N_DOUT, 0x00000000);
+ writel(GPIO(n) + GP_N_OE, 0xffffffff);
+ writel(GPIO(n) + GP_N_EVST, 0xffffffff);
+ writel(GPIO(n) + GP_N_EVEN, 0x00000000);
+
+ /* Trigger an event; interrupts are masked. */
+ g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00000000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+ writel(GPIO(n) + GP_N_DOS, 0x00008000);
+ g_assert_cmphex(readl(GPIO(n) + GP_N_EVST), ==, 0x00008000);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+
+ /* Unmask all event interrupts; verify that the interrupt fired. */
+ writel(GPIO(n) + GP_N_EVEN, 0xffffffff);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+
+ /* Clear the current bit, set a new bit, irq stays asserted. */
+ writel(GPIO(n) + GP_N_DOC, 0x00008000);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+ writel(GPIO(n) + GP_N_DOS, 0x00000200);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+ writel(GPIO(n) + GP_N_EVST, 0x00008000);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+
+ /* Mask/unmask the event that's currently active. */
+ writel(GPIO(n) + GP_N_EVENC, 0x00000200);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+ writel(GPIO(n) + GP_N_EVENS, 0x00000200);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+
+ /* Clear the input and the status bit, irq is deasserted. */
+ writel(GPIO(n) + GP_N_DOC, 0x00000200);
+ g_assert_true(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+ writel(GPIO(n) + GP_N_EVST, 0x00000200);
+ g_assert_false(qtest_get_irq(global_qtest, GPIO_IRQ(n)));
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+ int i;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ qtest_add_func("/npcm7xx_gpio/dout_to_din", test_dout_to_din);
+ qtest_add_func("/npcm7xx_gpio/pullup_pulldown", test_pullup_pulldown);
+ qtest_add_func("/npcm7xx_gpio/output_enable", test_output_enable);
+ qtest_add_func("/npcm7xx_gpio/open_drain", test_open_drain);
+ qtest_add_func("/npcm7xx_gpio/polarity", test_polarity);
+ qtest_add_func("/npcm7xx_gpio/input_mask", test_input_mask);
+ qtest_add_func("/npcm7xx_gpio/temp_lock", test_temp_lock);
+ qtest_add_func("/npcm7xx_gpio/events/level", test_events_level);
+ qtest_add_func("/npcm7xx_gpio/events/rising_edge", test_events_rising_edge);
+ qtest_add_func("/npcm7xx_gpio/events/both_edges", test_events_both_edges);
+
+ for (i = 0; i < NR_GPIO_DEVICES; i++) {
+ g_autofree char *test_name =
+ g_strdup_printf("/npcm7xx_gpio/gpio[%d]/irq", i);
+ qtest_add_data_func(test_name, (void *)(intptr_t)i, test_gpion_irq);
+ }
+
+ qtest_start("-machine npcm750-evb");
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/a9mpcore/gic");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
--- /dev/null
+/*
+ * QTest testcase for the Nuvoton NPCM7xx Random Number Generator
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include <math.h>
+
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+
+#define RNG_BASE_ADDR 0xf000b000
+
+/* Control and Status Register */
+#define RNGCS 0x00
+# define DVALID BIT(1) /* Data Valid */
+# define RNGE BIT(0) /* RNG Enable */
+/* Data Register */
+#define RNGD 0x04
+/* Mode Register */
+#define RNGMODE 0x08
+# define ROSEL_NORMAL (2) /* RNG only works in this mode */
+
+/* Number of bits to collect for randomness tests. */
+#define TEST_INPUT_BITS (128)
+
+static void rng_writeb(unsigned int offset, uint8_t value)
+{
+ writeb(RNG_BASE_ADDR + offset, value);
+}
+
+static uint8_t rng_readb(unsigned int offset)
+{
+ return readb(RNG_BASE_ADDR + offset);
+}
+
+/* Disable RNG and set normal ring oscillator mode. */
+static void rng_reset(void)
+{
+ rng_writeb(RNGCS, 0);
+ rng_writeb(RNGMODE, ROSEL_NORMAL);
+}
+
+/* Reset RNG and then enable it. */
+static void rng_reset_enable(void)
+{
+ rng_reset();
+ rng_writeb(RNGCS, RNGE);
+}
+
+/* Wait until Data Valid bit is set. */
+static bool rng_wait_ready(void)
+{
+ /* qemu_guest_getrandom may fail. Assume it won't fail 10 times in a row. */
+ int retries = 10;
+
+ while (retries-- > 0) {
+ if (rng_readb(RNGCS) & DVALID) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/*
+ * Perform a frequency (monobit) test, as defined by NIST SP 800-22, on the
+ * sequence in buf and return the P-value. This represents the probability of a
+ * truly random sequence having the same proportion of zeros and ones as the
+ * sequence in buf.
+ *
+ * An RNG which always returns 0x00 or 0xff, or has some bits stuck at 0 or 1,
+ * will fail this test. However, an RNG which always returns 0x55, 0xf0 or some
+ * other value with an equal number of zeroes and ones will pass.
+ */
+static double calc_monobit_p(const uint8_t *buf, unsigned int len)
+{
+ unsigned int i;
+ double s_obs;
+ int sn = 0;
+
+ for (i = 0; i < len; i++) {
+ /*
+ * Each 1 counts as 1, each 0 counts as -1.
+ * s = cp - (8 - cp) = 2 * cp - 8
+ */
+ sn += 2 * ctpop8(buf[i]) - 8;
+ }
+
+ s_obs = abs(sn) / sqrt(len * BITS_PER_BYTE);
+
+ return erfc(s_obs / sqrt(2));
+}
+
+/*
+ * Perform a runs test, as defined by NIST SP 800-22, and return the P-value.
+ * This represents the probability of a truly random sequence having the same
+ * number of runs (i.e. uninterrupted sequences of identical bits) as the
+ * sequence in buf.
+ */
+static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
+{
+ unsigned int j;
+ unsigned int k;
+ int nr_ones = 0;
+ int vn_obs = 0;
+ double pi;
+
+ g_assert(nr_bits % BITS_PER_LONG == 0);
+
+ for (j = 0; j < nr_bits / BITS_PER_LONG; j++) {
+ nr_ones += __builtin_popcountl(buf[j]);
+ }
+ pi = (double)nr_ones / nr_bits;
+
+ for (k = 0; k < nr_bits - 1; k++) {
+ vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
+ }
+ vn_obs += 1;
+
+ return erfc(fabs(vn_obs - 2 * nr_bits * pi * (1.0 - pi))
+ / (2 * sqrt(2 * nr_bits) * pi * (1.0 - pi)));
+}
+
+/*
+ * Verifies that DVALID is clear, and RNGD reads zero, when RNGE is cleared,
+ * and DVALID eventually becomes set when RNGE is set.
+ */
+static void test_enable_disable(void)
+{
+ /* Disable: DVALID should not be set, and RNGD should read zero */
+ rng_reset();
+ g_assert_cmphex(rng_readb(RNGCS), ==, 0);
+ g_assert_cmphex(rng_readb(RNGD), ==, 0);
+
+ /* Enable: DVALID should be set, but we can't make assumptions about RNGD */
+ rng_writeb(RNGCS, RNGE);
+ g_assert_true(rng_wait_ready());
+ g_assert_cmphex(rng_readb(RNGCS), ==, DVALID | RNGE);
+
+ /* Disable: DVALID should not be set, and RNGD should read zero */
+ rng_writeb(RNGCS, 0);
+ g_assert_cmphex(rng_readb(RNGCS), ==, 0);
+ g_assert_cmphex(rng_readb(RNGD), ==, 0);
+}
+
+/*
+ * Verifies that the RNG only produces data when RNGMODE is set to 'normal'
+ * ring oscillator mode.
+ */
+static void test_rosel(void)
+{
+ rng_reset_enable();
+ g_assert_true(rng_wait_ready());
+ rng_writeb(RNGMODE, 0);
+ g_assert_false(rng_wait_ready());
+ rng_writeb(RNGMODE, ROSEL_NORMAL);
+ g_assert_true(rng_wait_ready());
+ rng_writeb(RNGMODE, 0);
+ g_assert_false(rng_wait_ready());
+}
+
+/*
+ * Verifies that a continuous sequence of bits collected after enabling the RNG
+ * satisfies a monobit test.
+ */
+static void test_continuous_monobit(void)
+{
+ uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
+ unsigned int i;
+
+ rng_reset_enable();
+ for (i = 0; i < sizeof(buf); i++) {
+ g_assert_true(rng_wait_ready());
+ buf[i] = rng_readb(RNGD);
+ }
+
+ g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
+}
+
+/*
+ * Verifies that a continuous sequence of bits collected after enabling the RNG
+ * satisfies a runs test.
+ */
+static void test_continuous_runs(void)
+{
+ union {
+ unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
+ uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
+ } buf;
+ unsigned int i;
+
+ rng_reset_enable();
+ for (i = 0; i < sizeof(buf); i++) {
+ g_assert_true(rng_wait_ready());
+ buf.c[i] = rng_readb(RNGD);
+ }
+
+ g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
+}
+
+/*
+ * Verifies that the first data byte collected after enabling the RNG satisfies
+ * a monobit test.
+ */
+static void test_first_byte_monobit(void)
+{
+ /* Enable, collect one byte, disable. Repeat until we have 100 bits. */
+ uint8_t buf[TEST_INPUT_BITS / BITS_PER_BYTE];
+ unsigned int i;
+
+ rng_reset();
+ for (i = 0; i < sizeof(buf); i++) {
+ rng_writeb(RNGCS, RNGE);
+ g_assert_true(rng_wait_ready());
+ buf[i] = rng_readb(RNGD);
+ rng_writeb(RNGCS, 0);
+ }
+
+ g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
+}
+
+/*
+ * Verifies that the first data byte collected after enabling the RNG satisfies
+ * a runs test.
+ */
+static void test_first_byte_runs(void)
+{
+ /* Enable, collect one byte, disable. Repeat until we have 100 bits. */
+ union {
+ unsigned long l[TEST_INPUT_BITS / BITS_PER_LONG];
+ uint8_t c[TEST_INPUT_BITS / BITS_PER_BYTE];
+ } buf;
+ unsigned int i;
+
+ rng_reset();
+ for (i = 0; i < sizeof(buf); i++) {
+ rng_writeb(RNGCS, RNGE);
+ g_assert_true(rng_wait_ready());
+ buf.c[i] = rng_readb(RNGD);
+ rng_writeb(RNGCS, 0);
+ }
+
+ g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
+ qtest_add_func("npcm7xx_rng/rosel", test_rosel);
+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
+
+ qtest_start("-machine npcm750-evb");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
--- /dev/null
+/*
+ * QTests for Nuvoton NPCM7xx Timer Watchdog Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/timer.h"
+
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+
+#define WTCR_OFFSET 0x1c
+#define REF_HZ (25000000)
+
+/* WTCR bit fields */
+#define WTCLK(rv) ((rv) << 10)
+#define WTE BIT(7)
+#define WTIE BIT(6)
+#define WTIS(rv) ((rv) << 4)
+#define WTIF BIT(3)
+#define WTRF BIT(2)
+#define WTRE BIT(1)
+#define WTR BIT(0)
+
+typedef struct Watchdog {
+ int irq;
+ uint64_t base_addr;
+} Watchdog;
+
+static const Watchdog watchdog_list[] = {
+ {
+ .irq = 47,
+ .base_addr = 0xf0008000
+ },
+ {
+ .irq = 48,
+ .base_addr = 0xf0009000
+ },
+ {
+ .irq = 49,
+ .base_addr = 0xf000a000
+ }
+};
+
+static int watchdog_index(const Watchdog *wd)
+{
+ ptrdiff_t diff = wd - watchdog_list;
+
+ g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list));
+
+ return diff;
+}
+
+static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd)
+{
+ return qtest_readl(qts, wd->base_addr + WTCR_OFFSET);
+}
+
+static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd,
+ uint32_t value)
+{
+ qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value);
+}
+
+static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd)
+{
+ switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) {
+ case 0:
+ return 1;
+ case 1:
+ return 256;
+ case 2:
+ return 2048;
+ case 3:
+ return 65536;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static QDict *get_watchdog_action(QTestState *qts)
+{
+ QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG");
+ QDict *data;
+
+ data = qdict_get_qdict(ev, "data");
+ qobject_ref(data);
+ qobject_unref(ev);
+ return data;
+}
+
+#define RESET_CYCLES 1024
+static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd)
+{
+ uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2);
+ return 1 << (14 + 2 * wtis);
+}
+
+static int64_t watchdog_calculate_steps(uint32_t count, uint32_t prescale)
+{
+ return (NANOSECONDS_PER_SECOND / REF_HZ) * count * prescale;
+}
+
+static int64_t watchdog_interrupt_steps(QTestState *qts, const Watchdog *wd)
+{
+ return watchdog_calculate_steps(watchdog_interrupt_cycles(qts, wd),
+ watchdog_prescaler(qts, wd));
+}
+
+/* Check wtcr can be reset to default value */
+static void test_init(gconstpointer watchdog)
+{
+ const Watchdog *wd = watchdog;
+ QTestState *qts = qtest_init("-machine quanta-gsj");
+
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+ watchdog_write_wtcr(qts, wd, WTCLK(1) | WTRF | WTIF | WTR);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1));
+
+ qtest_quit(qts);
+}
+
+/* Check a watchdog can generate interrupt and reset actions */
+static void test_reset_action(gconstpointer watchdog)
+{
+ const Watchdog *wd = watchdog;
+ QTestState *qts = qtest_init("-machine quanta-gsj");
+ QDict *ad;
+
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+ watchdog_write_wtcr(qts, wd,
+ WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
+ WTCLK(0) | WTE | WTRE | WTIE);
+
+ /* Check a watchdog can generate an interrupt */
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
+ WTCLK(0) | WTE | WTIF | WTIE | WTRE);
+ g_assert_true(qtest_get_irq(qts, wd->irq));
+
+ /* Check a watchdog can generate a reset signal */
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
+ watchdog_prescaler(qts, wd)));
+ ad = get_watchdog_action(qts);
+ /* The signal is a reset signal */
+ g_assert_false(strcmp(qdict_get_str(ad, "action"), "reset"));
+ qobject_unref(ad);
+ qtest_qmp_eventwait(qts, "RESET");
+ /*
+ * Make sure WTCR is reset to default except for WTRF bit which shouldn't
+ * be reset.
+ */
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1) | WTRF);
+ qtest_quit(qts);
+}
+
+/* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
+static void test_prescaler(gconstpointer watchdog)
+{
+ const Watchdog *wd = watchdog;
+
+ for (int wtclk = 0; wtclk < 4; ++wtclk) {
+ for (int wtis = 0; wtis < 4; ++wtis) {
+ QTestState *qts = qtest_init("-machine quanta-gsj");
+
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+ watchdog_write_wtcr(qts, wd,
+ WTCLK(wtclk) | WTE | WTIF | WTIS(wtis) | WTIE | WTR);
+ /*
+ * The interrupt doesn't fire until watchdog_interrupt_steps()
+ * cycles passed
+ */
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd) - 1);
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_false(qtest_get_irq(qts, wd->irq));
+ qtest_clock_step(qts, 1);
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_true(qtest_get_irq(qts, wd->irq));
+
+ qtest_quit(qts);
+ }
+ }
+}
+
+/*
+ * Check a watchdog doesn't fire if corresponding flags (WTIE and WTRE) are not
+ * set.
+ */
+static void test_enabling_flags(gconstpointer watchdog)
+{
+ const Watchdog *wd = watchdog;
+ QTestState *qts;
+
+ /* Neither WTIE or WTRE is set, no interrupt or reset should happen */
+ qts = qtest_init("-machine quanta-gsj");
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRF | WTR);
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_false(qtest_get_irq(qts, wd->irq));
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
+ watchdog_prescaler(qts, wd)));
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
+ qtest_quit(qts);
+
+ /* Only WTIE is set, interrupt is triggered but reset should not happen */
+ qts = qtest_init("-machine quanta-gsj");
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_true(qtest_get_irq(qts, wd->irq));
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
+ watchdog_prescaler(qts, wd)));
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
+ qtest_quit(qts);
+
+ /* Only WTRE is set, interrupt is triggered but reset should not happen */
+ qts = qtest_init("-machine quanta-gsj");
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRE | WTRF | WTR);
+ qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
+ g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
+ g_assert_false(qtest_get_irq(qts, wd->irq));
+ qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
+ watchdog_prescaler(qts, wd)));
+ g_assert_false(strcmp(qdict_get_str(get_watchdog_action(qts), "action"),
+ "reset"));
+ qtest_qmp_eventwait(qts, "RESET");
+ qtest_quit(qts);
+
+ /*
+ * The case when both flags are set is already tested in
+ * test_reset_action().
+ */
+}
+
+/* Check a watchdog can pause and resume by setting WTE bits */
+static void test_pause(gconstpointer watchdog)
+{
+ const Watchdog *wd = watchdog;
+ QTestState *qts;
+ int64_t remaining_steps, steps;
+
+ qts = qtest_init("-machine quanta-gsj");
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
+ remaining_steps = watchdog_interrupt_steps(qts, wd);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
+
+ /* Run for half of the execution period. */
+ steps = remaining_steps / 2;
+ remaining_steps -= steps;
+ qtest_clock_step(qts, steps);
+
+ /* Pause the watchdog */
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTIE);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
+
+ /* Run for a long period of time, the watchdog shouldn't fire */
+ qtest_clock_step(qts, steps << 4);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
+ g_assert_false(qtest_get_irq(qts, wd->irq));
+
+ /* Resume the watchdog */
+ watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIE);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
+
+ /* Run for the reset of the execution period, the watchdog should fire */
+ qtest_clock_step(qts, remaining_steps);
+ g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
+ WTCLK(0) | WTE | WTIF | WTIE);
+ g_assert_true(qtest_get_irq(qts, wd->irq));
+
+ qtest_quit(qts);
+}
+
+static void watchdog_add_test(const char *name, const Watchdog* wd,
+ GTestDataFunc fn)
+{
+ g_autofree char *full_name = g_strdup_printf(
+ "npcm7xx_watchdog_timer[%d]/%s", watchdog_index(wd), name);
+ qtest_add_data_func(full_name, wd, fn);
+}
+#define add_test(name, td) watchdog_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ for (int i = 0; i < ARRAY_SIZE(watchdog_list); ++i) {
+ const Watchdog *wd = &watchdog_list[i];
+
+ add_test(init, wd);
+ add_test(reset_action, wd);
+ add_test(prescaler, wd);
+ add_test(enabling_flags, wd);
+ add_test(pause, wd);
+ }
+
+ return g_test_run();
+}
run-plugin-pauth-%: QEMU_OPTS += -cpu max
endif
+# BTI Tests
+# bti-1 tests the elf notes, so we require special compiler support.
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_BTI),)
+AARCH64_TESTS += bti-1
+bti-1: CFLAGS += -mbranch-protection=standard
+bti-1: LDFLAGS += -nostdlib
+endif
+# bti-2 tests PROT_BTI, so no special compiler support required.
+AARCH64_TESTS += bti-2
+
# Semihosting smoke test for linux-user
AARCH64_TESTS += semihosting
run-semihosting: semihosting
--- /dev/null
+/*
+ * Branch target identification, basic notskip cases.
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+ uc->uc_mcontext.pc += 8;
+ uc->uc_mcontext.pstate = 1;
+}
+
+#define NOP "nop"
+#define BTI_N "hint #32"
+#define BTI_C "hint #34"
+#define BTI_J "hint #36"
+#define BTI_JC "hint #38"
+
+#define BTYPE_1(DEST) \
+ asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x16")
+
+#define BTYPE_2(DEST) \
+ asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3(DEST) \
+ asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
+ : "=r"(skipped) : : "x15")
+
+#define TEST(WHICH, DEST, EXPECT) \
+ do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0)
+
+
+int main()
+{
+ int fail = 0;
+ int skipped;
+
+ /* Signal-like with SA_SIGINFO. */
+ signal_info(SIGILL, skip2_sigill);
+
+ TEST(BTYPE_1, NOP, 1);
+ TEST(BTYPE_1, BTI_N, 1);
+ TEST(BTYPE_1, BTI_C, 0);
+ TEST(BTYPE_1, BTI_J, 0);
+ TEST(BTYPE_1, BTI_JC, 0);
+
+ TEST(BTYPE_2, NOP, 1);
+ TEST(BTYPE_2, BTI_N, 1);
+ TEST(BTYPE_2, BTI_C, 0);
+ TEST(BTYPE_2, BTI_J, 1);
+ TEST(BTYPE_2, BTI_JC, 0);
+
+ TEST(BTYPE_3, NOP, 1);
+ TEST(BTYPE_3, BTI_N, 1);
+ TEST(BTYPE_3, BTI_C, 1);
+ TEST(BTYPE_3, BTI_J, 0);
+ TEST(BTYPE_3, BTI_JC, 0);
+
+ return fail;
+}
--- /dev/null
+/*
+ * Branch target identification, basic notskip cases.
+ */
+
+#include <stdio.h>
+#include <signal.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/mman.h>
+
+#ifndef PROT_BTI
+#define PROT_BTI 0x10
+#endif
+
+static void skip2_sigill(int sig, siginfo_t *info, void *vuc)
+{
+ ucontext_t *uc = vuc;
+ uc->uc_mcontext.pc += 8;
+ uc->uc_mcontext.pstate = 1;
+}
+
+#define NOP "nop"
+#define BTI_N "hint #32"
+#define BTI_C "hint #34"
+#define BTI_J "hint #36"
+#define BTI_JC "hint #38"
+
+#define BTYPE_1(DEST) \
+ "mov x1, #1\n\t" \
+ "adr x16, 1f\n\t" \
+ "br x16\n" \
+"1: " DEST "\n\t" \
+ "mov x1, #0"
+
+#define BTYPE_2(DEST) \
+ "mov x1, #1\n\t" \
+ "adr x16, 1f\n\t" \
+ "blr x16\n" \
+"1: " DEST "\n\t" \
+ "mov x1, #0"
+
+#define BTYPE_3(DEST) \
+ "mov x1, #1\n\t" \
+ "adr x15, 1f\n\t" \
+ "br x15\n" \
+"1: " DEST "\n\t" \
+ "mov x1, #0"
+
+#define TEST(WHICH, DEST, EXPECT) \
+ WHICH(DEST) "\n" \
+ ".if " #EXPECT "\n\t" \
+ "eor x1, x1," #EXPECT "\n" \
+ ".endif\n\t" \
+ "add x0, x0, x1\n\t"
+
+asm("\n"
+"test_begin:\n\t"
+ BTI_C "\n\t"
+ "mov x2, x30\n\t"
+ "mov x0, #0\n\t"
+
+ TEST(BTYPE_1, NOP, 1)
+ TEST(BTYPE_1, BTI_N, 1)
+ TEST(BTYPE_1, BTI_C, 0)
+ TEST(BTYPE_1, BTI_J, 0)
+ TEST(BTYPE_1, BTI_JC, 0)
+
+ TEST(BTYPE_2, NOP, 1)
+ TEST(BTYPE_2, BTI_N, 1)
+ TEST(BTYPE_2, BTI_C, 0)
+ TEST(BTYPE_2, BTI_J, 1)
+ TEST(BTYPE_2, BTI_JC, 0)
+
+ TEST(BTYPE_3, NOP, 1)
+ TEST(BTYPE_3, BTI_N, 1)
+ TEST(BTYPE_3, BTI_C, 1)
+ TEST(BTYPE_3, BTI_J, 0)
+ TEST(BTYPE_3, BTI_JC, 0)
+
+ "ret x2\n"
+"test_end:"
+);
+
+int main()
+{
+ struct sigaction sa;
+ void *tb, *te;
+
+ void *p = mmap(0, getpagesize(),
+ PROT_EXEC | PROT_READ | PROT_WRITE | PROT_BTI,
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (p == MAP_FAILED) {
+ perror("mmap");
+ return 1;
+ }
+
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = skip2_sigill;
+ sa.sa_flags = SA_SIGINFO;
+ if (sigaction(SIGILL, &sa, NULL) < 0) {
+ perror("sigaction");
+ return 1;
+ }
+
+ /*
+ * ??? With "extern char test_begin[]", some compiler versions
+ * will use :got references, and some linker versions will
+ * resolve this reference to a static symbol incorrectly.
+ * Bypass this error by using a pc-relative reference directly.
+ */
+ asm("adr %0, test_begin; adr %1, test_end" : "=r"(tb), "=r"(te));
+
+ memcpy(p, tb, te - tb);
+
+ return ((int (*)(void))p)();
+}
--- /dev/null
+/*
+ * Minimal user-environment for testing BTI.
+ *
+ * Normal libc is not (yet) built with BTI support enabled,
+ * and so could generate a BTI TRAP before ever reaching main.
+ */
+
+#include <stdlib.h>
+#include <signal.h>
+#include <ucontext.h>
+#include <asm/unistd.h>
+
+int main(void);
+
+void _start(void)
+{
+ exit(main());
+}
+
+void exit(int ret)
+{
+ register int x0 __asm__("x0") = ret;
+ register int x8 __asm__("x8") = __NR_exit;
+
+ asm volatile("svc #0" : : "r"(x0), "r"(x8));
+ __builtin_unreachable();
+}
+
+/*
+ * Irritatingly, the user API struct sigaction does not match the
+ * kernel API struct sigaction. So for simplicity, isolate the
+ * kernel ABI here, and make this act like signal.
+ */
+void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *))
+{
+ struct kernel_sigaction {
+ void (*handler)(int, siginfo_t *, ucontext_t *);
+ unsigned long flags;
+ unsigned long restorer;
+ unsigned long mask;
+ } sa = { fn, SA_SIGINFO, 0, 0 };
+
+ register int x0 __asm__("x0") = sig;
+ register void *x1 __asm__("x1") = &sa;
+ register void *x2 __asm__("x2") = 0;
+ register int x3 __asm__("x3") = sizeof(unsigned long);
+ register int x8 __asm__("x8") = __NR_rt_sigaction;
+
+ asm volatile("svc #0"
+ : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory");
+}
-march=armv8.3-a -o $TMPE $TMPC; then
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
fi
+ if do_compiler "$target_compiler" $target_compiler_cflags \
+ -mbranch-protection=standard -o $TMPE $TMPC; then
+ echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
+ fi
;;
esac
g_assert_cmpint(bs_b->quiesce_counter, ==, 0);
g_assert_cmpint(b_s->drain_count, ==, 0);
+ g_assert_cmpint(qemu_get_aio_context()->external_disable_cnt, ==, 0);
bdrv_unref(bs_b);
blk_unref(blk_b);
projects / mirror_qemu.git / commitdiff