Second RISC-V PR for 8.2
* Add support for the max CPU
* Detect user choice in TCG
* Clear CSR values at reset and sync MPSTATE with host
* Fix the typo of inverted order of pmpaddr13 and pmpaddr14
* Split TCG/KVM accelerators from cpu.c
* Add extension properties for all cpus
* Replace GDB exit calls with proper shutdown
* Support KVM_GET_REG_LIST
* Remove RVG warning
* Use env_archcpu for better performance
* Deprecate capital 'Z' CPU properties
* Fix vfwmaccbf16.vf
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# =SUon
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 12 Oct 2023 00:09:36 EDT
# gpg: using RSA key
6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-
20231012-1' of https://github.com/alistair23/qemu: (54 commits)
target/riscv: Fix vfwmaccbf16.vf
target/riscv: deprecate capital 'Z' CPU properties
target/riscv: Use env_archcpu for better performance
target/riscv/tcg: remove RVG warning
target/riscv/kvm: support KVM_GET_REG_LIST
target/riscv/kvm: improve 'init_multiext_cfg' error msg
gdbstub: replace exit calls with proper shutdown for softmmu
hw/char: riscv_htif: replace exit calls with proper shutdown
hw/misc/sifive_test.c: replace exit calls with proper shutdown
softmmu: pass the main loop status to gdb "Wxx" packet
softmmu: add means to pass an exit code when requesting a shutdown
target/riscv/tcg-cpu.c: add extension properties for all cpus
target/riscv: add riscv_cpu_get_name()
target/riscv/cpu: move priv spec functions to tcg-cpu.c
target/riscv/cpu.c: export isa_edata_arr[]
target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c
target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
target/riscv/tcg: introduce tcg_cpu_instance_init()
target/riscv/cpu.c: export set_misa()
target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: configs/targets/riscv*
+F: docs/system/target-riscv.rst
F: target/riscv/
F: hw/riscv/
+F: hw/intc/riscv*
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
S: Supported
F: target/riscv/insn_trans/trans_xthead.c.inc
F: target/riscv/xthead*.decode
+F: disas/riscv-xthead*
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+F: disas/riscv-xventana*
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
M: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: linux-headers/
+F: include/standard-headers/
F: scripts/update-linux-headers.sh
POSIX
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/sbsa-ref.c
+F: hw/misc/sbsa_ec.c
+F: hw/watchdog/sbsa_gwdt.c
+F: include/hw/watchdog/sbsa_gwdt.h
F: docs/system/arm/sbsa.rst
F: tests/avocado/machine_aarch64_sbsaref.py
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/mips/jazz.c
+F: hw/display/g364fb.c
F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
+F: hw/nvram/ds1225y.c
Malta
M: Philippe Mathieu-Daudé <philmd@linaro.org>
M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/microchip-icicle-kit.rst
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/shakti-c.rst
F: hw/riscv/shakti_c.c
F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
M: Palmer Dabbelt <palmer@dabbelt.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
R: Paolo Bonzini <pbonzini@redhat.com>
S: Odd Fixes
F: hw/char/
+F: include/hw/char/
Network devices
M: Jason Wang <jasowang@redhat.com>
S: Maintained
F: contrib/elf2dmp/
+Overall sensors
+M: Philippe Mathieu-Daudé <philmd@linaro.org>
+S: Odd Fixes
+F: hw/sensor
+F: include/hw/sensor
+
I2C and SMBus
M: Corey Minyard <cminyard@mvista.com>
S: Maintained
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv/
-F: disas/riscv.c
+F: disas/riscv.[ch]
S390 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
F: .gitlab-ci.yml
F: .gitlab-ci.d/
F: .travis.yml
+F: docs/devel/ci*
F: scripts/ci/
F: tests/docker/
F: tests/vm/
----------
`AMD Memory Encryption whitepaper
-<https://developer.amd.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf>`_
+<https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/memory-encryption-white-paper.pdf>`_
.. [SEVAPI] `Secure Encrypted Virtualization API
<https://www.amd.com/system/files/TechDocs/55766_SEV-KM_API_Specification.pdf>`_
.. [APMVOL2] `AMD64 Architecture Programmer's Manual Volume 2: System Programming
- <https://www.amd.com/system/files/TechDocs/24593.pdf>`_
+ <https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
KVM Forum slides:
<https://www.linux-kvm.org/images/9/94/Extending-Secure-Encrypted-Virtualization-with-SEV-ES-Thomas-Lendacky-AMD.pdf>`_
`AMD64 Architecture Programmer's Manual:
-<http://support.amd.com/TechDocs/24593.pdf>`_
+<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf>`_
* SME is section 7.10
* SEV is section 15.34
void cpu_synchronize_all_post_init(void);
void cpu_synchronize_all_pre_loadvm(void);
-#ifndef CONFIG_USER_ONLY
-/* vl.c */
-/* *-user doesn't have configurable SMP topology */
-extern int smp_cores;
-extern int smp_threads;
-#endif
-
#endif
return win2qemu[(int)bus];
}
-DEFINE_GUID(GUID_DEVINTERFACE_DISK,
- 0x53f56307L, 0xb6bf, 0x11d0, 0x94, 0xf2,
- 0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
-DEFINE_GUID(GUID_DEVINTERFACE_STORAGEPORT,
- 0x2accfe60L, 0xc130, 0x11d2, 0xb0, 0x82,
- 0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
-
static void get_pci_address_for_device(GuestPCIAddress *pci,
HDEVINFO dev_info)
{
#endif
if (gei->out.length > 0) {
ges->out_data = g_base64_encode(gei->out.data, gei->out.length);
- g_free(gei->out.data);
ges->has_out_truncated = gei->out.truncated;
}
+ g_free(gei->out.data);
if (gei->err.length > 0) {
ges->err_data = g_base64_encode(gei->err.data, gei->err.length);
- g_free(gei->err.data);
ges->has_err_truncated = gei->err.truncated;
}
+ g_free(gei->err.data);
QTAILQ_REMOVE(&guest_exec_state.processes, gei, next);
g_free(gei);
# @signal: signal number (linux) or unhandled exception code (windows)
# if the process was abnormally terminated.
#
-# @out-data: base64-encoded stdout of the process
+# @out-data: base64-encoded stdout of the process. This field will only
+# be populated after the process exits.
#
-# @err-data: base64-encoded stderr of the process Note: @out-data and
+# @err-data: base64-encoded stderr of the process. Note: @out-data and
# @err-data are present only if 'capture-output' was specified for
-# 'guest-exec'
+# 'guest-exec'. This field will only be populated after the process
+# exits.
#
# @out-truncated: true if stdout was not fully captured due to size
# limitation.
cp skiboot/skiboot.lid ../pc-bios/skiboot.lid
efi:
- python3 edk2-build.py --config edk2-build.config \
+ $(PYTHON) edk2-build.py --config edk2-build.config \
--version-override "edk2-stable202302-for-qemu" \
--release-date "03/01/2023"
rm -f ../pc-bios/edk2-*.fd.bz2
generate_faults(VuDev *dev) {
unsigned int i;
for (i = 0; i < dev->nregions; i++) {
+#ifdef UFFDIO_REGISTER
VuDevRegion *dev_region = &dev->regions[i];
int ret;
-#ifdef UFFDIO_REGISTER
struct uffdio_register reg_struct;
/*
projects / mirror_qemu.git / commitdiff