Merge remote-tracking branch 'stefanha/trivial-patches' into staging

Conflicts:
	cpu-all.h

diff --combined cpu-exec.c
index 6d4372661c0a6df1a7fee78af40b2f2b7c10d9fd,1b20f7b22b284cdf4e0298cfd624ed284caa26a9..7323f3c2604ad4de1580055f472004756e2f9724
--- 1/cpu-exec.c
--- 2/cpu-exec.c
+++ b/cpu-exec.c
@@@ -360,7 -360,10 +360,7 @@@ int cpu_exec(CPUState *env1
                  if (unlikely(interrupt_request)) {
                      if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
                          /* Mask out external interrupts for this step. */
 -                        interrupt_request &= ~(CPU_INTERRUPT_HARD |
 -                                               CPU_INTERRUPT_FIQ |
 -                                               CPU_INTERRUPT_SMI |
 -                                               CPU_INTERRUPT_NMI);
 +                        interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
                      }
                      if (interrupt_request & CPU_INTERRUPT_DEBUG) {
                          env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
@@@ -489,6 -492,9 +489,6 @@@
                                  next_tb = 0;
                              }
                          }
 -                  } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 -                      //do_interrupt(0, 0, 0, 0, 0);
 -                      env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
                    }
  #elif defined(TARGET_ARM)
                      if (interrupt_request & CPU_INTERRUPT_FIQ
@@@ -503,7 -509,7 +503,7 @@@
                         jump normally, then does the exception return when the
                         CPU tries to execute code at the magic address.
                         This will cause the magic PC value to be pushed to
-                        the stack if an interrupt occured at the wrong time.
+                        the stack if an interrupt occurred at the wrong time.
                         We avoid this by disabling interrupts when
                         pc contains a magic address.  */
                      if (interrupt_request & CPU_INTERRUPT_HARD
@@@ -563,7 -569,7 +563,7 @@@
                          next_tb = 0;
                      }
  #endif
-                    /* Don't use the cached interupt_request value,
+                    /* Don't use the cached interrupt_request value,
                        do_interrupt may have updated the EXITTB flag. */
                      if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
                          env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;

diff --combined hw/pci.c
index 631d77cccb1be17a01a76788c38212e1effb0f13,20dfa728395edeb2c2a7b6a4a7c93c2d5d3a0dfe..1d297d6c7c96e5cd02ed923267aa0b373aa9fea6
--- 1/hw/pci.c
--- 2/hw/pci.c
+++ b/hw/pci.c
@@@ -168,7 -168,7 +168,7 @@@ void pci_device_reset(PCIDevice *dev
      dev->irq_state = 0;
      pci_update_irq_status(dev);
      pci_device_deassert_intx(dev);
-     /* Clear all writeable bits */
+     /* Clear all writable bits */
      pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
                                   pci_get_word(dev->wmask + PCI_COMMAND) |
                                   pci_get_word(dev->w1cmask + PCI_COMMAND));
@@@ -871,7 -871,7 +871,7 @@@ void pci_register_bar(PCIDevice *pci_de
      wmask = ~(size - 1);
      addr = pci_bar(pci_dev, region_num);
      if (region_num == PCI_ROM_SLOT) {
-         /* ROM enable bit is writeable */
+         /* ROM enable bit is writable */
          wmask |= PCI_ROM_ADDRESS_ENABLE;
      }
      pci_set_long(pci_dev->config + addr, type);
@@@ -1922,8 -1922,6 +1922,8 @@@ static int pci_add_option_rom(PCIDevic
          pci_patch_ids(pdev, ptr, size);
      }
  
 +    qemu_put_ram_ptr(ptr);
 +
      pci_register_bar(pdev, PCI_ROM_SLOT, size,
                       0, pci_map_option_rom);
  
@@@ -1977,7 -1975,7 +1977,7 @@@ void pci_del_capability(PCIDevice *pdev
      if (!offset)
          return;
      pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
-     /* Make capability writeable again */
+     /* Make capability writable again */
      memset(pdev->wmask + offset, 0xff, size);
      memset(pdev->w1cmask + offset, 0, size);
      /* Clear cmask as device-specific registers can't be checked */

diff --combined target-cris/cpu.h
index 8686dbaf2e0f02b287fbbbfc455d9092e08f1e21,4a9032b10de45f338d2a618b82211e1de361563e..2bc35e49754a3d78a2d955aa3b9bc3945b245164
--- 1/target-cris/cpu.h
--- 2/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@@ -36,9 -36,6 +36,9 @@@
  #define EXCP_IRQ        4
  #define EXCP_BREAK      5
  
 +/* CRIS-specific interrupt pending bits.  */
 +#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 +
  /* Register aliases. R0 - R15 */
  #define R_FP  8
  #define R_SP  14
@@@ -104,7 -101,7 +104,7 @@@ typedef struct CPUCRISState 
        /* P0 - P15 are referred to as special registers in the docs.  */
        uint32_t pregs[16];
  
-       /* Pseudo register for the PC. Not directly accessable on CRIS.  */
+       /* Pseudo register for the PC. Not directly accessible on CRIS.  */
        uint32_t pc;
  
        /* Pseudo register for the kernel stack.  */