{ "pcie-root-port", "x-width", "1" },
{ "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
{ "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
+ { "tpm-crb", "ppi", "false" },
+ { "tpm-tis", "ppi", "false" },
};
const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
MemoryRegion cmdmem;
size_t be_buffer_size;
+
+ bool ppi_enabled;
} CRBState;
#define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB)
static Property tpm_crb_properties[] = {
DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe),
+ DEFINE_PROP_BOOL("ppi", CRBState, ppi_enabled, true),
DEFINE_PROP_END_OF_LIST(),
};
TPMVersion be_tpm_version;
size_t be_buffer_size;
+
+ bool ppi_enabled;
} TPMState;
#define TPM(obj) OBJECT_CHECK(TPMState, (obj), TYPE_TPM_TIS)
static Property tpm_tis_properties[] = {
DEFINE_PROP_UINT32("irq", TPMState, irq_num, TPM_TIS_IRQ),
DEFINE_PROP_TPMBE("tpmdev", TPMState, be_driver),
+ DEFINE_PROP_BOOL("ppi", TPMState, ppi_enabled, true),
DEFINE_PROP_END_OF_LIST(),
};