cmdline_size = strlen(info->kernel_cmdline);
address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
- (const uint8_t *)info->kernel_cmdline,
- cmdline_size + 1);
+ info->kernel_cmdline, cmdline_size + 1);
cmdline_size = (cmdline_size >> 2) + 1;
WRITE_WORD(p, cmdline_size + 2);
WRITE_WORD(p, 0x54410009);
}
s = info->kernel_cmdline;
if (s) {
- address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
- (const uint8_t *)s, strlen(s) + 1);
+ address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
} else {
WRITE_WORD(p, 0);
}
if (i < s->dma_tl_limit / sizeof(entry)) {
entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
if (address_space_read(ret.target_as, entry_address,
- MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry,
- sizeof(entry)) == MEMTX_OK) {
+ MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
+ == MEMTX_OK) {
ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
ret.perm = IOMMU_RW;
}
} else {
addr = zdma_get_regaddr64(s, basereg);
addr += sizeof(s->dsc_dst);
- address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false);
+ address_space_rw(s->dma_as, addr, s->attr, &next, 8, false);
zdma_put_regaddr64(s, basereg, next);
}
return next;
/* read current descriptor */
address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)s->rx_desc[q],
+ s->rx_desc[q],
sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Descriptor owned by software ? */
/* Descriptor write-back. */
desc_addr = gem_get_rx_desc_addr(s, q);
- address_space_write(&s->dma_as, desc_addr,
- MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)s->rx_desc[q],
+ address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
+ s->rx_desc[q],
sizeof(uint32_t) * gem_get_desc_len(s, true));
/* Next descriptor */
DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
address_space_read(&s->dma_as, packet_desc_addr,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
+ MEMTXATTRS_UNSPECIFIED, desc,
sizeof(uint32_t) * gem_get_desc_len(s, false));
/* Handle all descriptors owned by hardware */
while (tx_desc_get_used(desc) == 0) {
* the processor.
*/
address_space_read(&s->dma_as, desc_addr,
- MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)desc_first,
+ MEMTXATTRS_UNSPECIFIED, desc_first,
sizeof(desc_first));
tx_desc_set_used(desc_first);
address_space_write(&s->dma_as, desc_addr,
- MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)desc_first,
- sizeof(desc_first));
+ MEMTXATTRS_UNSPECIFIED, desc_first,
+ sizeof(desc_first));
/* Advance the hardware current descriptor past this packet */
if (tx_desc_get_wrap(desc)) {
s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
}
DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
address_space_read(&s->dma_as, packet_desc_addr,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
- sizeof(uint32_t) * gem_get_desc_len(s, false));
+ MEMTXATTRS_UNSPECIFIED, desc,
+ sizeof(uint32_t) * gem_get_desc_len(s, false));
}
if (tx_desc_get_used(desc)) {
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
/* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
address_space_rw(&s->as, dp8393x_rrp(s),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
/* Update SONIC registers */
s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
tx_len = 0;
/* Update registers */
size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
s->regs[SONIC_TCR] & 0x0fff); /* status */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
- dp8393x_ttda(s),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
+ dp8393x_ttda(s),
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
- dp8393x_ttda(s) +
+ dp8393x_ttda(s) +
sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1;
if (dp8393x_get(s, width, 0) & 0x1) {
/* EOL detected */
size = sizeof(uint16_t) * 1 * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)s->data, size, 0);
+ s->data, size, 0);
if (dp8393x_get(s, width, 0) & 0x1) {
/* Still EOL ; stop reception */
return -1;
address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len);
address += rx_len;
address_space_rw(&s->as, address,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
+ MEMTXATTRS_UNSPECIFIED, &checksum, 4, 1);
rx_len += 4;
s->regs[SONIC_CRBA1] = address >> 16;
s->regs[SONIC_CRBA0] = address & 0xffff;
dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 1);
/* Move to next descriptor */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0);
+ MEMTXATTRS_UNSPECIFIED, s->data, size, 0);
s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
}
s->data[0] = 0;
address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)s->data, sizeof(uint16_t), 1);
+ s->data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
return -EINVAL; /* channel program check */
}
ret = address_space_rw(&address_space_memory, idaw_addr,
- MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2,
+ MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
sizeof(idaw.fmt2), false);
cds->cda = be64_to_cpu(idaw.fmt2);
} else {
return -EINVAL; /* channel program check */
}
ret = address_space_rw(&address_space_memory, idaw_addr,
- MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1,
+ MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
sizeof(idaw.fmt1), false);
cds->cda = be64_to_cpu(idaw.fmt1);
if (cds->cda & 0x80000000) {
uint16_t data = value;
tswap16s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &data, 2, true);
+ &data, 2, true);
} else if (words[0][5] == 'l') {
uint32_t data = value;
tswap32s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &data, 4, true);
+ &data, 4, true);
} else if (words[0][5] == 'q') {
uint64_t data = value;
tswap64s(&data);
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &data, 8, true);
+ &data, 8, true);
}
qtest_send_prefix(chr);
qtest_send(chr, "OK\n");
} else if (words[0][4] == 'w') {
uint16_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &data, 2, false);
+ &data, 2, false);
value = tswap16(data);
} else if (words[0][4] == 'l') {
uint32_t data;
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &data, 4, false);
+ &data, 4, false);
value = tswap32(data);
} else if (words[0][4] == 'q') {
address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *) &value, 8, false);
+ &value, 8, false);
tswap64s(&value);
}
qtest_send_prefix(chr);
// Remove useless cast
@@
-expression E1, E2, E3, E4;
+expression E1, E2, E3, E4, E5, E6;
type T;
@@
(
+- address_space_rw(E1, E2, E3, (T *)(E4), E5, E6)
++ address_space_rw(E1, E2, E3, E4, E5, E6)
+|
+- address_space_read(E1, E2, E3, (T *)(E4), E5)
++ address_space_read(E1, E2, E3, E4, E5)
+|
+- address_space_write(E1, E2, E3, (T *)(E4), E5)
++ address_space_write(E1, E2, E3, E4, E5)
+|
+- address_space_write_rom(E1, E2, E3, (T *)(E4), E5)
++ address_space_write_rom(E1, E2, E3, E4, E5)
+|
+
- dma_memory_read(E1, E2, (T *)(E3), E4)
+ dma_memory_read(E1, E2, E3, E4)
|
address_space_rw(&address_space_memory,
rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)pdpte, 32, 0);
+ pdpte, 32, 0);
/* Only set PDPTE when appropriate. */
for (i = 0; i < 4; i++) {
wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
index = gpt_entry(pt->gva, level, pae);
address_space_rw(&address_space_memory, gpa + index * pte_size(pae),
- MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
+ MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), 0);
pt->pte[level - 1] = pte;
{
MemTxAttrs attrs = { 0 };
address_space_rw(&address_space_io, IoAccess->Port, attrs,
- (uint8_t *)&IoAccess->Data, IoAccess->AccessSize,
+ &IoAccess->Data, IoAccess->AccessSize,
IoAccess->Direction);
return S_OK;
}
* We treat them as absolute addresses and don't wrap them.
*/
if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)entry, sizeof(*entry)) !=
+ entry, sizeof(*entry)) !=
MEMTX_OK)) {
return false;
}