#include "ui/pixel_ops.h"
#include "qemu/timer.h"
#include "hw/loader.h"
+#include "hw/display/edid.h"
enum vga_pci_flags {
PCI_VGA_FLAG_ENABLE_MMIO = 1,
PCI_VGA_FLAG_ENABLE_QEXT = 2,
+ PCI_VGA_FLAG_ENABLE_EDID = 3,
};
typedef struct PCIVGAState {
PCIDevice dev;
VGACommonState vga;
uint32_t flags;
+ qemu_edid_info edid_info;
MemoryRegion mmio;
- MemoryRegion mrs[3];
+ MemoryRegion mrs[4];
+ uint8_t edid[256];
} PCIVGAState;
#define TYPE_PCI_VGA "pci-vga"
Object *owner,
MemoryRegion *parent,
MemoryRegion *subs,
- bool qext)
+ bool qext, bool edid)
{
+ PCIVGAState *d = container_of(s, PCIVGAState, vga);
+
memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
&subs[2]);
}
+
+ if (edid) {
+ qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
+ qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
+ memory_region_add_subregion(parent, 0, &subs[3]);
+ }
}
static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
PCIVGAState *d = PCI_VGA(dev);
VGACommonState *s = &d->vga;
bool qext = false;
+ bool edid = false;
/* vga + console init */
vga_common_init(s, OBJECT(dev));
qext = true;
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
}
- pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext);
+ if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
+ edid = true;
+ }
+ pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
+ qext, edid);
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
}
PCIVGAState *d = PCI_VGA(dev);
VGACommonState *s = &d->vga;
bool qext = false;
+ bool edid = false;
/* vga + console init */
vga_common_init(s, OBJECT(dev));
qext = true;
pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
}
- pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext);
+ if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
+ edid = true;
+ }
+ pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
DEFINE_PROP_BIT("qemu-extended-regs",
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
+ DEFINE_PROP_BIT("edid",
+ PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
+ DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
DEFINE_PROP_END_OF_LIST(),
};
DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
DEFINE_PROP_BIT("qemu-extended-regs",
PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
+ DEFINE_PROP_BIT("edid",
+ PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
+ DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
DEFINE_PROP_END_OF_LIST(),
};