projects / mirror_qemu.git / search
| 2020-03-20 | Alistair Francis | linux-user/riscv: Update the syscall_nr's to the 5... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...d9c4013ee033442827a4a0.1584051142.git.alistair.francis@wdc.com> |
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| 2020-03-20 | Alistair Francis | linux-user/syscall: Add support for clock_gettime64... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...0f684c9043e2ac7b34d91c.1584051142.git.alistair.francis@wdc.com> |
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| 2020-03-20 | Alistair Francis | linux-user: Protect more syscalls Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...57f16622be5f6edfa2aee6.1584051142.git.alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow enabling the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the MSTATUS_MPV_ISSET helper macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the 32-bit MSTATUSH CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set htval and mtval2 on execptions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Raise the new execptions when 2nd stage... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Implement second stage MMU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow specifying MMU stage Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Respect MPRV and SPRV for floating point ops Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Mark both sstatus and msstatus_hs as... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Disable guest FP support based on virtual... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Only set TB flags with FP status if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Remove the hret instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor trap return support Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hypvervisor trap support Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Generate illegal instruction on WFI when V=1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/ricsv: Flush the TLB on virtulisation mode changes Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for virtual interrupt setting Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the SIP CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the MIE CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set VS bits in mideleg for Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add virtual register swapping function Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor machine CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor virtual CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor CSR access functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Dump Hypervisor registers if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Print priv and virt in disas log Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Fix CSR perm checking for HS mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the force HS exception mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the virtulisation mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Rename the H irqs to VS irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the new execption numbers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor CSRs to CPUState Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Convert MIP CSR to target_ulong Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-11-14 | Alistair Francis | riscv/virt: Increase flash size Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-11-14 | Alistair Francis | opensbi: Upgrade from v0.4 to v0.5 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-11-14 | Alistair Francis | target/riscv: Remove atomic accesses to MIP CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/boot: Fix possible memory leak Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Jump to pflash if specified Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Add the PFlash CFI01 device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/virt: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add the start-in-flash property Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add QSPI memory region Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-10-28 | Alistair Francis | riscv/sifive_u: Add L2-LIM cache memory Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Use TB_FLAGS_MSTATUS_FS for floating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Fix mstatus dirty mask Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Update the Hypervisor CSRs to v0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-09-17 | Alistair Francis | target/riscv: Create function to test if FP is enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-09-17 | Alistair Francis | riscv: plic: Remove unused interrupt functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-07-26 | Alistair Francis | riscv/boot: Fixup the RISC-V firmware warning Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-07-18 | Alistair Francis | hw/riscv: Load OpenSBI as the default firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-07-18 | Alistair Francis | roms: Add OpenSBI version 0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-07-09 | Alistair Francis | tcg/riscv: Fix RISC-VH host build failure Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...5c4aa0aa8a52847af70c0f.1561039316.git.alistair.francis@wdc.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Extend the kernel loading support Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Add support for loading a firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-27 | Alistair Francis | hw/riscv: Split out the boot functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Add support for disabling/enabling Counters Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Remove user version information Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Require either I or E base extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Set privledge spec 1.11.0 as default Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-25 | Alistair Francis | target/riscv: Add the mcountinhibit CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Add the privledge spec version 1.11.0 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Restructure deprecatd CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-06-24 | Alistair Francis | target/riscv: Allow setting ISA extensions via CPU... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the HGATP register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the HSTATUS register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add Hypervisor CSR macros Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Allow setting mstatus virtulisation bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add the MPV and MTL mstatus bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Improve the scause logic Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Trigger interrupt on MIP update asynchronously Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Mark privilege level 2 as reserved Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | riscv: spike: Add a generic spike machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Deprecate the generic no MMU CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Add a base 32 and 64 bit CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | target/riscv: Create settable CPU properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | riscv: virt: Allow specifying a CPU via commandline Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-24 | Alistair Francis | linux-user/riscv: Add the CPU type as a comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-05-23 | Alistair Francis | target/arm: Fix vector operation segfault Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com |
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| 2019-05-09 | Alistair Francis | linux-user/elfload: Fix GCC 9 build warnings Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...00b91361af9302823a72a9.1556666645.git.alistair.francis@wdc.com> |
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| 2019-04-04 | Alistair Francis | riscv: plic: Log guest errors Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-04-04 | Alistair Francis | riscv: plic: Fix incorrect irq calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-27 | Alistair Francis | MAINTAINERS: Update the device tree maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-19 | Alistair Francis | target/riscv: Remove unused struct Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-19 | Alistair Francis | riscv: sifive_u: Allow up to 4 CPUs to be created Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-19 | Alistair Francis | riscv: pmp: Log pmp access errors as guest errors Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-03-18 | Alistair Francis | riscv: plic: Set msi_nonbroken as true Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...159b0f4a4fc0d95c050660.1552679970.git.alistair.francis@wdc.com> |
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| 2019-02-11 | Alistair Francis | riscv: Ensure the kernel start address is correctly... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-02-11 | Alistair Francis | RISC-V: Add priv_ver to DisasContext Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2019-01-10 | Alistair Francis | default-configs: Enable USB support for RISC-V machines Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2018-12-25 | Alistair Francis | configure: Add support for building RISC-V host Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...c43a412fa3e74ddd6277fb.1545246859.git.alistair.francis@wdc.com> |
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| 2018-12-25 | Alistair Francis | disas: Add RISC-V support Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...4bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com> |
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| 2018-12-25 | Alistair Francis | tcg: Add RISC-V cpu signal handler Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...fd862a55628907f0093194.1545246859.git.alistair.francis@wdc.com> |
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| 2018-12-25 | Alistair Francis | tcg/riscv: Add the target init code Signed-off-by: Alistair Francis <alistair.francis@wdc.com> ...8fd91f904f6de26ab5d697.1545246859.git.alistair.francis@wdc.com> |
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