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| 2018-12-21 | Palmer Dabbelt | MAINTAINERS: Mark RISC-V as Supported Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Mao Zhongyi | riscv/cpu: use device_class_set_parent_realize Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | target/riscv/pmp.c: Fix pmp_decode_napot() Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Nathaniel Graff | sifive_uart: Implement interrupt pending register Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Enable second UART on sifive_e and sifive_u Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Fix PLIC pending bitfield reads Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Fix CLINT timecmp low 32-bit writes Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Add hartid and \n to interrupt logging Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Set 'clock-frequency' DT property for SiFive... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Add clock DT node for GEM ethernet Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | riscv: Enable VGA and PCIE_VGA Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Connect the gpex PCIe Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Adjust memory layout spacing Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Increase the number of interrupts Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Palmer Dabbelt | RISC-V: Respect fences for user-only emulators Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Bastian Koppelmann | target/riscv: Fix sfence.vm/a both available in any... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Bastian Koppelmann | target/riscv: Fix FCLASS_D being treated as RV64 only Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Alistair Francis | hw/riscv/virt: Free the test device tree node name Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-08 | Alistair Francis | riscv: spike: Fix memory leak in the board init Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Palmer Dabbelt | Add qemu-riscv@nongnu.org as the RISC-V list Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Palmer Dabbelt | Add Alistair as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Dayeol Lee | target/riscv/pmp.c: pmpcfg_csr_read returns bogus value... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Don't add NULL bootargs to device-tree Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Add missing free for plic_hart_config Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Update CSR and interrupt definitions Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Move non-ops from op_helper to cpu_helper Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Allow setting and clearing multiple irqs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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