]> git.proxmox.com Git - mirror_spl-debian.git/blame - module/spl/spl-rwlock.c
New upstream version 0.7.11
[mirror_spl-debian.git] / module / spl / spl-rwlock.c
CommitLineData
716154c5
BB
1/*****************************************************************************\
2 * Copyright (C) 2007-2010 Lawrence Livermore National Security, LLC.
3 * Copyright (C) 2007 The Regents of the University of California.
4 * Produced at Lawrence Livermore National Laboratory (cf, DISCLAIMER).
5 * Written by Brian Behlendorf <behlendorf1@llnl.gov>.
715f6251 6 * UCRL-CODE-235197
7 *
716154c5 8 * This file is part of the SPL, Solaris Porting Layer.
3d6af2dd 9 * For details, see <http://zfsonlinux.org/>.
715f6251 10 *
716154c5
BB
11 * The SPL is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * The SPL is distributed in the hope that it will be useful, but WITHOUT
715f6251 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
716154c5 22 * with the SPL. If not, see <http://www.gnu.org/licenses/>.
34ee731f 23 *
716154c5
BB
24 * Solaris Porting Layer (SPL) Reader/Writer Lock Implementation.
25\*****************************************************************************/
715f6251 26
f4b37741 27#include <sys/rwlock.h>
f1ca4da6 28
ec06701b
AX
29#if defined(CONFIG_PREEMPT_RT_FULL)
30
31#include <linux/rtmutex.h>
32#define RT_MUTEX_OWNER_MASKALL 1UL
33
34static int
35__rwsem_tryupgrade(struct rw_semaphore *rwsem)
36{
b97c7791
MZ
37#if defined(READER_BIAS) && defined(WRITER_BIAS)
38 /*
39 * After the 4.9.20-rt16 kernel the realtime patch series lifted the
40 * single reader restriction. While this could be accommodated by
41 * adding additional compatibility code assume the rwsem can never
42 * be upgraded. All caller must already cleanly handle this case.
43 */
44 return (0);
45#else
ec06701b
AX
46 ASSERT((struct task_struct *)
47 ((unsigned long)rwsem->lock.owner & ~RT_MUTEX_OWNER_MASKALL) ==
48 current);
49
50 /*
b97c7791
MZ
51 * Prior to 4.9.20-rt16 kernel the realtime patch series, rwsem is
52 * implemented as a single mutex held by readers and writers alike.
53 * However, this implementation would prevent a thread from taking
54 * a read lock twice, as the mutex would already be locked on
ec06701b
AX
55 * the second attempt. Therefore the implementation allows a
56 * single thread to take a rwsem as read lock multiple times
57 * tracking that nesting as read_depth counter.
58 */
59 if (rwsem->read_depth <= 1) {
60 /*
61 * In case, the current thread has not taken the lock
62 * more than once as read lock, we can allow an
63 * upgrade to a write lock. rwsem_rt.h implements
64 * write locks as read_depth == 0.
65 */
66 rwsem->read_depth = 0;
67 return (1);
68 }
69 return (0);
b97c7791 70#endif
ec06701b
AX
71}
72#elif defined(CONFIG_RWSEM_GENERIC_SPINLOCK)
0f836a62
AX
73static int
74__rwsem_tryupgrade(struct rw_semaphore *rwsem)
e8b31e84 75{
0f836a62
AX
76 int ret = 0;
77 unsigned long flags;
78 spl_rwsem_lock_irqsave(&rwsem->wait_lock, flags);
79 if (RWSEM_COUNT(rwsem) == SPL_RWSEM_SINGLE_READER_VALUE &&
80 list_empty(&rwsem->wait_list)) {
81 ret = 1;
82 RWSEM_COUNT(rwsem) = SPL_RWSEM_SINGLE_WRITER_VALUE;
83 }
84 spl_rwsem_unlock_irqrestore(&rwsem->wait_lock, flags);
85 return (ret);
e8b31e84 86}
0f836a62
AX
87#elif defined(HAVE_RWSEM_ATOMIC_LONG_COUNT)
88static int
89__rwsem_tryupgrade(struct rw_semaphore *rwsem)
e8b31e84 90{
0f836a62
AX
91 long val;
92 val = atomic_long_cmpxchg(&rwsem->count, SPL_RWSEM_SINGLE_READER_VALUE,
93 SPL_RWSEM_SINGLE_WRITER_VALUE);
94 return (val == SPL_RWSEM_SINGLE_READER_VALUE);
e8b31e84 95}
0f836a62
AX
96#else
97static int
98__rwsem_tryupgrade(struct rw_semaphore *rwsem)
e8b31e84 99{
34ee731f 100 typeof(rwsem->count) val;
0f836a62
AX
101 val = cmpxchg(&rwsem->count, SPL_RWSEM_SINGLE_READER_VALUE,
102 SPL_RWSEM_SINGLE_WRITER_VALUE);
103 return (val == SPL_RWSEM_SINGLE_READER_VALUE);
f1ca4da6 104}
0f836a62 105#endif
79f92663 106
0f836a62
AX
107int
108rwsem_tryupgrade(struct rw_semaphore *rwsem)
109{
110 if (__rwsem_tryupgrade(rwsem)) {
111 rwsem_release(&rwsem->dep_map, 1, _RET_IP_);
112 rwsem_acquire(&rwsem->dep_map, 0, 1, _RET_IP_);
113#ifdef CONFIG_RWSEM_SPIN_ON_OWNER
114 rwsem->owner = current;
ed61a7d0 115#endif
0f836a62
AX
116 return (1);
117 }
118 return (0);
119}
120EXPORT_SYMBOL(rwsem_tryupgrade);
d28db80f
BB
121
122int spl_rw_init(void) { return 0; }
123void spl_rw_fini(void) { }