[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / cpufeatures.h

#ifndef _ASM_X86_CPUFEATURES_H
#define _ASM_X86_CPUFEATURES_H

#ifndef _ASM_X86_REQUIRED_FEATURES_H
#include <asm/required-features.h>
#endif

#ifndef _ASM_X86_DISABLED_FEATURES_H
#include <asm/disabled-features.h>
#endif

/*
 * Defines x86 CPU feature bits
 */
#define NCAPINTS	16	/* N 32-bit words worth of info */
#define NBUGINTS	1	/* N 32-bit bug flags */

/*
 * Note: If the comment begins with a quoted string, that string is used
 * in /proc/cpuinfo instead of the macro name.  If the string is "",
 * this feature bit is not displayed in /proc/cpuinfo at all.
 */

/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
#define X86_FEATURE_FPU		( 0*32+ 0) /* Onboard FPU */
#define X86_FEATURE_VME		( 0*32+ 1) /* Virtual Mode Extensions */
#define X86_FEATURE_DE		( 0*32+ 2) /* Debugging Extensions */
#define X86_FEATURE_PSE		( 0*32+ 3) /* Page Size Extensions */
#define X86_FEATURE_TSC		( 0*32+ 4) /* Time Stamp Counter */
#define X86_FEATURE_MSR		( 0*32+ 5) /* Model-Specific Registers */
#define X86_FEATURE_PAE		( 0*32+ 6) /* Physical Address Extensions */
#define X86_FEATURE_MCE		( 0*32+ 7) /* Machine Check Exception */
#define X86_FEATURE_CX8		( 0*32+ 8) /* CMPXCHG8 instruction */
#define X86_FEATURE_APIC	( 0*32+ 9) /* Onboard APIC */
#define X86_FEATURE_SEP		( 0*32+11) /* SYSENTER/SYSEXIT */
#define X86_FEATURE_MTRR	( 0*32+12) /* Memory Type Range Registers */
#define X86_FEATURE_PGE		( 0*32+13) /* Page Global Enable */
#define X86_FEATURE_MCA		( 0*32+14) /* Machine Check Architecture */
#define X86_FEATURE_CMOV	( 0*32+15) /* CMOV instructions */
					  /* (plus FCMOVcc, FCOMI with FPU) */
#define X86_FEATURE_PAT		( 0*32+16) /* Page Attribute Table */
#define X86_FEATURE_PSE36	( 0*32+17) /* 36-bit PSEs */
#define X86_FEATURE_PN		( 0*32+18) /* Processor serial number */
#define X86_FEATURE_CLFLUSH	( 0*32+19) /* CLFLUSH instruction */
#define X86_FEATURE_DS		( 0*32+21) /* "dts" Debug Store */
#define X86_FEATURE_ACPI	( 0*32+22) /* ACPI via MSR */
#define X86_FEATURE_MMX		( 0*32+23) /* Multimedia Extensions */
#define X86_FEATURE_FXSR	( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
#define X86_FEATURE_XMM		( 0*32+25) /* "sse" */
#define X86_FEATURE_XMM2	( 0*32+26) /* "sse2" */
#define X86_FEATURE_SELFSNOOP	( 0*32+27) /* "ss" CPU self snoop */
#define X86_FEATURE_HT		( 0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC		( 0*32+29) /* "tm" Automatic clock control */
#define X86_FEATURE_IA64	( 0*32+30) /* IA-64 processor */
#define X86_FEATURE_PBE		( 0*32+31) /* Pending Break Enable */

/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
#define X86_FEATURE_SYSCALL	( 1*32+11) /* SYSCALL/SYSRET */
#define X86_FEATURE_MP		( 1*32+19) /* MP Capable. */
#define X86_FEATURE_NX		( 1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT	( 1*32+22) /* AMD MMX extensions */
#define X86_FEATURE_FXSR_OPT	( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
#define X86_FEATURE_GBPAGES	( 1*32+26) /* "pdpe1gb" GB pages */
#define X86_FEATURE_RDTSCP	( 1*32+27) /* RDTSCP */
#define X86_FEATURE_LM		( 1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT	( 1*32+30) /* AMD 3DNow! extensions */
#define X86_FEATURE_3DNOW	( 1*32+31) /* 3DNow! */

/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
#define X86_FEATURE_RECOVERY	( 2*32+ 0) /* CPU in recovery mode */
#define X86_FEATURE_LONGRUN	( 2*32+ 1) /* Longrun power control */
#define X86_FEATURE_LRTI	( 2*32+ 3) /* LongRun table interface */

/* Other features, Linux-defined mapping, word 3 */
/* This range is used for feature bits which conflict or are synthesized */
#define X86_FEATURE_CXMMX	( 3*32+ 0) /* Cyrix MMX extensions */
#define X86_FEATURE_K6_MTRR	( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
#define X86_FEATURE_CYRIX_ARR	( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
#define X86_FEATURE_CENTAUR_MCR	( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
/* cpu types for specific tunings: */
#define X86_FEATURE_K8		( 3*32+ 4) /* "" Opteron, Athlon64 */
#define X86_FEATURE_K7		( 3*32+ 5) /* "" Athlon */
#define X86_FEATURE_P3		( 3*32+ 6) /* "" P3 */
#define X86_FEATURE_P4		( 3*32+ 7) /* "" P4 */
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP		( 3*32+ 9) /* smp kernel running on up */
/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS	( 3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS		( 3*32+13) /* Branch Trace Store */
#define X86_FEATURE_SYSCALL32	( 3*32+14) /* "" syscall in ia32 userspace */
#define X86_FEATURE_SYSENTER32	( 3*32+15) /* "" sysenter in ia32 userspace */
#define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */
#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
/* free, was #define X86_FEATURE_11AP	( 3*32+19) * "" Bad local APIC aka 11AP */
#define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */
#define X86_FEATURE_ALWAYS	( 3*32+21) /* "" Always-present feature */
#define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */
/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
#define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
#define X86_FEATURE_EAGER_FPU	( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */

/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3	( 4*32+ 0) /* "pni" SSE-3 */
#define X86_FEATURE_PCLMULQDQ	( 4*32+ 1) /* PCLMULQDQ instruction */
#define X86_FEATURE_DTES64	( 4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT	( 4*32+ 3) /* "monitor" Monitor/Mwait support */
#define X86_FEATURE_DSCPL	( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
#define X86_FEATURE_VMX		( 4*32+ 5) /* Hardware virtualization */
#define X86_FEATURE_SMX		( 4*32+ 6) /* Safer mode */
#define X86_FEATURE_EST		( 4*32+ 7) /* Enhanced SpeedStep */
#define X86_FEATURE_TM2		( 4*32+ 8) /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3	( 4*32+ 9) /* Supplemental SSE-3 */
#define X86_FEATURE_CID		( 4*32+10) /* Context ID */
#define X86_FEATURE_SDBG	( 4*32+11) /* Silicon Debug */
#define X86_FEATURE_FMA		( 4*32+12) /* Fused multiply-add */
#define X86_FEATURE_CX16	( 4*32+13) /* CMPXCHG16B */
#define X86_FEATURE_XTPR	( 4*32+14) /* Send Task Priority Messages */
#define X86_FEATURE_PDCM	( 4*32+15) /* Performance Capabilities */
#define X86_FEATURE_PCID	( 4*32+17) /* Process Context Identifiers */
#define X86_FEATURE_DCA		( 4*32+18) /* Direct Cache Access */
#define X86_FEATURE_XMM4_1	( 4*32+19) /* "sse4_1" SSE-4.1 */
#define X86_FEATURE_XMM4_2	( 4*32+20) /* "sse4_2" SSE-4.2 */
#define X86_FEATURE_X2APIC	( 4*32+21) /* x2APIC */
#define X86_FEATURE_MOVBE	( 4*32+22) /* MOVBE instruction */
#define X86_FEATURE_POPCNT      ( 4*32+23) /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE_TIMER	( 4*32+24) /* Tsc deadline timer */
#define X86_FEATURE_AES		( 4*32+25) /* AES instructions */
#define X86_FEATURE_XSAVE	( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
#define X86_FEATURE_OSXSAVE	( 4*32+27) /* "" XSAVE enabled in the OS */
#define X86_FEATURE_AVX		( 4*32+28) /* Advanced Vector Extensions */
#define X86_FEATURE_F16C	( 4*32+29) /* 16-bit fp conversions */
#define X86_FEATURE_RDRAND	( 4*32+30) /* The RDRAND instruction */
#define X86_FEATURE_HYPERVISOR	( 4*32+31) /* Running on a hypervisor */

/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_XSTORE	( 5*32+ 2) /* "rng" RNG present (xstore) */
#define X86_FEATURE_XSTORE_EN	( 5*32+ 3) /* "rng_en" RNG enabled */
#define X86_FEATURE_XCRYPT	( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
#define X86_FEATURE_XCRYPT_EN	( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
#define X86_FEATURE_ACE2	( 5*32+ 8) /* Advanced Cryptography Engine v2 */
#define X86_FEATURE_ACE2_EN	( 5*32+ 9) /* ACE v2 enabled */
#define X86_FEATURE_PHE		( 5*32+10) /* PadLock Hash Engine */
#define X86_FEATURE_PHE_EN	( 5*32+11) /* PHE enabled */
#define X86_FEATURE_PMM		( 5*32+12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN	( 5*32+13) /* PMM enabled */

/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM	( 6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY	( 6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVM		( 6*32+ 2) /* Secure virtual machine */
#define X86_FEATURE_EXTAPIC	( 6*32+ 3) /* Extended APIC space */
#define X86_FEATURE_CR8_LEGACY	( 6*32+ 4) /* CR8 in 32-bit mode */
#define X86_FEATURE_ABM		( 6*32+ 5) /* Advanced bit manipulation */
#define X86_FEATURE_SSE4A	( 6*32+ 6) /* SSE-4A */
#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
#define X86_FEATURE_OSVW	( 6*32+ 9) /* OS Visible Workaround */
#define X86_FEATURE_IBS		( 6*32+10) /* Instruction Based Sampling */
#define X86_FEATURE_XOP		( 6*32+11) /* extended AVX instructions */
#define X86_FEATURE_SKINIT	( 6*32+12) /* SKINIT/STGI instructions */
#define X86_FEATURE_WDT		( 6*32+13) /* Watchdog timer */
#define X86_FEATURE_LWP		( 6*32+15) /* Light Weight Profiling */
#define X86_FEATURE_FMA4	( 6*32+16) /* 4 operands MAC instructions */
#define X86_FEATURE_TCE		( 6*32+17) /* translation cache extension */
#define X86_FEATURE_NODEID_MSR	( 6*32+19) /* NodeId MSR */
#define X86_FEATURE_TBM		( 6*32+21) /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT	( 6*32+22) /* topology extensions CPUID leafs */
#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
#define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */
#define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */
#define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */
#define X86_FEATURE_MWAITX	( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */

/*
 * Auxiliary flags: Linux defined - For features scattered in various
 * CPUID levels like 0x6, 0xA etc, word 7.
 *
 * Reuse free bits when adding new feature flags!
 */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */
#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_INTEL_PT	( 7*32+15) /* Intel Processor Trace */

/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
#define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
#define X86_FEATURE_EPT         ( 8*32+ 3) /* Intel Extended Page Table */
#define X86_FEATURE_VPID        ( 8*32+ 4) /* Intel Virtual Processor ID */

#define X86_FEATURE_VMMCALL     ( 8*32+15) /* Prefer vmmcall to vmcall */
#define X86_FEATURE_XENPV       ( 8*32+16) /* "" Xen paravirtual guest */


/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
#define X86_FEATURE_FSGSBASE	( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
#define X86_FEATURE_TSC_ADJUST	( 9*32+ 1) /* TSC adjustment MSR 0x3b */
#define X86_FEATURE_BMI1	( 9*32+ 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE		( 9*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2	( 9*32+ 5) /* AVX2 instructions */
#define X86_FEATURE_SMEP	( 9*32+ 7) /* Supervisor Mode Execution Protection */
#define X86_FEATURE_BMI2	( 9*32+ 8) /* 2nd group bit manipulation extensions */
#define X86_FEATURE_ERMS	( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID	( 9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM		( 9*32+11) /* Restricted Transactional Memory */
#define X86_FEATURE_CQM		( 9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX		( 9*32+14) /* Memory Protection Extension */
#define X86_FEATURE_AVX512F	( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED	( 9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX		( 9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP	( 9*32+20) /* Supervisor Mode Access Prevention */
#define X86_FEATURE_PCOMMIT	( 9*32+22) /* PCOMMIT instruction */
#define X86_FEATURE_CLFLUSHOPT	( 9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB	( 9*32+24) /* CLWB instruction */
#define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */

/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
#define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
#define X86_FEATURE_XSAVEC	(10*32+ 1) /* XSAVEC */
#define X86_FEATURE_XGETBV1	(10*32+ 2) /* XGETBV with ECX = 1 */
#define X86_FEATURE_XSAVES	(10*32+ 3) /* XSAVES/XRSTORS */

/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
#define X86_FEATURE_CQM_LLC	(11*32+ 1) /* LLC QoS if 1 */

/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */

/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */

/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
#define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */
#define X86_FEATURE_IDA		(14*32+ 1) /* Intel Dynamic Acceleration */
#define X86_FEATURE_ARAT	(14*32+ 2) /* Always Running APIC Timer */
#define X86_FEATURE_PLN		(14*32+ 4) /* Intel Power Limit Notification */
#define X86_FEATURE_PTS		(14*32+ 6) /* Intel Package Thermal Status */
#define X86_FEATURE_HWP		(14*32+ 7) /* Intel Hardware P-states */
#define X86_FEATURE_HWP_NOTIFY	(14*32+ 8) /* HWP Notification */
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
#define X86_FEATURE_HWP_EPP	(14*32+10) /* HWP Energy Perf. Preference */
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */

/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
#define X86_FEATURE_NPT		(15*32+ 0) /* Nested Page Table support */
#define X86_FEATURE_LBRV	(15*32+ 1) /* LBR Virtualization support */
#define X86_FEATURE_SVML	(15*32+ 2) /* "svm_lock" SVM locking MSR */
#define X86_FEATURE_NRIPS	(15*32+ 3) /* "nrip_save" SVM next_rip save */
#define X86_FEATURE_TSCRATEMSR  (15*32+ 4) /* "tsc_scale" TSC scaling support */
#define X86_FEATURE_VMCBCLEAN   (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
#define X86_FEATURE_AVIC	(15*32+13) /* Virtual Interrupt Controller */

/*
 * BUG word(s)
 */
#define X86_BUG(x)		(NCAPINTS*32 + (x))

#define X86_BUG_F00F		X86_BUG(0) /* Intel F00F */
#define X86_BUG_FDIV		X86_BUG(1) /* FPU FDIV */
#define X86_BUG_COMA		X86_BUG(2) /* Cyrix 6x86 coma */
#define X86_BUG_AMD_TLB_MMATCH	X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
#define X86_BUG_AMD_APIC_C1E	X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
#define X86_BUG_11AP		X86_BUG(5) /* Bad local APIC aka 11AP */
#define X86_BUG_FXSAVE_LEAK	X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
#define X86_BUG_CLFLUSH_MONITOR	X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
#define X86_BUG_SYSRET_SS_ATTRS	X86_BUG(8) /* SYSRET doesn't fix up SS attrs */

#endif /* _ASM_X86_CPUFEATURES_H */
Commit	Line	Data
cd4d09ec BP	1	#ifndef _ASM_X86_CPUFEATURES_H
	2	#define _ASM_X86_CPUFEATURES_H
	3
	4	#ifndef _ASM_X86_REQUIRED_FEATURES_H
	5	#include <asm/required-features.h>
	6	#endif
	7
	8	#ifndef _ASM_X86_DISABLED_FEATURES_H
	9	#include <asm/disabled-features.h>
	10	#endif
	11
	12	/*
	13	* Defines x86 CPU feature bits
	14	*/
	15	#define NCAPINTS 16 /* N 32-bit words worth of info */
	16	#define NBUGINTS 1 /* N 32-bit bug flags */
	17
	18	/*
	19	* Note: If the comment begins with a quoted string, that string is used
	20	* in /proc/cpuinfo instead of the macro name. If the string is "",
	21	* this feature bit is not displayed in /proc/cpuinfo at all.
	22	*/
	23
	24	/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
	25	#define X86_FEATURE_FPU ( 032+ 0) / Onboard FPU */
	26	#define X86_FEATURE_VME ( 032+ 1) / Virtual Mode Extensions */
	27	#define X86_FEATURE_DE ( 032+ 2) / Debugging Extensions */
	28	#define X86_FEATURE_PSE ( 032+ 3) / Page Size Extensions */
	29	#define X86_FEATURE_TSC ( 032+ 4) / Time Stamp Counter */
	30	#define X86_FEATURE_MSR ( 032+ 5) / Model-Specific Registers */
	31	#define X86_FEATURE_PAE ( 032+ 6) / Physical Address Extensions */
	32	#define X86_FEATURE_MCE ( 032+ 7) / Machine Check Exception */
	33	#define X86_FEATURE_CX8 ( 032+ 8) / CMPXCHG8 instruction */
	34	#define X86_FEATURE_APIC ( 032+ 9) / Onboard APIC */
	35	#define X86_FEATURE_SEP ( 032+11) / SYSENTER/SYSEXIT */
	36	#define X86_FEATURE_MTRR ( 032+12) / Memory Type Range Registers */
	37	#define X86_FEATURE_PGE ( 032+13) / Page Global Enable */
	38	#define X86_FEATURE_MCA ( 032+14) / Machine Check Architecture */
	39	#define X86_FEATURE_CMOV ( 032+15) / CMOV instructions */
	40	/* (plus FCMOVcc, FCOMI with FPU) */
	41	#define X86_FEATURE_PAT ( 032+16) / Page Attribute Table */
	42	#define X86_FEATURE_PSE36 ( 032+17) / 36-bit PSEs */
	43	#define X86_FEATURE_PN ( 032+18) / Processor serial number */
	44	#define X86_FEATURE_CLFLUSH ( 032+19) / CLFLUSH instruction */
	45	#define X86_FEATURE_DS ( 032+21) / "dts" Debug Store */
	46	#define X86_FEATURE_ACPI ( 032+22) / ACPI via MSR */
	47	#define X86_FEATURE_MMX ( 032+23) / Multimedia Extensions */
	48	#define X86_FEATURE_FXSR ( 032+24) / FXSAVE/FXRSTOR, CR4.OSFXSR */
	49	#define X86_FEATURE_XMM ( 032+25) / "sse" */
	50	#define X86_FEATURE_XMM2 ( 032+26) / "sse2" */
	51	#define X86_FEATURE_SELFSNOOP ( 032+27) / "ss" CPU self snoop */
	52	#define X86_FEATURE_HT ( 032+28) / Hyper-Threading */
	53	#define X86_FEATURE_ACC ( 032+29) / "tm" Automatic clock control */
	54	#define X86_FEATURE_IA64 ( 032+30) / IA-64 processor */
	55	#define X86_FEATURE_PBE ( 032+31) / Pending Break Enable */
	56
	57	/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
	58	/* Don't duplicate feature flags which are redundant with Intel! */
	59	#define X86_FEATURE_SYSCALL ( 132+11) / SYSCALL/SYSRET */
	60	#define X86_FEATURE_MP ( 132+19) / MP Capable. */
	61	#define X86_FEATURE_NX ( 132+20) / Execute Disable */
	62	#define X86_FEATURE_MMXEXT ( 132+22) / AMD MMX extensions */
	63	#define X86_FEATURE_FXSR_OPT ( 132+25) / FXSAVE/FXRSTOR optimizations */
	64	#define X86_FEATURE_GBPAGES ( 132+26) / "pdpe1gb" GB pages */
65	#define X86_FEATURE_RDTSCP ( 132+27) / RDTSCP */
66	#define X86_FEATURE_LM ( 132+29) / Long Mode (x86-64) */
67	#define X86_FEATURE_3DNOWEXT ( 132+30) / AMD 3DNow! extensions */
68	#define X86_FEATURE_3DNOW ( 132+31) / 3DNow! */
69
70	/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
71	#define X86_FEATURE_RECOVERY ( 232+ 0) / CPU in recovery mode */
72	#define X86_FEATURE_LONGRUN ( 232+ 1) / Longrun power control */
73	#define X86_FEATURE_LRTI ( 232+ 3) / LongRun table interface */
74
75	/* Other features, Linux-defined mapping, word 3 */
76	/* This range is used for feature bits which conflict or are synthesized */
77	#define X86_FEATURE_CXMMX ( 332+ 0) / Cyrix MMX extensions */
78	#define X86_FEATURE_K6_MTRR ( 332+ 1) / AMD K6 nonstandard MTRRs */
79	#define X86_FEATURE_CYRIX_ARR ( 332+ 2) / Cyrix ARRs (= MTRRs) */
80	#define X86_FEATURE_CENTAUR_MCR ( 332+ 3) / Centaur MCRs (= MTRRs) */
81	/* cpu types for specific tunings: */
82	#define X86_FEATURE_K8 ( 332+ 4) / "" Opteron, Athlon64 */
83	#define X86_FEATURE_K7 ( 332+ 5) / "" Athlon */
84	#define X86_FEATURE_P3 ( 332+ 6) / "" P3 */
85	#define X86_FEATURE_P4 ( 332+ 7) / "" P4 */
86	#define X86_FEATURE_CONSTANT_TSC ( 332+ 8) / TSC ticks at a constant rate */
87	#define X86_FEATURE_UP ( 332+ 9) / smp kernel running on up */
88	/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 332+10) "" FXSAVE leaks FOP/FIP/FOP */
89	#define X86_FEATURE_ARCH_PERFMON ( 332+11) / Intel Architectural PerfMon */
90	#define X86_FEATURE_PEBS ( 332+12) / Precise-Event Based Sampling */
91	#define X86_FEATURE_BTS ( 332+13) / Branch Trace Store */
92	#define X86_FEATURE_SYSCALL32 ( 332+14) / "" syscall in ia32 userspace */
93	#define X86_FEATURE_SYSENTER32 ( 332+15) / "" sysenter in ia32 userspace */
94	#define X86_FEATURE_REP_GOOD ( 332+16) / rep microcode works well */
95	#define X86_FEATURE_MFENCE_RDTSC ( 332+17) / "" Mfence synchronizes RDTSC */
96	#define X86_FEATURE_LFENCE_RDTSC ( 332+18) / "" Lfence synchronizes RDTSC */
97	/* free, was #define X86_FEATURE_11AP ( 332+19) "" Bad local APIC aka 11AP */
98	#define X86_FEATURE_NOPL ( 332+20) / The NOPL (0F 1F) instructions */
99	#define X86_FEATURE_ALWAYS ( 332+21) / "" Always-present feature */
100	#define X86_FEATURE_XTOPOLOGY ( 332+22) / cpu topology enum extensions */
101	#define X86_FEATURE_TSC_RELIABLE ( 332+23) / TSC is known to be reliable */
102	#define X86_FEATURE_NONSTOP_TSC ( 332+24) / TSC does not stop in C states */
103	/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 332+25) "" clflush reqd with monitor */
104	#define X86_FEATURE_EXTD_APICID ( 332+26) / has extended APICID (8 bits) */
105	#define X86_FEATURE_AMD_DCM ( 332+27) / multi-node processor */
106	#define X86_FEATURE_APERFMPERF ( 332+28) / APERFMPERF */
107	#define X86_FEATURE_EAGER_FPU ( 332+29) / "eagerfpu" Non lazy FPU restore */
108	#define X86_FEATURE_NONSTOP_TSC_S3 ( 332+30) / TSC doesn't stop in S3 state */
109
110	/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
111	#define X86_FEATURE_XMM3 ( 432+ 0) / "pni" SSE-3 */
112	#define X86_FEATURE_PCLMULQDQ ( 432+ 1) / PCLMULQDQ instruction */
113	#define X86_FEATURE_DTES64 ( 432+ 2) / 64-bit Debug Store */
114	#define X86_FEATURE_MWAIT ( 432+ 3) / "monitor" Monitor/Mwait support */
115	#define X86_FEATURE_DSCPL ( 432+ 4) / "ds_cpl" CPL Qual. Debug Store */
116	#define X86_FEATURE_VMX ( 432+ 5) / Hardware virtualization */
117	#define X86_FEATURE_SMX ( 432+ 6) / Safer mode */
118	#define X86_FEATURE_EST ( 432+ 7) / Enhanced SpeedStep */
119	#define X86_FEATURE_TM2 ( 432+ 8) / Thermal Monitor 2 */
120	#define X86_FEATURE_SSSE3 ( 432+ 9) / Supplemental SSE-3 */
121	#define X86_FEATURE_CID ( 432+10) / Context ID */
122	#define X86_FEATURE_SDBG ( 432+11) / Silicon Debug */
123	#define X86_FEATURE_FMA ( 432+12) / Fused multiply-add */
124	#define X86_FEATURE_CX16 ( 432+13) / CMPXCHG16B */
125	#define X86_FEATURE_XTPR ( 432+14) / Send Task Priority Messages */
126	#define X86_FEATURE_PDCM ( 432+15) / Performance Capabilities */
127	#define X86_FEATURE_PCID ( 432+17) / Process Context Identifiers */
128	#define X86_FEATURE_DCA ( 432+18) / Direct Cache Access */
129	#define X86_FEATURE_XMM4_1 ( 432+19) / "sse4_1" SSE-4.1 */
130	#define X86_FEATURE_XMM4_2 ( 432+20) / "sse4_2" SSE-4.2 */
131	#define X86_FEATURE_X2APIC ( 432+21) / x2APIC */
132	#define X86_FEATURE_MOVBE ( 432+22) / MOVBE instruction */
133	#define X86_FEATURE_POPCNT ( 432+23) / POPCNT instruction */
134	#define X86_FEATURE_TSC_DEADLINE_TIMER ( 432+24) / Tsc deadline timer */
135	#define X86_FEATURE_AES ( 432+25) / AES instructions */
136	#define X86_FEATURE_XSAVE ( 432+26) / XSAVE/XRSTOR/XSETBV/XGETBV */
137	#define X86_FEATURE_OSXSAVE ( 432+27) / "" XSAVE enabled in the OS */
138	#define X86_FEATURE_AVX ( 432+28) / Advanced Vector Extensions */
139	#define X86_FEATURE_F16C ( 432+29) / 16-bit fp conversions */
140	#define X86_FEATURE_RDRAND ( 432+30) / The RDRAND instruction */
141	#define X86_FEATURE_HYPERVISOR ( 432+31) / Running on a hypervisor */
142
143	/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
144	#define X86_FEATURE_XSTORE ( 532+ 2) / "rng" RNG present (xstore) */
145	#define X86_FEATURE_XSTORE_EN ( 532+ 3) / "rng_en" RNG enabled */
146	#define X86_FEATURE_XCRYPT ( 532+ 6) / "ace" on-CPU crypto (xcrypt) */
147	#define X86_FEATURE_XCRYPT_EN ( 532+ 7) / "ace_en" on-CPU crypto enabled */
148	#define X86_FEATURE_ACE2 ( 532+ 8) / Advanced Cryptography Engine v2 */
149	#define X86_FEATURE_ACE2_EN ( 532+ 9) / ACE v2 enabled */
150	#define X86_FEATURE_PHE ( 532+10) / PadLock Hash Engine */
151	#define X86_FEATURE_PHE_EN ( 532+11) / PHE enabled */
152	#define X86_FEATURE_PMM ( 532+12) / PadLock Montgomery Multiplier */
153	#define X86_FEATURE_PMM_EN ( 532+13) / PMM enabled */
154
155	/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
156	#define X86_FEATURE_LAHF_LM ( 632+ 0) / LAHF/SAHF in long mode */
157	#define X86_FEATURE_CMP_LEGACY ( 632+ 1) / If yes HyperThreading not valid */
158	#define X86_FEATURE_SVM ( 632+ 2) / Secure virtual machine */
159	#define X86_FEATURE_EXTAPIC ( 632+ 3) / Extended APIC space */
160	#define X86_FEATURE_CR8_LEGACY ( 632+ 4) / CR8 in 32-bit mode */
161	#define X86_FEATURE_ABM ( 632+ 5) / Advanced bit manipulation */
162	#define X86_FEATURE_SSE4A ( 632+ 6) / SSE-4A */
163	#define X86_FEATURE_MISALIGNSSE ( 632+ 7) / Misaligned SSE mode */
164	#define X86_FEATURE_3DNOWPREFETCH ( 632+ 8) / 3DNow prefetch instructions */
165	#define X86_FEATURE_OSVW ( 632+ 9) / OS Visible Workaround */
166	#define X86_FEATURE_IBS ( 632+10) / Instruction Based Sampling */
167	#define X86_FEATURE_XOP ( 632+11) / extended AVX instructions */
168	#define X86_FEATURE_SKINIT ( 632+12) / SKINIT/STGI instructions */
169	#define X86_FEATURE_WDT ( 632+13) / Watchdog timer */
170	#define X86_FEATURE_LWP ( 632+15) / Light Weight Profiling */
171	#define X86_FEATURE_FMA4 ( 632+16) / 4 operands MAC instructions */
172	#define X86_FEATURE_TCE ( 632+17) / translation cache extension */
173	#define X86_FEATURE_NODEID_MSR ( 632+19) / NodeId MSR */
174	#define X86_FEATURE_TBM ( 632+21) / trailing bit manipulations */
175	#define X86_FEATURE_TOPOEXT ( 632+22) / topology extensions CPUID leafs */
176	#define X86_FEATURE_PERFCTR_CORE ( 632+23) / core performance counter extensions */
177	#define X86_FEATURE_PERFCTR_NB ( 632+24) / NB performance counter extensions */
178	#define X86_FEATURE_BPEXT (632+26) / data breakpoint extension */
179	#define X86_FEATURE_PERFCTR_L2 ( 632+28) / L2 performance counter extensions */
180	#define X86_FEATURE_MWAITX ( 632+29) / MWAIT extension (MONITORX/MWAITX) */
181
182	/*
183	* Auxiliary flags: Linux defined - For features scattered in various
184	* CPUID levels like 0x6, 0xA etc, word 7.
185	*
186	* Reuse free bits when adding new feature flags!
187	*/
188
189	#define X86_FEATURE_CPB ( 732+ 2) / AMD Core Performance Boost */
190	#define X86_FEATURE_EPB ( 732+ 3) / IA32_ENERGY_PERF_BIAS support */
191
192	#define X86_FEATURE_HW_PSTATE ( 732+ 8) / AMD HW-PState */
193	#define X86_FEATURE_PROC_FEEDBACK ( 732+ 9) / AMD ProcFeedbackInterface */
194
195	#define X86_FEATURE_INTEL_PT ( 732+15) / Intel Processor Trace */
196
197	/* Virtualization flags: Linux defined, word 8 */
198	#define X86_FEATURE_TPR_SHADOW ( 832+ 0) / Intel TPR Shadow */
199	#define X86_FEATURE_VNMI ( 832+ 1) / Intel Virtual NMI */
200	#define X86_FEATURE_FLEXPRIORITY ( 832+ 2) / Intel FlexPriority */
201	#define X86_FEATURE_EPT ( 832+ 3) / Intel Extended Page Table */
202	#define X86_FEATURE_VPID ( 832+ 4) / Intel Virtual Processor ID */
203
204	#define X86_FEATURE_VMMCALL ( 832+15) / Prefer vmmcall to vmcall */
205	#define X86_FEATURE_XENPV ( 832+16) / "" Xen paravirtual guest */
206
207
208	/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
209	#define X86_FEATURE_FSGSBASE ( 932+ 0) / {RD/WR}{FS/GS}BASE instructions*/
210	#define X86_FEATURE_TSC_ADJUST ( 932+ 1) / TSC adjustment MSR 0x3b */
211	#define X86_FEATURE_BMI1 ( 932+ 3) / 1st group bit manipulation extensions */
212	#define X86_FEATURE_HLE ( 932+ 4) / Hardware Lock Elision */
213	#define X86_FEATURE_AVX2 ( 932+ 5) / AVX2 instructions */
214	#define X86_FEATURE_SMEP ( 932+ 7) / Supervisor Mode Execution Protection */
215	#define X86_FEATURE_BMI2 ( 932+ 8) / 2nd group bit manipulation extensions */
216	#define X86_FEATURE_ERMS ( 932+ 9) / Enhanced REP MOVSB/STOSB */
217	#define X86_FEATURE_INVPCID ( 932+10) / Invalidate Processor Context ID */
218	#define X86_FEATURE_RTM ( 932+11) / Restricted Transactional Memory */
219	#define X86_FEATURE_CQM ( 932+12) / Cache QoS Monitoring */
220	#define X86_FEATURE_MPX ( 932+14) / Memory Protection Extension */
221	#define X86_FEATURE_AVX512F ( 932+16) / AVX-512 Foundation */
222	#define X86_FEATURE_RDSEED ( 932+18) / The RDSEED instruction */
223	#define X86_FEATURE_ADX ( 932+19) / The ADCX and ADOX instructions */
224	#define X86_FEATURE_SMAP ( 932+20) / Supervisor Mode Access Prevention */
225	#define X86_FEATURE_PCOMMIT ( 932+22) / PCOMMIT instruction */
226	#define X86_FEATURE_CLFLUSHOPT ( 932+23) / CLFLUSHOPT instruction */
227	#define X86_FEATURE_CLWB ( 932+24) / CLWB instruction */
228	#define X86_FEATURE_AVX512PF ( 932+26) / AVX-512 Prefetch */
229	#define X86_FEATURE_AVX512ER ( 932+27) / AVX-512 Exponential and Reciprocal */
230	#define X86_FEATURE_AVX512CD ( 932+28) / AVX-512 Conflict Detection */
231	#define X86_FEATURE_SHA_NI ( 932+29) / SHA1/SHA256 Instruction Extensions */
232
233	/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
234	#define X86_FEATURE_XSAVEOPT (1032+ 0) / XSAVEOPT */
235	#define X86_FEATURE_XSAVEC (1032+ 1) / XSAVEC */
236	#define X86_FEATURE_XGETBV1 (1032+ 2) / XGETBV with ECX = 1 */
237	#define X86_FEATURE_XSAVES (1032+ 3) / XSAVES/XRSTORS */
238
239	/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
240	#define X86_FEATURE_CQM_LLC (1132+ 1) / LLC QoS if 1 */
241
242	/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
243	#define X86_FEATURE_CQM_OCCUP_LLC (1232+ 0) / LLC occupancy monitoring if 1 */
244
245	/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
246	#define X86_FEATURE_CLZERO (1332+0) / CLZERO instruction */
247
248	/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
249	#define X86_FEATURE_DTHERM (1432+ 0) / Digital Thermal Sensor */
250	#define X86_FEATURE_IDA (1432+ 1) / Intel Dynamic Acceleration */
251	#define X86_FEATURE_ARAT (1432+ 2) / Always Running APIC Timer */
252	#define X86_FEATURE_PLN (1432+ 4) / Intel Power Limit Notification */
253	#define X86_FEATURE_PTS (1432+ 6) / Intel Package Thermal Status */
254	#define X86_FEATURE_HWP (1432+ 7) / Intel Hardware P-states */
255	#define X86_FEATURE_HWP_NOTIFY (1432+ 8) / HWP Notification */
256	#define X86_FEATURE_HWP_ACT_WINDOW (1432+ 9) / HWP Activity Window */
257	#define X86_FEATURE_HWP_EPP (1432+10) / HWP Energy Perf. Preference */
258	#define X86_FEATURE_HWP_PKG_REQ (1432+11) / HWP Package Level Request */
259
260	/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
261	#define X86_FEATURE_NPT (1532+ 0) / Nested Page Table support */
262	#define X86_FEATURE_LBRV (1532+ 1) / LBR Virtualization support */
263	#define X86_FEATURE_SVML (1532+ 2) / "svm_lock" SVM locking MSR */
264	#define X86_FEATURE_NRIPS (1532+ 3) / "nrip_save" SVM next_rip save */
265	#define X86_FEATURE_TSCRATEMSR (1532+ 4) / "tsc_scale" TSC scaling support */
266	#define X86_FEATURE_VMCBCLEAN (1532+ 5) / "vmcb_clean" VMCB clean bits support */
267	#define X86_FEATURE_FLUSHBYASID (1532+ 6) / flush-by-ASID support */
268	#define X86_FEATURE_DECODEASSISTS (1532+ 7) / Decode Assists support */
269	#define X86_FEATURE_PAUSEFILTER (1532+10) / filtered pause intercept */
270	#define X86_FEATURE_PFTHRESHOLD (1532+12) / pause filter threshold */
271	#define X86_FEATURE_AVIC (1532+13) / Virtual Interrupt Controller */
272
273	/*
274	* BUG word(s)
275	*/
276	#define X86_BUG(x) (NCAPINTS*32 + (x))
277
278	#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
279	#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
280	#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
281	#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
282	#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
283	#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
284	#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
285	#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
286	#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
287
288	#endif /* _ASM_X86_CPUFEATURES_H */