]>
Commit | Line | Data |
---|---|---|
69c60c88 | 1 | #include <linux/export.h> |
1da177e4 | 2 | #include <linux/bitops.h> |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
c98fdeaa | 7 | #include <linux/sched.h> |
e6017571 | 8 | #include <linux/sched/clock.h> |
4e26d11f | 9 | #include <linux/random.h> |
1da177e4 | 10 | #include <asm/processor.h> |
d3f7eae1 | 11 | #include <asm/apic.h> |
1f442d70 | 12 | #include <asm/cpu.h> |
20b509bf | 13 | #include <asm/spec-ctrl.h> |
26bfa5f8 | 14 | #include <asm/smp.h> |
42937e81 | 15 | #include <asm/pci-direct.h> |
b466bdb6 | 16 | #include <asm/delay.h> |
1da177e4 | 17 | |
8d71a2ea | 18 | #ifdef CONFIG_X86_64 |
8d71a2ea | 19 | # include <asm/mmconfig.h> |
d1163651 | 20 | # include <asm/set_memory.h> |
8d71a2ea YL |
21 | #endif |
22 | ||
1da177e4 LT |
23 | #include "cpu.h" |
24 | ||
3344ed30 TG |
25 | static const int amd_erratum_383[]; |
26 | static const int amd_erratum_400[]; | |
27 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); | |
28 | ||
cc2749e4 AG |
29 | /* |
30 | * nodes_per_socket: Stores the number of nodes per socket. | |
31 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX | |
32 | * Node Identifiers[10:8] | |
33 | */ | |
34 | static u32 nodes_per_socket = 1; | |
35 | ||
2c929ce6 BP |
36 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
37 | { | |
2c929ce6 BP |
38 | u32 gprs[8] = { 0 }; |
39 | int err; | |
40 | ||
682469a5 BP |
41 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
42 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
43 | |
44 | gprs[1] = msr; | |
45 | gprs[7] = 0x9c5a203a; | |
46 | ||
47 | err = rdmsr_safe_regs(gprs); | |
48 | ||
49 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
50 | ||
51 | return err; | |
52 | } | |
53 | ||
54 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
55 | { | |
2c929ce6 BP |
56 | u32 gprs[8] = { 0 }; |
57 | ||
682469a5 BP |
58 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
59 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
60 | |
61 | gprs[0] = (u32)val; | |
62 | gprs[1] = msr; | |
63 | gprs[2] = val >> 32; | |
64 | gprs[7] = 0x9c5a203a; | |
65 | ||
66 | return wrmsr_safe_regs(gprs); | |
67 | } | |
68 | ||
1da177e4 LT |
69 | /* |
70 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
71 | * misexecution of code under Linux. Owners of such processors should | |
72 | * contact AMD for precise details and a CPU swap. | |
73 | * | |
74 | * See http://www.multimania.com/poulot/k6bug.html | |
d7de8649 AH |
75 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
76 | * (Publication # 21266 Issue Date: August 1998) | |
1da177e4 LT |
77 | * |
78 | * The following test is erm.. interesting. AMD neglected to up | |
79 | * the chip setting when fixing the bug but they also tweaked some | |
80 | * performance at the same time.. | |
81 | */ | |
fb87a298 | 82 | |
277d5b40 | 83 | extern __visible void vide(void); |
de642faf JP |
84 | __asm__(".globl vide\n" |
85 | ".type vide, @function\n" | |
86 | ".align 4\n" | |
87 | "vide: ret\n"); | |
1da177e4 | 88 | |
148f9bb8 | 89 | static void init_amd_k5(struct cpuinfo_x86 *c) |
11fdd252 | 90 | { |
26bfa5f8 | 91 | #ifdef CONFIG_X86_32 |
11fdd252 YL |
92 | /* |
93 | * General Systems BIOSen alias the cpu frequency registers | |
6a6256f9 | 94 | * of the Elan at 0x000df000. Unfortunately, one of the Linux |
11fdd252 YL |
95 | * drivers subsequently pokes it, and changes the CPU speed. |
96 | * Workaround : Remove the unneeded alias. | |
97 | */ | |
98 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
99 | #define CBAR_ENB (0x80000000) | |
100 | #define CBAR_KEY (0X000000CB) | |
101 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
102 | if (inl(CBAR) & CBAR_ENB) |
103 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 | 104 | } |
26bfa5f8 | 105 | #endif |
11fdd252 YL |
106 | } |
107 | ||
148f9bb8 | 108 | static void init_amd_k6(struct cpuinfo_x86 *c) |
11fdd252 | 109 | { |
26bfa5f8 | 110 | #ifdef CONFIG_X86_32 |
11fdd252 | 111 | u32 l, h; |
46a84132 | 112 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
11fdd252 YL |
113 | |
114 | if (c->x86_model < 6) { | |
115 | /* Based on AMD doc 20734R - June 2000 */ | |
116 | if (c->x86_model == 0) { | |
117 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
118 | set_cpu_cap(c, X86_FEATURE_PGE); | |
119 | } | |
120 | return; | |
121 | } | |
122 | ||
123 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
124 | const int K6_BUG_LOOP = 1000000; | |
125 | int n; | |
126 | void (*f_vide)(void); | |
37963666 | 127 | u64 d, d2; |
11fdd252 | 128 | |
1b74dde7 | 129 | pr_info("AMD K6 stepping B detected - "); |
11fdd252 YL |
130 | |
131 | /* | |
132 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
133 | * calls at the same time. | |
134 | */ | |
135 | ||
136 | n = K6_BUG_LOOP; | |
137 | f_vide = vide; | |
5f8a1615 | 138 | OPTIMIZER_HIDE_VAR(f_vide); |
4ea1636b | 139 | d = rdtsc(); |
11fdd252 YL |
140 | while (n--) |
141 | f_vide(); | |
4ea1636b | 142 | d2 = rdtsc(); |
11fdd252 YL |
143 | d = d2-d; |
144 | ||
145 | if (d > 20*K6_BUG_LOOP) | |
1b74dde7 | 146 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); |
11fdd252 | 147 | else |
1b74dde7 | 148 | pr_cont("probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
149 | } |
150 | ||
151 | /* K6 with old style WHCR */ | |
152 | if (c->x86_model < 8 || | |
153 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
154 | /* We can only write allocate on the low 508Mb */ | |
155 | if (mbytes > 508) | |
156 | mbytes = 508; | |
157 | ||
158 | rdmsr(MSR_K6_WHCR, l, h); | |
159 | if ((l&0x0000FFFF) == 0) { | |
160 | unsigned long flags; | |
161 | l = (1<<0)|((mbytes/4)<<1); | |
162 | local_irq_save(flags); | |
163 | wbinvd(); | |
164 | wrmsr(MSR_K6_WHCR, l, h); | |
165 | local_irq_restore(flags); | |
1b74dde7 | 166 | pr_info("Enabling old style K6 write allocation for %d Mb\n", |
11fdd252 YL |
167 | mbytes); |
168 | } | |
169 | return; | |
170 | } | |
171 | ||
172 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
173 | c->x86_model == 9 || c->x86_model == 13) { | |
174 | /* The more serious chips .. */ | |
175 | ||
176 | if (mbytes > 4092) | |
177 | mbytes = 4092; | |
178 | ||
179 | rdmsr(MSR_K6_WHCR, l, h); | |
180 | if ((l&0xFFFF0000) == 0) { | |
181 | unsigned long flags; | |
182 | l = ((mbytes>>2)<<22)|(1<<16); | |
183 | local_irq_save(flags); | |
184 | wbinvd(); | |
185 | wrmsr(MSR_K6_WHCR, l, h); | |
186 | local_irq_restore(flags); | |
1b74dde7 | 187 | pr_info("Enabling new style K6 write allocation for %d Mb\n", |
11fdd252 YL |
188 | mbytes); |
189 | } | |
190 | ||
191 | return; | |
192 | } | |
193 | ||
194 | if (c->x86_model == 10) { | |
195 | /* AMD Geode LX is model 10 */ | |
196 | /* placeholder for any needed mods */ | |
197 | return; | |
198 | } | |
26bfa5f8 | 199 | #endif |
11fdd252 YL |
200 | } |
201 | ||
26bfa5f8 | 202 | static void init_amd_k7(struct cpuinfo_x86 *c) |
1f442d70 | 203 | { |
26bfa5f8 BP |
204 | #ifdef CONFIG_X86_32 |
205 | u32 l, h; | |
206 | ||
207 | /* | |
208 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
209 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
210 | * If the BIOS didn't enable it already, enable it here. | |
211 | */ | |
212 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
213 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
1b74dde7 | 214 | pr_info("Enabling disabled K7/SSE Support.\n"); |
26bfa5f8 BP |
215 | msr_clear_bit(MSR_K7_HWCR, 15); |
216 | set_cpu_cap(c, X86_FEATURE_XMM); | |
217 | } | |
218 | } | |
219 | ||
220 | /* | |
221 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
222 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
223 | * As per AMD technical note 27212 0.2 | |
224 | */ | |
225 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
226 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
227 | if ((l & 0xfff00000) != 0x20000000) { | |
1b74dde7 CY |
228 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
229 | l, ((l & 0x000fffff)|0x20000000)); | |
26bfa5f8 BP |
230 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
231 | } | |
232 | } | |
233 | ||
234 | set_cpu_cap(c, X86_FEATURE_K7); | |
235 | ||
1f442d70 | 236 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 237 | if (!c->cpu_index) |
1f442d70 YL |
238 | return; |
239 | ||
240 | /* | |
241 | * Certain Athlons might work (for various values of 'work') in SMP | |
242 | * but they are not certified as MP capable. | |
243 | */ | |
244 | /* Athlon 660/661 is valid. */ | |
245 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
246 | (c->x86_mask == 1))) | |
1077c932 | 247 | return; |
1f442d70 YL |
248 | |
249 | /* Duron 670 is valid */ | |
250 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
1077c932 | 251 | return; |
1f442d70 YL |
252 | |
253 | /* | |
254 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
255 | * bit. It's worth noting that the A5 stepping (662) of some | |
256 | * Athlon XP's have the MP bit set. | |
257 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
258 | * more. | |
259 | */ | |
260 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
261 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
262 | (c->x86_model > 7)) | |
26bfa5f8 | 263 | if (cpu_has(c, X86_FEATURE_MP)) |
1077c932 | 264 | return; |
1f442d70 YL |
265 | |
266 | /* If we get here, not a certified SMP capable AMD system. */ | |
267 | ||
268 | /* | |
269 | * Don't taint if we are running SMP kernel on a single non-MP | |
270 | * approved Athlon | |
271 | */ | |
272 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 273 | " processors is not suitable for SMP.\n"); |
8c90487c | 274 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
6c62aa4a | 275 | #endif |
26bfa5f8 | 276 | } |
6c62aa4a | 277 | |
645a7919 | 278 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
279 | /* |
280 | * To workaround broken NUMA config. Read the comment in | |
281 | * srat_detect_node(). | |
282 | */ | |
148f9bb8 | 283 | static int nearby_node(int apicid) |
6c62aa4a YL |
284 | { |
285 | int i, node; | |
286 | ||
287 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 288 | node = __apicid_to_node[i]; |
6c62aa4a YL |
289 | if (node != NUMA_NO_NODE && node_online(node)) |
290 | return node; | |
291 | } | |
292 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 293 | node = __apicid_to_node[i]; |
6c62aa4a YL |
294 | if (node != NUMA_NO_NODE && node_online(node)) |
295 | return node; | |
296 | } | |
297 | return first_node(node_online_map); /* Shouldn't happen */ | |
298 | } | |
299 | #endif | |
11fdd252 | 300 | |
4a376ec3 | 301 | /* |
23588c38 AH |
302 | * Fixup core topology information for |
303 | * (1) AMD multi-node processors | |
304 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 305 | * (2) AMD processors supporting compute units |
4a376ec3 | 306 | */ |
c8e56d20 | 307 | #ifdef CONFIG_SMP |
148f9bb8 | 308 | static void amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 309 | { |
23588c38 | 310 | u8 node_id; |
4a376ec3 AH |
311 | int cpu = smp_processor_id(); |
312 | ||
23588c38 | 313 | /* get information required for multi-node processors */ |
362f924b | 314 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
79a8b9aa | 315 | u32 eax, ebx, ecx, edx; |
6057b4d3 | 316 | |
79a8b9aa BP |
317 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); |
318 | ||
319 | node_id = ecx & 0xff; | |
320 | smp_num_siblings = ((ebx >> 8) & 0xff) + 1; | |
321 | ||
322 | if (c->x86 == 0x15) | |
323 | c->cu_id = ebx & 0xff; | |
b6a50cdd | 324 | |
08b25963 YG |
325 | if (c->x86 >= 0x17) { |
326 | c->cpu_core_id = ebx & 0xff; | |
327 | ||
328 | if (smp_num_siblings > 1) | |
329 | c->x86_max_cores /= smp_num_siblings; | |
330 | } | |
331 | ||
b6a50cdd YG |
332 | /* |
333 | * We may have multiple LLCs if L3 caches exist, so check if we | |
334 | * have an L3 cache by looking at the L3 cache CPUID leaf. | |
335 | */ | |
336 | if (cpuid_edx(0x80000006)) { | |
337 | if (c->x86 == 0x17) { | |
338 | /* | |
339 | * LLC is at the core complex level. | |
340 | * Core complex id is ApicId[3]. | |
341 | */ | |
342 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; | |
343 | } else { | |
344 | /* LLC is at the node level. */ | |
345 | per_cpu(cpu_llc_id, cpu) = node_id; | |
346 | } | |
347 | } | |
23588c38 | 348 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
349 | u64 value; |
350 | ||
23588c38 | 351 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
23588c38 | 352 | node_id = value & 7; |
b6a50cdd YG |
353 | |
354 | per_cpu(cpu_llc_id, cpu) = node_id; | |
23588c38 | 355 | } else |
4a376ec3 AH |
356 | return; |
357 | ||
23588c38 | 358 | /* fixup multi-node processor information */ |
cc2749e4 | 359 | if (nodes_per_socket > 1) { |
d518573d | 360 | u32 cus_per_node; |
6057b4d3 | 361 | |
23588c38 | 362 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
ee6825c8 | 363 | cus_per_node = c->x86_max_cores / nodes_per_socket; |
9d260ebc | 364 | |
9e81509e | 365 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
8196dab4 | 366 | c->cpu_core_id %= cus_per_node; |
23588c38 | 367 | } |
4a376ec3 AH |
368 | } |
369 | #endif | |
370 | ||
11fdd252 | 371 | /* |
aa5e5dc2 | 372 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
11fdd252 YL |
373 | * Assumes number of cores is a power of two. |
374 | */ | |
148f9bb8 | 375 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
11fdd252 | 376 | { |
c8e56d20 | 377 | #ifdef CONFIG_SMP |
11fdd252 | 378 | unsigned bits; |
99bd0c0f | 379 | int cpu = smp_processor_id(); |
11fdd252 YL |
380 | |
381 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
382 | /* Low order bits define the core id (index of core in socket) */ |
383 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
384 | /* Convert the initial APIC ID into the socket ID */ | |
385 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
386 | /* use socket ID also for last level cache */ |
387 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 388 | amd_get_topology(c); |
11fdd252 YL |
389 | #endif |
390 | } | |
391 | ||
8b84c8df | 392 | u16 amd_get_nb_id(int cpu) |
6a812691 | 393 | { |
8b84c8df | 394 | u16 id = 0; |
6a812691 AH |
395 | #ifdef CONFIG_SMP |
396 | id = per_cpu(cpu_llc_id, cpu); | |
397 | #endif | |
398 | return id; | |
399 | } | |
400 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
401 | ||
cc2749e4 AG |
402 | u32 amd_get_nodes_per_socket(void) |
403 | { | |
404 | return nodes_per_socket; | |
405 | } | |
406 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); | |
407 | ||
148f9bb8 | 408 | static void srat_detect_node(struct cpuinfo_x86 *c) |
6c62aa4a | 409 | { |
645a7919 | 410 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
411 | int cpu = smp_processor_id(); |
412 | int node; | |
0d96b9ff | 413 | unsigned apicid = c->apicid; |
6c62aa4a | 414 | |
bbc9e2f4 TH |
415 | node = numa_cpu_node(cpu); |
416 | if (node == NUMA_NO_NODE) | |
417 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 418 | |
64be4c1c | 419 | /* |
68894632 AH |
420 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
421 | * platform-specific handler needs to be called to fixup some | |
422 | * IDs of the CPU. | |
64be4c1c | 423 | */ |
68894632 | 424 | if (x86_cpuinit.fixup_cpu_id) |
64be4c1c DB |
425 | x86_cpuinit.fixup_cpu_id(c, node); |
426 | ||
6c62aa4a | 427 | if (!node_online(node)) { |
bbc9e2f4 TH |
428 | /* |
429 | * Two possibilities here: | |
430 | * | |
431 | * - The CPU is missing memory and no node was created. In | |
432 | * that case try picking one from a nearby CPU. | |
433 | * | |
434 | * - The APIC IDs differ from the HyperTransport node IDs | |
435 | * which the K8 northbridge parsing fills in. Assume | |
436 | * they are all increased by a constant offset, but in | |
437 | * the same order as the HT nodeids. If that doesn't | |
438 | * result in a usable node fall back to the path for the | |
439 | * previous case. | |
440 | * | |
441 | * This workaround operates directly on the mapping between | |
442 | * APIC ID and NUMA node, assuming certain relationship | |
443 | * between APIC ID, HT node ID and NUMA topology. As going | |
444 | * through CPU mapping may alter the outcome, directly | |
445 | * access __apicid_to_node[]. | |
446 | */ | |
6c62aa4a YL |
447 | int ht_nodeid = c->initial_apicid; |
448 | ||
7030a7e9 | 449 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
bbc9e2f4 | 450 | node = __apicid_to_node[ht_nodeid]; |
6c62aa4a YL |
451 | /* Pick a nearby node */ |
452 | if (!node_online(node)) | |
453 | node = nearby_node(apicid); | |
454 | } | |
455 | numa_set_node(cpu, node); | |
6c62aa4a YL |
456 | #endif |
457 | } | |
458 | ||
148f9bb8 | 459 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
11fdd252 | 460 | { |
c8e56d20 | 461 | #ifdef CONFIG_SMP |
11fdd252 YL |
462 | unsigned bits, ecx; |
463 | ||
464 | /* Multi core CPU? */ | |
465 | if (c->extended_cpuid_level < 0x80000008) | |
466 | return; | |
467 | ||
468 | ecx = cpuid_ecx(0x80000008); | |
469 | ||
470 | c->x86_max_cores = (ecx & 0xff) + 1; | |
471 | ||
472 | /* CPU telling us the core id bits shift? */ | |
473 | bits = (ecx >> 12) & 0xF; | |
474 | ||
475 | /* Otherwise recompute */ | |
476 | if (bits == 0) { | |
477 | while ((1 << bits) < c->x86_max_cores) | |
478 | bits++; | |
479 | } | |
480 | ||
481 | c->x86_coreid_bits = bits; | |
482 | #endif | |
483 | } | |
484 | ||
148f9bb8 | 485 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
8fa8b035 | 486 | { |
26bfa5f8 BP |
487 | |
488 | #ifdef CONFIG_X86_64 | |
489 | if (c->x86 >= 0xf) { | |
490 | unsigned long long tseg; | |
491 | ||
492 | /* | |
493 | * Split up direct mapping around the TSEG SMM area. | |
494 | * Don't do it for gbpages because there seems very little | |
495 | * benefit in doing so. | |
496 | */ | |
497 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
498 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
499 | ||
1b74dde7 | 500 | pr_debug("tseg: %010llx\n", tseg); |
26bfa5f8 BP |
501 | if (pfn_range_is_mapped(pfn, pfn + 1)) |
502 | set_memory_4k((unsigned long)__va(tseg), 1); | |
503 | } | |
504 | } | |
505 | #endif | |
506 | ||
8fa8b035 BP |
507 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
508 | ||
509 | if (c->x86 > 0x10 || | |
510 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
511 | u64 val; | |
512 | ||
513 | rdmsrl(MSR_K7_HWCR, val); | |
514 | if (!(val & BIT(24))) | |
1b74dde7 | 515 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); |
8fa8b035 BP |
516 | } |
517 | } | |
518 | ||
519 | if (c->x86 == 0x15) { | |
520 | unsigned long upperbit; | |
521 | u32 cpuid, assoc; | |
522 | ||
523 | cpuid = cpuid_edx(0x80000005); | |
524 | assoc = cpuid >> 16 & 0xff; | |
525 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
526 | ||
527 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
528 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
4e26d11f HMG |
529 | |
530 | /* A random value per boot for bit slice [12:upper_bit) */ | |
531 | va_align.bits = get_random_int() & va_align.mask; | |
8fa8b035 | 532 | } |
b466bdb6 HR |
533 | |
534 | if (cpu_has(c, X86_FEATURE_MWAITX)) | |
535 | use_mwaitx_delay(); | |
8dfeae0d HR |
536 | |
537 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
538 | u32 ecx; | |
539 | ||
540 | ecx = cpuid_ecx(0x8000001e); | |
541 | nodes_per_socket = ((ecx >> 8) & 7) + 1; | |
542 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { | |
543 | u64 value; | |
544 | ||
545 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
546 | nodes_per_socket = ((value >> 3) & 7) + 1; | |
547 | } | |
7c60cee4 KRW |
548 | |
549 | if (c->x86 >= 0x15 && c->x86 <= 0x17) { | |
550 | unsigned int bit; | |
551 | ||
552 | switch (c->x86) { | |
553 | case 0x15: bit = 54; break; | |
554 | case 0x16: bit = 33; break; | |
555 | case 0x17: bit = 10; break; | |
556 | default: return; | |
557 | } | |
558 | /* | |
559 | * Try to cache the base value so further operations can | |
0c0f6741 | 560 | * avoid RMW. If that faults, do not enable SSBD. |
7c60cee4 KRW |
561 | */ |
562 | if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { | |
0c0f6741 KRW |
563 | setup_force_cpu_cap(X86_FEATURE_SSBD); |
564 | setup_force_cpu_cap(X86_FEATURE_AMD_SSBD); | |
565 | x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; | |
7c60cee4 KRW |
566 | } |
567 | } | |
8fa8b035 BP |
568 | } |
569 | ||
148f9bb8 | 570 | static void early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 571 | { |
11fdd252 YL |
572 | early_init_amd_mc(c); |
573 | ||
40fb1715 VP |
574 | /* |
575 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
576 | * with P/T states and does not stop in deep C-states | |
577 | */ | |
578 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 579 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
580 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
581 | } | |
5fef55fd | 582 | |
01fe03ff HR |
583 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ |
584 | if (c->x86_power & BIT(12)) | |
585 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); | |
586 | ||
6c62aa4a YL |
587 | #ifdef CONFIG_X86_64 |
588 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
589 | #else | |
5fef55fd | 590 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
591 | if (c->x86 == 5) |
592 | if (c->x86_model == 13 || c->x86_model == 9 || | |
593 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
594 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
595 | #endif | |
42937e81 | 596 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
b9d16a2a AG |
597 | /* |
598 | * ApicID can always be treated as an 8-bit value for AMD APIC versions | |
599 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we | |
600 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families | |
601 | * after 16h. | |
602 | */ | |
425d8c2f BP |
603 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
604 | if (c->x86 > 0x16) | |
42937e81 | 605 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
425d8c2f BP |
606 | else if (c->x86 >= 0xf) { |
607 | /* check CPU config space for extended APIC ID */ | |
608 | unsigned int val; | |
609 | ||
610 | val = read_pci_config(0, 24, 0, 0x68); | |
611 | if ((val >> 17 & 0x3) == 0x3) | |
612 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
613 | } | |
42937e81 AH |
614 | } |
615 | #endif | |
3b564968 | 616 | |
c1118b36 PB |
617 | /* |
618 | * This is only needed to tell the kernel whether to use VMCALL | |
619 | * and VMMCALL. VMMCALL is never executed except under virt, so | |
620 | * we can set it unconditionally. | |
621 | */ | |
622 | set_cpu_cap(c, X86_FEATURE_VMMCALL); | |
623 | ||
3b564968 | 624 | /* F16h erratum 793, CVE-2013-6885 */ |
8f86a737 BP |
625 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
626 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
2b16a235 | 627 | |
3344ed30 TG |
628 | /* |
629 | * Check whether the machine is affected by erratum 400. This is | |
630 | * used to select the proper idle routine and to enable the check | |
631 | * whether the machine is affected in arch_post_acpi_init(), which | |
632 | * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. | |
633 | */ | |
634 | if (cpu_has_amd_erratum(c, amd_erratum_400)) | |
635 | set_cpu_bug(c, X86_BUG_AMD_E400); | |
636 | } | |
e6ee94d5 | 637 | |
26bfa5f8 BP |
638 | static void init_amd_k8(struct cpuinfo_x86 *c) |
639 | { | |
640 | u32 level; | |
641 | u64 value; | |
642 | ||
643 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
644 | level = cpuid_eax(1); | |
645 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
646 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
647 | ||
648 | /* | |
649 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
650 | * (model = 0x14) and later actually support it. | |
651 | * (AMD Erratum #110, docId: 25759). | |
652 | */ | |
653 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
654 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
655 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
656 | value &= ~BIT_64(32); | |
657 | wrmsrl_amd_safe(0xc001100d, value); | |
658 | } | |
659 | } | |
660 | ||
661 | if (!c->x86_model_id[0]) | |
662 | strcpy(c->x86_model_id, "Hammer"); | |
6f9b63a0 BP |
663 | |
664 | #ifdef CONFIG_SMP | |
665 | /* | |
666 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
667 | * bit 6 of msr C001_0015 | |
668 | * | |
669 | * Errata 63 for SH-B3 steppings | |
670 | * Errata 122 for all steppings (F+ have it disabled by default) | |
671 | */ | |
672 | msr_set_bit(MSR_K7_HWCR, 6); | |
673 | #endif | |
96e5d28a | 674 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); |
26bfa5f8 BP |
675 | } |
676 | ||
677 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
678 | { | |
679 | #ifdef CONFIG_X86_64 | |
680 | /* do this for boot cpu */ | |
681 | if (c == &boot_cpu_data) | |
682 | check_enable_amd_mmconf_dmi(); | |
683 | ||
684 | fam10h_check_enable_mmcfg(); | |
685 | #endif | |
686 | ||
687 | /* | |
688 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
689 | * is always needed when GART is enabled, even in a kernel which has no | |
690 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
691 | * If it doesn't, we do it here as suggested by the BKDG. | |
692 | * | |
693 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
694 | */ | |
695 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
696 | ||
697 | /* | |
698 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
699 | * it to be converted to CD memtype. This may result in performance | |
700 | * degradation for certain nested-paging guests. Prevent this conversion | |
701 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
702 | * | |
703 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
704 | * guests on older kvm hosts. | |
705 | */ | |
706 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
707 | ||
708 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
709 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
710 | } | |
711 | ||
d1992996 EC |
712 | #define MSR_AMD64_DE_CFG 0xC0011029 |
713 | ||
714 | static void init_amd_ln(struct cpuinfo_x86 *c) | |
715 | { | |
716 | /* | |
717 | * Apply erratum 665 fix unconditionally so machines without a BIOS | |
718 | * fix work. | |
719 | */ | |
720 | msr_set_bit(MSR_AMD64_DE_CFG, 31); | |
721 | } | |
722 | ||
26bfa5f8 BP |
723 | static void init_amd_bd(struct cpuinfo_x86 *c) |
724 | { | |
725 | u64 value; | |
726 | ||
727 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
96685a55 | 728 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && |
26bfa5f8 BP |
729 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
730 | ||
731 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
732 | rdmsrl(0xc0011005, value); | |
733 | if (value & BIT_64(54)) { | |
734 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
96685a55 | 735 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); |
26bfa5f8 BP |
736 | } |
737 | } | |
738 | } | |
739 | ||
740 | /* | |
741 | * The way access filter has a performance penalty on some workloads. | |
742 | * Disable it on the affected CPUs. | |
743 | */ | |
744 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
ae8b7875 | 745 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { |
26bfa5f8 | 746 | value |= 0x1E; |
ae8b7875 | 747 | wrmsrl_safe(MSR_F15H_IC_CFG, value); |
26bfa5f8 BP |
748 | } |
749 | } | |
750 | } | |
751 | ||
44fccfc0 BP |
752 | static void init_amd_zn(struct cpuinfo_x86 *c) |
753 | { | |
754 | /* | |
755 | * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects | |
756 | * all up to and including B1. | |
757 | */ | |
758 | if (c->x86_model <= 1 && c->x86_mask <= 1) | |
759 | set_cpu_cap(c, X86_FEATURE_CPB); | |
760 | } | |
761 | ||
148f9bb8 | 762 | static void init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 763 | { |
8e8da023 | 764 | u32 dummy; |
7d318d77 | 765 | |
2b16a235 AK |
766 | early_init_amd(c); |
767 | ||
fb87a298 PC |
768 | /* |
769 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 770 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 771 | */ |
16282a8e | 772 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 773 | |
12d8a961 | 774 | if (c->x86 >= 0x10) |
6c62aa4a | 775 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
776 | |
777 | /* get apicid instead of initial apic id from cpuid */ | |
778 | c->apicid = hard_smp_processor_id(); | |
11fdd252 YL |
779 | |
780 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
781 | if (c->x86 < 6) | |
782 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
26bfa5f8 BP |
783 | |
784 | switch (c->x86) { | |
785 | case 4: init_amd_k5(c); break; | |
786 | case 5: init_amd_k6(c); break; | |
787 | case 6: init_amd_k7(c); break; | |
788 | case 0xf: init_amd_k8(c); break; | |
789 | case 0x10: init_amd_gh(c); break; | |
d1992996 | 790 | case 0x12: init_amd_ln(c); break; |
26bfa5f8 | 791 | case 0x15: init_amd_bd(c); break; |
44fccfc0 | 792 | case 0x17: init_amd_zn(c); break; |
26bfa5f8 | 793 | } |
11fdd252 | 794 | |
281b6221 RM |
795 | /* |
796 | * Enable workaround for FXSAVE leak on CPUs | |
797 | * without a XSaveErPtr feature | |
798 | */ | |
799 | if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) | |
9b13a93d | 800 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
1da177e4 | 801 | |
27c13ece | 802 | cpu_detect_cache_sizes(c); |
3dd9d514 | 803 | |
11fdd252 | 804 | /* Multi core CPU? */ |
6c62aa4a | 805 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 806 | amd_detect_cmp(c); |
6c62aa4a YL |
807 | srat_detect_node(c); |
808 | } | |
faee9a5d | 809 | |
6c62aa4a | 810 | #ifdef CONFIG_X86_32 |
11fdd252 | 811 | detect_ht(c); |
6c62aa4a | 812 | #endif |
39b3a791 | 813 | |
04a15418 | 814 | init_amd_cacheinfo(c); |
3556ddfa | 815 | |
12d8a961 | 816 | if (c->x86 >= 0xf) |
11fdd252 | 817 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 818 | |
054efb64 | 819 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
dc39f26b TL |
820 | unsigned long long val; |
821 | int ret; | |
822 | ||
bde94319 TL |
823 | /* |
824 | * A serializing LFENCE has less overhead than MFENCE, so | |
825 | * use it for execution serialization. On families which | |
826 | * don't have that MSR, LFENCE is already serializing. | |
827 | * msr_set_bit() uses the safe accessors, too, even if the MSR | |
828 | * is not present. | |
829 | */ | |
830 | msr_set_bit(MSR_F10H_DECFG, | |
831 | MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); | |
832 | ||
dc39f26b TL |
833 | /* |
834 | * Verify that the MSR write was successful (could be running | |
835 | * under a hypervisor) and only then assume that LFENCE is | |
836 | * serializing. | |
837 | */ | |
838 | ret = rdmsrl_safe(MSR_F10H_DECFG, &val); | |
839 | if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { | |
840 | /* A serializing LFENCE stops RDTSC speculation */ | |
841 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
842 | } else { | |
843 | /* MFENCE stops RDTSC speculation */ | |
844 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
845 | } | |
11fdd252 | 846 | } |
6c62aa4a | 847 | |
e9cdd343 BO |
848 | /* |
849 | * Family 0x12 and above processors have APIC timer | |
850 | * running in deep C states. | |
851 | */ | |
852 | if (c->x86 > 0x11) | |
b87cf80a | 853 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d | 854 | |
8e8da023 | 855 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
a930dc45 BP |
856 | |
857 | /* 3DNow or LM implies PREFETCHW */ | |
858 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) | |
859 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) | |
860 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); | |
61f01dd9 | 861 | |
def9331a JG |
862 | /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ |
863 | if (!cpu_has(c, X86_FEATURE_XENPV)) | |
864 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); | |
f93a37e2 TL |
865 | |
866 | /* AMD speculative control support */ | |
867 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
868 | pr_info_once("FEATURE SPEC_CTRL Present\n"); | |
869 | set_ibrs_supported(); | |
870 | set_ibpb_supported(); | |
871 | if (ibrs_inuse) | |
872 | sysctl_ibrs_enabled = 1; | |
873 | if (ibpb_inuse) | |
874 | sysctl_ibpb_enabled = 1; | |
875 | } else if (cpu_has(c, X86_FEATURE_IBPB)) { | |
876 | pr_info_once("FEATURE SPEC_CTRL Not Present\n"); | |
877 | pr_info_once("FEATURE IBPB Present\n"); | |
878 | set_ibpb_supported(); | |
879 | if (ibpb_inuse) | |
880 | sysctl_ibpb_enabled = 1; | |
881 | } else { | |
882 | pr_info_once("FEATURE SPEC_CTRL Not Present\n"); | |
883 | pr_info_once("FEATURE IBPB Not Present\n"); | |
884 | /* | |
885 | * On AMD processors that do not support the speculative | |
886 | * control features, IBPB type support can be achieved by | |
887 | * disabling indirect branch predictor support. | |
888 | */ | |
889 | if (!ibpb_disabled) { | |
890 | u64 val; | |
891 | ||
892 | switch (c->x86) { | |
893 | case 0x10: | |
894 | case 0x12: | |
895 | case 0x16: | |
896 | pr_info_once("Disabling indirect branch predictor support\n"); | |
897 | rdmsrl(MSR_F15H_IC_CFG, val); | |
898 | val |= MSR_F15H_IC_CFG_DIS_IND; | |
899 | wrmsrl(MSR_F15H_IC_CFG, val); | |
900 | break; | |
901 | } | |
902 | } | |
903 | } | |
7c60cee4 | 904 | |
0c0f6741 KRW |
905 | if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) { |
906 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
907 | set_cpu_cap(c, X86_FEATURE_AMD_SSBD); | |
7c60cee4 | 908 | } |
1da177e4 LT |
909 | } |
910 | ||
6c62aa4a | 911 | #ifdef CONFIG_X86_32 |
148f9bb8 | 912 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
913 | { |
914 | /* AMD errata T13 (order #21922) */ | |
915 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
916 | /* Duron Rev A0 */ |
917 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 918 | size = 64; |
8bdbd962 | 919 | /* Tbird rev A1/A2 */ |
1da177e4 | 920 | if (c->x86_model == 4 && |
8bdbd962 | 921 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
922 | size = 256; |
923 | } | |
924 | return size; | |
925 | } | |
6c62aa4a | 926 | #endif |
1da177e4 | 927 | |
148f9bb8 | 928 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
b46882e4 BP |
929 | { |
930 | u32 ebx, eax, ecx, edx; | |
931 | u16 mask = 0xfff; | |
932 | ||
933 | if (c->x86 < 0xf) | |
934 | return; | |
935 | ||
936 | if (c->extended_cpuid_level < 0x80000006) | |
937 | return; | |
938 | ||
939 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
940 | ||
941 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
942 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
943 | ||
944 | /* | |
945 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
946 | * characteristics from the CPUID function 0x80000005 instead. | |
947 | */ | |
948 | if (c->x86 == 0xf) { | |
949 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
950 | mask = 0xff; | |
951 | } | |
952 | ||
953 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
d1393367 BP |
954 | if (!((eax >> 16) & mask)) |
955 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
956 | else | |
b46882e4 | 957 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
b46882e4 BP |
958 | |
959 | /* a 4M entry uses two 2M entries */ | |
960 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
961 | ||
962 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
963 | if (!(eax & mask)) { | |
964 | /* Erratum 658 */ | |
965 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
966 | tlb_lli_2m[ENTRIES] = 1024; | |
967 | } else { | |
968 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
969 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
970 | } | |
971 | } else | |
972 | tlb_lli_2m[ENTRIES] = eax & mask; | |
973 | ||
974 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
975 | } | |
976 | ||
148f9bb8 | 977 | static const struct cpu_dev amd_cpu_dev = { |
1da177e4 | 978 | .c_vendor = "AMD", |
fb87a298 | 979 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 980 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
981 | .legacy_models = { |
982 | { .family = 4, .model_names = | |
1da177e4 LT |
983 | { |
984 | [3] = "486 DX/2", | |
985 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
986 | [8] = "486 DX/4", |
987 | [9] = "486 DX/4-WB", | |
1da177e4 | 988 | [14] = "Am5x86-WT", |
fb87a298 | 989 | [15] = "Am5x86-WB" |
1da177e4 LT |
990 | } |
991 | }, | |
992 | }, | |
09dc68d9 | 993 | .legacy_cache_size = amd_size_cache, |
6c62aa4a | 994 | #endif |
03ae5768 | 995 | .c_early_init = early_init_amd, |
b46882e4 | 996 | .c_detect_tlb = cpu_detect_tlb_amd, |
8fa8b035 | 997 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 998 | .c_init = init_amd, |
10a434fc | 999 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
1000 | }; |
1001 | ||
10a434fc | 1002 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
1003 | |
1004 | /* | |
1005 | * AMD errata checking | |
1006 | * | |
1007 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
1008 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
1009 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
1010 | * variable number of family-specific model-stepping ranges created by | |
7d7dc116 | 1011 | * AMD_MODEL_RANGE(). |
d78d671d HR |
1012 | * |
1013 | * Example: | |
1014 | * | |
1015 | * const int amd_erratum_319[] = | |
1016 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
1017 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
1018 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
1019 | */ | |
1020 | ||
7d7dc116 BP |
1021 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
1022 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
1023 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
1024 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
1025 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
1026 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
1027 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
1028 | ||
1029 | static const int amd_erratum_400[] = | |
328935e6 | 1030 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 HR |
1031 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
1032 | ||
e6ee94d5 | 1033 | static const int amd_erratum_383[] = |
1be85a6d | 1034 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
9d8888c2 | 1035 | |
8c6b79bb TK |
1036 | |
1037 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
d78d671d | 1038 | { |
d78d671d HR |
1039 | int osvw_id = *erratum++; |
1040 | u32 range; | |
1041 | u32 ms; | |
1042 | ||
d78d671d HR |
1043 | if (osvw_id >= 0 && osvw_id < 65536 && |
1044 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
1045 | u64 osvw_len; | |
1046 | ||
1047 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
1048 | if (osvw_id < osvw_len) { | |
1049 | u64 osvw_bits; | |
1050 | ||
1051 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
1052 | osvw_bits); | |
1053 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 1058 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
1059 | while ((range = *erratum++)) |
1060 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
1061 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
1062 | (ms <= AMD_MODEL_RANGE_END(range))) | |
1063 | return true; | |
1064 | ||
1065 | return false; | |
1066 | } | |
d6d55f0b JS |
1067 | |
1068 | void set_dr_addr_mask(unsigned long mask, int dr) | |
1069 | { | |
362f924b | 1070 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) |
d6d55f0b JS |
1071 | return; |
1072 | ||
1073 | switch (dr) { | |
1074 | case 0: | |
1075 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); | |
1076 | break; | |
1077 | case 1: | |
1078 | case 2: | |
1079 | case 3: | |
1080 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); | |
1081 | break; | |
1082 | default: | |
1083 | break; | |
1084 | } | |
1085 | } |