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1353ebb4 | 1 | /* |
1353ebb4 JF |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Cyrix stuff, June 1998 by: | |
5 | * - Rafael R. Reilova (moved everything from head.S), | |
6 | * <rreilova@ececs.uc.edu> | |
7 | * - Channing Corn (tests & fixes), | |
8 | * - Andrew D. Balsa (code cleanup). | |
9 | */ | |
10 | #include <linux/init.h> | |
11 | #include <linux/utsname.h> | |
6d283d72 | 12 | #include <linux/cpu.h> |
86cdbc59 | 13 | #include <linux/smp.h> |
1de873cb TG |
14 | #include <linux/nospec.h> |
15 | #include <linux/prctl.h> | |
687cc97a | 16 | |
20b509bf | 17 | #include <asm/spec-ctrl.h> |
687cc97a | 18 | #include <asm/cmdline.h> |
91eb1b79 | 19 | #include <asm/bugs.h> |
1353ebb4 | 20 | #include <asm/processor.h> |
7ebad705 | 21 | #include <asm/processor-flags.h> |
952f07ec | 22 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
23 | #include <asm/msr.h> |
24 | #include <asm/paravirt.h> | |
25 | #include <asm/alternative.h> | |
62a67e12 | 26 | #include <asm/pgtable.h> |
d1163651 | 27 | #include <asm/set_memory.h> |
12aa317c | 28 | #include <asm/intel-family.h> |
1353ebb4 | 29 | |
687cc97a | 30 | static void __init spectre_v2_select_mitigation(void); |
ef68a13e | 31 | static void __init ssb_select_mitigation(void); |
687cc97a | 32 | |
3ef956dd KRW |
33 | /* |
34 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
35 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
36 | */ | |
0b35aca2 | 37 | u64 __ro_after_init x86_spec_ctrl_base; |
adae8f0d | 38 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
3ef956dd | 39 | |
ca6704cf KRW |
40 | /* |
41 | * The vendor and possibly platform specific bits which can be modified in | |
42 | * x86_spec_ctrl_base. | |
43 | */ | |
4e1f9641 | 44 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
ca6704cf | 45 | |
7c60cee4 KRW |
46 | /* |
47 | * AMD specific MSR info for Speculative Store Bypass control. | |
0c0f6741 | 48 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
7c60cee4 KRW |
49 | */ |
50 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
0c0f6741 | 51 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
7c60cee4 | 52 | |
1353ebb4 JF |
53 | void __init check_bugs(void) |
54 | { | |
55 | identify_boot_cpu(); | |
55a36b65 | 56 | |
62a67e12 BP |
57 | if (!IS_ENABLED(CONFIG_SMP)) { |
58 | pr_info("CPU: "); | |
59 | print_cpu_info(&boot_cpu_data); | |
60 | } | |
61 | ||
3ef956dd KRW |
62 | /* |
63 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
7c60cee4 KRW |
64 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
65 | * init code as it is not enumerated and depends on the family. | |
3ef956dd | 66 | */ |
200e837f | 67 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
3ef956dd KRW |
68 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
69 | ||
687cc97a DW |
70 | /* Select the proper spectre mitigation before patching alternatives */ |
71 | spectre_v2_select_mitigation(); | |
72 | ||
ef68a13e KRW |
73 | /* |
74 | * Select proper mitigation for any exposure to the Speculative Store | |
75 | * Bypass vulnerability. | |
76 | */ | |
77 | ssb_select_mitigation(); | |
78 | ||
62a67e12 | 79 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
80 | /* |
81 | * Check whether we are able to run this kernel safely on SMP. | |
82 | * | |
83 | * - i386 is no longer supported. | |
84 | * - In order to run on anything without a TSC, we need to be | |
85 | * compiled for a i486. | |
86 | */ | |
87 | if (boot_cpu_data.x86 < 4) | |
88 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
89 | ||
bfe4bb15 MV |
90 | init_utsname()->machine[1] = |
91 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 92 | alternative_instructions(); |
304bceda | 93 | |
4d164092 | 94 | fpu__init_check_bugs(); |
62a67e12 BP |
95 | #else /* CONFIG_X86_64 */ |
96 | alternative_instructions(); | |
97 | ||
98 | /* | |
99 | * Make sure the first 2MB area is not mapped by huge pages | |
100 | * There are typically fixed size MTRRs in there and overlapping | |
101 | * MTRRs into large pages causes slow downs. | |
102 | * | |
103 | * Right now we don't do that with gbpages because there seems | |
104 | * very little benefit for that case. | |
105 | */ | |
106 | if (!direct_gbpages) | |
107 | set_memory_4k((unsigned long)__va(0), 1); | |
108 | #endif | |
1353ebb4 | 109 | } |
6d283d72 | 110 | |
687cc97a DW |
111 | /* The kernel command line selection */ |
112 | enum spectre_v2_mitigation_cmd { | |
113 | SPECTRE_V2_CMD_NONE, | |
114 | SPECTRE_V2_CMD_AUTO, | |
115 | SPECTRE_V2_CMD_FORCE, | |
116 | SPECTRE_V2_CMD_RETPOLINE, | |
117 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
118 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
119 | }; | |
120 | ||
121 | static const char *spectre_v2_strings[] = { | |
122 | [SPECTRE_V2_NONE] = "Vulnerable", | |
123 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
124 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
125 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
126 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
127 | }; | |
128 | ||
129 | #undef pr_fmt | |
130 | #define pr_fmt(fmt) "Spectre V2 mitigation: " fmt | |
131 | ||
ed0cbc9e KC |
132 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
133 | SPECTRE_V2_NONE; | |
687cc97a | 134 | |
3a403df4 BP |
135 | void |
136 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
fe170612 | 137 | { |
4e1f9641 | 138 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
3a403df4 | 139 | struct thread_info *ti = current_thread_info(); |
0b35aca2 | 140 | |
200e837f | 141 | /* Is MSR_SPEC_CTRL implemented ? */ |
3a403df4 | 142 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
4e1f9641 TG |
143 | /* |
144 | * Restrict guest_spec_ctrl to supported values. Clear the | |
145 | * modifiable bits in the host base value and or the | |
146 | * modifiable bits from the guest value. | |
147 | */ | |
148 | guestval = hostval & ~x86_spec_ctrl_mask; | |
149 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
150 | ||
3a403df4 BP |
151 | /* SSBD controlled in MSR_SPEC_CTRL */ |
152 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
4e1f9641 | 153 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
3a403df4 | 154 | |
4e1f9641 TG |
155 | if (hostval != guestval) { |
156 | msrval = setguest ? guestval : hostval; | |
157 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
3a403df4 BP |
158 | } |
159 | } | |
fe170612 | 160 | } |
3a403df4 | 161 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
fe170612 | 162 | |
0c0f6741 | 163 | static void x86_amd_ssb_disable(void) |
7c60cee4 | 164 | { |
0c0f6741 | 165 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
7c60cee4 | 166 | |
08e65b2a TL |
167 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
168 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
169 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
7c60cee4 KRW |
170 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
171 | } | |
172 | ||
687cc97a DW |
173 | static void __init spec2_print_if_insecure(const char *reason) |
174 | { | |
175 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
176 | pr_info("%s\n", reason); | |
177 | } | |
178 | ||
179 | static void __init spec2_print_if_secure(const char *reason) | |
180 | { | |
181 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
182 | pr_info("%s\n", reason); | |
183 | } | |
184 | ||
185 | static inline bool retp_compiler(void) | |
186 | { | |
187 | return __is_defined(RETPOLINE); | |
188 | } | |
189 | ||
190 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
191 | { | |
192 | int len = strlen(opt); | |
193 | ||
194 | return len == arglen && !strncmp(arg, opt, len); | |
195 | } | |
196 | ||
197 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) | |
198 | { | |
199 | char arg[20]; | |
200 | int ret; | |
201 | ||
202 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, | |
203 | sizeof(arg)); | |
204 | if (ret > 0) { | |
205 | if (match_option(arg, ret, "off")) { | |
206 | goto disable; | |
207 | } else if (match_option(arg, ret, "on")) { | |
208 | spec2_print_if_secure("force enabled on command line."); | |
209 | return SPECTRE_V2_CMD_FORCE; | |
210 | } else if (match_option(arg, ret, "retpoline")) { | |
211 | spec2_print_if_insecure("retpoline selected on command line."); | |
212 | return SPECTRE_V2_CMD_RETPOLINE; | |
213 | } else if (match_option(arg, ret, "retpoline,amd")) { | |
214 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
215 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
216 | return SPECTRE_V2_CMD_AUTO; | |
217 | } | |
218 | spec2_print_if_insecure("AMD retpoline selected on command line."); | |
219 | return SPECTRE_V2_CMD_RETPOLINE_AMD; | |
220 | } else if (match_option(arg, ret, "retpoline,generic")) { | |
221 | spec2_print_if_insecure("generic retpoline selected on command line."); | |
222 | return SPECTRE_V2_CMD_RETPOLINE_GENERIC; | |
223 | } else if (match_option(arg, ret, "auto")) { | |
224 | return SPECTRE_V2_CMD_AUTO; | |
225 | } | |
226 | } | |
227 | ||
228 | if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
229 | return SPECTRE_V2_CMD_AUTO; | |
230 | disable: | |
231 | spec2_print_if_insecure("disabled on command line."); | |
232 | return SPECTRE_V2_CMD_NONE; | |
233 | } | |
234 | ||
12aa317c DW |
235 | /* Check for Skylake-like CPUs (for RSB handling) */ |
236 | static bool __init is_skylake_era(void) | |
237 | { | |
238 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
239 | boot_cpu_data.x86 == 6) { | |
240 | switch (boot_cpu_data.x86_model) { | |
241 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
242 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
243 | case INTEL_FAM6_SKYLAKE_X: | |
244 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
245 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
246 | return true; | |
247 | } | |
248 | } | |
249 | return false; | |
250 | } | |
251 | ||
687cc97a DW |
252 | static void __init spectre_v2_select_mitigation(void) |
253 | { | |
254 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
255 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
256 | ||
257 | /* | |
258 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
259 | * then nothing to do. | |
260 | */ | |
261 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
262 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
263 | return; | |
264 | ||
265 | switch (cmd) { | |
266 | case SPECTRE_V2_CMD_NONE: | |
267 | return; | |
268 | ||
269 | case SPECTRE_V2_CMD_FORCE: | |
270 | /* FALLTRHU */ | |
271 | case SPECTRE_V2_CMD_AUTO: | |
272 | goto retpoline_auto; | |
273 | ||
274 | case SPECTRE_V2_CMD_RETPOLINE_AMD: | |
275 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
276 | goto retpoline_amd; | |
277 | break; | |
278 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
279 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
280 | goto retpoline_generic; | |
281 | break; | |
282 | case SPECTRE_V2_CMD_RETPOLINE: | |
283 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
284 | goto retpoline_auto; | |
285 | break; | |
286 | } | |
287 | pr_err("kernel not compiled with retpoline; no mitigation available!"); | |
288 | return; | |
289 | ||
290 | retpoline_auto: | |
291 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
292 | retpoline_amd: | |
293 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
294 | pr_err("LFENCE not serializing. Switching to generic retpoline\n"); | |
295 | goto retpoline_generic; | |
296 | } | |
297 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
298 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
299 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
300 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
301 | } else { | |
302 | retpoline_generic: | |
303 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
304 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
305 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
306 | } | |
307 | ||
308 | spectre_v2_enabled = mode; | |
309 | pr_info("%s\n", spectre_v2_strings[mode]); | |
12aa317c | 310 | |
86cdbc59 AW |
311 | pr_info("Speculation control IBPB %s IBRS %s", |
312 | ibpb_supported ? "supported" : "not-supported", | |
313 | ibrs_supported ? "supported" : "not-supported"); | |
314 | ||
315 | /* | |
316 | * If we have a full retpoline mode and then disable IBPB in kernel mode | |
317 | * we do not require both. | |
318 | */ | |
319 | if (mode == SPECTRE_V2_RETPOLINE_AMD || | |
320 | mode == SPECTRE_V2_RETPOLINE_GENERIC) | |
321 | { | |
322 | if (ibrs_supported) { | |
323 | pr_info("Retpoline compiled kernel. Defaulting IBRS to disabled"); | |
324 | set_ibrs_disabled(); | |
325 | if (!ibrs_inuse) | |
326 | sysctl_ibrs_enabled = 0; | |
327 | } | |
328 | } | |
329 | ||
12aa317c DW |
330 | /* |
331 | * If neither SMEP or KPTI are available, there is a risk of | |
332 | * hitting userspace addresses in the RSB after a context switch | |
333 | * from a shallow call stack to a deeper one. To prevent this fill | |
334 | * the entire RSB, even when using IBRS. | |
335 | * | |
336 | * Skylake era CPUs have a separate issue with *underflow* of the | |
337 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
338 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
339 | * or deactivated in favour of retpolines the RSB fill on context | |
340 | * switch is required. | |
341 | */ | |
342 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
343 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
344 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
345 | pr_info("Filling RSB on context switch\n"); | |
346 | } | |
687cc97a DW |
347 | } |
348 | ||
ef68a13e KRW |
349 | #undef pr_fmt |
350 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
351 | ||
ed0cbc9e | 352 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
ef68a13e KRW |
353 | |
354 | /* The kernel command line selection */ | |
355 | enum ssb_mitigation_cmd { | |
356 | SPEC_STORE_BYPASS_CMD_NONE, | |
357 | SPEC_STORE_BYPASS_CMD_AUTO, | |
358 | SPEC_STORE_BYPASS_CMD_ON, | |
1de873cb | 359 | SPEC_STORE_BYPASS_CMD_PRCTL, |
4eae6d51 | 360 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
ef68a13e KRW |
361 | }; |
362 | ||
363 | static const char *ssb_strings[] = { | |
364 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
1de873cb | 365 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
4eae6d51 KC |
366 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
367 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
ef68a13e KRW |
368 | }; |
369 | ||
370 | static const struct { | |
371 | const char *option; | |
372 | enum ssb_mitigation_cmd cmd; | |
373 | } ssb_mitigation_options[] = { | |
4eae6d51 KC |
374 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
375 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
376 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
377 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
378 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
ef68a13e KRW |
379 | }; |
380 | ||
381 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
382 | { | |
383 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
384 | char arg[20]; | |
385 | int ret, i; | |
386 | ||
387 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
388 | return SPEC_STORE_BYPASS_CMD_NONE; | |
389 | } else { | |
390 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
391 | arg, sizeof(arg)); | |
392 | if (ret < 0) | |
393 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
394 | ||
395 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
396 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
397 | continue; | |
398 | ||
399 | cmd = ssb_mitigation_options[i].cmd; | |
400 | break; | |
401 | } | |
402 | ||
403 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
404 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
405 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
406 | } | |
407 | } | |
408 | ||
409 | return cmd; | |
410 | } | |
411 | ||
7124b2d7 | 412 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
ef68a13e KRW |
413 | { |
414 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
415 | enum ssb_mitigation_cmd cmd; | |
416 | ||
0c0f6741 | 417 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
ef68a13e KRW |
418 | return mode; |
419 | ||
420 | cmd = ssb_parse_cmdline(); | |
421 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
422 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
423 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
424 | return mode; | |
425 | ||
426 | switch (cmd) { | |
427 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
4eae6d51 KC |
428 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
429 | /* | |
430 | * Choose prctl+seccomp as the default mode if seccomp is | |
431 | * enabled. | |
432 | */ | |
433 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
434 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
435 | else | |
436 | mode = SPEC_STORE_BYPASS_PRCTL; | |
1de873cb | 437 | break; |
ef68a13e KRW |
438 | case SPEC_STORE_BYPASS_CMD_ON: |
439 | mode = SPEC_STORE_BYPASS_DISABLE; | |
440 | break; | |
1de873cb TG |
441 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
442 | mode = SPEC_STORE_BYPASS_PRCTL; | |
443 | break; | |
ef68a13e KRW |
444 | case SPEC_STORE_BYPASS_CMD_NONE: |
445 | break; | |
446 | } | |
447 | ||
2b83aba8 KRW |
448 | /* |
449 | * We have three CPU feature flags that are in play here: | |
450 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
0c0f6741 | 451 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
2b83aba8 KRW |
452 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
453 | */ | |
1de873cb | 454 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
ef68a13e | 455 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
2b83aba8 KRW |
456 | /* |
457 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses | |
458 | * a completely different MSR and bit dependent on family. | |
459 | */ | |
460 | switch (boot_cpu_data.x86_vendor) { | |
461 | case X86_VENDOR_INTEL: | |
0c0f6741 | 462 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
4e1f9641 | 463 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
adb60371 | 464 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
2b83aba8 KRW |
465 | break; |
466 | case X86_VENDOR_AMD: | |
0c0f6741 | 467 | x86_amd_ssb_disable(); |
2b83aba8 KRW |
468 | break; |
469 | } | |
470 | } | |
471 | ||
ef68a13e KRW |
472 | return mode; |
473 | } | |
474 | ||
d762db65 | 475 | static void ssb_select_mitigation(void) |
ef68a13e KRW |
476 | { |
477 | ssb_mode = __ssb_select_mitigation(); | |
478 | ||
479 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
480 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
481 | } | |
482 | ||
687cc97a | 483 | #undef pr_fmt |
4eae6d51 | 484 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
687cc97a | 485 | |
bd90e222 | 486 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
1de873cb | 487 | { |
e29928d4 | 488 | bool update; |
1de873cb | 489 | |
4eae6d51 KC |
490 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
491 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
1de873cb TG |
492 | return -ENXIO; |
493 | ||
e29928d4 TG |
494 | switch (ctrl) { |
495 | case PR_SPEC_ENABLE: | |
496 | /* If speculation is force disabled, enable is not allowed */ | |
497 | if (task_spec_ssb_force_disable(task)) | |
498 | return -EPERM; | |
499 | task_clear_spec_ssb_disable(task); | |
0c0f6741 | 500 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
e29928d4 TG |
501 | break; |
502 | case PR_SPEC_DISABLE: | |
503 | task_set_spec_ssb_disable(task); | |
0c0f6741 | 504 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
e29928d4 TG |
505 | break; |
506 | case PR_SPEC_FORCE_DISABLE: | |
507 | task_set_spec_ssb_disable(task); | |
508 | task_set_spec_ssb_force_disable(task); | |
0c0f6741 | 509 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
e29928d4 TG |
510 | break; |
511 | default: | |
512 | return -ERANGE; | |
513 | } | |
1de873cb | 514 | |
bd90e222 KC |
515 | /* |
516 | * If being set on non-current task, delay setting the CPU | |
517 | * mitigation until it is next scheduled. | |
518 | */ | |
e29928d4 | 519 | if (task == current && update) |
559c7a59 | 520 | speculative_store_bypass_update_current(); |
1de873cb TG |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
32e3c480 TG |
525 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
526 | unsigned long ctrl) | |
527 | { | |
528 | switch (which) { | |
529 | case PR_SPEC_STORE_BYPASS: | |
530 | return ssb_prctl_set(task, ctrl); | |
531 | default: | |
532 | return -ENODEV; | |
533 | } | |
534 | } | |
535 | ||
536 | #ifdef CONFIG_SECCOMP | |
537 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
538 | { | |
4eae6d51 KC |
539 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
540 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
32e3c480 TG |
541 | } |
542 | #endif | |
543 | ||
bd90e222 | 544 | static int ssb_prctl_get(struct task_struct *task) |
1de873cb TG |
545 | { |
546 | switch (ssb_mode) { | |
547 | case SPEC_STORE_BYPASS_DISABLE: | |
548 | return PR_SPEC_DISABLE; | |
4eae6d51 | 549 | case SPEC_STORE_BYPASS_SECCOMP: |
1de873cb | 550 | case SPEC_STORE_BYPASS_PRCTL: |
e29928d4 TG |
551 | if (task_spec_ssb_force_disable(task)) |
552 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
553 | if (task_spec_ssb_disable(task)) | |
1de873cb TG |
554 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
555 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
556 | default: | |
557 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
558 | return PR_SPEC_ENABLE; | |
559 | return PR_SPEC_NOT_AFFECTED; | |
560 | } | |
561 | } | |
562 | ||
bd90e222 | 563 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
1de873cb TG |
564 | { |
565 | switch (which) { | |
566 | case PR_SPEC_STORE_BYPASS: | |
bd90e222 | 567 | return ssb_prctl_get(task); |
1de873cb TG |
568 | default: |
569 | return -ENODEV; | |
570 | } | |
571 | } | |
572 | ||
2b83aba8 KRW |
573 | void x86_spec_ctrl_setup_ap(void) |
574 | { | |
200e837f | 575 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
adb60371 | 576 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
7c60cee4 KRW |
577 | |
578 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
0c0f6741 | 579 | x86_amd_ssb_disable(); |
2b83aba8 KRW |
580 | } |
581 | ||
6d283d72 | 582 | #ifdef CONFIG_SYSFS |
d4c8cc47 | 583 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
d762db65 | 584 | char *buf, unsigned int bug) |
6d283d72 | 585 | { |
8f04f8ba | 586 | if (!boot_cpu_has_bug(bug)) |
6d283d72 | 587 | return sprintf(buf, "Not affected\n"); |
8f04f8ba KRW |
588 | |
589 | switch (bug) { | |
590 | case X86_BUG_CPU_MELTDOWN: | |
591 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
592 | return sprintf(buf, "Mitigation: PTI\n"); | |
593 | break; | |
594 | ||
595 | case X86_BUG_SPECTRE_V1: | |
596 | if (osb_is_enabled) | |
597 | return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n"); | |
598 | ||
599 | case X86_BUG_SPECTRE_V2: | |
600 | return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : ""); | |
601 | ||
ef68a13e KRW |
602 | case X86_BUG_SPEC_STORE_BYPASS: |
603 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
604 | ||
8f04f8ba KRW |
605 | default: |
606 | break; | |
607 | } | |
608 | ||
6d283d72 TG |
609 | return sprintf(buf, "Vulnerable\n"); |
610 | } | |
611 | ||
8f04f8ba KRW |
612 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, |
613 | char *buf) | |
6d283d72 | 614 | { |
8f04f8ba | 615 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); |
6d283d72 TG |
616 | } |
617 | ||
8f04f8ba KRW |
618 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, |
619 | char *buf) | |
6d283d72 | 620 | { |
8f04f8ba KRW |
621 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
622 | } | |
687cc97a | 623 | |
8f04f8ba KRW |
624 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, |
625 | char *buf) | |
626 | { | |
627 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); | |
6d283d72 | 628 | } |
abe4b60b KRW |
629 | |
630 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
631 | { | |
632 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
633 | } | |
6d283d72 | 634 | #endif |