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1da177e4 LT |
1 | #include <linux/kernel.h> |
2 | ||
3 | #include <linux/string.h> | |
4 | #include <linux/bitops.h> | |
5 | #include <linux/smp.h> | |
83ce4009 | 6 | #include <linux/sched.h> |
e6017571 | 7 | #include <linux/sched/clock.h> |
1da177e4 | 8 | #include <linux/thread_info.h> |
186f4360 | 9 | #include <linux/init.h> |
8bdbd962 | 10 | #include <linux/uaccess.h> |
1da177e4 | 11 | |
cd4d09ec | 12 | #include <asm/cpufeature.h> |
d72b1b4f | 13 | #include <asm/pgtable.h> |
1da177e4 | 14 | #include <asm/msr.h> |
73bdb73f | 15 | #include <asm/bugs.h> |
1f442d70 | 16 | #include <asm/cpu.h> |
08e237fa | 17 | #include <asm/intel-family.h> |
4167709b | 18 | #include <asm/microcode_intel.h> |
e16fd002 GA |
19 | #include <asm/hwcap2.h> |
20 | #include <asm/elf.h> | |
1da177e4 | 21 | |
185f3b9d | 22 | #ifdef CONFIG_X86_64 |
8bdbd962 | 23 | #include <linux/topology.h> |
185f3b9d YL |
24 | #endif |
25 | ||
1da177e4 LT |
26 | #include "cpu.h" |
27 | ||
28 | #ifdef CONFIG_X86_LOCAL_APIC | |
29 | #include <asm/mpspec.h> | |
30 | #include <asm/apic.h> | |
1da177e4 LT |
31 | #endif |
32 | ||
0f6ff2bc DH |
33 | /* |
34 | * Just in case our CPU detection goes bad, or you have a weird system, | |
35 | * allow a way to override the automatic disabling of MPX. | |
36 | */ | |
37 | static int forcempx; | |
38 | ||
39 | static int __init forcempx_setup(char *__unused) | |
40 | { | |
41 | forcempx = 1; | |
42 | ||
43 | return 1; | |
44 | } | |
45 | __setup("intel-skd-046-workaround=disable", forcempx_setup); | |
46 | ||
47 | void check_mpx_erratum(struct cpuinfo_x86 *c) | |
48 | { | |
49 | if (forcempx) | |
50 | return; | |
51 | /* | |
52 | * Turn off the MPX feature on CPUs where SMEP is not | |
53 | * available or disabled. | |
54 | * | |
55 | * Works around Intel Erratum SKD046: "Branch Instructions | |
56 | * May Initialize MPX Bound Registers Incorrectly". | |
57 | * | |
58 | * This might falsely disable MPX on systems without | |
59 | * SMEP, like Atom processors without SMEP. But there | |
60 | * is no such hardware known at the moment. | |
61 | */ | |
62 | if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { | |
63 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
64 | pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); | |
65 | } | |
66 | } | |
67 | ||
e16fd002 GA |
68 | static bool ring3mwait_disabled __read_mostly; |
69 | ||
70 | static int __init ring3mwait_disable(char *__unused) | |
71 | { | |
72 | ring3mwait_disabled = true; | |
73 | return 0; | |
74 | } | |
75 | __setup("ring3mwait=disable", ring3mwait_disable); | |
76 | ||
77 | static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) | |
78 | { | |
79 | /* | |
80 | * Ring 3 MONITOR/MWAIT feature cannot be detected without | |
81 | * cpu model and family comparison. | |
82 | */ | |
4d8bb006 | 83 | if (c->x86 != 6) |
e16fd002 | 84 | return; |
4d8bb006 PL |
85 | switch (c->x86_model) { |
86 | case INTEL_FAM6_XEON_PHI_KNL: | |
87 | case INTEL_FAM6_XEON_PHI_KNM: | |
88 | break; | |
89 | default: | |
90 | return; | |
91 | } | |
e16fd002 | 92 | |
e9ea1e7f | 93 | if (ring3mwait_disabled) |
e16fd002 | 94 | return; |
e16fd002 GA |
95 | |
96 | set_cpu_cap(c, X86_FEATURE_RING3MWAIT); | |
e9ea1e7f KH |
97 | this_cpu_or(msr_misc_features_shadow, |
98 | 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); | |
e16fd002 GA |
99 | |
100 | if (c == &boot_cpu_data) | |
101 | ELF_HWCAP2 |= HWCAP2_RING3MWAIT; | |
102 | } | |
103 | ||
148f9bb8 | 104 | static void early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 105 | { |
161ec53c FY |
106 | u64 misc_enable; |
107 | ||
99fb4d34 | 108 | /* Unmask CPUID levels if masked: */ |
30a0fb94 | 109 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
0b131be8 PA |
110 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
111 | MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { | |
99fb4d34 | 112 | c->cpuid_level = cpuid_eax(0); |
d900329e | 113 | get_cpu_cap(c); |
99fb4d34 | 114 | } |
066941bd PA |
115 | } |
116 | ||
2b16a235 AK |
117 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
118 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
119 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d | 120 | |
4167709b BP |
121 | if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) |
122 | c->microcode = intel_get_microcode_revision(); | |
506ed6b5 | 123 | |
7a0fc404 PA |
124 | /* |
125 | * Atom erratum AAE44/AAF40/AAG38/AAH41: | |
126 | * | |
127 | * A race condition between speculative fetches and invalidating | |
128 | * a large page. This is worked around in microcode, but we | |
129 | * need the microcode to have already been loaded... so if it is | |
130 | * not, recommend a BIOS update and disable large pages. | |
131 | */ | |
30963c0a AK |
132 | if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && |
133 | c->microcode < 0x20e) { | |
1b74dde7 | 134 | pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); |
30963c0a | 135 | clear_cpu_cap(c, X86_FEATURE_PSE); |
7a0fc404 PA |
136 | } |
137 | ||
185f3b9d YL |
138 | #ifdef CONFIG_X86_64 |
139 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
140 | #else | |
141 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
142 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
143 | c->x86_cache_alignment = 128; | |
144 | #endif | |
40fb1715 | 145 | |
13c6c532 JB |
146 | /* CPUID workaround for 0F33/0F34 CPU */ |
147 | if (c->x86 == 0xF && c->x86_model == 0x3 | |
148 | && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) | |
149 | c->x86_phys_bits = 36; | |
150 | ||
40fb1715 VP |
151 | /* |
152 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
83ce4009 IM |
153 | * with P/T states and does not stop in deep C-states. |
154 | * | |
155 | * It is also reliable across cores and sockets. (but not across | |
156 | * cabinets - we turn it off in that case explicitly.) | |
40fb1715 VP |
157 | */ |
158 | if (c->x86_power & (1 << 8)) { | |
159 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
160 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
161 | } | |
162 | ||
c54fdbb2 FT |
163 | /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ |
164 | if (c->x86 == 6) { | |
165 | switch (c->x86_model) { | |
166 | case 0x27: /* Penwell */ | |
167 | case 0x35: /* Cloverview */ | |
354dbaa7 | 168 | case 0x4a: /* Merrifield */ |
c54fdbb2 FT |
169 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); |
170 | break; | |
171 | default: | |
172 | break; | |
173 | } | |
174 | } | |
175 | ||
75a04811 PA |
176 | /* |
177 | * There is a known erratum on Pentium III and Core Solo | |
178 | * and Core Duo CPUs. | |
179 | * " Page with PAT set to WC while associated MTRR is UC | |
180 | * may consolidate to UC " | |
181 | * Because of this erratum, it is better to stick with | |
182 | * setting WC in MTRR rather than using PAT on these CPUs. | |
183 | * | |
184 | * Enable PAT WC only on P4, Core 2 or later CPUs. | |
185 | */ | |
186 | if (c->x86 == 6 && c->x86_model < 15) | |
187 | clear_cpu_cap(c, X86_FEATURE_PAT); | |
f8561296 VN |
188 | |
189 | #ifdef CONFIG_KMEMCHECK | |
190 | /* | |
191 | * P4s have a "fast strings" feature which causes single- | |
192 | * stepping REP instructions to only generate a #DB on | |
193 | * cache-line boundaries. | |
194 | * | |
195 | * Ingo Molnar reported a Pentium D (model 6) and a Xeon | |
196 | * (model 2) with the same problem. | |
197 | */ | |
c0a639ad | 198 | if (c->x86 == 15) |
0b131be8 PA |
199 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
200 | MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) | |
c0a639ad | 201 | pr_info("kmemcheck: Disabling fast string operations\n"); |
f8561296 | 202 | #endif |
161ec53c FY |
203 | |
204 | /* | |
205 | * If fast string is not enabled in IA32_MISC_ENABLE for any reason, | |
206 | * clear the fast string and enhanced fast string CPU capabilities. | |
207 | */ | |
208 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { | |
209 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
210 | if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { | |
1b74dde7 | 211 | pr_info("Disabled fast string operations\n"); |
161ec53c FY |
212 | setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); |
213 | setup_clear_cpu_cap(X86_FEATURE_ERMS); | |
214 | } | |
215 | } | |
ee1b5b16 BD |
216 | |
217 | /* | |
218 | * Intel Quark Core DevMan_001.pdf section 6.4.11 | |
219 | * "The operating system also is required to invalidate (i.e., flush) | |
220 | * the TLB when any changes are made to any of the page table entries. | |
221 | * The operating system must reload CR3 to cause the TLB to be flushed" | |
222 | * | |
c109bf95 BP |
223 | * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h |
224 | * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE | |
225 | * to be modified. | |
ee1b5b16 BD |
226 | */ |
227 | if (c->x86 == 5 && c->x86_model == 9) { | |
228 | pr_info("Disabling PGE capability bit\n"); | |
229 | setup_clear_cpu_cap(X86_FEATURE_PGE); | |
230 | } | |
1f12e32f TG |
231 | |
232 | if (c->cpuid_level >= 0x00000001) { | |
233 | u32 eax, ebx, ecx, edx; | |
234 | ||
235 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); | |
236 | /* | |
237 | * If HTT (EDX[28]) is set EBX[16:23] contain the number of | |
238 | * apicids which are reserved per package. Store the resulting | |
239 | * shift value for the package management code. | |
240 | */ | |
241 | if (edx & (1U << 28)) | |
242 | c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); | |
243 | } | |
0f6ff2bc DH |
244 | |
245 | check_mpx_erratum(c); | |
1da177e4 LT |
246 | } |
247 | ||
185f3b9d | 248 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
249 | /* |
250 | * Early probe support logic for ppro memory erratum #50 | |
251 | * | |
252 | * This is called before we do cpu ident work | |
253 | */ | |
65eb6b43 | 254 | |
148f9bb8 | 255 | int ppro_with_ram_bug(void) |
1da177e4 LT |
256 | { |
257 | /* Uses data from early_cpu_detect now */ | |
258 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
259 | boot_cpu_data.x86 == 6 && | |
260 | boot_cpu_data.x86_model == 1 && | |
261 | boot_cpu_data.x86_mask < 8) { | |
1b74dde7 | 262 | pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); |
1da177e4 LT |
263 | return 1; |
264 | } | |
265 | return 0; | |
266 | } | |
65eb6b43 | 267 | |
148f9bb8 | 268 | static void intel_smp_check(struct cpuinfo_x86 *c) |
1f442d70 | 269 | { |
1f442d70 | 270 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 271 | if (!c->cpu_index) |
1f442d70 YL |
272 | return; |
273 | ||
274 | /* | |
275 | * Mask B, Pentium, but not Pentium MMX | |
276 | */ | |
277 | if (c->x86 == 5 && | |
278 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
279 | c->x86_model <= 3) { | |
280 | /* | |
281 | * Remember we have B step Pentia with bugs | |
282 | */ | |
283 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | |
284 | "with B stepping processors.\n"); | |
285 | } | |
1f442d70 YL |
286 | } |
287 | ||
69f2366c CB |
288 | static int forcepae; |
289 | static int __init forcepae_setup(char *__unused) | |
290 | { | |
291 | forcepae = 1; | |
292 | return 1; | |
293 | } | |
294 | __setup("forcepae", forcepae_setup); | |
295 | ||
148f9bb8 | 296 | static void intel_workarounds(struct cpuinfo_x86 *c) |
1da177e4 | 297 | { |
4052704d YL |
298 | #ifdef CONFIG_X86_F00F_BUG |
299 | /* | |
d4e1a0af | 300 | * All models of Pentium and Pentium with MMX technology CPUs |
8bdbd962 | 301 | * have the F0 0F bug, which lets nonprivileged users lock up the |
4eefbe79 | 302 | * system. Announce that the fault handler will be checking for it. |
d4e1a0af | 303 | * The Quark is also family 5, but does not have the same bug. |
4052704d | 304 | */ |
e2604b49 | 305 | clear_cpu_bug(c, X86_BUG_F00F); |
fa392794 | 306 | if (c->x86 == 5 && c->x86_model < 9) { |
4052704d YL |
307 | static int f00f_workaround_enabled; |
308 | ||
e2604b49 | 309 | set_cpu_bug(c, X86_BUG_F00F); |
4052704d | 310 | if (!f00f_workaround_enabled) { |
1b74dde7 | 311 | pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); |
4052704d YL |
312 | f00f_workaround_enabled = 1; |
313 | } | |
314 | } | |
315 | #endif | |
316 | ||
317 | /* | |
318 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
319 | * model 3 mask 3 | |
320 | */ | |
321 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
322 | clear_cpu_cap(c, X86_FEATURE_SEP); | |
323 | ||
69f2366c CB |
324 | /* |
325 | * PAE CPUID issue: many Pentium M report no PAE but may have a | |
326 | * functionally usable PAE implementation. | |
327 | * Forcefully enable PAE if kernel parameter "forcepae" is present. | |
328 | */ | |
329 | if (forcepae) { | |
1b74dde7 | 330 | pr_warn("PAE forced!\n"); |
69f2366c CB |
331 | set_cpu_cap(c, X86_FEATURE_PAE); |
332 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); | |
333 | } | |
334 | ||
4052704d | 335 | /* |
f0133acc | 336 | * P4 Xeon erratum 037 workaround. |
4052704d YL |
337 | * Hardware prefetcher may cause stale data to be loaded into the cache. |
338 | */ | |
1da177e4 | 339 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { |
0b131be8 | 340 | if (msr_set_bit(MSR_IA32_MISC_ENABLE, |
f0133acc | 341 | MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { |
c0a639ad | 342 | pr_info("CPU: C0 stepping P4 Xeon detected.\n"); |
f0133acc | 343 | pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); |
1da177e4 LT |
344 | } |
345 | } | |
1da177e4 | 346 | |
4052704d YL |
347 | /* |
348 | * See if we have a good local APIC by checking for buggy Pentia, | |
349 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
350 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
351 | * Specification Update"). | |
352 | */ | |
93984fbd | 353 | if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && |
4052704d | 354 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) |
9b13a93d | 355 | set_cpu_bug(c, X86_BUG_11AP); |
185f3b9d | 356 | |
185f3b9d | 357 | |
4052704d | 358 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 359 | /* |
4052704d | 360 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 361 | */ |
4052704d YL |
362 | switch (c->x86) { |
363 | case 4: /* 486: untested */ | |
364 | break; | |
365 | case 5: /* Old Pentia: untested */ | |
366 | break; | |
367 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
368 | movsl_mask.mask = 7; | |
369 | break; | |
370 | case 15: /* P4 is OK down to 8-byte alignment */ | |
371 | movsl_mask.mask = 7; | |
372 | break; | |
373 | } | |
185f3b9d | 374 | #endif |
4052704d | 375 | |
1f442d70 | 376 | intel_smp_check(c); |
4052704d YL |
377 | } |
378 | #else | |
148f9bb8 | 379 | static void intel_workarounds(struct cpuinfo_x86 *c) |
4052704d YL |
380 | { |
381 | } | |
185f3b9d YL |
382 | #endif |
383 | ||
148f9bb8 | 384 | static void srat_detect_node(struct cpuinfo_x86 *c) |
185f3b9d | 385 | { |
645a7919 | 386 | #ifdef CONFIG_NUMA |
185f3b9d YL |
387 | unsigned node; |
388 | int cpu = smp_processor_id(); | |
185f3b9d YL |
389 | |
390 | /* Don't do the funky fallback heuristics the AMD version employs | |
391 | for now. */ | |
bbc9e2f4 | 392 | node = numa_cpu_node(cpu); |
50f2d7f6 | 393 | if (node == NUMA_NO_NODE || !node_online(node)) { |
d9c2d5ac YL |
394 | /* reuse the value from init_cpu_to_node() */ |
395 | node = cpu_to_node(cpu); | |
396 | } | |
185f3b9d | 397 | numa_set_node(cpu, node); |
185f3b9d YL |
398 | #endif |
399 | } | |
400 | ||
3dd9d514 AK |
401 | /* |
402 | * find out the number of processor cores on the die | |
403 | */ | |
148f9bb8 | 404 | static int intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 405 | { |
f2ab4461 | 406 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 | 407 | |
8d415ee2 | 408 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
3dd9d514 AK |
409 | return 1; |
410 | ||
f2ab4461 ZA |
411 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
412 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 | 413 | if (eax & 0x1f) |
8bdbd962 | 414 | return (eax >> 26) + 1; |
3dd9d514 AK |
415 | else |
416 | return 1; | |
417 | } | |
418 | ||
148f9bb8 | 419 | static void detect_vmx_virtcap(struct cpuinfo_x86 *c) |
e38e05a8 SY |
420 | { |
421 | /* Intel VMX MSR indicated features */ | |
422 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 | |
423 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
424 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
425 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
426 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
427 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
428 | ||
429 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
430 | ||
431 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
432 | clear_cpu_cap(c, X86_FEATURE_VNMI); | |
433 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
434 | clear_cpu_cap(c, X86_FEATURE_EPT); | |
435 | clear_cpu_cap(c, X86_FEATURE_VPID); | |
436 | ||
437 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
438 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
439 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
440 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
441 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
442 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
443 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
444 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
445 | vmx_msr_low, vmx_msr_high); | |
446 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
447 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
448 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
449 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
450 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
451 | set_cpu_cap(c, X86_FEATURE_EPT); | |
452 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
453 | set_cpu_cap(c, X86_FEATURE_VPID); | |
454 | } | |
455 | } | |
456 | ||
b51ef52d LA |
457 | static void init_intel_energy_perf(struct cpuinfo_x86 *c) |
458 | { | |
459 | u64 epb; | |
460 | ||
461 | /* | |
462 | * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. | |
463 | * (x86_energy_perf_policy(8) is available to change it at run-time.) | |
464 | */ | |
465 | if (!cpu_has(c, X86_FEATURE_EPB)) | |
466 | return; | |
467 | ||
468 | rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
469 | if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) | |
470 | return; | |
471 | ||
472 | pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); | |
473 | pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); | |
474 | epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; | |
475 | wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
476 | } | |
477 | ||
478 | static void intel_bsp_resume(struct cpuinfo_x86 *c) | |
479 | { | |
480 | /* | |
481 | * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, | |
482 | * so reinitialize it properly like during bootup: | |
483 | */ | |
484 | init_intel_energy_perf(c); | |
485 | } | |
486 | ||
90218ac7 KH |
487 | static void init_cpuid_fault(struct cpuinfo_x86 *c) |
488 | { | |
489 | u64 msr; | |
490 | ||
491 | if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { | |
492 | if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) | |
493 | set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); | |
494 | } | |
495 | } | |
496 | ||
497 | static void init_intel_misc_features(struct cpuinfo_x86 *c) | |
498 | { | |
499 | u64 msr; | |
500 | ||
501 | if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) | |
502 | return; | |
503 | ||
e9ea1e7f KH |
504 | /* Clear all MISC features */ |
505 | this_cpu_write(msr_misc_features_shadow, 0); | |
506 | ||
507 | /* Check features and update capabilities and shadow control bits */ | |
90218ac7 KH |
508 | init_cpuid_fault(c); |
509 | probe_xeon_phi_r3mwait(c); | |
e9ea1e7f KH |
510 | |
511 | msr = this_cpu_read(msr_misc_features_shadow); | |
512 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); | |
90218ac7 KH |
513 | } |
514 | ||
148f9bb8 | 515 | static void init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
516 | { |
517 | unsigned int l2 = 0; | |
1da177e4 | 518 | |
2b16a235 AK |
519 | early_init_intel(c); |
520 | ||
4052704d | 521 | intel_workarounds(c); |
1da177e4 | 522 | |
345077cd SS |
523 | /* |
524 | * Detect the extended topology information if available. This | |
525 | * will reinitialise the initial_apicid which will be used | |
526 | * in init_intel_cacheinfo() | |
527 | */ | |
528 | detect_extended_topology(c); | |
529 | ||
2a226155 PZ |
530 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
531 | /* | |
532 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
533 | * detection. | |
534 | */ | |
535 | c->x86_max_cores = intel_num_cpu_cores(c); | |
536 | #ifdef CONFIG_X86_32 | |
537 | detect_ht(c); | |
538 | #endif | |
539 | } | |
540 | ||
1da177e4 | 541 | l2 = init_intel_cacheinfo(c); |
aece118e BD |
542 | |
543 | /* Detect legacy cache sizes if init_intel_cacheinfo did not */ | |
544 | if (l2 == 0) { | |
545 | cpu_detect_cache_sizes(c); | |
546 | l2 = c->x86_cache_size; | |
547 | } | |
548 | ||
65eb6b43 | 549 | if (c->cpuid_level > 9) { |
0080e667 VP |
550 | unsigned eax = cpuid_eax(10); |
551 | /* Check for version and the number of counters */ | |
552 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 553 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 554 | } |
1da177e4 | 555 | |
054efb64 | 556 | if (cpu_has(c, X86_FEATURE_XMM2)) |
4052704d | 557 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
362f924b BP |
558 | |
559 | if (boot_cpu_has(X86_FEATURE_DS)) { | |
4052704d YL |
560 | unsigned int l1; |
561 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
562 | if (!(l1 & (1<<11))) | |
563 | set_cpu_cap(c, X86_FEATURE_BTS); | |
564 | if (!(l1 & (1<<12))) | |
565 | set_cpu_cap(c, X86_FEATURE_PEBS); | |
4052704d | 566 | } |
1da177e4 | 567 | |
906bf7fd | 568 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && |
40e2d7f9 | 569 | (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) |
9b13a93d | 570 | set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); |
e736ad54 | 571 | |
08e237fa PZ |
572 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && |
573 | ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) | |
574 | set_cpu_bug(c, X86_BUG_MONITOR); | |
575 | ||
4052704d YL |
576 | #ifdef CONFIG_X86_64 |
577 | if (c->x86 == 15) | |
578 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
579 | if (c->x86 == 6) | |
580 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
581 | #else | |
65eb6b43 PC |
582 | /* |
583 | * Names for the Pentium II/Celeron processors | |
584 | * detectable only by also checking the cache size. | |
585 | * Dixon is NOT a Celeron. | |
586 | */ | |
1da177e4 | 587 | if (c->x86 == 6) { |
4052704d YL |
588 | char *p = NULL; |
589 | ||
1da177e4 LT |
590 | switch (c->x86_model) { |
591 | case 5: | |
865be7a8 OZ |
592 | if (l2 == 0) |
593 | p = "Celeron (Covington)"; | |
594 | else if (l2 == 256) | |
595 | p = "Mobile Pentium II (Dixon)"; | |
1da177e4 | 596 | break; |
65eb6b43 | 597 | |
1da177e4 LT |
598 | case 6: |
599 | if (l2 == 128) | |
600 | p = "Celeron (Mendocino)"; | |
601 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
602 | p = "Celeron-A"; | |
603 | break; | |
65eb6b43 | 604 | |
1da177e4 LT |
605 | case 8: |
606 | if (l2 == 128) | |
607 | p = "Celeron (Coppermine)"; | |
608 | break; | |
609 | } | |
1da177e4 | 610 | |
4052704d YL |
611 | if (p) |
612 | strcpy(c->x86_model_id, p); | |
1da177e4 | 613 | } |
1da177e4 | 614 | |
185f3b9d YL |
615 | if (c->x86 == 15) |
616 | set_cpu_cap(c, X86_FEATURE_P4); | |
617 | if (c->x86 == 6) | |
618 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 619 | #endif |
185f3b9d | 620 | |
185f3b9d | 621 | /* Work around errata */ |
2759c328 | 622 | srat_detect_node(c); |
e38e05a8 SY |
623 | |
624 | if (cpu_has(c, X86_FEATURE_VMX)) | |
625 | detect_vmx_virtcap(c); | |
abe48b10 | 626 | |
b51ef52d | 627 | init_intel_energy_perf(c); |
e16fd002 | 628 | |
90218ac7 | 629 | init_intel_misc_features(c); |
b11de7a2 | 630 | |
11133ff3 TC |
631 | if (!c->cpu_index) { |
632 | if (boot_cpu_has(X86_FEATURE_SPEC_CTRL)) { | |
633 | printk(KERN_INFO "FEATURE SPEC_CTRL Present\n"); | |
634 | set_ibrs_supported(); | |
635 | set_ibpb_supported(); | |
636 | if (ibrs_inuse) | |
637 | sysctl_ibrs_enabled = 1; | |
638 | if (ibpb_inuse) | |
639 | sysctl_ibpb_enabled = 1; | |
200e837f | 640 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
11133ff3 TC |
641 | } else { |
642 | printk(KERN_INFO "FEATURE SPEC_CTRL Not Present\n"); | |
643 | } | |
357b57d7 | 644 | } |
42ed458a | 645 | } |
1da177e4 | 646 | |
185f3b9d | 647 | #ifdef CONFIG_X86_32 |
148f9bb8 | 648 | static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 649 | { |
65eb6b43 PC |
650 | /* |
651 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
652 | * One has 256kb of cache, the other 512. We have no way |
653 | * to determine which, so we use a boottime override | |
654 | * for the 512kb model, and assume 256 otherwise. | |
655 | */ | |
656 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
657 | size = 256; | |
aece118e BD |
658 | |
659 | /* | |
660 | * Intel Quark SoC X1000 contains a 4-way set associative | |
661 | * 16K cache with a 16 byte cache line and 256 lines per tag | |
662 | */ | |
663 | if ((c->x86 == 5) && (c->x86_model == 9)) | |
664 | size = 16; | |
1da177e4 LT |
665 | return size; |
666 | } | |
185f3b9d | 667 | #endif |
1da177e4 | 668 | |
e0ba94f1 AS |
669 | #define TLB_INST_4K 0x01 |
670 | #define TLB_INST_4M 0x02 | |
671 | #define TLB_INST_2M_4M 0x03 | |
672 | ||
673 | #define TLB_INST_ALL 0x05 | |
674 | #define TLB_INST_1G 0x06 | |
675 | ||
676 | #define TLB_DATA_4K 0x11 | |
677 | #define TLB_DATA_4M 0x12 | |
678 | #define TLB_DATA_2M_4M 0x13 | |
679 | #define TLB_DATA_4K_4M 0x14 | |
680 | ||
681 | #define TLB_DATA_1G 0x16 | |
682 | ||
683 | #define TLB_DATA0_4K 0x21 | |
684 | #define TLB_DATA0_4M 0x22 | |
685 | #define TLB_DATA0_2M_4M 0x23 | |
686 | ||
687 | #define STLB_4K 0x41 | |
dd360393 | 688 | #define STLB_4K_2M 0x42 |
e0ba94f1 | 689 | |
148f9bb8 | 690 | static const struct _tlb_table intel_tlb_table[] = { |
e0ba94f1 AS |
691 | { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, |
692 | { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, | |
693 | { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
694 | { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
695 | { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
696 | { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, | |
697 | { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, | |
698 | { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
699 | { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
700 | { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
701 | { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
702 | { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, | |
703 | { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, | |
704 | { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, | |
705 | { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, | |
706 | { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
707 | { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
708 | { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
dd360393 KS |
709 | { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, |
710 | { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, | |
711 | { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
e0ba94f1 AS |
712 | { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, |
713 | { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, | |
714 | { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, | |
715 | { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
716 | { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, | |
a927792c YG |
717 | { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, |
718 | { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, | |
e0ba94f1 AS |
719 | { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, |
720 | { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, | |
dd360393 KS |
721 | { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, |
722 | { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, | |
e0ba94f1 AS |
723 | { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, |
724 | { 0x00, 0, 0 } | |
725 | }; | |
726 | ||
148f9bb8 | 727 | static void intel_tlb_lookup(const unsigned char desc) |
e0ba94f1 AS |
728 | { |
729 | unsigned char k; | |
730 | if (desc == 0) | |
731 | return; | |
732 | ||
733 | /* look up this descriptor in the table */ | |
734 | for (k = 0; intel_tlb_table[k].descriptor != desc && \ | |
735 | intel_tlb_table[k].descriptor != 0; k++) | |
736 | ; | |
737 | ||
738 | if (intel_tlb_table[k].tlb_type == 0) | |
739 | return; | |
740 | ||
741 | switch (intel_tlb_table[k].tlb_type) { | |
742 | case STLB_4K: | |
743 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
744 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
745 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
746 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
747 | break; | |
dd360393 KS |
748 | case STLB_4K_2M: |
749 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
750 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
751 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
752 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
753 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
754 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
755 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
756 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
757 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
758 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
759 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
760 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
761 | break; | |
e0ba94f1 AS |
762 | case TLB_INST_ALL: |
763 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
764 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
765 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
766 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
767 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
768 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
769 | break; | |
770 | case TLB_INST_4K: | |
771 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
772 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
773 | break; | |
774 | case TLB_INST_4M: | |
775 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
776 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
777 | break; | |
778 | case TLB_INST_2M_4M: | |
779 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
780 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
781 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
782 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
783 | break; | |
784 | case TLB_DATA_4K: | |
785 | case TLB_DATA0_4K: | |
786 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
787 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
788 | break; | |
789 | case TLB_DATA_4M: | |
790 | case TLB_DATA0_4M: | |
791 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
792 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
793 | break; | |
794 | case TLB_DATA_2M_4M: | |
795 | case TLB_DATA0_2M_4M: | |
796 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
797 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
798 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
799 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
800 | break; | |
801 | case TLB_DATA_4K_4M: | |
802 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
803 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
804 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
805 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
806 | break; | |
dd360393 KS |
807 | case TLB_DATA_1G: |
808 | if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) | |
809 | tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; | |
e0ba94f1 AS |
810 | break; |
811 | } | |
812 | } | |
813 | ||
148f9bb8 | 814 | static void intel_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
815 | { |
816 | int i, j, n; | |
817 | unsigned int regs[4]; | |
818 | unsigned char *desc = (unsigned char *)regs; | |
5b556332 BP |
819 | |
820 | if (c->cpuid_level < 2) | |
821 | return; | |
822 | ||
e0ba94f1 AS |
823 | /* Number of times to iterate */ |
824 | n = cpuid_eax(2) & 0xFF; | |
825 | ||
826 | for (i = 0 ; i < n ; i++) { | |
827 | cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); | |
828 | ||
829 | /* If bit 31 is set, this is an unknown format */ | |
830 | for (j = 0 ; j < 3 ; j++) | |
831 | if (regs[j] & (1 << 31)) | |
832 | regs[j] = 0; | |
833 | ||
834 | /* Byte 0 is level count, not a descriptor */ | |
835 | for (j = 1 ; j < 16 ; j++) | |
836 | intel_tlb_lookup(desc[j]); | |
837 | } | |
838 | } | |
839 | ||
148f9bb8 | 840 | static const struct cpu_dev intel_cpu_dev = { |
1da177e4 | 841 | .c_vendor = "Intel", |
65eb6b43 | 842 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 843 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
844 | .legacy_models = { |
845 | { .family = 4, .model_names = | |
65eb6b43 PC |
846 | { |
847 | [0] = "486 DX-25/33", | |
848 | [1] = "486 DX-50", | |
849 | [2] = "486 SX", | |
850 | [3] = "486 DX/2", | |
851 | [4] = "486 SL", | |
852 | [5] = "486 SX/2", | |
853 | [7] = "486 DX/2-WB", | |
854 | [8] = "486 DX/4", | |
1da177e4 LT |
855 | [9] = "486 DX/4-WB" |
856 | } | |
857 | }, | |
09dc68d9 | 858 | { .family = 5, .model_names = |
65eb6b43 PC |
859 | { |
860 | [0] = "Pentium 60/66 A-step", | |
861 | [1] = "Pentium 60/66", | |
1da177e4 | 862 | [2] = "Pentium 75 - 200", |
65eb6b43 | 863 | [3] = "OverDrive PODP5V83", |
1da177e4 | 864 | [4] = "Pentium MMX", |
65eb6b43 | 865 | [7] = "Mobile Pentium 75 - 200", |
aece118e BD |
866 | [8] = "Mobile Pentium MMX", |
867 | [9] = "Quark SoC X1000", | |
1da177e4 LT |
868 | } |
869 | }, | |
09dc68d9 | 870 | { .family = 6, .model_names = |
65eb6b43 | 871 | { |
1da177e4 | 872 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
873 | [1] = "Pentium Pro", |
874 | [3] = "Pentium II (Klamath)", | |
875 | [4] = "Pentium II (Deschutes)", | |
876 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 877 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
878 | [7] = "Pentium III (Katmai)", |
879 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
880 | [10] = "Pentium III (Cascades)", |
881 | [11] = "Pentium III (Tualatin)", | |
882 | } | |
883 | }, | |
09dc68d9 | 884 | { .family = 15, .model_names = |
1da177e4 LT |
885 | { |
886 | [0] = "Pentium 4 (Unknown)", | |
887 | [1] = "Pentium 4 (Willamette)", | |
888 | [2] = "Pentium 4 (Northwood)", | |
889 | [4] = "Pentium 4 (Foster)", | |
890 | [5] = "Pentium 4 (Foster)", | |
891 | } | |
892 | }, | |
893 | }, | |
09dc68d9 | 894 | .legacy_cache_size = intel_size_cache, |
185f3b9d | 895 | #endif |
e0ba94f1 | 896 | .c_detect_tlb = intel_detect_tlb, |
03ae5768 | 897 | .c_early_init = early_init_intel, |
1da177e4 | 898 | .c_init = init_intel, |
b51ef52d | 899 | .c_bsp_resume = intel_bsp_resume, |
10a434fc | 900 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
901 | }; |
902 | ||
10a434fc | 903 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 904 |