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Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
7c68af6e | 12 | #include <linux/user-return-notifier.h> |
61613521 | 13 | #include <trace/events/power.h> |
24f1e32c | 14 | #include <linux/hw_breakpoint.h> |
c1e3b377 | 15 | #include <asm/system.h> |
d3ec5cae | 16 | #include <asm/apic.h> |
2c1b284e | 17 | #include <asm/syscalls.h> |
389d1fb1 JF |
18 | #include <asm/idle.h> |
19 | #include <asm/uaccess.h> | |
20 | #include <asm/i387.h> | |
2311f0de | 21 | #include <asm/ds.h> |
66cb5917 | 22 | #include <asm/debugreg.h> |
c1e3b377 ZY |
23 | |
24 | unsigned long idle_halt; | |
25 | EXPORT_SYMBOL(idle_halt); | |
da5e09a1 ZY |
26 | unsigned long idle_nomwait; |
27 | EXPORT_SYMBOL(idle_nomwait); | |
61c4628b | 28 | |
aa283f49 | 29 | struct kmem_cache *task_xstate_cachep; |
61c4628b SS |
30 | |
31 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
32 | { | |
33 | *dst = *src; | |
aa283f49 SS |
34 | if (src->thread.xstate) { |
35 | dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
36 | GFP_KERNEL); | |
37 | if (!dst->thread.xstate) | |
38 | return -ENOMEM; | |
39 | WARN_ON((unsigned long)dst->thread.xstate & 15); | |
40 | memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); | |
41 | } | |
61c4628b SS |
42 | return 0; |
43 | } | |
44 | ||
aa283f49 | 45 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 46 | { |
aa283f49 SS |
47 | if (tsk->thread.xstate) { |
48 | kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); | |
49 | tsk->thread.xstate = NULL; | |
50 | } | |
2311f0de MM |
51 | |
52 | WARN(tsk->thread.ds_ctx, "leaking DS context\n"); | |
aa283f49 SS |
53 | } |
54 | ||
aa283f49 SS |
55 | void free_thread_info(struct thread_info *ti) |
56 | { | |
57 | free_thread_xstate(ti->task); | |
1679f271 | 58 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
59 | } |
60 | ||
61 | void arch_task_cache_init(void) | |
62 | { | |
63 | task_xstate_cachep = | |
64 | kmem_cache_create("task_xstate", xstate_size, | |
65 | __alignof__(union thread_xstate), | |
2dff4405 | 66 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 67 | } |
7f424a8b | 68 | |
389d1fb1 JF |
69 | /* |
70 | * Free current thread data structures etc.. | |
71 | */ | |
72 | void exit_thread(void) | |
73 | { | |
74 | struct task_struct *me = current; | |
75 | struct thread_struct *t = &me->thread; | |
250981e6 | 76 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 77 | |
250981e6 | 78 | if (bp) { |
389d1fb1 JF |
79 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
80 | ||
389d1fb1 JF |
81 | t->io_bitmap_ptr = NULL; |
82 | clear_thread_flag(TIF_IO_BITMAP); | |
83 | /* | |
84 | * Careful, clear this in the TSS too: | |
85 | */ | |
86 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
87 | t->io_bitmap_max = 0; | |
88 | put_cpu(); | |
250981e6 | 89 | kfree(bp); |
389d1fb1 | 90 | } |
389d1fb1 JF |
91 | } |
92 | ||
93 | void flush_thread(void) | |
94 | { | |
95 | struct task_struct *tsk = current; | |
96 | ||
97 | #ifdef CONFIG_X86_64 | |
98 | if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) { | |
99 | clear_tsk_thread_flag(tsk, TIF_ABI_PENDING); | |
100 | if (test_tsk_thread_flag(tsk, TIF_IA32)) { | |
101 | clear_tsk_thread_flag(tsk, TIF_IA32); | |
102 | } else { | |
103 | set_tsk_thread_flag(tsk, TIF_IA32); | |
104 | current_thread_info()->status |= TS_COMPAT; | |
105 | } | |
106 | } | |
107 | #endif | |
108 | ||
24f1e32c | 109 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
110 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
111 | /* | |
112 | * Forget coprocessor state.. | |
113 | */ | |
114 | tsk->fpu_counter = 0; | |
115 | clear_fpu(tsk); | |
116 | clear_used_math(); | |
117 | } | |
118 | ||
119 | static void hard_disable_TSC(void) | |
120 | { | |
121 | write_cr4(read_cr4() | X86_CR4_TSD); | |
122 | } | |
123 | ||
124 | void disable_TSC(void) | |
125 | { | |
126 | preempt_disable(); | |
127 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
128 | /* | |
129 | * Must flip the CPU state synchronously with | |
130 | * TIF_NOTSC in the current running context. | |
131 | */ | |
132 | hard_disable_TSC(); | |
133 | preempt_enable(); | |
134 | } | |
135 | ||
136 | static void hard_enable_TSC(void) | |
137 | { | |
138 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
139 | } | |
140 | ||
141 | static void enable_TSC(void) | |
142 | { | |
143 | preempt_disable(); | |
144 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
145 | /* | |
146 | * Must flip the CPU state synchronously with | |
147 | * TIF_NOTSC in the current running context. | |
148 | */ | |
149 | hard_enable_TSC(); | |
150 | preempt_enable(); | |
151 | } | |
152 | ||
153 | int get_tsc_mode(unsigned long adr) | |
154 | { | |
155 | unsigned int val; | |
156 | ||
157 | if (test_thread_flag(TIF_NOTSC)) | |
158 | val = PR_TSC_SIGSEGV; | |
159 | else | |
160 | val = PR_TSC_ENABLE; | |
161 | ||
162 | return put_user(val, (unsigned int __user *)adr); | |
163 | } | |
164 | ||
165 | int set_tsc_mode(unsigned int val) | |
166 | { | |
167 | if (val == PR_TSC_SIGSEGV) | |
168 | disable_TSC(); | |
169 | else if (val == PR_TSC_ENABLE) | |
170 | enable_TSC(); | |
171 | else | |
172 | return -EINVAL; | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
178 | struct tss_struct *tss) | |
179 | { | |
180 | struct thread_struct *prev, *next; | |
181 | ||
182 | prev = &prev_p->thread; | |
183 | next = &next_p->thread; | |
184 | ||
185 | if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) || | |
186 | test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR)) | |
187 | ds_switch_to(prev_p, next_p); | |
188 | else if (next->debugctlmsr != prev->debugctlmsr) | |
189 | update_debugctlmsr(next->debugctlmsr); | |
190 | ||
389d1fb1 JF |
191 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
192 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
193 | /* prev and next are different */ | |
194 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
195 | hard_disable_TSC(); | |
196 | else | |
197 | hard_enable_TSC(); | |
198 | } | |
199 | ||
200 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
201 | /* | |
202 | * Copy the relevant range of the IO bitmap. | |
203 | * Normally this is 128 bytes or less: | |
204 | */ | |
205 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
206 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
207 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
208 | /* | |
209 | * Clear any possible leftover bits: | |
210 | */ | |
211 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
212 | } | |
7c68af6e | 213 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
214 | } |
215 | ||
216 | int sys_fork(struct pt_regs *regs) | |
217 | { | |
218 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
219 | } | |
220 | ||
221 | /* | |
222 | * This is trivial, and on the face of it looks like it | |
223 | * could equally well be done in user mode. | |
224 | * | |
225 | * Not so, for quite unobvious reasons - register pressure. | |
226 | * In user mode vfork() cannot have a stack frame, and if | |
227 | * done by calling the "clone()" system call directly, you | |
228 | * do not have enough call-clobbered registers to hold all | |
229 | * the information you need. | |
230 | */ | |
231 | int sys_vfork(struct pt_regs *regs) | |
232 | { | |
233 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
234 | NULL, NULL); | |
235 | } | |
236 | ||
237 | ||
00dba564 TG |
238 | /* |
239 | * Idle related variables and functions | |
240 | */ | |
241 | unsigned long boot_option_idle_override = 0; | |
242 | EXPORT_SYMBOL(boot_option_idle_override); | |
243 | ||
244 | /* | |
245 | * Powermanagement idle function, if any.. | |
246 | */ | |
247 | void (*pm_idle)(void); | |
248 | EXPORT_SYMBOL(pm_idle); | |
249 | ||
250 | #ifdef CONFIG_X86_32 | |
251 | /* | |
252 | * This halt magic was a workaround for ancient floppy DMA | |
253 | * wreckage. It should be safe to remove. | |
254 | */ | |
255 | static int hlt_counter; | |
256 | void disable_hlt(void) | |
257 | { | |
258 | hlt_counter++; | |
259 | } | |
260 | EXPORT_SYMBOL(disable_hlt); | |
261 | ||
262 | void enable_hlt(void) | |
263 | { | |
264 | hlt_counter--; | |
265 | } | |
266 | EXPORT_SYMBOL(enable_hlt); | |
267 | ||
268 | static inline int hlt_use_halt(void) | |
269 | { | |
270 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
271 | } | |
272 | #else | |
273 | static inline int hlt_use_halt(void) | |
274 | { | |
275 | return 1; | |
276 | } | |
277 | #endif | |
278 | ||
279 | /* | |
280 | * We use this if we don't have any better | |
281 | * idle routine.. | |
282 | */ | |
283 | void default_idle(void) | |
284 | { | |
285 | if (hlt_use_halt()) { | |
61613521 | 286 | trace_power_start(POWER_CSTATE, 1); |
00dba564 TG |
287 | current_thread_info()->status &= ~TS_POLLING; |
288 | /* | |
289 | * TS_POLLING-cleared state must be visible before we | |
290 | * test NEED_RESCHED: | |
291 | */ | |
292 | smp_mb(); | |
293 | ||
294 | if (!need_resched()) | |
295 | safe_halt(); /* enables interrupts racelessly */ | |
296 | else | |
297 | local_irq_enable(); | |
298 | current_thread_info()->status |= TS_POLLING; | |
299 | } else { | |
300 | local_irq_enable(); | |
301 | /* loop is done by the caller */ | |
302 | cpu_relax(); | |
303 | } | |
304 | } | |
305 | #ifdef CONFIG_APM_MODULE | |
306 | EXPORT_SYMBOL(default_idle); | |
307 | #endif | |
308 | ||
d3ec5cae IV |
309 | void stop_this_cpu(void *dummy) |
310 | { | |
311 | local_irq_disable(); | |
312 | /* | |
313 | * Remove this CPU: | |
314 | */ | |
4f062896 | 315 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
316 | disable_local_APIC(); |
317 | ||
318 | for (;;) { | |
319 | if (hlt_works(smp_processor_id())) | |
320 | halt(); | |
321 | } | |
322 | } | |
323 | ||
7f424a8b PZ |
324 | static void do_nothing(void *unused) |
325 | { | |
326 | } | |
327 | ||
328 | /* | |
329 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
330 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
331 | * handler on SMP systems. | |
332 | * | |
333 | * Caller must have changed pm_idle to the new value before the call. Old | |
334 | * pm_idle value will not be used by any CPU after the return of this function. | |
335 | */ | |
336 | void cpu_idle_wait(void) | |
337 | { | |
338 | smp_mb(); | |
339 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 340 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
341 | } |
342 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
343 | ||
344 | /* | |
345 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
346 | * which can obviate IPI to trigger checking of need_resched. | |
347 | * We execute MONITOR against need_resched and enter optimized wait state | |
348 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
349 | * up from MWAIT (without an IPI). | |
350 | * | |
351 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
352 | * capability. | |
353 | */ | |
354 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
355 | { | |
61613521 | 356 | trace_power_start(POWER_CSTATE, (ax>>4)+1); |
7f424a8b | 357 | if (!need_resched()) { |
e736ad54 PV |
358 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
359 | clflush((void *)¤t_thread_info()->flags); | |
360 | ||
7f424a8b PZ |
361 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
362 | smp_mb(); | |
363 | if (!need_resched()) | |
364 | __mwait(ax, cx); | |
365 | } | |
366 | } | |
367 | ||
368 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
369 | static void mwait_idle(void) | |
370 | { | |
371 | if (!need_resched()) { | |
61613521 | 372 | trace_power_start(POWER_CSTATE, 1); |
e736ad54 PV |
373 | if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR)) |
374 | clflush((void *)¤t_thread_info()->flags); | |
375 | ||
7f424a8b PZ |
376 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
377 | smp_mb(); | |
378 | if (!need_resched()) | |
379 | __sti_mwait(0, 0); | |
380 | else | |
381 | local_irq_enable(); | |
382 | } else | |
383 | local_irq_enable(); | |
384 | } | |
385 | ||
7f424a8b PZ |
386 | /* |
387 | * On SMP it's slightly faster (but much more power-consuming!) | |
388 | * to poll the ->work.need_resched flag instead of waiting for the | |
389 | * cross-CPU IPI to arrive. Use this option with caution. | |
390 | */ | |
391 | static void poll_idle(void) | |
392 | { | |
61613521 | 393 | trace_power_start(POWER_CSTATE, 0); |
7f424a8b | 394 | local_irq_enable(); |
2c7e9fd4 JK |
395 | while (!need_resched()) |
396 | cpu_relax(); | |
61613521 | 397 | trace_power_end(0); |
7f424a8b PZ |
398 | } |
399 | ||
e9623b35 TG |
400 | /* |
401 | * mwait selection logic: | |
402 | * | |
403 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
404 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
405 | * then depend on a clock divisor and current Pstate of the core. If | |
406 | * all cores of a processor are in halt state (C1) the processor can | |
407 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
408 | * happen. | |
409 | * | |
410 | * idle=mwait overrides this decision and forces the usage of mwait. | |
411 | */ | |
08ad8afa | 412 | static int __cpuinitdata force_mwait; |
09fd4b4e TG |
413 | |
414 | #define MWAIT_INFO 0x05 | |
415 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
416 | #define MWAIT_EDX_C1 0xf0 | |
417 | ||
e9623b35 TG |
418 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) |
419 | { | |
09fd4b4e TG |
420 | u32 eax, ebx, ecx, edx; |
421 | ||
e9623b35 TG |
422 | if (force_mwait) |
423 | return 1; | |
424 | ||
09fd4b4e TG |
425 | if (c->cpuid_level < MWAIT_INFO) |
426 | return 0; | |
427 | ||
428 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
429 | /* Check, whether EDX has extended info about MWAIT */ | |
430 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
431 | return 1; | |
432 | ||
433 | /* | |
434 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
435 | * C1 supports MWAIT | |
436 | */ | |
437 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
438 | } |
439 | ||
aa276e1c TG |
440 | /* |
441 | * Check for AMD CPUs, which have potentially C1E support | |
442 | */ | |
443 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) | |
444 | { | |
445 | if (c->x86_vendor != X86_VENDOR_AMD) | |
446 | return 0; | |
447 | ||
448 | if (c->x86 < 0x0F) | |
449 | return 0; | |
450 | ||
451 | /* Family 0x0f models < rev F do not have C1E */ | |
452 | if (c->x86 == 0x0f && c->x86_model < 0x40) | |
453 | return 0; | |
454 | ||
455 | return 1; | |
456 | } | |
457 | ||
bc9b83dd | 458 | static cpumask_var_t c1e_mask; |
4faac97d TG |
459 | static int c1e_detected; |
460 | ||
461 | void c1e_remove_cpu(int cpu) | |
462 | { | |
30e1e6d1 RR |
463 | if (c1e_mask != NULL) |
464 | cpumask_clear_cpu(cpu, c1e_mask); | |
4faac97d TG |
465 | } |
466 | ||
aa276e1c TG |
467 | /* |
468 | * C1E aware idle routine. We check for C1E active in the interrupt | |
469 | * pending message MSR. If we detect C1E, then we handle it the same | |
470 | * way as C3 power states (local apic timer and TSC stop) | |
471 | */ | |
472 | static void c1e_idle(void) | |
473 | { | |
aa276e1c TG |
474 | if (need_resched()) |
475 | return; | |
476 | ||
477 | if (!c1e_detected) { | |
478 | u32 lo, hi; | |
479 | ||
480 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
481 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { | |
482 | c1e_detected = 1; | |
40fb1715 | 483 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
484 | mark_tsc_unstable("TSC halt in AMD C1E"); |
485 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
a8d68290 | 486 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); |
aa276e1c TG |
487 | } |
488 | } | |
489 | ||
490 | if (c1e_detected) { | |
491 | int cpu = smp_processor_id(); | |
492 | ||
bc9b83dd RR |
493 | if (!cpumask_test_cpu(cpu, c1e_mask)) { |
494 | cpumask_set_cpu(cpu, c1e_mask); | |
0beefa20 | 495 | /* |
f833bab8 | 496 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 497 | */ |
aa276e1c TG |
498 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
499 | &cpu); | |
500 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
501 | cpu); | |
502 | } | |
503 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 504 | |
aa276e1c | 505 | default_idle(); |
0beefa20 TG |
506 | |
507 | /* | |
508 | * The switch back from broadcast mode needs to be | |
509 | * called with interrupts disabled. | |
510 | */ | |
511 | local_irq_disable(); | |
512 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
513 | local_irq_enable(); | |
aa276e1c TG |
514 | } else |
515 | default_idle(); | |
516 | } | |
517 | ||
7f424a8b PZ |
518 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
519 | { | |
3e5095d1 | 520 | #ifdef CONFIG_SMP |
7f424a8b PZ |
521 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
522 | printk(KERN_WARNING "WARNING: polling idle and HT enabled," | |
523 | " performance may degrade.\n"); | |
524 | } | |
525 | #endif | |
6ddd2a27 TG |
526 | if (pm_idle) |
527 | return; | |
528 | ||
e9623b35 | 529 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 530 | /* |
7f424a8b PZ |
531 | * One CPU supports mwait => All CPUs supports mwait |
532 | */ | |
6ddd2a27 TG |
533 | printk(KERN_INFO "using mwait in idle threads.\n"); |
534 | pm_idle = mwait_idle; | |
aa276e1c TG |
535 | } else if (check_c1e_idle(c)) { |
536 | printk(KERN_INFO "using C1E aware idle routine\n"); | |
537 | pm_idle = c1e_idle; | |
6ddd2a27 TG |
538 | } else |
539 | pm_idle = default_idle; | |
7f424a8b PZ |
540 | } |
541 | ||
30e1e6d1 RR |
542 | void __init init_c1e_mask(void) |
543 | { | |
544 | /* If we're using c1e_idle, we need to allocate c1e_mask. */ | |
79f55997 LZ |
545 | if (pm_idle == c1e_idle) |
546 | zalloc_cpumask_var(&c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
547 | } |
548 | ||
7f424a8b PZ |
549 | static int __init idle_setup(char *str) |
550 | { | |
ab6bc3e3 CG |
551 | if (!str) |
552 | return -EINVAL; | |
553 | ||
7f424a8b PZ |
554 | if (!strcmp(str, "poll")) { |
555 | printk("using polling idle threads.\n"); | |
556 | pm_idle = poll_idle; | |
557 | } else if (!strcmp(str, "mwait")) | |
558 | force_mwait = 1; | |
c1e3b377 ZY |
559 | else if (!strcmp(str, "halt")) { |
560 | /* | |
561 | * When the boot option of idle=halt is added, halt is | |
562 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
563 | * won't be used again. | |
564 | * To continue to load the CPU idle driver, don't touch | |
565 | * the boot_option_idle_override. | |
566 | */ | |
567 | pm_idle = default_idle; | |
568 | idle_halt = 1; | |
569 | return 0; | |
da5e09a1 ZY |
570 | } else if (!strcmp(str, "nomwait")) { |
571 | /* | |
572 | * If the boot option of "idle=nomwait" is added, | |
573 | * it means that mwait will be disabled for CPU C2/C3 | |
574 | * states. In such case it won't touch the variable | |
575 | * of boot_option_idle_override. | |
576 | */ | |
577 | idle_nomwait = 1; | |
578 | return 0; | |
c1e3b377 | 579 | } else |
7f424a8b PZ |
580 | return -1; |
581 | ||
582 | boot_option_idle_override = 1; | |
583 | return 0; | |
584 | } | |
585 | early_param("idle", idle_setup); | |
586 | ||
9d62dcdf AW |
587 | unsigned long arch_align_stack(unsigned long sp) |
588 | { | |
589 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
590 | sp -= get_random_int() % 8192; | |
591 | return sp & ~0xf; | |
592 | } | |
593 | ||
594 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
595 | { | |
596 | unsigned long range_end = mm->brk + 0x02000000; | |
597 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
598 | } | |
599 |