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c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
ced3fcae | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
ced3fcae | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
282ccf6e | 117 | #include <linux/interrupt.h> |
c5aa9e3b LT |
118 | #include <linux/module.h> |
119 | #include <linux/kmod.h> | |
c5aa9e3b LT |
120 | #include <linux/mdio.h> |
121 | #include <linux/phy.h> | |
122 | #include <linux/of.h> | |
7c12aa08 LT |
123 | #include <linux/bitops.h> |
124 | #include <linux/jiffies.h> | |
c5aa9e3b LT |
125 | |
126 | #include "xgbe.h" | |
127 | #include "xgbe-common.h" | |
128 | ||
1bf40ada LT |
129 | static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) |
130 | { | |
131 | int reg; | |
132 | ||
133 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
134 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
135 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
136 | } | |
137 | ||
138 | static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) | |
139 | { | |
140 | int reg; | |
141 | ||
142 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
143 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
144 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
145 | ||
146 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
147 | reg &= ~XGBE_PCS_CL37_BP; | |
148 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
149 | } | |
150 | ||
151 | static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) | |
152 | { | |
153 | int reg; | |
154 | ||
155 | reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); | |
156 | reg |= XGBE_PCS_CL37_BP; | |
157 | XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); | |
158 | ||
159 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
160 | reg |= XGBE_AN_CL37_INT_MASK; | |
161 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
162 | } | |
163 | ||
a64def41 LT |
164 | static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) |
165 | { | |
166 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); | |
167 | } | |
168 | ||
169 | static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) | |
170 | { | |
171 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); | |
172 | } | |
173 | ||
174 | static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) | |
175 | { | |
176 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); | |
177 | } | |
178 | ||
179 | static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) | |
180 | { | |
181 | switch (pdata->an_mode) { | |
182 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 183 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
184 | xgbe_an73_enable_interrupts(pdata); |
185 | break; | |
1bf40ada LT |
186 | case XGBE_AN_MODE_CL37: |
187 | case XGBE_AN_MODE_CL37_SGMII: | |
188 | xgbe_an37_enable_interrupts(pdata); | |
189 | break; | |
a64def41 LT |
190 | default: |
191 | break; | |
192 | } | |
193 | } | |
194 | ||
1bf40ada LT |
195 | static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) |
196 | { | |
197 | xgbe_an73_clear_interrupts(pdata); | |
198 | xgbe_an37_clear_interrupts(pdata); | |
199 | } | |
200 | ||
a64def41 | 201 | static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata) |
c5aa9e3b | 202 | { |
7c12aa08 | 203 | unsigned int reg; |
c5aa9e3b | 204 | |
7c12aa08 | 205 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); |
c5aa9e3b | 206 | |
7c12aa08 LT |
207 | reg |= XGBE_KR_TRAINING_ENABLE; |
208 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
209 | } | |
210 | ||
a64def41 | 211 | static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
212 | { |
213 | unsigned int reg; | |
214 | ||
215 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
216 | ||
217 | reg &= ~XGBE_KR_TRAINING_ENABLE; | |
218 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); | |
219 | } | |
220 | ||
e57f7a3f | 221 | static void xgbe_kr_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 222 | { |
7c12aa08 | 223 | /* Enable KR training */ |
a64def41 | 224 | xgbe_an73_enable_kr_training(pdata); |
7c12aa08 LT |
225 | |
226 | /* Set MAC to 10G speed */ | |
e57f7a3f LT |
227 | pdata->hw_if.set_speed(pdata, SPEED_10000); |
228 | ||
229 | /* Call PHY implementation support to complete rate change */ | |
230 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); | |
7c12aa08 LT |
231 | } |
232 | ||
e57f7a3f | 233 | static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 234 | { |
7c12aa08 | 235 | /* Disable KR training */ |
a64def41 | 236 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
237 | |
238 | /* Set MAC to 2.5G speed */ | |
e57f7a3f LT |
239 | pdata->hw_if.set_speed(pdata, SPEED_2500); |
240 | ||
241 | /* Call PHY implementation support to complete rate change */ | |
242 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); | |
7c12aa08 LT |
243 | } |
244 | ||
e57f7a3f | 245 | static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 246 | { |
7c12aa08 | 247 | /* Disable KR training */ |
a64def41 | 248 | xgbe_an73_disable_kr_training(pdata); |
7c12aa08 LT |
249 | |
250 | /* Set MAC to 1G speed */ | |
e57f7a3f LT |
251 | pdata->hw_if.set_speed(pdata, SPEED_1000); |
252 | ||
253 | /* Call PHY implementation support to complete rate change */ | |
254 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); | |
7c12aa08 LT |
255 | } |
256 | ||
abf0a1c2 LT |
257 | static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) |
258 | { | |
d7445d1f LT |
259 | /* If a KR re-driver is present, change to KR mode instead */ |
260 | if (pdata->kr_redrv) | |
261 | return xgbe_kr_mode(pdata); | |
262 | ||
abf0a1c2 LT |
263 | /* Disable KR training */ |
264 | xgbe_an73_disable_kr_training(pdata); | |
265 | ||
266 | /* Set MAC to 10G speed */ | |
267 | pdata->hw_if.set_speed(pdata, SPEED_10000); | |
268 | ||
269 | /* Call PHY implementation support to complete rate change */ | |
270 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); | |
271 | } | |
272 | ||
273 | static void xgbe_x_mode(struct xgbe_prv_data *pdata) | |
274 | { | |
275 | /* Disable KR training */ | |
276 | xgbe_an73_disable_kr_training(pdata); | |
277 | ||
278 | /* Set MAC to 1G speed */ | |
279 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
280 | ||
281 | /* Call PHY implementation support to complete rate change */ | |
282 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); | |
283 | } | |
284 | ||
285 | static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) | |
286 | { | |
287 | /* Disable KR training */ | |
288 | xgbe_an73_disable_kr_training(pdata); | |
289 | ||
290 | /* Set MAC to 1G speed */ | |
291 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
292 | ||
293 | /* Call PHY implementation support to complete rate change */ | |
294 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); | |
295 | } | |
296 | ||
297 | static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) | |
298 | { | |
299 | /* Disable KR training */ | |
300 | xgbe_an73_disable_kr_training(pdata); | |
301 | ||
302 | /* Set MAC to 1G speed */ | |
303 | pdata->hw_if.set_speed(pdata, SPEED_1000); | |
304 | ||
305 | /* Call PHY implementation support to complete rate change */ | |
306 | pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); | |
307 | } | |
308 | ||
e57f7a3f | 309 | static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) |
7c12aa08 | 310 | { |
e57f7a3f | 311 | return pdata->phy_if.phy_impl.cur_mode(pdata); |
7c12aa08 LT |
312 | } |
313 | ||
314 | static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) | |
315 | { | |
e57f7a3f | 316 | return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); |
7c12aa08 LT |
317 | } |
318 | ||
e57f7a3f LT |
319 | static void xgbe_change_mode(struct xgbe_prv_data *pdata, |
320 | enum xgbe_mode mode) | |
7c12aa08 | 321 | { |
e57f7a3f LT |
322 | switch (mode) { |
323 | case XGBE_MODE_KX_1000: | |
324 | xgbe_kx_1000_mode(pdata); | |
325 | break; | |
326 | case XGBE_MODE_KX_2500: | |
327 | xgbe_kx_2500_mode(pdata); | |
328 | break; | |
329 | case XGBE_MODE_KR: | |
330 | xgbe_kr_mode(pdata); | |
331 | break; | |
abf0a1c2 LT |
332 | case XGBE_MODE_SGMII_100: |
333 | xgbe_sgmii_100_mode(pdata); | |
334 | break; | |
335 | case XGBE_MODE_SGMII_1000: | |
336 | xgbe_sgmii_1000_mode(pdata); | |
337 | break; | |
338 | case XGBE_MODE_X: | |
339 | xgbe_x_mode(pdata); | |
340 | break; | |
341 | case XGBE_MODE_SFI: | |
342 | xgbe_sfi_mode(pdata); | |
343 | break; | |
e57f7a3f LT |
344 | case XGBE_MODE_UNKNOWN: |
345 | break; | |
346 | default: | |
347 | netif_dbg(pdata, link, pdata->netdev, | |
348 | "invalid operation mode requested (%u)\n", mode); | |
7c12aa08 LT |
349 | } |
350 | } | |
351 | ||
e57f7a3f | 352 | static void xgbe_switch_mode(struct xgbe_prv_data *pdata) |
471e14b2 | 353 | { |
e57f7a3f | 354 | xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); |
471e14b2 LT |
355 | } |
356 | ||
e57f7a3f LT |
357 | static void xgbe_set_mode(struct xgbe_prv_data *pdata, |
358 | enum xgbe_mode mode) | |
471e14b2 | 359 | { |
e57f7a3f LT |
360 | if (mode == xgbe_cur_mode(pdata)) |
361 | return; | |
471e14b2 | 362 | |
e57f7a3f | 363 | xgbe_change_mode(pdata, mode); |
471e14b2 LT |
364 | } |
365 | ||
e57f7a3f LT |
366 | static bool xgbe_use_mode(struct xgbe_prv_data *pdata, |
367 | enum xgbe_mode mode) | |
471e14b2 | 368 | { |
e57f7a3f | 369 | return pdata->phy_if.phy_impl.use_mode(pdata, mode); |
471e14b2 LT |
370 | } |
371 | ||
1bf40ada LT |
372 | static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, |
373 | bool restart) | |
374 | { | |
375 | unsigned int reg; | |
376 | ||
377 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); | |
378 | reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; | |
379 | ||
380 | if (enable) | |
381 | reg |= MDIO_VEND2_CTRL1_AN_ENABLE; | |
382 | ||
383 | if (restart) | |
384 | reg |= MDIO_VEND2_CTRL1_AN_RESTART; | |
385 | ||
386 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); | |
387 | } | |
388 | ||
389 | static void xgbe_an37_restart(struct xgbe_prv_data *pdata) | |
390 | { | |
391 | xgbe_an37_enable_interrupts(pdata); | |
392 | xgbe_an37_set(pdata, true, true); | |
393 | ||
394 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); | |
395 | } | |
396 | ||
397 | static void xgbe_an37_disable(struct xgbe_prv_data *pdata) | |
398 | { | |
399 | xgbe_an37_set(pdata, false, false); | |
400 | xgbe_an37_disable_interrupts(pdata); | |
401 | ||
402 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); | |
403 | } | |
404 | ||
a64def41 LT |
405 | static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, |
406 | bool restart) | |
7c12aa08 LT |
407 | { |
408 | unsigned int reg; | |
409 | ||
410 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); | |
411 | reg &= ~MDIO_AN_CTRL1_ENABLE; | |
412 | ||
413 | if (enable) | |
414 | reg |= MDIO_AN_CTRL1_ENABLE; | |
415 | ||
416 | if (restart) | |
417 | reg |= MDIO_AN_CTRL1_RESTART; | |
418 | ||
419 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); | |
420 | } | |
421 | ||
a64def41 | 422 | static void xgbe_an73_restart(struct xgbe_prv_data *pdata) |
7c12aa08 | 423 | { |
a64def41 LT |
424 | xgbe_an73_enable_interrupts(pdata); |
425 | xgbe_an73_set(pdata, true, true); | |
d5c78399 | 426 | |
a64def41 | 427 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); |
7c12aa08 LT |
428 | } |
429 | ||
a64def41 | 430 | static void xgbe_an73_disable(struct xgbe_prv_data *pdata) |
7c12aa08 | 431 | { |
a64def41 LT |
432 | xgbe_an73_set(pdata, false, false); |
433 | xgbe_an73_disable_interrupts(pdata); | |
d5c78399 | 434 | |
a64def41 | 435 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); |
7c12aa08 LT |
436 | } |
437 | ||
a64def41 LT |
438 | static void xgbe_an_restart(struct xgbe_prv_data *pdata) |
439 | { | |
440 | switch (pdata->an_mode) { | |
441 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 442 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
443 | xgbe_an73_restart(pdata); |
444 | break; | |
1bf40ada LT |
445 | case XGBE_AN_MODE_CL37: |
446 | case XGBE_AN_MODE_CL37_SGMII: | |
447 | xgbe_an37_restart(pdata); | |
448 | break; | |
a64def41 LT |
449 | default: |
450 | break; | |
451 | } | |
452 | } | |
453 | ||
454 | static void xgbe_an_disable(struct xgbe_prv_data *pdata) | |
455 | { | |
456 | switch (pdata->an_mode) { | |
457 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 458 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
459 | xgbe_an73_disable(pdata); |
460 | break; | |
1bf40ada LT |
461 | case XGBE_AN_MODE_CL37: |
462 | case XGBE_AN_MODE_CL37_SGMII: | |
463 | xgbe_an37_disable(pdata); | |
464 | break; | |
a64def41 LT |
465 | default: |
466 | break; | |
467 | } | |
468 | } | |
469 | ||
1bf40ada LT |
470 | static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) |
471 | { | |
472 | xgbe_an73_disable(pdata); | |
473 | xgbe_an37_disable(pdata); | |
474 | } | |
475 | ||
a64def41 LT |
476 | static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, |
477 | enum xgbe_rx *state) | |
7c12aa08 LT |
478 | { |
479 | unsigned int ad_reg, lp_reg, reg; | |
480 | ||
481 | *state = XGBE_RX_COMPLETE; | |
482 | ||
483 | /* If we're not in KR mode then we're done */ | |
484 | if (!xgbe_in_kr_mode(pdata)) | |
485 | return XGBE_AN_PAGE_RECEIVED; | |
486 | ||
487 | /* Enable/Disable FEC */ | |
488 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
489 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); | |
490 | ||
491 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); | |
492 | reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
493 | if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) | |
494 | reg |= pdata->fec_ability; | |
495 | ||
496 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); | |
497 | ||
498 | /* Start KR training */ | |
499 | reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); | |
500 | if (reg & XGBE_KR_TRAINING_ENABLE) { | |
e57f7a3f LT |
501 | if (pdata->phy_if.phy_impl.kr_training_pre) |
502 | pdata->phy_if.phy_impl.kr_training_pre(pdata); | |
7c12aa08 LT |
503 | |
504 | reg |= XGBE_KR_TRAINING_START; | |
505 | XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, | |
506 | reg); | |
507 | ||
e57f7a3f LT |
508 | if (pdata->phy_if.phy_impl.kr_training_post) |
509 | pdata->phy_if.phy_impl.kr_training_post(pdata); | |
d5c78399 LT |
510 | |
511 | netif_dbg(pdata, link, pdata->netdev, | |
512 | "KR training initiated\n"); | |
7c12aa08 LT |
513 | } |
514 | ||
515 | return XGBE_AN_PAGE_RECEIVED; | |
516 | } | |
517 | ||
a64def41 LT |
518 | static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, |
519 | enum xgbe_rx *state) | |
7c12aa08 LT |
520 | { |
521 | u16 msg; | |
522 | ||
523 | *state = XGBE_RX_XNP; | |
524 | ||
525 | msg = XGBE_XNP_MCF_NULL_MESSAGE; | |
526 | msg |= XGBE_XNP_MP_FORMATTED; | |
527 | ||
528 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); | |
529 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); | |
530 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); | |
531 | ||
532 | return XGBE_AN_PAGE_RECEIVED; | |
533 | } | |
534 | ||
a64def41 LT |
535 | static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, |
536 | enum xgbe_rx *state) | |
7c12aa08 LT |
537 | { |
538 | unsigned int link_support; | |
539 | unsigned int reg, ad_reg, lp_reg; | |
540 | ||
541 | /* Read Base Ability register 2 first */ | |
542 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); | |
543 | ||
544 | /* Check for a supported mode, otherwise restart in a different one */ | |
545 | link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; | |
546 | if (!(reg & link_support)) | |
547 | return XGBE_AN_INCOMPAT_LINK; | |
548 | ||
549 | /* Check Extended Next Page support */ | |
550 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
551 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); | |
552 | ||
553 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
554 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
555 | ? xgbe_an73_tx_xnp(pdata, state) |
556 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
557 | } |
558 | ||
a64def41 LT |
559 | static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, |
560 | enum xgbe_rx *state) | |
7c12aa08 LT |
561 | { |
562 | unsigned int ad_reg, lp_reg; | |
563 | ||
564 | /* Check Extended Next Page support */ | |
565 | ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); | |
566 | lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); | |
567 | ||
568 | return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || | |
569 | (lp_reg & XGBE_XNP_NP_EXCHANGE)) | |
a64def41 LT |
570 | ? xgbe_an73_tx_xnp(pdata, state) |
571 | : xgbe_an73_tx_training(pdata, state); | |
7c12aa08 LT |
572 | } |
573 | ||
a64def41 | 574 | static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
575 | { |
576 | enum xgbe_rx *state; | |
577 | unsigned long an_timeout; | |
578 | enum xgbe_an ret; | |
579 | ||
580 | if (!pdata->an_start) { | |
581 | pdata->an_start = jiffies; | |
582 | } else { | |
583 | an_timeout = pdata->an_start + | |
584 | msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); | |
585 | if (time_after(jiffies, an_timeout)) { | |
586 | /* Auto-negotiation timed out, reset state */ | |
587 | pdata->kr_state = XGBE_RX_BPA; | |
588 | pdata->kx_state = XGBE_RX_BPA; | |
589 | ||
590 | pdata->an_start = jiffies; | |
d5c78399 LT |
591 | |
592 | netif_dbg(pdata, link, pdata->netdev, | |
a64def41 | 593 | "CL73 AN timed out, resetting state\n"); |
7c12aa08 LT |
594 | } |
595 | } | |
596 | ||
597 | state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state | |
e57f7a3f | 598 | : &pdata->kx_state; |
7c12aa08 LT |
599 | |
600 | switch (*state) { | |
601 | case XGBE_RX_BPA: | |
a64def41 | 602 | ret = xgbe_an73_rx_bpa(pdata, state); |
7c12aa08 LT |
603 | break; |
604 | ||
605 | case XGBE_RX_XNP: | |
a64def41 | 606 | ret = xgbe_an73_rx_xnp(pdata, state); |
7c12aa08 LT |
607 | break; |
608 | ||
609 | default: | |
610 | ret = XGBE_AN_ERROR; | |
611 | } | |
612 | ||
613 | return ret; | |
614 | } | |
615 | ||
a64def41 | 616 | static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) |
7c12aa08 LT |
617 | { |
618 | /* Be sure we aren't looping trying to negotiate */ | |
619 | if (xgbe_in_kr_mode(pdata)) { | |
620 | pdata->kr_state = XGBE_RX_ERROR; | |
621 | ||
622 | if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) && | |
623 | !(pdata->phy.advertising & ADVERTISED_2500baseX_Full)) | |
624 | return XGBE_AN_NO_LINK; | |
625 | ||
626 | if (pdata->kx_state != XGBE_RX_BPA) | |
627 | return XGBE_AN_NO_LINK; | |
628 | } else { | |
629 | pdata->kx_state = XGBE_RX_ERROR; | |
630 | ||
631 | if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full)) | |
632 | return XGBE_AN_NO_LINK; | |
633 | ||
634 | if (pdata->kr_state != XGBE_RX_BPA) | |
635 | return XGBE_AN_NO_LINK; | |
636 | } | |
637 | ||
a64def41 | 638 | xgbe_an73_disable(pdata); |
7c12aa08 LT |
639 | |
640 | xgbe_switch_mode(pdata); | |
641 | ||
a64def41 | 642 | xgbe_an73_restart(pdata); |
7c12aa08 LT |
643 | |
644 | return XGBE_AN_INCOMPAT_LINK; | |
645 | } | |
646 | ||
1bf40ada LT |
647 | static void xgbe_an37_isr(struct xgbe_prv_data *pdata) |
648 | { | |
649 | unsigned int reg; | |
650 | ||
651 | /* Disable AN interrupts */ | |
652 | xgbe_an37_disable_interrupts(pdata); | |
653 | ||
654 | /* Save the interrupt(s) that fired */ | |
655 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); | |
656 | pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; | |
657 | pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; | |
658 | ||
659 | if (pdata->an_int) { | |
660 | /* Clear the interrupt(s) that fired and process them */ | |
661 | reg &= ~XGBE_AN_CL37_INT_MASK; | |
662 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); | |
663 | ||
664 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
665 | } else { | |
666 | /* Enable AN interrupts */ | |
667 | xgbe_an37_enable_interrupts(pdata); | |
668 | } | |
669 | } | |
670 | ||
a64def41 | 671 | static void xgbe_an73_isr(struct xgbe_prv_data *pdata) |
7c12aa08 | 672 | { |
ced3fcae | 673 | /* Disable AN interrupts */ |
a64def41 | 674 | xgbe_an73_disable_interrupts(pdata); |
7c12aa08 | 675 | |
ced3fcae LT |
676 | /* Save the interrupt(s) that fired */ |
677 | pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); | |
678 | ||
679 | if (pdata->an_int) { | |
680 | /* Clear the interrupt(s) that fired and process them */ | |
681 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); | |
682 | ||
683 | queue_work(pdata->an_workqueue, &pdata->an_irq_work); | |
684 | } else { | |
685 | /* Enable AN interrupts */ | |
a64def41 LT |
686 | xgbe_an73_enable_interrupts(pdata); |
687 | } | |
688 | } | |
689 | ||
690 | static irqreturn_t xgbe_an_isr(int irq, void *data) | |
691 | { | |
692 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
693 | ||
694 | netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); | |
695 | ||
696 | switch (pdata->an_mode) { | |
697 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 698 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
699 | xgbe_an73_isr(pdata); |
700 | break; | |
1bf40ada LT |
701 | case XGBE_AN_MODE_CL37: |
702 | case XGBE_AN_MODE_CL37_SGMII: | |
703 | xgbe_an37_isr(pdata); | |
704 | break; | |
a64def41 LT |
705 | default: |
706 | break; | |
ced3fcae | 707 | } |
7c12aa08 LT |
708 | |
709 | return IRQ_HANDLED; | |
710 | } | |
711 | ||
47f164de LT |
712 | static irqreturn_t xgbe_an_combined_isr(int irq, struct xgbe_prv_data *pdata) |
713 | { | |
714 | return xgbe_an_isr(irq, pdata); | |
715 | } | |
716 | ||
7c12aa08 LT |
717 | static void xgbe_an_irq_work(struct work_struct *work) |
718 | { | |
719 | struct xgbe_prv_data *pdata = container_of(work, | |
720 | struct xgbe_prv_data, | |
721 | an_irq_work); | |
722 | ||
723 | /* Avoid a race between enabling the IRQ and exiting the work by | |
724 | * waiting for the work to finish and then queueing it | |
725 | */ | |
726 | flush_work(&pdata->an_work); | |
727 | queue_work(pdata->an_workqueue, &pdata->an_work); | |
728 | } | |
729 | ||
d5c78399 LT |
730 | static const char *xgbe_state_as_string(enum xgbe_an state) |
731 | { | |
732 | switch (state) { | |
733 | case XGBE_AN_READY: | |
734 | return "Ready"; | |
735 | case XGBE_AN_PAGE_RECEIVED: | |
736 | return "Page-Received"; | |
737 | case XGBE_AN_INCOMPAT_LINK: | |
738 | return "Incompatible-Link"; | |
739 | case XGBE_AN_COMPLETE: | |
740 | return "Complete"; | |
741 | case XGBE_AN_NO_LINK: | |
742 | return "No-Link"; | |
743 | case XGBE_AN_ERROR: | |
744 | return "Error"; | |
745 | default: | |
746 | return "Undefined"; | |
747 | } | |
748 | } | |
749 | ||
1bf40ada LT |
750 | static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) |
751 | { | |
752 | enum xgbe_an cur_state = pdata->an_state; | |
753 | ||
754 | if (!pdata->an_int) | |
755 | return; | |
756 | ||
757 | if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { | |
758 | pdata->an_state = XGBE_AN_COMPLETE; | |
759 | pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; | |
760 | ||
761 | /* If SGMII is enabled, check the link status */ | |
762 | if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && | |
763 | !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) | |
764 | pdata->an_state = XGBE_AN_NO_LINK; | |
765 | } | |
766 | ||
767 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", | |
768 | xgbe_state_as_string(pdata->an_state)); | |
769 | ||
770 | cur_state = pdata->an_state; | |
771 | ||
772 | switch (pdata->an_state) { | |
773 | case XGBE_AN_READY: | |
774 | break; | |
775 | ||
776 | case XGBE_AN_COMPLETE: | |
777 | netif_dbg(pdata, link, pdata->netdev, | |
778 | "Auto negotiation successful\n"); | |
779 | break; | |
780 | ||
781 | case XGBE_AN_NO_LINK: | |
782 | break; | |
783 | ||
784 | default: | |
785 | pdata->an_state = XGBE_AN_ERROR; | |
786 | } | |
787 | ||
788 | if (pdata->an_state == XGBE_AN_ERROR) { | |
789 | netdev_err(pdata->netdev, | |
790 | "error during auto-negotiation, state=%u\n", | |
791 | cur_state); | |
792 | ||
793 | pdata->an_int = 0; | |
794 | xgbe_an37_clear_interrupts(pdata); | |
795 | } | |
796 | ||
797 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
798 | pdata->an_result = pdata->an_state; | |
799 | pdata->an_state = XGBE_AN_READY; | |
800 | ||
801 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", | |
802 | xgbe_state_as_string(pdata->an_result)); | |
803 | } | |
804 | ||
805 | xgbe_an37_enable_interrupts(pdata); | |
806 | } | |
807 | ||
a64def41 | 808 | static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) |
7c12aa08 | 809 | { |
7c12aa08 | 810 | enum xgbe_an cur_state = pdata->an_state; |
7c12aa08 | 811 | |
ced3fcae | 812 | if (!pdata->an_int) |
a64def41 | 813 | return; |
7c12aa08 LT |
814 | |
815 | next_int: | |
a64def41 | 816 | if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { |
7c12aa08 | 817 | pdata->an_state = XGBE_AN_PAGE_RECEIVED; |
a64def41 LT |
818 | pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; |
819 | } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { | |
7c12aa08 | 820 | pdata->an_state = XGBE_AN_INCOMPAT_LINK; |
a64def41 LT |
821 | pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; |
822 | } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { | |
7c12aa08 | 823 | pdata->an_state = XGBE_AN_COMPLETE; |
a64def41 | 824 | pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; |
7c12aa08 LT |
825 | } else { |
826 | pdata->an_state = XGBE_AN_ERROR; | |
7c12aa08 LT |
827 | } |
828 | ||
7c12aa08 | 829 | again: |
a64def41 | 830 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", |
d5c78399 LT |
831 | xgbe_state_as_string(pdata->an_state)); |
832 | ||
7c12aa08 LT |
833 | cur_state = pdata->an_state; |
834 | ||
835 | switch (pdata->an_state) { | |
836 | case XGBE_AN_READY: | |
837 | pdata->an_supported = 0; | |
838 | break; | |
839 | ||
840 | case XGBE_AN_PAGE_RECEIVED: | |
a64def41 | 841 | pdata->an_state = xgbe_an73_page_received(pdata); |
7c12aa08 LT |
842 | pdata->an_supported++; |
843 | break; | |
c5aa9e3b | 844 | |
7c12aa08 LT |
845 | case XGBE_AN_INCOMPAT_LINK: |
846 | pdata->an_supported = 0; | |
847 | pdata->parallel_detect = 0; | |
a64def41 | 848 | pdata->an_state = xgbe_an73_incompat_link(pdata); |
7c12aa08 | 849 | break; |
c5aa9e3b | 850 | |
7c12aa08 LT |
851 | case XGBE_AN_COMPLETE: |
852 | pdata->parallel_detect = pdata->an_supported ? 0 : 1; | |
d5c78399 LT |
853 | netif_dbg(pdata, link, pdata->netdev, "%s successful\n", |
854 | pdata->an_supported ? "Auto negotiation" | |
855 | : "Parallel detection"); | |
7c12aa08 LT |
856 | break; |
857 | ||
858 | case XGBE_AN_NO_LINK: | |
859 | break; | |
860 | ||
861 | default: | |
862 | pdata->an_state = XGBE_AN_ERROR; | |
863 | } | |
864 | ||
865 | if (pdata->an_state == XGBE_AN_NO_LINK) { | |
ced3fcae | 866 | pdata->an_int = 0; |
a64def41 | 867 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
868 | } else if (pdata->an_state == XGBE_AN_ERROR) { |
869 | netdev_err(pdata->netdev, | |
870 | "error during auto-negotiation, state=%u\n", | |
871 | cur_state); | |
872 | ||
ced3fcae | 873 | pdata->an_int = 0; |
a64def41 | 874 | xgbe_an73_clear_interrupts(pdata); |
7c12aa08 LT |
875 | } |
876 | ||
877 | if (pdata->an_state >= XGBE_AN_COMPLETE) { | |
878 | pdata->an_result = pdata->an_state; | |
879 | pdata->an_state = XGBE_AN_READY; | |
880 | pdata->kr_state = XGBE_RX_BPA; | |
881 | pdata->kx_state = XGBE_RX_BPA; | |
882 | pdata->an_start = 0; | |
d5c78399 | 883 | |
a64def41 | 884 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", |
d5c78399 | 885 | xgbe_state_as_string(pdata->an_result)); |
7c12aa08 LT |
886 | } |
887 | ||
888 | if (cur_state != pdata->an_state) | |
889 | goto again; | |
890 | ||
ced3fcae | 891 | if (pdata->an_int) |
7c12aa08 LT |
892 | goto next_int; |
893 | ||
a64def41 LT |
894 | xgbe_an73_enable_interrupts(pdata); |
895 | } | |
896 | ||
897 | static void xgbe_an_state_machine(struct work_struct *work) | |
898 | { | |
899 | struct xgbe_prv_data *pdata = container_of(work, | |
900 | struct xgbe_prv_data, | |
901 | an_work); | |
902 | ||
903 | mutex_lock(&pdata->an_mutex); | |
904 | ||
905 | switch (pdata->an_mode) { | |
906 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 907 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
908 | xgbe_an73_state_machine(pdata); |
909 | break; | |
1bf40ada LT |
910 | case XGBE_AN_MODE_CL37: |
911 | case XGBE_AN_MODE_CL37_SGMII: | |
912 | xgbe_an37_state_machine(pdata); | |
913 | break; | |
a64def41 LT |
914 | default: |
915 | break; | |
916 | } | |
7c12aa08 LT |
917 | |
918 | mutex_unlock(&pdata->an_mutex); | |
c5aa9e3b LT |
919 | } |
920 | ||
1bf40ada LT |
921 | static void xgbe_an37_init(struct xgbe_prv_data *pdata) |
922 | { | |
d7445d1f LT |
923 | unsigned int advertising, reg; |
924 | ||
925 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
1bf40ada LT |
926 | |
927 | /* Set up Advertisement register */ | |
928 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); | |
d7445d1f | 929 | if (advertising & ADVERTISED_Pause) |
1bf40ada LT |
930 | reg |= 0x100; |
931 | else | |
932 | reg &= ~0x100; | |
933 | ||
d7445d1f | 934 | if (advertising & ADVERTISED_Asym_Pause) |
1bf40ada LT |
935 | reg |= 0x80; |
936 | else | |
937 | reg &= ~0x80; | |
938 | ||
939 | /* Full duplex, but not half */ | |
940 | reg |= XGBE_AN_CL37_FD_MASK; | |
941 | reg &= ~XGBE_AN_CL37_HD_MASK; | |
942 | ||
943 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); | |
944 | ||
945 | /* Set up the Control register */ | |
946 | reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); | |
e6fbd47a LT |
947 | reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; |
948 | reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; | |
1bf40ada LT |
949 | |
950 | switch (pdata->an_mode) { | |
951 | case XGBE_AN_MODE_CL37: | |
952 | reg |= XGBE_AN_CL37_PCS_MODE_BASEX; | |
953 | break; | |
954 | case XGBE_AN_MODE_CL37_SGMII: | |
955 | reg |= XGBE_AN_CL37_PCS_MODE_SGMII; | |
956 | break; | |
957 | default: | |
958 | break; | |
959 | } | |
960 | ||
961 | XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); | |
962 | ||
963 | netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", | |
964 | (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); | |
965 | } | |
966 | ||
a64def41 | 967 | static void xgbe_an73_init(struct xgbe_prv_data *pdata) |
c5aa9e3b | 968 | { |
d7445d1f LT |
969 | unsigned int advertising, reg; |
970 | ||
971 | advertising = pdata->phy_if.phy_impl.an_advertising(pdata); | |
7c12aa08 LT |
972 | |
973 | /* Set up Advertisement register 3 first */ | |
974 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); | |
d7445d1f | 975 | if (advertising & ADVERTISED_10000baseR_FEC) |
7c12aa08 LT |
976 | reg |= 0xc000; |
977 | else | |
978 | reg &= ~0xc000; | |
979 | ||
980 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); | |
981 | ||
982 | /* Set up Advertisement register 2 next */ | |
983 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); | |
d7445d1f | 984 | if (advertising & ADVERTISED_10000baseKR_Full) |
7c12aa08 LT |
985 | reg |= 0x80; |
986 | else | |
987 | reg &= ~0x80; | |
988 | ||
d7445d1f LT |
989 | if ((advertising & ADVERTISED_1000baseKX_Full) || |
990 | (advertising & ADVERTISED_2500baseX_Full)) | |
7c12aa08 LT |
991 | reg |= 0x20; |
992 | else | |
993 | reg &= ~0x20; | |
994 | ||
995 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); | |
c5aa9e3b | 996 | |
7c12aa08 LT |
997 | /* Set up Advertisement register 1 last */ |
998 | reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); | |
d7445d1f | 999 | if (advertising & ADVERTISED_Pause) |
7c12aa08 LT |
1000 | reg |= 0x400; |
1001 | else | |
1002 | reg &= ~0x400; | |
c5aa9e3b | 1003 | |
d7445d1f | 1004 | if (advertising & ADVERTISED_Asym_Pause) |
7c12aa08 LT |
1005 | reg |= 0x800; |
1006 | else | |
1007 | reg &= ~0x800; | |
1008 | ||
1009 | /* We don't intend to perform XNP */ | |
1010 | reg &= ~XGBE_XNP_NP_EXCHANGE; | |
1011 | ||
1012 | XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); | |
d5c78399 | 1013 | |
a64def41 LT |
1014 | netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); |
1015 | } | |
1016 | ||
1017 | static void xgbe_an_init(struct xgbe_prv_data *pdata) | |
1018 | { | |
1019 | /* Set up advertisement registers based on current settings */ | |
1020 | pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); | |
1021 | switch (pdata->an_mode) { | |
1022 | case XGBE_AN_MODE_CL73: | |
d7445d1f | 1023 | case XGBE_AN_MODE_CL73_REDRV: |
a64def41 LT |
1024 | xgbe_an73_init(pdata); |
1025 | break; | |
1bf40ada LT |
1026 | case XGBE_AN_MODE_CL37: |
1027 | case XGBE_AN_MODE_CL37_SGMII: | |
1028 | xgbe_an37_init(pdata); | |
1029 | break; | |
a64def41 LT |
1030 | default: |
1031 | break; | |
1032 | } | |
7c12aa08 LT |
1033 | } |
1034 | ||
c1ce2f77 LT |
1035 | static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) |
1036 | { | |
1037 | if (pdata->tx_pause && pdata->rx_pause) | |
1038 | return "rx/tx"; | |
1039 | else if (pdata->rx_pause) | |
1040 | return "rx"; | |
1041 | else if (pdata->tx_pause) | |
1042 | return "tx"; | |
1043 | else | |
1044 | return "off"; | |
1045 | } | |
1046 | ||
7c12aa08 LT |
1047 | static const char *xgbe_phy_speed_string(int speed) |
1048 | { | |
1049 | switch (speed) { | |
abf0a1c2 LT |
1050 | case SPEED_100: |
1051 | return "100Mbps"; | |
7c12aa08 LT |
1052 | case SPEED_1000: |
1053 | return "1Gbps"; | |
1054 | case SPEED_2500: | |
1055 | return "2.5Gbps"; | |
1056 | case SPEED_10000: | |
1057 | return "10Gbps"; | |
1058 | case SPEED_UNKNOWN: | |
1059 | return "Unknown"; | |
1060 | default: | |
1061 | return "Unsupported"; | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) | |
1066 | { | |
1067 | if (pdata->phy.link) | |
1068 | netdev_info(pdata->netdev, | |
1069 | "Link is Up - %s/%s - flow control %s\n", | |
1070 | xgbe_phy_speed_string(pdata->phy.speed), | |
1071 | pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", | |
c1ce2f77 | 1072 | xgbe_phy_fc_string(pdata)); |
7c12aa08 LT |
1073 | else |
1074 | netdev_info(pdata->netdev, "Link is Down\n"); | |
1075 | } | |
1076 | ||
1077 | static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) | |
1078 | { | |
1079 | int new_state = 0; | |
1080 | ||
1081 | if (pdata->phy.link) { | |
1082 | /* Flow control support */ | |
c1ce2f77 | 1083 | pdata->pause_autoneg = pdata->phy.pause_autoneg; |
7c12aa08 | 1084 | |
c1ce2f77 LT |
1085 | if (pdata->tx_pause != pdata->phy.tx_pause) { |
1086 | new_state = 1; | |
7c12aa08 | 1087 | pdata->hw_if.config_tx_flow_control(pdata); |
c1ce2f77 | 1088 | pdata->tx_pause = pdata->phy.tx_pause; |
7c12aa08 LT |
1089 | } |
1090 | ||
c1ce2f77 LT |
1091 | if (pdata->rx_pause != pdata->phy.rx_pause) { |
1092 | new_state = 1; | |
7c12aa08 | 1093 | pdata->hw_if.config_rx_flow_control(pdata); |
c1ce2f77 | 1094 | pdata->rx_pause = pdata->phy.rx_pause; |
7c12aa08 LT |
1095 | } |
1096 | ||
1097 | /* Speed support */ | |
1098 | if (pdata->phy_speed != pdata->phy.speed) { | |
1099 | new_state = 1; | |
1100 | pdata->phy_speed = pdata->phy.speed; | |
1101 | } | |
1102 | ||
1103 | if (pdata->phy_link != pdata->phy.link) { | |
1104 | new_state = 1; | |
1105 | pdata->phy_link = pdata->phy.link; | |
1106 | } | |
1107 | } else if (pdata->phy_link) { | |
1108 | new_state = 1; | |
1109 | pdata->phy_link = 0; | |
1110 | pdata->phy_speed = SPEED_UNKNOWN; | |
1111 | } | |
1112 | ||
1113 | if (new_state && netif_msg_link(pdata)) | |
1114 | xgbe_phy_print_status(pdata); | |
1115 | } | |
1116 | ||
e57f7a3f LT |
1117 | static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) |
1118 | { | |
1119 | return pdata->phy_if.phy_impl.valid_speed(pdata, speed); | |
1120 | } | |
1121 | ||
7c12aa08 LT |
1122 | static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) |
1123 | { | |
e57f7a3f LT |
1124 | enum xgbe_mode mode; |
1125 | ||
d5c78399 LT |
1126 | netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); |
1127 | ||
7c12aa08 | 1128 | /* Disable auto-negotiation */ |
a64def41 | 1129 | xgbe_an_disable(pdata); |
7c12aa08 | 1130 | |
e57f7a3f LT |
1131 | /* Set specified mode for specified speed */ |
1132 | mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); | |
1133 | switch (mode) { | |
1134 | case XGBE_MODE_KX_1000: | |
1135 | case XGBE_MODE_KX_2500: | |
1136 | case XGBE_MODE_KR: | |
abf0a1c2 LT |
1137 | case XGBE_MODE_SGMII_100: |
1138 | case XGBE_MODE_SGMII_1000: | |
1139 | case XGBE_MODE_X: | |
1140 | case XGBE_MODE_SFI: | |
7c12aa08 | 1141 | break; |
e57f7a3f | 1142 | case XGBE_MODE_UNKNOWN: |
7c12aa08 LT |
1143 | default: |
1144 | return -EINVAL; | |
1145 | } | |
c5aa9e3b | 1146 | |
7c12aa08 LT |
1147 | /* Validate duplex mode */ |
1148 | if (pdata->phy.duplex != DUPLEX_FULL) | |
1149 | return -EINVAL; | |
1150 | ||
e57f7a3f LT |
1151 | xgbe_set_mode(pdata, mode); |
1152 | ||
c5aa9e3b LT |
1153 | return 0; |
1154 | } | |
1155 | ||
7c12aa08 LT |
1156 | static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) |
1157 | { | |
abf0a1c2 LT |
1158 | int ret; |
1159 | ||
7c12aa08 LT |
1160 | set_bit(XGBE_LINK_INIT, &pdata->dev_state); |
1161 | pdata->link_check = jiffies; | |
1162 | ||
abf0a1c2 LT |
1163 | ret = pdata->phy_if.phy_impl.an_config(pdata); |
1164 | if (ret) | |
1165 | return ret; | |
1166 | ||
d7445d1f LT |
1167 | if (pdata->phy.autoneg != AUTONEG_ENABLE) { |
1168 | ret = xgbe_phy_config_fixed(pdata); | |
1169 | if (ret || !pdata->kr_redrv) | |
1170 | return ret; | |
7c12aa08 | 1171 | |
d7445d1f LT |
1172 | netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); |
1173 | } else { | |
1174 | netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); | |
1175 | } | |
d5c78399 | 1176 | |
7c12aa08 LT |
1177 | /* Disable auto-negotiation interrupt */ |
1178 | disable_irq(pdata->an_irq); | |
1179 | ||
1180 | /* Start auto-negotiation in a supported mode */ | |
e57f7a3f | 1181 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
7c12aa08 | 1182 | xgbe_set_mode(pdata, XGBE_MODE_KR); |
e57f7a3f LT |
1183 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { |
1184 | xgbe_set_mode(pdata, XGBE_MODE_KX_2500); | |
1185 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1186 | xgbe_set_mode(pdata, XGBE_MODE_KX_1000); | |
abf0a1c2 LT |
1187 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1188 | xgbe_set_mode(pdata, XGBE_MODE_SFI); | |
1189 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1190 | xgbe_set_mode(pdata, XGBE_MODE_X); | |
1191 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1192 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); | |
1193 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1194 | xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); | |
7c12aa08 LT |
1195 | } else { |
1196 | enable_irq(pdata->an_irq); | |
1197 | return -EINVAL; | |
1198 | } | |
1199 | ||
1200 | /* Disable and stop any in progress auto-negotiation */ | |
1bf40ada | 1201 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1202 | |
1203 | /* Clear any auto-negotitation interrupts */ | |
1bf40ada | 1204 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1205 | |
1206 | pdata->an_result = XGBE_AN_READY; | |
1207 | pdata->an_state = XGBE_AN_READY; | |
1208 | pdata->kr_state = XGBE_RX_BPA; | |
1209 | pdata->kx_state = XGBE_RX_BPA; | |
1210 | ||
1211 | /* Re-enable auto-negotiation interrupt */ | |
1212 | enable_irq(pdata->an_irq); | |
1213 | ||
7c12aa08 | 1214 | xgbe_an_init(pdata); |
a64def41 | 1215 | xgbe_an_restart(pdata); |
7c12aa08 LT |
1216 | |
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) | |
1221 | { | |
1222 | int ret; | |
1223 | ||
1224 | mutex_lock(&pdata->an_mutex); | |
1225 | ||
1226 | ret = __xgbe_phy_config_aneg(pdata); | |
1227 | if (ret) | |
1228 | set_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1229 | else | |
1230 | clear_bit(XGBE_LINK_ERR, &pdata->dev_state); | |
1231 | ||
1232 | mutex_unlock(&pdata->an_mutex); | |
1233 | ||
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) | |
1238 | { | |
1239 | return (pdata->an_result == XGBE_AN_COMPLETE); | |
1240 | } | |
1241 | ||
1242 | static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) | |
1243 | { | |
1244 | unsigned long link_timeout; | |
1245 | ||
1246 | link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); | |
d5c78399 LT |
1247 | if (time_after(jiffies, link_timeout)) { |
1248 | netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); | |
7c12aa08 | 1249 | xgbe_phy_config_aneg(pdata); |
d5c78399 | 1250 | } |
7c12aa08 LT |
1251 | } |
1252 | ||
e57f7a3f | 1253 | static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) |
7c12aa08 | 1254 | { |
e57f7a3f | 1255 | return pdata->phy_if.phy_impl.an_outcome(pdata); |
7c12aa08 LT |
1256 | } |
1257 | ||
e57f7a3f | 1258 | static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) |
7c12aa08 | 1259 | { |
e57f7a3f | 1260 | enum xgbe_mode mode; |
7c12aa08 LT |
1261 | |
1262 | pdata->phy.lp_advertising = 0; | |
1263 | ||
1264 | if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) | |
e57f7a3f LT |
1265 | mode = xgbe_cur_mode(pdata); |
1266 | else | |
1267 | mode = xgbe_phy_status_aneg(pdata); | |
7c12aa08 | 1268 | |
e57f7a3f | 1269 | switch (mode) { |
abf0a1c2 LT |
1270 | case XGBE_MODE_SGMII_100: |
1271 | pdata->phy.speed = SPEED_100; | |
1272 | break; | |
1273 | case XGBE_MODE_X: | |
e57f7a3f | 1274 | case XGBE_MODE_KX_1000: |
abf0a1c2 | 1275 | case XGBE_MODE_SGMII_1000: |
e57f7a3f LT |
1276 | pdata->phy.speed = SPEED_1000; |
1277 | break; | |
1278 | case XGBE_MODE_KX_2500: | |
1279 | pdata->phy.speed = SPEED_2500; | |
1280 | break; | |
1281 | case XGBE_MODE_KR: | |
abf0a1c2 | 1282 | case XGBE_MODE_SFI: |
7c12aa08 | 1283 | pdata->phy.speed = SPEED_10000; |
e57f7a3f LT |
1284 | break; |
1285 | case XGBE_MODE_UNKNOWN: | |
1286 | default: | |
7c12aa08 LT |
1287 | pdata->phy.speed = SPEED_UNKNOWN; |
1288 | } | |
1289 | ||
7c12aa08 | 1290 | pdata->phy.duplex = DUPLEX_FULL; |
e57f7a3f LT |
1291 | |
1292 | xgbe_set_mode(pdata, mode); | |
7c12aa08 LT |
1293 | } |
1294 | ||
1295 | static void xgbe_phy_status(struct xgbe_prv_data *pdata) | |
1296 | { | |
e57f7a3f | 1297 | unsigned int link_aneg; |
abf0a1c2 | 1298 | int an_restart; |
7c12aa08 LT |
1299 | |
1300 | if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { | |
50789845 | 1301 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1302 | |
1303 | pdata->phy.link = 0; | |
1304 | goto adjust_link; | |
1305 | } | |
1306 | ||
1307 | link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); | |
1308 | ||
abf0a1c2 LT |
1309 | pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, |
1310 | &an_restart); | |
1311 | if (an_restart) { | |
1312 | xgbe_phy_config_aneg(pdata); | |
1313 | return; | |
1314 | } | |
1315 | ||
7c12aa08 LT |
1316 | if (pdata->phy.link) { |
1317 | if (link_aneg && !xgbe_phy_aneg_done(pdata)) { | |
1318 | xgbe_check_link_timeout(pdata); | |
1319 | return; | |
1320 | } | |
1321 | ||
e57f7a3f | 1322 | xgbe_phy_status_result(pdata); |
7c12aa08 LT |
1323 | |
1324 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) | |
1325 | clear_bit(XGBE_LINK_INIT, &pdata->dev_state); | |
1326 | ||
50789845 | 1327 | netif_carrier_on(pdata->netdev); |
7c12aa08 LT |
1328 | } else { |
1329 | if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { | |
1330 | xgbe_check_link_timeout(pdata); | |
1331 | ||
1332 | if (link_aneg) | |
1333 | return; | |
1334 | } | |
1335 | ||
e57f7a3f | 1336 | xgbe_phy_status_result(pdata); |
7c12aa08 | 1337 | |
50789845 | 1338 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1339 | } |
1340 | ||
1341 | adjust_link: | |
1342 | xgbe_phy_adjust_link(pdata); | |
1343 | } | |
1344 | ||
1345 | static void xgbe_phy_stop(struct xgbe_prv_data *pdata) | |
1346 | { | |
d5c78399 LT |
1347 | netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); |
1348 | ||
e57f7a3f LT |
1349 | if (!pdata->phy_started) |
1350 | return; | |
1351 | ||
1352 | /* Indicate the PHY is down */ | |
1353 | pdata->phy_started = 0; | |
1354 | ||
7c12aa08 | 1355 | /* Disable auto-negotiation */ |
1bf40ada | 1356 | xgbe_an_disable_all(pdata); |
7c12aa08 | 1357 | |
47f164de LT |
1358 | if (pdata->dev_irq != pdata->an_irq) |
1359 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1360 | |
e57f7a3f LT |
1361 | pdata->phy_if.phy_impl.stop(pdata); |
1362 | ||
7c12aa08 | 1363 | pdata->phy.link = 0; |
50789845 | 1364 | netif_carrier_off(pdata->netdev); |
7c12aa08 LT |
1365 | |
1366 | xgbe_phy_adjust_link(pdata); | |
1367 | } | |
1368 | ||
1369 | static int xgbe_phy_start(struct xgbe_prv_data *pdata) | |
1370 | { | |
1371 | struct net_device *netdev = pdata->netdev; | |
1372 | int ret; | |
1373 | ||
d5c78399 LT |
1374 | netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); |
1375 | ||
e57f7a3f LT |
1376 | ret = pdata->phy_if.phy_impl.start(pdata); |
1377 | if (ret) | |
1378 | return ret; | |
1379 | ||
47f164de LT |
1380 | /* If we have a separate AN irq, enable it */ |
1381 | if (pdata->dev_irq != pdata->an_irq) { | |
1382 | ret = devm_request_irq(pdata->dev, pdata->an_irq, | |
1383 | xgbe_an_isr, 0, pdata->an_name, | |
1384 | pdata); | |
1385 | if (ret) { | |
1386 | netdev_err(netdev, "phy irq request failed\n"); | |
1387 | goto err_stop; | |
1388 | } | |
7c12aa08 LT |
1389 | } |
1390 | ||
1391 | /* Set initial mode - call the mode setting routines | |
1392 | * directly to insure we are properly configured | |
1393 | */ | |
e57f7a3f LT |
1394 | if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { |
1395 | xgbe_kr_mode(pdata); | |
1396 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { | |
1397 | xgbe_kx_2500_mode(pdata); | |
1398 | } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { | |
1399 | xgbe_kx_1000_mode(pdata); | |
abf0a1c2 LT |
1400 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { |
1401 | xgbe_sfi_mode(pdata); | |
1402 | } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { | |
1403 | xgbe_x_mode(pdata); | |
1404 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { | |
1405 | xgbe_sgmii_1000_mode(pdata); | |
1406 | } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { | |
1407 | xgbe_sgmii_100_mode(pdata); | |
7c12aa08 LT |
1408 | } else { |
1409 | ret = -EINVAL; | |
1410 | goto err_irq; | |
1411 | } | |
1412 | ||
e57f7a3f LT |
1413 | /* Indicate the PHY is up and running */ |
1414 | pdata->phy_started = 1; | |
1415 | ||
7c12aa08 | 1416 | xgbe_an_init(pdata); |
a64def41 | 1417 | xgbe_an_enable_interrupts(pdata); |
7c12aa08 LT |
1418 | |
1419 | return xgbe_phy_config_aneg(pdata); | |
1420 | ||
1421 | err_irq: | |
47f164de LT |
1422 | if (pdata->dev_irq != pdata->an_irq) |
1423 | devm_free_irq(pdata->dev, pdata->an_irq, pdata); | |
7c12aa08 | 1424 | |
e57f7a3f LT |
1425 | err_stop: |
1426 | pdata->phy_if.phy_impl.stop(pdata); | |
1427 | ||
7c12aa08 LT |
1428 | return ret; |
1429 | } | |
1430 | ||
1431 | static int xgbe_phy_reset(struct xgbe_prv_data *pdata) | |
1432 | { | |
e57f7a3f | 1433 | int ret; |
7c12aa08 | 1434 | |
e57f7a3f LT |
1435 | ret = pdata->phy_if.phy_impl.reset(pdata); |
1436 | if (ret) | |
1437 | return ret; | |
7c12aa08 LT |
1438 | |
1439 | /* Disable auto-negotiation for now */ | |
1bf40ada | 1440 | xgbe_an_disable_all(pdata); |
7c12aa08 LT |
1441 | |
1442 | /* Clear auto-negotiation interrupts */ | |
1bf40ada | 1443 | xgbe_an_clear_interrupts_all(pdata); |
7c12aa08 LT |
1444 | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
1449 | { |
1450 | struct device *dev = pdata->dev; | |
c5aa9e3b | 1451 | |
34bf65df LT |
1452 | dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); |
1453 | ||
d9682c90 | 1454 | dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1455 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); |
d9682c90 | 1456 | dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1457 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); |
d9682c90 | 1458 | dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, |
34bf65df | 1459 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); |
d9682c90 | 1460 | dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, |
34bf65df | 1461 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); |
d9682c90 | 1462 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, |
34bf65df | 1463 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); |
d9682c90 | 1464 | dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, |
34bf65df LT |
1465 | XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); |
1466 | ||
d9682c90 | 1467 | dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, |
34bf65df | 1468 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); |
d9682c90 | 1469 | dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, |
34bf65df | 1470 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); |
d9682c90 | 1471 | dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", |
34bf65df LT |
1472 | MDIO_AN_ADVERTISE, |
1473 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); | |
d9682c90 | 1474 | dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", |
34bf65df LT |
1475 | MDIO_AN_ADVERTISE + 1, |
1476 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); | |
d9682c90 | 1477 | dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", |
34bf65df LT |
1478 | MDIO_AN_ADVERTISE + 2, |
1479 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); | |
d9682c90 | 1480 | dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", |
34bf65df LT |
1481 | MDIO_AN_COMP_STAT, |
1482 | XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); | |
1483 | ||
34bf65df | 1484 | dev_dbg(dev, "\n*************************************************\n"); |
c5aa9e3b LT |
1485 | } |
1486 | ||
e57f7a3f LT |
1487 | static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) |
1488 | { | |
1489 | if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) | |
1490 | return SPEED_10000; | |
abf0a1c2 LT |
1491 | else if (pdata->phy.advertising & ADVERTISED_10000baseT_Full) |
1492 | return SPEED_10000; | |
e57f7a3f LT |
1493 | else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) |
1494 | return SPEED_2500; | |
1495 | else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) | |
1496 | return SPEED_1000; | |
abf0a1c2 LT |
1497 | else if (pdata->phy.advertising & ADVERTISED_1000baseT_Full) |
1498 | return SPEED_1000; | |
1499 | else if (pdata->phy.advertising & ADVERTISED_100baseT_Full) | |
1500 | return SPEED_100; | |
e57f7a3f LT |
1501 | |
1502 | return SPEED_UNKNOWN; | |
1503 | } | |
1504 | ||
1505 | static void xgbe_phy_exit(struct xgbe_prv_data *pdata) | |
c5aa9e3b | 1506 | { |
e57f7a3f LT |
1507 | xgbe_phy_stop(pdata); |
1508 | ||
1509 | pdata->phy_if.phy_impl.exit(pdata); | |
1510 | } | |
1511 | ||
1512 | static int xgbe_phy_init(struct xgbe_prv_data *pdata) | |
1513 | { | |
1514 | int ret; | |
1515 | ||
7c12aa08 LT |
1516 | mutex_init(&pdata->an_mutex); |
1517 | INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); | |
1518 | INIT_WORK(&pdata->an_work, xgbe_an_state_machine); | |
1519 | pdata->mdio_mmd = MDIO_MMD_PCS; | |
c5aa9e3b | 1520 | |
e57f7a3f | 1521 | /* Check for FEC support */ |
7c12aa08 LT |
1522 | pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, |
1523 | MDIO_PMA_10GBR_FECABLE); | |
1524 | pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | | |
1525 | MDIO_PMA_10GBR_FECABLE_ERRABLE); | |
c5aa9e3b | 1526 | |
e57f7a3f LT |
1527 | /* Setup the phy (including supported features) */ |
1528 | ret = pdata->phy_if.phy_impl.init(pdata); | |
1529 | if (ret) | |
1530 | return ret; | |
7c12aa08 | 1531 | pdata->phy.advertising = pdata->phy.supported; |
c5aa9e3b | 1532 | |
7c12aa08 | 1533 | pdata->phy.address = 0; |
c5aa9e3b | 1534 | |
e57f7a3f LT |
1535 | if (pdata->phy.advertising & ADVERTISED_Autoneg) { |
1536 | pdata->phy.autoneg = AUTONEG_ENABLE; | |
1537 | pdata->phy.speed = SPEED_UNKNOWN; | |
1538 | pdata->phy.duplex = DUPLEX_UNKNOWN; | |
1539 | } else { | |
1540 | pdata->phy.autoneg = AUTONEG_DISABLE; | |
1541 | pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); | |
1542 | pdata->phy.duplex = DUPLEX_FULL; | |
1543 | } | |
c5aa9e3b | 1544 | |
7c12aa08 | 1545 | pdata->phy.link = 0; |
c5aa9e3b | 1546 | |
c1ce2f77 LT |
1547 | pdata->phy.pause_autoneg = pdata->pause_autoneg; |
1548 | pdata->phy.tx_pause = pdata->tx_pause; | |
1549 | pdata->phy.rx_pause = pdata->rx_pause; | |
1550 | ||
1551 | /* Fix up Flow Control advertising */ | |
1552 | pdata->phy.advertising &= ~ADVERTISED_Pause; | |
1553 | pdata->phy.advertising &= ~ADVERTISED_Asym_Pause; | |
1554 | ||
1555 | if (pdata->rx_pause) { | |
1556 | pdata->phy.advertising |= ADVERTISED_Pause; | |
1557 | pdata->phy.advertising |= ADVERTISED_Asym_Pause; | |
1558 | } | |
1559 | ||
1560 | if (pdata->tx_pause) | |
1561 | pdata->phy.advertising ^= ADVERTISED_Asym_Pause; | |
1562 | ||
34bf65df LT |
1563 | if (netif_msg_drv(pdata)) |
1564 | xgbe_dump_phy_registers(pdata); | |
e57f7a3f LT |
1565 | |
1566 | return 0; | |
c5aa9e3b LT |
1567 | } |
1568 | ||
7c12aa08 | 1569 | void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) |
c5aa9e3b | 1570 | { |
7c12aa08 | 1571 | phy_if->phy_init = xgbe_phy_init; |
e57f7a3f | 1572 | phy_if->phy_exit = xgbe_phy_exit; |
c5aa9e3b | 1573 | |
7c12aa08 LT |
1574 | phy_if->phy_reset = xgbe_phy_reset; |
1575 | phy_if->phy_start = xgbe_phy_start; | |
1576 | phy_if->phy_stop = xgbe_phy_stop; | |
c5aa9e3b | 1577 | |
7c12aa08 LT |
1578 | phy_if->phy_status = xgbe_phy_status; |
1579 | phy_if->phy_config_aneg = xgbe_phy_config_aneg; | |
e57f7a3f LT |
1580 | |
1581 | phy_if->phy_valid_speed = xgbe_phy_valid_speed; | |
47f164de LT |
1582 | |
1583 | phy_if->an_isr = xgbe_an_combined_isr; | |
c5aa9e3b | 1584 | } |