2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/clk/at91_pmc.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91sam9g45.h>
23 #include <mach/hardware.h>
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
37 * The peripheral clocks.
39 static struct clk pioA_clk
= {
41 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOA
,
42 .type
= CLK_TYPE_PERIPHERAL
,
44 static struct clk pioB_clk
= {
46 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOB
,
47 .type
= CLK_TYPE_PERIPHERAL
,
49 static struct clk pioC_clk
= {
51 .pmc_mask
= 1 << AT91SAM9G45_ID_PIOC
,
52 .type
= CLK_TYPE_PERIPHERAL
,
54 static struct clk pioDE_clk
= {
56 .pmc_mask
= 1 << AT91SAM9G45_ID_PIODE
,
57 .type
= CLK_TYPE_PERIPHERAL
,
59 static struct clk trng_clk
= {
61 .pmc_mask
= 1 << AT91SAM9G45_ID_TRNG
,
62 .type
= CLK_TYPE_PERIPHERAL
,
64 static struct clk usart0_clk
= {
66 .pmc_mask
= 1 << AT91SAM9G45_ID_US0
,
67 .type
= CLK_TYPE_PERIPHERAL
,
69 static struct clk usart1_clk
= {
71 .pmc_mask
= 1 << AT91SAM9G45_ID_US1
,
72 .type
= CLK_TYPE_PERIPHERAL
,
74 static struct clk usart2_clk
= {
76 .pmc_mask
= 1 << AT91SAM9G45_ID_US2
,
77 .type
= CLK_TYPE_PERIPHERAL
,
79 static struct clk usart3_clk
= {
81 .pmc_mask
= 1 << AT91SAM9G45_ID_US3
,
82 .type
= CLK_TYPE_PERIPHERAL
,
84 static struct clk mmc0_clk
= {
86 .pmc_mask
= 1 << AT91SAM9G45_ID_MCI0
,
87 .type
= CLK_TYPE_PERIPHERAL
,
89 static struct clk twi0_clk
= {
91 .pmc_mask
= 1 << AT91SAM9G45_ID_TWI0
,
92 .type
= CLK_TYPE_PERIPHERAL
,
94 static struct clk twi1_clk
= {
96 .pmc_mask
= 1 << AT91SAM9G45_ID_TWI1
,
97 .type
= CLK_TYPE_PERIPHERAL
,
99 static struct clk spi0_clk
= {
101 .pmc_mask
= 1 << AT91SAM9G45_ID_SPI0
,
102 .type
= CLK_TYPE_PERIPHERAL
,
104 static struct clk spi1_clk
= {
106 .pmc_mask
= 1 << AT91SAM9G45_ID_SPI1
,
107 .type
= CLK_TYPE_PERIPHERAL
,
109 static struct clk ssc0_clk
= {
111 .pmc_mask
= 1 << AT91SAM9G45_ID_SSC0
,
112 .type
= CLK_TYPE_PERIPHERAL
,
114 static struct clk ssc1_clk
= {
116 .pmc_mask
= 1 << AT91SAM9G45_ID_SSC1
,
117 .type
= CLK_TYPE_PERIPHERAL
,
119 static struct clk tcb0_clk
= {
121 .pmc_mask
= 1 << AT91SAM9G45_ID_TCB
,
122 .type
= CLK_TYPE_PERIPHERAL
,
124 static struct clk pwm_clk
= {
126 .pmc_mask
= 1 << AT91SAM9G45_ID_PWMC
,
127 .type
= CLK_TYPE_PERIPHERAL
,
129 static struct clk tsc_clk
= {
131 .pmc_mask
= 1 << AT91SAM9G45_ID_TSC
,
132 .type
= CLK_TYPE_PERIPHERAL
,
134 static struct clk dma_clk
= {
136 .pmc_mask
= 1 << AT91SAM9G45_ID_DMA
,
137 .type
= CLK_TYPE_PERIPHERAL
,
139 static struct clk uhphs_clk
= {
141 .pmc_mask
= 1 << AT91SAM9G45_ID_UHPHS
,
142 .type
= CLK_TYPE_PERIPHERAL
,
144 static struct clk lcdc_clk
= {
146 .pmc_mask
= 1 << AT91SAM9G45_ID_LCDC
,
147 .type
= CLK_TYPE_PERIPHERAL
,
149 static struct clk ac97_clk
= {
151 .pmc_mask
= 1 << AT91SAM9G45_ID_AC97C
,
152 .type
= CLK_TYPE_PERIPHERAL
,
154 static struct clk macb_clk
= {
156 .pmc_mask
= 1 << AT91SAM9G45_ID_EMAC
,
157 .type
= CLK_TYPE_PERIPHERAL
,
159 static struct clk isi_clk
= {
161 .pmc_mask
= 1 << AT91SAM9G45_ID_ISI
,
162 .type
= CLK_TYPE_PERIPHERAL
,
164 static struct clk udphs_clk
= {
166 .pmc_mask
= 1 << AT91SAM9G45_ID_UDPHS
,
167 .type
= CLK_TYPE_PERIPHERAL
,
169 static struct clk mmc1_clk
= {
171 .pmc_mask
= 1 << AT91SAM9G45_ID_MCI1
,
172 .type
= CLK_TYPE_PERIPHERAL
,
175 /* Video decoder clock - Only for sam9m10/sam9m11 */
176 static struct clk vdec_clk
= {
178 .pmc_mask
= 1 << AT91SAM9G45_ID_VDEC
,
179 .type
= CLK_TYPE_PERIPHERAL
,
182 static struct clk adc_op_clk
= {
183 .name
= "adc_op_clk",
184 .type
= CLK_TYPE_PERIPHERAL
,
188 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
189 static struct clk aestdessha_clk
= {
190 .name
= "aestdessha_clk",
191 .pmc_mask
= 1 << AT91SAM9G45_ID_AESTDESSHA
,
192 .type
= CLK_TYPE_PERIPHERAL
,
195 static struct clk
*periph_clocks
[] __initdata
= {
228 static struct clk_lookup periph_clocks_lookups
[] = {
229 /* One additional fake clock for macb_hclk */
230 CLKDEV_CON_ID("hclk", &macb_clk
),
231 /* One additional fake clock for ohci */
232 CLKDEV_CON_ID("ohci_clk", &uhphs_clk
),
233 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk
),
234 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk
),
235 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk
),
236 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk
),
237 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk
),
238 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk
),
239 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk
),
240 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk
),
241 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk
),
242 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk
),
243 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk
),
244 CLKDEV_CON_DEV_ID(NULL
, "i2c-at91sam9g10.0", &twi0_clk
),
245 CLKDEV_CON_DEV_ID(NULL
, "i2c-at91sam9g10.1", &twi1_clk
),
246 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk
),
247 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk
),
248 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk
),
249 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk
),
250 CLKDEV_CON_DEV_ID(NULL
, "atmel-trng", &trng_clk
),
251 CLKDEV_CON_DEV_ID(NULL
, "atmel_sha", &aestdessha_clk
),
252 CLKDEV_CON_DEV_ID(NULL
, "atmel_tdes", &aestdessha_clk
),
253 CLKDEV_CON_DEV_ID(NULL
, "atmel_aes", &aestdessha_clk
),
254 /* more usart lookup table for DT entries */
255 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck
),
256 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk
),
257 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk
),
258 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk
),
259 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk
),
260 /* more tc lookup table for DT entries */
261 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk
),
262 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk
),
263 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk
),
264 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk
),
265 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk
),
266 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk
),
267 CLKDEV_CON_DEV_ID(NULL
, "fff84000.i2c", &twi0_clk
),
268 CLKDEV_CON_DEV_ID(NULL
, "fff88000.i2c", &twi1_clk
),
269 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk
),
270 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk
),
271 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk
),
272 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk
),
273 /* fake hclk clock */
274 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk
),
275 CLKDEV_CON_DEV_ID(NULL
, "fffff200.gpio", &pioA_clk
),
276 CLKDEV_CON_DEV_ID(NULL
, "fffff400.gpio", &pioB_clk
),
277 CLKDEV_CON_DEV_ID(NULL
, "fffff600.gpio", &pioC_clk
),
278 CLKDEV_CON_DEV_ID(NULL
, "fffff800.gpio", &pioDE_clk
),
279 CLKDEV_CON_DEV_ID(NULL
, "fffffa00.gpio", &pioDE_clk
),
281 CLKDEV_CON_ID("pioA", &pioA_clk
),
282 CLKDEV_CON_ID("pioB", &pioB_clk
),
283 CLKDEV_CON_ID("pioC", &pioC_clk
),
284 CLKDEV_CON_ID("pioD", &pioDE_clk
),
285 CLKDEV_CON_ID("pioE", &pioDE_clk
),
287 CLKDEV_CON_ID("adc_clk", &tsc_clk
),
290 static struct clk_lookup usart_clocks_lookups
[] = {
291 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck
),
292 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk
),
293 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk
),
294 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk
),
295 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk
),
299 * The two programmable clocks.
300 * You must configure pin multiplexing to bring these signals out.
302 static struct clk pck0
= {
304 .pmc_mask
= AT91_PMC_PCK0
,
305 .type
= CLK_TYPE_PROGRAMMABLE
,
308 static struct clk pck1
= {
310 .pmc_mask
= AT91_PMC_PCK1
,
311 .type
= CLK_TYPE_PROGRAMMABLE
,
315 static void __init
at91sam9g45_register_clocks(void)
319 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
320 clk_register(periph_clocks
[i
]);
322 clkdev_add_table(periph_clocks_lookups
,
323 ARRAY_SIZE(periph_clocks_lookups
));
324 clkdev_add_table(usart_clocks_lookups
,
325 ARRAY_SIZE(usart_clocks_lookups
));
327 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
328 clk_register(&vdec_clk
);
334 /* --------------------------------------------------------------------
336 * -------------------------------------------------------------------- */
338 static struct at91_gpio_bank at91sam9g45_gpio
[] __initdata
= {
340 .id
= AT91SAM9G45_ID_PIOA
,
341 .regbase
= AT91SAM9G45_BASE_PIOA
,
343 .id
= AT91SAM9G45_ID_PIOB
,
344 .regbase
= AT91SAM9G45_BASE_PIOB
,
346 .id
= AT91SAM9G45_ID_PIOC
,
347 .regbase
= AT91SAM9G45_BASE_PIOC
,
349 .id
= AT91SAM9G45_ID_PIODE
,
350 .regbase
= AT91SAM9G45_BASE_PIOD
,
352 .id
= AT91SAM9G45_ID_PIODE
,
353 .regbase
= AT91SAM9G45_BASE_PIOE
,
357 /* --------------------------------------------------------------------
358 * AT91SAM9G45 processor initialization
359 * -------------------------------------------------------------------- */
361 static void __init
at91sam9g45_map_io(void)
363 at91_init_sram(0, AT91SAM9G45_SRAM_BASE
, AT91SAM9G45_SRAM_SIZE
);
366 static void __init
at91sam9g45_ioremap_registers(void)
368 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC
);
369 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC
);
370 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1
, 512);
371 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0
, 512);
372 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT
);
373 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC
);
374 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX
);
375 at91_pm_set_standby(at91_ddr_standby
);
378 static void __init
at91sam9g45_initialize(void)
380 arm_pm_idle
= at91sam9_idle
;
381 arm_pm_restart
= at91sam9g45_restart
;
383 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC
);
384 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT
);
386 /* Register GPIO subsystem */
387 at91_gpio_init(at91sam9g45_gpio
, 5);
390 /* --------------------------------------------------------------------
391 * Interrupt initialization
392 * -------------------------------------------------------------------- */
395 * The default interrupt priority levels (0 = lowest, 7 = highest).
397 static unsigned int at91sam9g45_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
398 7, /* Advanced Interrupt Controller (FIQ) */
399 7, /* System Peripherals */
400 1, /* Parallel IO Controller A */
401 1, /* Parallel IO Controller B */
402 1, /* Parallel IO Controller C */
403 1, /* Parallel IO Controller D and E */
409 0, /* Multimedia Card Interface 0 */
410 6, /* Two-Wire Interface 0 */
411 6, /* Two-Wire Interface 1 */
412 5, /* Serial Peripheral Interface 0 */
413 5, /* Serial Peripheral Interface 1 */
414 4, /* Serial Synchronous Controller 0 */
415 4, /* Serial Synchronous Controller 1 */
416 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
417 0, /* Pulse Width Modulation Controller */
418 0, /* Touch Screen Controller */
419 0, /* DMA Controller */
420 2, /* USB Host High Speed port */
421 3, /* LDC Controller */
422 5, /* AC97 Controller */
424 0, /* Image Sensor Interface */
425 2, /* USB Device High speed port */
426 0, /* AESTDESSHA Crypto HW Accelerators */
427 0, /* Multimedia Card Interface 1 */
429 0, /* Advanced Interrupt Controller (IRQ0) */
432 AT91_SOC_START(at91sam9g45
)
433 .map_io
= at91sam9g45_map_io
,
434 .default_irq_priority
= at91sam9g45_default_irq_priority
,
435 .extern_irq
= (1 << AT91SAM9G45_ID_IRQ0
),
436 .ioremap_registers
= at91sam9g45_ioremap_registers
,
437 .register_clocks
= at91sam9g45_register_clocks
,
438 .init
= at91sam9g45_initialize
,