arch/arm/mm/proc-arm922.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
   3  *
   4  *  Copyright (C) 1999,2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *  Copyright (C) 2001 Altera Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22  *
  23  * These are the low level assembler for performing cache and TLB
  24  * functions on the arm922.
  25  *
  26  *  CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
  27  */
  28 #include <linux/linkage.h>
  29 #include <linux/config.h>
  30 #include <linux/init.h>
  31 #include <asm/assembler.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/procinfo.h>
  34 #include <asm/hardware.h>
  35 #include <asm/page.h>
  36 #include <asm/ptrace.h>
  37 #include "proc-macros.S"
  38
  39 /*
  40  * The size of one data cache line.
  41  */
  42 #define CACHE_DLINESIZE 32
  43
  44 /*
  45  * The number of data cache segments.
  46  */
  47 #define CACHE_DSEGMENTS 4
  48
  49 /*
  50  * The number of lines in a cache segment.
  51  */
  52 #define CACHE_DENTRIES  64
  53
  54 /*
  55  * This is the size at which it becomes more efficient to
  56  * clean the whole cache, rather than using the individual
  57  * cache line maintainence instructions.  (I think this should
  58  * be 32768).
  59  */
  60 #define CACHE_DLIMIT    8192
  61
  62
  63         .text
  64 /*
  65  * cpu_arm922_proc_init()
  66  */
  67 ENTRY(cpu_arm922_proc_init)
  68         mov     pc, lr
  69
  70 /*
  71  * cpu_arm922_proc_fin()
  72  */
  73 ENTRY(cpu_arm922_proc_fin)
  74         stmfd   sp!, {lr}
  75         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  76         msr     cpsr_c, ip
  77 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  78         bl      arm922_flush_kern_cache_all
  79 #else
  80         bl      v4wt_flush_kern_cache_all
  81 #endif
  82         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  83         bic     r0, r0, #0x1000                 @ ...i............
  84         bic     r0, r0, #0x000e                 @ ............wca.
  85         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  86         ldmfd   sp!, {pc}
  87
  88 /*
  89  * cpu_arm922_reset(loc)
  90  *
  91  * Perform a soft reset of the system.  Put the CPU into the
  92  * same state as it would be if it had been reset, and branch
  93  * to what would be the reset vector.
  94  *
  95  * loc: location to jump to for soft reset
  96  */
  97         .align  5
  98 ENTRY(cpu_arm922_reset)
  99         mov     ip, #0
 100         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
 101         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 102         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 103         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
 104         bic     ip, ip, #0x000f                 @ ............wcam
 105         bic     ip, ip, #0x1100                 @ ...i...s........
 106         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
 107         mov     pc, r0
 108
 109 /*
 110  * cpu_arm922_do_idle()
 111  */
 112         .align  5
 113 ENTRY(cpu_arm922_do_idle)
 114         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 115         mov     pc, lr
 116
 117
 118 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 119
 120 /*
 121  *      flush_user_cache_all()
 122  *
 123  *      Clean and invalidate all cache entries in a particular
 124  *      address space.
 125  */
 126 ENTRY(arm922_flush_user_cache_all)
 127         /* FALLTHROUGH */
 128
 129 /*
 130  *      flush_kern_cache_all()
 131  *
 132  *      Clean and invalidate the entire cache.
 133  */
 134 ENTRY(arm922_flush_kern_cache_all)
 135         mov     r2, #VM_EXEC
 136         mov     ip, #0
 137 __flush_whole_cache:
 138         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
 139 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 140 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 141         subs    r3, r3, #1 << 26
 142         bcs     2b                              @ entries 63 to 0
 143         subs    r1, r1, #1 << 5
 144         bcs     1b                              @ segments 7 to 0
 145         tst     r2, #VM_EXEC
 146         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 147         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 148         mov     pc, lr
 149
 150 /*
 151  *      flush_user_cache_range(start, end, flags)
 152  *
 153  *      Clean and invalidate a range of cache entries in the
 154  *      specified address range.
 155  *
 156  *      - start - start address (inclusive)
 157  *      - end   - end address (exclusive)
 158  *      - flags - vm_flags describing address space
 159  */
 160 ENTRY(arm922_flush_user_cache_range)
 161         mov     ip, #0
 162         sub     r3, r1, r0                      @ calculate total size
 163         cmp     r3, #CACHE_DLIMIT
 164         bhs     __flush_whole_cache
 165
 166 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 167         tst     r2, #VM_EXEC
 168         mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
 169         add     r0, r0, #CACHE_DLINESIZE
 170         cmp     r0, r1
 171         blo     1b
 172         tst     r2, #VM_EXEC
 173         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 174         mov     pc, lr
 175
 176 /*
 177  *      coherent_kern_range(start, end)
 178  *
 179  *      Ensure coherency between the Icache and the Dcache in the
 180  *      region described by start, end.  If you have non-snooping
 181  *      Harvard caches, you need to implement this function.
 182  *
 183  *      - start - virtual start address
 184  *      - end   - virtual end address
 185  */
 186 ENTRY(arm922_coherent_kern_range)
 187         /* FALLTHROUGH */
 188
 189 /*
 190  *      coherent_user_range(start, end)
 191  *
 192  *      Ensure coherency between the Icache and the Dcache in the
 193  *      region described by start, end.  If you have non-snooping
 194  *      Harvard caches, you need to implement this function.
 195  *
 196  *      - start - virtual start address
 197  *      - end   - virtual end address
 198  */
 199 ENTRY(arm922_coherent_user_range)
 200         bic     r0, r0, #CACHE_DLINESIZE - 1
 201 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 202         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 203         add     r0, r0, #CACHE_DLINESIZE
 204         cmp     r0, r1
 205         blo     1b
 206         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 207         mov     pc, lr
 208
 209 /*
 210  *      flush_kern_dcache_page(void *page)
 211  *
 212  *      Ensure no D cache aliasing occurs, either with itself or
 213  *      the I cache
 214  *
 215  *      - addr  - page aligned address
 216  */
 217 ENTRY(arm922_flush_kern_dcache_page)
 218         add     r1, r0, #PAGE_SZ
 219 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 220         add     r0, r0, #CACHE_DLINESIZE
 221         cmp     r0, r1
 222         blo     1b
 223         mov     r0, #0
 224         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 225         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 226         mov     pc, lr
 227
 228 /*
 229  *      dma_inv_range(start, end)
 230  *
 231  *      Invalidate (discard) the specified virtual address range.
 232  *      May not write back any entries.  If 'start' or 'end'
 233  *      are not cache line aligned, those lines must be written
 234  *      back.
 235  *
 236  *      - start - virtual start address
 237  *      - end   - virtual end address
 238  *
 239  * (same as v4wb)
 240  */
 241 ENTRY(arm922_dma_inv_range)
 242         tst     r0, #CACHE_DLINESIZE - 1
 243         bic     r0, r0, #CACHE_DLINESIZE - 1
 244         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 245         tst     r1, #CACHE_DLINESIZE - 1
 246         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 247 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 248         add     r0, r0, #CACHE_DLINESIZE
 249         cmp     r0, r1
 250         blo     1b
 251         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 252         mov     pc, lr
 253
 254 /*
 255  *      dma_clean_range(start, end)
 256  *
 257  *      Clean the specified virtual address range.
 258  *
 259  *      - start - virtual start address
 260  *      - end   - virtual end address
 261  *
 262  * (same as v4wb)
 263  */
 264 ENTRY(arm922_dma_clean_range)
 265         bic     r0, r0, #CACHE_DLINESIZE - 1
 266 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 267         add     r0, r0, #CACHE_DLINESIZE
 268         cmp     r0, r1
 269         blo     1b
 270         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 271         mov     pc, lr
 272
 273 /*
 274  *      dma_flush_range(start, end)
 275  *
 276  *      Clean and invalidate the specified virtual address range.
 277  *
 278  *      - start - virtual start address
 279  *      - end   - virtual end address
 280  */
 281 ENTRY(arm922_dma_flush_range)
 282         bic     r0, r0, #CACHE_DLINESIZE - 1
 283 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 284         add     r0, r0, #CACHE_DLINESIZE
 285         cmp     r0, r1
 286         blo     1b
 287         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 288         mov     pc, lr
 289
 290 ENTRY(arm922_cache_fns)
 291         .long   arm922_flush_kern_cache_all
 292         .long   arm922_flush_user_cache_all
 293         .long   arm922_flush_user_cache_range
 294         .long   arm922_coherent_kern_range
 295         .long   arm922_coherent_user_range
 296         .long   arm922_flush_kern_dcache_page
 297         .long   arm922_dma_inv_range
 298         .long   arm922_dma_clean_range
 299         .long   arm922_dma_flush_range
 300
 301 #endif
 302
 303
 304 ENTRY(cpu_arm922_dcache_clean_area)
 305 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 306 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 307         add     r0, r0, #CACHE_DLINESIZE
 308         subs    r1, r1, #CACHE_DLINESIZE
 309         bhi     1b
 310 #endif
 311         mov     pc, lr
 312
 313 /* =============================== PageTable ============================== */
 314
 315 /*
 316  * cpu_arm922_switch_mm(pgd)
 317  *
 318  * Set the translation base pointer to be as described by pgd.
 319  *
 320  * pgd: new page tables
 321  */
 322         .align  5
 323 ENTRY(cpu_arm922_switch_mm)
 324         mov     ip, #0
 325 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 326         mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 327 #else
 328 @ && 'Clean & Invalidate whole DCache'
 329 @ && Re-written to use Index Ops.
 330 @ && Uses registers r1, r3 and ip
 331
 332         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
 333 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 334 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean & invalidate D index
 335         subs    r3, r3, #1 << 26
 336         bcs     2b                              @ entries 63 to 0
 337         subs    r1, r1, #1 << 5
 338         bcs     1b                              @ segments 7 to 0
 339 #endif
 340         mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
 341         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 342         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 343         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 344         mov     pc, lr
 345
 346 /*
 347  * cpu_arm922_set_pte(ptep, pte)
 348  *
 349  * Set a PTE and flush it out
 350  */
 351         .align  5
 352 ENTRY(cpu_arm922_set_pte)
 353         str     r1, [r0], #-2048                @ linux version
 354
 355         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 356
 357         bic     r2, r1, #PTE_SMALL_AP_MASK
 358         bic     r2, r2, #PTE_TYPE_MASK
 359         orr     r2, r2, #PTE_TYPE_SMALL
 360
 361         tst     r1, #L_PTE_USER                 @ User?
 362         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 363
 364         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 365         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 366
 367         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 368         movne   r2, #0
 369
 370 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 371         eor     r3, r2, #0x0a                   @ C & small page?
 372         tst     r3, #0x0b
 373         biceq   r2, r2, #4
 374 #endif
 375         str     r2, [r0]                        @ hardware version
 376         mov     r0, r0
 377         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 378         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 379         mov     pc, lr
 380
 381         __INIT
 382
 383         .type   __arm922_setup, #function
 384 __arm922_setup:
 385         mov     r0, #0
 386         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 387         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 388         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 389         mrc     p15, 0, r0, c1, c0              @ get control register v4
 390         ldr     r5, arm922_cr1_clear
 391         bic     r0, r0, r5
 392         ldr     r5, arm922_cr1_set
 393         orr     r0, r0, r5
 394         mov     pc, lr
 395         .size   __arm922_setup, . - __arm922_setup
 396
 397         /*
 398          *  R
 399          * .RVI ZFRS BLDP WCAM
 400          * ..11 0001 ..11 0101
 401          *
 402          */
 403         .type   arm922_cr1_clear, #object
 404         .type   arm922_cr1_set, #object
 405 arm922_cr1_clear:
 406         .word   0x3f3f
 407 arm922_cr1_set:
 408         .word   0x3135
 409
 410         __INITDATA
 411
 412 /*
 413  * Purpose : Function pointers used to access above functions - all calls
 414  *           come through these
 415  */
 416         .type   arm922_processor_functions, #object
 417 arm922_processor_functions:
 418         .word   v4t_early_abort
 419         .word   cpu_arm922_proc_init
 420         .word   cpu_arm922_proc_fin
 421         .word   cpu_arm922_reset
 422         .word   cpu_arm922_do_idle
 423         .word   cpu_arm922_dcache_clean_area
 424         .word   cpu_arm922_switch_mm
 425         .word   cpu_arm922_set_pte
 426         .size   arm922_processor_functions, . - arm922_processor_functions
 427
 428         .section ".rodata"
 429
 430         .type   cpu_arch_name, #object
 431 cpu_arch_name:
 432         .asciz  "armv4t"
 433         .size   cpu_arch_name, . - cpu_arch_name
 434
 435         .type   cpu_elf_name, #object
 436 cpu_elf_name:
 437         .asciz  "v4"
 438         .size   cpu_elf_name, . - cpu_elf_name
 439
 440         .type   cpu_arm922_name, #object
 441 cpu_arm922_name:
 442         .ascii  "ARM922T"
 443 #ifndef CONFIG_CPU_ICACHE_DISABLE
 444         .ascii  "i"
 445 #endif
 446 #ifndef CONFIG_CPU_DCACHE_DISABLE
 447         .ascii  "d"
 448 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 449         .ascii  "(wt)"
 450 #else
 451         .ascii  "(wb)"
 452 #endif
 453 #endif
 454         .ascii  "\0"
 455         .size   cpu_arm922_name, . - cpu_arm922_name
 456
 457         .align
 458
 459         .section ".proc.info", #alloc, #execinstr
 460
 461         .type   __arm922_proc_info,#object
 462 __arm922_proc_info:
 463         .long   0x41009220
 464         .long   0xff00fff0
 465         .long   PMD_TYPE_SECT | \
 466                 PMD_SECT_BUFFERABLE | \
 467                 PMD_SECT_CACHEABLE | \
 468                 PMD_BIT4 | \
 469                 PMD_SECT_AP_WRITE | \
 470                 PMD_SECT_AP_READ
 471         b       __arm922_setup
 472         .long   cpu_arch_name
 473         .long   cpu_elf_name
 474         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
 475         .long   cpu_arm922_name
 476         .long   arm922_processor_functions
 477         .long   v4wbi_tlb_fns
 478         .long   v4wb_user_fns
 479 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 480         .long   arm922_cache_fns
 481 #else
 482         .long   v4wt_cache_fns
 483 #endif
 484         .size   __arm922_proc_info, . - __arm922_proc_info