2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/bootmem.h>
25 #include <asm/cacheflush.h>
26 #include <asm/mmu_context.h>
27 #include <asm/pgalloc.h>
28 #include <asm/pgtable.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
43 struct kvm_stats_debugfs_item debugfs_entries
[] = {
44 { "wait", VCPU_STAT(wait_exits
), KVM_STAT_VCPU
},
45 { "cache", VCPU_STAT(cache_exits
), KVM_STAT_VCPU
},
46 { "signal", VCPU_STAT(signal_exits
), KVM_STAT_VCPU
},
47 { "interrupt", VCPU_STAT(int_exits
), KVM_STAT_VCPU
},
48 { "cop_unsuable", VCPU_STAT(cop_unusable_exits
), KVM_STAT_VCPU
},
49 { "tlbmod", VCPU_STAT(tlbmod_exits
), KVM_STAT_VCPU
},
50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits
), KVM_STAT_VCPU
},
51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits
), KVM_STAT_VCPU
},
52 { "addrerr_st", VCPU_STAT(addrerr_st_exits
), KVM_STAT_VCPU
},
53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits
), KVM_STAT_VCPU
},
54 { "syscall", VCPU_STAT(syscall_exits
), KVM_STAT_VCPU
},
55 { "resvd_inst", VCPU_STAT(resvd_inst_exits
), KVM_STAT_VCPU
},
56 { "break_inst", VCPU_STAT(break_inst_exits
), KVM_STAT_VCPU
},
57 { "trap_inst", VCPU_STAT(trap_inst_exits
), KVM_STAT_VCPU
},
58 { "msa_fpe", VCPU_STAT(msa_fpe_exits
), KVM_STAT_VCPU
},
59 { "fpe", VCPU_STAT(fpe_exits
), KVM_STAT_VCPU
},
60 { "msa_disabled", VCPU_STAT(msa_disabled_exits
), KVM_STAT_VCPU
},
61 { "flush_dcache", VCPU_STAT(flush_dcache_exits
), KVM_STAT_VCPU
},
62 { "halt_successful_poll", VCPU_STAT(halt_successful_poll
), KVM_STAT_VCPU
},
63 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll
), KVM_STAT_VCPU
},
64 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid
), KVM_STAT_VCPU
},
65 { "halt_wakeup", VCPU_STAT(halt_wakeup
), KVM_STAT_VCPU
},
70 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
71 * Config7, so we are "runnable" if interrupts are pending
73 int kvm_arch_vcpu_runnable(struct kvm_vcpu
*vcpu
)
75 return !!(vcpu
->arch
.pending_exceptions
);
78 int kvm_arch_vcpu_should_kick(struct kvm_vcpu
*vcpu
)
83 int kvm_arch_hardware_enable(void)
88 int kvm_arch_hardware_setup(void)
93 void kvm_arch_check_processor_compat(void *rtn
)
98 int kvm_arch_init_vm(struct kvm
*kvm
, unsigned long type
)
100 /* Allocate page table to map GPA -> RPA */
101 kvm
->arch
.gpa_mm
.pgd
= kvm_pgd_alloc();
102 if (!kvm
->arch
.gpa_mm
.pgd
)
108 bool kvm_arch_has_vcpu_debugfs(void)
113 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu
*vcpu
)
118 void kvm_mips_free_vcpus(struct kvm
*kvm
)
121 struct kvm_vcpu
*vcpu
;
123 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
124 kvm_arch_vcpu_free(vcpu
);
127 mutex_lock(&kvm
->lock
);
129 for (i
= 0; i
< atomic_read(&kvm
->online_vcpus
); i
++)
130 kvm
->vcpus
[i
] = NULL
;
132 atomic_set(&kvm
->online_vcpus
, 0);
134 mutex_unlock(&kvm
->lock
);
137 static void kvm_mips_free_gpa_pt(struct kvm
*kvm
)
139 /* It should always be safe to remove after flushing the whole range */
140 WARN_ON(!kvm_mips_flush_gpa_pt(kvm
, 0, ~0));
141 pgd_free(NULL
, kvm
->arch
.gpa_mm
.pgd
);
144 void kvm_arch_destroy_vm(struct kvm
*kvm
)
146 kvm_mips_free_vcpus(kvm
);
147 kvm_mips_free_gpa_pt(kvm
);
150 long kvm_arch_dev_ioctl(struct file
*filp
, unsigned int ioctl
,
156 int kvm_arch_create_memslot(struct kvm
*kvm
, struct kvm_memory_slot
*slot
,
157 unsigned long npages
)
162 void kvm_arch_flush_shadow_all(struct kvm
*kvm
)
164 /* Flush whole GPA */
165 kvm_mips_flush_gpa_pt(kvm
, 0, ~0);
167 /* Let implementation do the rest */
168 kvm_mips_callbacks
->flush_shadow_all(kvm
);
171 void kvm_arch_flush_shadow_memslot(struct kvm
*kvm
,
172 struct kvm_memory_slot
*slot
)
175 * The slot has been made invalid (ready for moving or deletion), so we
176 * need to ensure that it can no longer be accessed by any guest VCPUs.
179 spin_lock(&kvm
->mmu_lock
);
180 /* Flush slot from GPA */
181 kvm_mips_flush_gpa_pt(kvm
, slot
->base_gfn
,
182 slot
->base_gfn
+ slot
->npages
- 1);
183 /* Let implementation do the rest */
184 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, slot
);
185 spin_unlock(&kvm
->mmu_lock
);
188 int kvm_arch_prepare_memory_region(struct kvm
*kvm
,
189 struct kvm_memory_slot
*memslot
,
190 const struct kvm_userspace_memory_region
*mem
,
191 enum kvm_mr_change change
)
196 void kvm_arch_commit_memory_region(struct kvm
*kvm
,
197 const struct kvm_userspace_memory_region
*mem
,
198 const struct kvm_memory_slot
*old
,
199 const struct kvm_memory_slot
*new,
200 enum kvm_mr_change change
)
204 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
205 __func__
, kvm
, mem
->slot
, mem
->guest_phys_addr
,
206 mem
->memory_size
, mem
->userspace_addr
);
209 * If dirty page logging is enabled, write protect all pages in the slot
210 * ready for dirty logging.
212 * There is no need to do this in any of the following cases:
213 * CREATE: No dirty mappings will already exist.
214 * MOVE/DELETE: The old mappings will already have been cleaned up by
215 * kvm_arch_flush_shadow_memslot()
217 if (change
== KVM_MR_FLAGS_ONLY
&&
218 (!(old
->flags
& KVM_MEM_LOG_DIRTY_PAGES
) &&
219 new->flags
& KVM_MEM_LOG_DIRTY_PAGES
)) {
220 spin_lock(&kvm
->mmu_lock
);
221 /* Write protect GPA page table entries */
222 needs_flush
= kvm_mips_mkclean_gpa_pt(kvm
, new->base_gfn
,
223 new->base_gfn
+ new->npages
- 1);
224 /* Let implementation do the rest */
226 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, new);
227 spin_unlock(&kvm
->mmu_lock
);
231 static inline void dump_handler(const char *symbol
, void *start
, void *end
)
235 pr_debug("LEAF(%s)\n", symbol
);
237 pr_debug("\t.set push\n");
238 pr_debug("\t.set noreorder\n");
240 for (p
= start
; p
< (u32
*)end
; ++p
)
241 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p
, p
);
243 pr_debug("\t.set\tpop\n");
245 pr_debug("\tEND(%s)\n", symbol
);
248 struct kvm_vcpu
*kvm_arch_vcpu_create(struct kvm
*kvm
, unsigned int id
)
251 void *gebase
, *p
, *handler
, *refill_start
, *refill_end
;
254 struct kvm_vcpu
*vcpu
= kzalloc(sizeof(struct kvm_vcpu
), GFP_KERNEL
);
261 err
= kvm_vcpu_init(vcpu
, kvm
, id
);
266 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm
, id
, vcpu
);
269 * Allocate space for host mode exception handlers that handle
272 if (cpu_has_veic
|| cpu_has_vint
)
273 size
= 0x200 + VECTORSPACING
* 64;
277 gebase
= kzalloc(ALIGN(size
, PAGE_SIZE
), GFP_KERNEL
);
283 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
284 ALIGN(size
, PAGE_SIZE
), gebase
);
287 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
288 * limits us to the low 512MB of physical address space. If the memory
289 * we allocate is out of range, just give up now.
291 if (!cpu_has_ebase_wg
&& virt_to_phys(gebase
) >= 0x20000000) {
292 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
295 goto out_free_gebase
;
299 vcpu
->arch
.guest_ebase
= gebase
;
301 /* Build guest exception vectors dynamically in unmapped memory */
302 handler
= gebase
+ 0x2000;
305 refill_start
= gebase
;
306 refill_end
= kvm_mips_build_tlb_refill_exception(refill_start
, handler
);
308 /* General Exception Entry point */
309 kvm_mips_build_exception(gebase
+ 0x180, handler
);
311 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
312 for (i
= 0; i
< 8; i
++) {
313 kvm_debug("L1 Vectored handler @ %p\n",
314 gebase
+ 0x200 + (i
* VECTORSPACING
));
315 kvm_mips_build_exception(gebase
+ 0x200 + i
* VECTORSPACING
,
319 /* General exit handler */
321 p
= kvm_mips_build_exit(p
);
323 /* Guest entry routine */
324 vcpu
->arch
.vcpu_run
= p
;
325 p
= kvm_mips_build_vcpu_run(p
);
327 /* Dump the generated code */
328 pr_debug("#include <asm/asm.h>\n");
329 pr_debug("#include <asm/regdef.h>\n");
331 dump_handler("kvm_vcpu_run", vcpu
->arch
.vcpu_run
, p
);
332 dump_handler("kvm_tlb_refill", refill_start
, refill_end
);
333 dump_handler("kvm_gen_exc", gebase
+ 0x180, gebase
+ 0x200);
334 dump_handler("kvm_exit", gebase
+ 0x2000, vcpu
->arch
.vcpu_run
);
336 /* Invalidate the icache for these ranges */
337 flush_icache_range((unsigned long)gebase
,
338 (unsigned long)gebase
+ ALIGN(size
, PAGE_SIZE
));
341 * Allocate comm page for guest kernel, a TLB will be reserved for
342 * mapping GVA @ 0xFFFF8000 to this page
344 vcpu
->arch
.kseg0_commpage
= kzalloc(PAGE_SIZE
<< 1, GFP_KERNEL
);
346 if (!vcpu
->arch
.kseg0_commpage
) {
348 goto out_free_gebase
;
351 kvm_debug("Allocated COMM page @ %p\n", vcpu
->arch
.kseg0_commpage
);
352 kvm_mips_commpage_init(vcpu
);
355 vcpu
->arch
.last_sched_cpu
= -1;
357 /* Start off the timer */
358 kvm_mips_init_count(vcpu
);
366 kvm_vcpu_uninit(vcpu
);
375 void kvm_arch_vcpu_free(struct kvm_vcpu
*vcpu
)
377 hrtimer_cancel(&vcpu
->arch
.comparecount_timer
);
379 kvm_vcpu_uninit(vcpu
);
381 kvm_mips_dump_stats(vcpu
);
383 kvm_mmu_free_memory_caches(vcpu
);
384 kfree(vcpu
->arch
.guest_ebase
);
385 kfree(vcpu
->arch
.kseg0_commpage
);
389 void kvm_arch_vcpu_destroy(struct kvm_vcpu
*vcpu
)
391 kvm_arch_vcpu_free(vcpu
);
394 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu
*vcpu
,
395 struct kvm_guest_debug
*dbg
)
400 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
)
405 if (vcpu
->sigset_active
)
406 sigprocmask(SIG_SETMASK
, &vcpu
->sigset
, &sigsaved
);
408 if (vcpu
->mmio_needed
) {
409 if (!vcpu
->mmio_is_write
)
410 kvm_mips_complete_mmio_load(vcpu
, run
);
411 vcpu
->mmio_needed
= 0;
414 if (run
->immediate_exit
)
420 guest_enter_irqoff();
421 trace_kvm_enter(vcpu
);
424 * Make sure the read of VCPU requests in vcpu_run() callback is not
425 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
426 * flush request while the requester sees the VCPU as outside of guest
427 * mode and not needing an IPI.
429 smp_store_mb(vcpu
->mode
, IN_GUEST_MODE
);
431 r
= kvm_mips_callbacks
->vcpu_run(run
, vcpu
);
438 if (vcpu
->sigset_active
)
439 sigprocmask(SIG_SETMASK
, &sigsaved
, NULL
);
444 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu
*vcpu
,
445 struct kvm_mips_interrupt
*irq
)
447 int intr
= (int)irq
->irq
;
448 struct kvm_vcpu
*dvcpu
= NULL
;
450 if (intr
== 3 || intr
== -3 || intr
== 4 || intr
== -4)
451 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__
, irq
->cpu
,
457 dvcpu
= vcpu
->kvm
->vcpus
[irq
->cpu
];
459 if (intr
== 2 || intr
== 3 || intr
== 4) {
460 kvm_mips_callbacks
->queue_io_int(dvcpu
, irq
);
462 } else if (intr
== -2 || intr
== -3 || intr
== -4) {
463 kvm_mips_callbacks
->dequeue_io_int(dvcpu
, irq
);
465 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__
,
470 dvcpu
->arch
.wait
= 0;
472 if (swait_active(&dvcpu
->wq
))
473 swake_up(&dvcpu
->wq
);
478 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu
*vcpu
,
479 struct kvm_mp_state
*mp_state
)
484 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu
*vcpu
,
485 struct kvm_mp_state
*mp_state
)
490 static u64 kvm_mips_get_one_regs
[] = {
524 #ifndef CONFIG_CPU_MIPSR6
531 static u64 kvm_mips_get_one_regs_fpu
[] = {
533 KVM_REG_MIPS_FCR_CSR
,
536 static u64 kvm_mips_get_one_regs_msa
[] = {
538 KVM_REG_MIPS_MSA_CSR
,
541 static unsigned long kvm_mips_num_regs(struct kvm_vcpu
*vcpu
)
545 ret
= ARRAY_SIZE(kvm_mips_get_one_regs
);
546 if (kvm_mips_guest_can_have_fpu(&vcpu
->arch
)) {
547 ret
+= ARRAY_SIZE(kvm_mips_get_one_regs_fpu
) + 48;
549 if (boot_cpu_data
.fpu_id
& MIPS_FPIR_F64
)
552 if (kvm_mips_guest_can_have_msa(&vcpu
->arch
))
553 ret
+= ARRAY_SIZE(kvm_mips_get_one_regs_msa
) + 32;
554 ret
+= kvm_mips_callbacks
->num_regs(vcpu
);
559 static int kvm_mips_copy_reg_indices(struct kvm_vcpu
*vcpu
, u64 __user
*indices
)
564 if (copy_to_user(indices
, kvm_mips_get_one_regs
,
565 sizeof(kvm_mips_get_one_regs
)))
567 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs
);
569 if (kvm_mips_guest_can_have_fpu(&vcpu
->arch
)) {
570 if (copy_to_user(indices
, kvm_mips_get_one_regs_fpu
,
571 sizeof(kvm_mips_get_one_regs_fpu
)))
573 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs_fpu
);
575 for (i
= 0; i
< 32; ++i
) {
576 index
= KVM_REG_MIPS_FPR_32(i
);
577 if (copy_to_user(indices
, &index
, sizeof(index
)))
581 /* skip odd doubles if no F64 */
582 if (i
& 1 && !(boot_cpu_data
.fpu_id
& MIPS_FPIR_F64
))
585 index
= KVM_REG_MIPS_FPR_64(i
);
586 if (copy_to_user(indices
, &index
, sizeof(index
)))
592 if (kvm_mips_guest_can_have_msa(&vcpu
->arch
)) {
593 if (copy_to_user(indices
, kvm_mips_get_one_regs_msa
,
594 sizeof(kvm_mips_get_one_regs_msa
)))
596 indices
+= ARRAY_SIZE(kvm_mips_get_one_regs_msa
);
598 for (i
= 0; i
< 32; ++i
) {
599 index
= KVM_REG_MIPS_VEC_128(i
);
600 if (copy_to_user(indices
, &index
, sizeof(index
)))
606 return kvm_mips_callbacks
->copy_reg_indices(vcpu
, indices
);
609 static int kvm_mips_get_reg(struct kvm_vcpu
*vcpu
,
610 const struct kvm_one_reg
*reg
)
612 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
613 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
620 /* General purpose registers */
621 case KVM_REG_MIPS_R0
... KVM_REG_MIPS_R31
:
622 v
= (long)vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
];
624 #ifndef CONFIG_CPU_MIPSR6
625 case KVM_REG_MIPS_HI
:
626 v
= (long)vcpu
->arch
.hi
;
628 case KVM_REG_MIPS_LO
:
629 v
= (long)vcpu
->arch
.lo
;
632 case KVM_REG_MIPS_PC
:
633 v
= (long)vcpu
->arch
.pc
;
636 /* Floating point registers */
637 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
638 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
640 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
641 /* Odd singles in top of even double when FR=0 */
642 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
643 v
= get_fpr32(&fpu
->fpr
[idx
], 0);
645 v
= get_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1);
647 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
648 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
650 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
651 /* Can't access odd doubles in FR=0 mode */
652 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
654 v
= get_fpr64(&fpu
->fpr
[idx
], 0);
656 case KVM_REG_MIPS_FCR_IR
:
657 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
659 v
= boot_cpu_data
.fpu_id
;
661 case KVM_REG_MIPS_FCR_CSR
:
662 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
667 /* MIPS SIMD Architecture (MSA) registers */
668 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
669 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
671 /* Can't access MSA registers in FR=0 mode */
672 if (!(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
674 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
675 #ifdef CONFIG_CPU_LITTLE_ENDIAN
676 /* least significant byte first */
677 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 0);
678 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 1);
680 /* most significant byte first */
681 vs
[0] = get_fpr64(&fpu
->fpr
[idx
], 1);
682 vs
[1] = get_fpr64(&fpu
->fpr
[idx
], 0);
685 case KVM_REG_MIPS_MSA_IR
:
686 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
688 v
= boot_cpu_data
.msa_id
;
690 case KVM_REG_MIPS_MSA_CSR
:
691 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
696 /* registers to be handled specially */
698 ret
= kvm_mips_callbacks
->get_one_reg(vcpu
, reg
, &v
);
703 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
704 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
706 return put_user(v
, uaddr64
);
707 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
708 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
711 return put_user(v32
, uaddr32
);
712 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
713 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
715 return copy_to_user(uaddr
, vs
, 16) ? -EFAULT
: 0;
721 static int kvm_mips_set_reg(struct kvm_vcpu
*vcpu
,
722 const struct kvm_one_reg
*reg
)
724 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
725 struct mips_fpu_struct
*fpu
= &vcpu
->arch
.fpu
;
730 if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
) {
731 u64 __user
*uaddr64
= (u64 __user
*)(long)reg
->addr
;
733 if (get_user(v
, uaddr64
) != 0)
735 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U32
) {
736 u32 __user
*uaddr32
= (u32 __user
*)(long)reg
->addr
;
739 if (get_user(v32
, uaddr32
) != 0)
742 } else if ((reg
->id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U128
) {
743 void __user
*uaddr
= (void __user
*)(long)reg
->addr
;
745 return copy_from_user(vs
, uaddr
, 16) ? -EFAULT
: 0;
751 /* General purpose registers */
752 case KVM_REG_MIPS_R0
:
753 /* Silently ignore requests to set $0 */
755 case KVM_REG_MIPS_R1
... KVM_REG_MIPS_R31
:
756 vcpu
->arch
.gprs
[reg
->id
- KVM_REG_MIPS_R0
] = v
;
758 #ifndef CONFIG_CPU_MIPSR6
759 case KVM_REG_MIPS_HI
:
762 case KVM_REG_MIPS_LO
:
766 case KVM_REG_MIPS_PC
:
770 /* Floating point registers */
771 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
772 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
774 idx
= reg
->id
- KVM_REG_MIPS_FPR_32(0);
775 /* Odd singles in top of even double when FR=0 */
776 if (kvm_read_c0_guest_status(cop0
) & ST0_FR
)
777 set_fpr32(&fpu
->fpr
[idx
], 0, v
);
779 set_fpr32(&fpu
->fpr
[idx
& ~1], idx
& 1, v
);
781 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
782 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
784 idx
= reg
->id
- KVM_REG_MIPS_FPR_64(0);
785 /* Can't access odd doubles in FR=0 mode */
786 if (idx
& 1 && !(kvm_read_c0_guest_status(cop0
) & ST0_FR
))
788 set_fpr64(&fpu
->fpr
[idx
], 0, v
);
790 case KVM_REG_MIPS_FCR_IR
:
791 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
795 case KVM_REG_MIPS_FCR_CSR
:
796 if (!kvm_mips_guest_has_fpu(&vcpu
->arch
))
801 /* MIPS SIMD Architecture (MSA) registers */
802 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
803 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
805 idx
= reg
->id
- KVM_REG_MIPS_VEC_128(0);
806 #ifdef CONFIG_CPU_LITTLE_ENDIAN
807 /* least significant byte first */
808 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[0]);
809 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[1]);
811 /* most significant byte first */
812 set_fpr64(&fpu
->fpr
[idx
], 1, vs
[0]);
813 set_fpr64(&fpu
->fpr
[idx
], 0, vs
[1]);
816 case KVM_REG_MIPS_MSA_IR
:
817 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
821 case KVM_REG_MIPS_MSA_CSR
:
822 if (!kvm_mips_guest_has_msa(&vcpu
->arch
))
827 /* registers to be handled specially */
829 return kvm_mips_callbacks
->set_one_reg(vcpu
, reg
, v
);
834 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu
*vcpu
,
835 struct kvm_enable_cap
*cap
)
839 if (!kvm_vm_ioctl_check_extension(vcpu
->kvm
, cap
->cap
))
847 case KVM_CAP_MIPS_FPU
:
848 vcpu
->arch
.fpu_enabled
= true;
850 case KVM_CAP_MIPS_MSA
:
851 vcpu
->arch
.msa_enabled
= true;
861 long kvm_arch_vcpu_ioctl(struct file
*filp
, unsigned int ioctl
,
864 struct kvm_vcpu
*vcpu
= filp
->private_data
;
865 void __user
*argp
= (void __user
*)arg
;
869 case KVM_SET_ONE_REG
:
870 case KVM_GET_ONE_REG
: {
871 struct kvm_one_reg reg
;
873 if (copy_from_user(®
, argp
, sizeof(reg
)))
875 if (ioctl
== KVM_SET_ONE_REG
)
876 return kvm_mips_set_reg(vcpu
, ®
);
878 return kvm_mips_get_reg(vcpu
, ®
);
880 case KVM_GET_REG_LIST
: {
881 struct kvm_reg_list __user
*user_list
= argp
;
882 struct kvm_reg_list reg_list
;
885 if (copy_from_user(®_list
, user_list
, sizeof(reg_list
)))
888 reg_list
.n
= kvm_mips_num_regs(vcpu
);
889 if (copy_to_user(user_list
, ®_list
, sizeof(reg_list
)))
893 return kvm_mips_copy_reg_indices(vcpu
, user_list
->reg
);
897 struct kvm_mips_interrupt irq
;
899 if (copy_from_user(&irq
, argp
, sizeof(irq
)))
901 kvm_debug("[%d] %s: irq: %d\n", vcpu
->vcpu_id
, __func__
,
904 r
= kvm_vcpu_ioctl_interrupt(vcpu
, &irq
);
907 case KVM_ENABLE_CAP
: {
908 struct kvm_enable_cap cap
;
910 if (copy_from_user(&cap
, argp
, sizeof(cap
)))
912 r
= kvm_vcpu_ioctl_enable_cap(vcpu
, &cap
);
922 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
924 * @log: slot id and address to which we copy the log
926 * Steps 1-4 below provide general overview of dirty page logging. See
927 * kvm_get_dirty_log_protect() function description for additional details.
929 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
930 * always flush the TLB (step 4) even if previous step failed and the dirty
931 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
932 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
933 * writes will be marked dirty for next log read.
935 * 1. Take a snapshot of the bit and clear it if needed.
936 * 2. Write protect the corresponding page.
937 * 3. Copy the snapshot to the userspace.
938 * 4. Flush TLB's if needed.
940 int kvm_vm_ioctl_get_dirty_log(struct kvm
*kvm
, struct kvm_dirty_log
*log
)
942 struct kvm_memslots
*slots
;
943 struct kvm_memory_slot
*memslot
;
944 bool is_dirty
= false;
947 mutex_lock(&kvm
->slots_lock
);
949 r
= kvm_get_dirty_log_protect(kvm
, log
, &is_dirty
);
952 slots
= kvm_memslots(kvm
);
953 memslot
= id_to_memslot(slots
, log
->slot
);
955 /* Let implementation handle TLB/GVA invalidation */
956 kvm_mips_callbacks
->flush_shadow_memslot(kvm
, memslot
);
959 mutex_unlock(&kvm
->slots_lock
);
963 long kvm_arch_vm_ioctl(struct file
*filp
, unsigned int ioctl
, unsigned long arg
)
975 int kvm_arch_init(void *opaque
)
977 if (kvm_mips_callbacks
) {
978 kvm_err("kvm: module already exists\n");
982 return kvm_mips_emulation_init(&kvm_mips_callbacks
);
985 void kvm_arch_exit(void)
987 kvm_mips_callbacks
= NULL
;
990 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu
*vcpu
,
991 struct kvm_sregs
*sregs
)
996 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu
*vcpu
,
997 struct kvm_sregs
*sregs
)
1002 void kvm_arch_vcpu_postcreate(struct kvm_vcpu
*vcpu
)
1006 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1008 return -ENOIOCTLCMD
;
1011 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu
*vcpu
, struct kvm_fpu
*fpu
)
1013 return -ENOIOCTLCMD
;
1016 int kvm_arch_vcpu_fault(struct kvm_vcpu
*vcpu
, struct vm_fault
*vmf
)
1018 return VM_FAULT_SIGBUS
;
1021 int kvm_vm_ioctl_check_extension(struct kvm
*kvm
, long ext
)
1026 case KVM_CAP_ONE_REG
:
1027 case KVM_CAP_ENABLE_CAP
:
1028 case KVM_CAP_READONLY_MEM
:
1029 case KVM_CAP_SYNC_MMU
:
1030 case KVM_CAP_IMMEDIATE_EXIT
:
1033 case KVM_CAP_COALESCED_MMIO
:
1034 r
= KVM_COALESCED_MMIO_PAGE_OFFSET
;
1036 case KVM_CAP_NR_VCPUS
:
1037 r
= num_online_cpus();
1039 case KVM_CAP_MAX_VCPUS
:
1042 case KVM_CAP_MIPS_FPU
:
1043 /* We don't handle systems with inconsistent cpu_has_fpu */
1044 r
= !!raw_cpu_has_fpu
;
1046 case KVM_CAP_MIPS_MSA
:
1048 * We don't support MSA vector partitioning yet:
1049 * 1) It would require explicit support which can't be tested
1050 * yet due to lack of support in current hardware.
1051 * 2) It extends the state that would need to be saved/restored
1052 * by e.g. QEMU for migration.
1054 * When vector partitioning hardware becomes available, support
1055 * could be added by requiring a flag when enabling
1056 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1057 * to save/restore the appropriate extra state.
1059 r
= cpu_has_msa
&& !(boot_cpu_data
.msa_id
& MSA_IR_WRPF
);
1068 int kvm_cpu_has_pending_timer(struct kvm_vcpu
*vcpu
)
1070 return kvm_mips_pending_timer(vcpu
);
1073 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu
*vcpu
)
1076 struct mips_coproc
*cop0
;
1081 kvm_debug("VCPU Register Dump:\n");
1082 kvm_debug("\tpc = 0x%08lx\n", vcpu
->arch
.pc
);
1083 kvm_debug("\texceptions: %08lx\n", vcpu
->arch
.pending_exceptions
);
1085 for (i
= 0; i
< 32; i
+= 4) {
1086 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i
,
1088 vcpu
->arch
.gprs
[i
+ 1],
1089 vcpu
->arch
.gprs
[i
+ 2], vcpu
->arch
.gprs
[i
+ 3]);
1091 kvm_debug("\thi: 0x%08lx\n", vcpu
->arch
.hi
);
1092 kvm_debug("\tlo: 0x%08lx\n", vcpu
->arch
.lo
);
1094 cop0
= vcpu
->arch
.cop0
;
1095 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1096 kvm_read_c0_guest_status(cop0
),
1097 kvm_read_c0_guest_cause(cop0
));
1099 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0
));
1104 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1108 for (i
= 1; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1109 vcpu
->arch
.gprs
[i
] = regs
->gpr
[i
];
1110 vcpu
->arch
.gprs
[0] = 0; /* zero is special, and cannot be set. */
1111 vcpu
->arch
.hi
= regs
->hi
;
1112 vcpu
->arch
.lo
= regs
->lo
;
1113 vcpu
->arch
.pc
= regs
->pc
;
1118 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu
*vcpu
, struct kvm_regs
*regs
)
1122 for (i
= 0; i
< ARRAY_SIZE(vcpu
->arch
.gprs
); i
++)
1123 regs
->gpr
[i
] = vcpu
->arch
.gprs
[i
];
1125 regs
->hi
= vcpu
->arch
.hi
;
1126 regs
->lo
= vcpu
->arch
.lo
;
1127 regs
->pc
= vcpu
->arch
.pc
;
1132 static void kvm_mips_comparecount_func(unsigned long data
)
1134 struct kvm_vcpu
*vcpu
= (struct kvm_vcpu
*)data
;
1136 kvm_mips_callbacks
->queue_timer_int(vcpu
);
1138 vcpu
->arch
.wait
= 0;
1139 if (swait_active(&vcpu
->wq
))
1140 swake_up(&vcpu
->wq
);
1143 /* low level hrtimer wake routine */
1144 static enum hrtimer_restart
kvm_mips_comparecount_wakeup(struct hrtimer
*timer
)
1146 struct kvm_vcpu
*vcpu
;
1148 vcpu
= container_of(timer
, struct kvm_vcpu
, arch
.comparecount_timer
);
1149 kvm_mips_comparecount_func((unsigned long) vcpu
);
1150 return kvm_mips_count_timeout(vcpu
);
1153 int kvm_arch_vcpu_init(struct kvm_vcpu
*vcpu
)
1157 err
= kvm_mips_callbacks
->vcpu_init(vcpu
);
1161 hrtimer_init(&vcpu
->arch
.comparecount_timer
, CLOCK_MONOTONIC
,
1163 vcpu
->arch
.comparecount_timer
.function
= kvm_mips_comparecount_wakeup
;
1167 void kvm_arch_vcpu_uninit(struct kvm_vcpu
*vcpu
)
1169 kvm_mips_callbacks
->vcpu_uninit(vcpu
);
1172 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu
*vcpu
,
1173 struct kvm_translation
*tr
)
1178 /* Initial guest state */
1179 int kvm_arch_vcpu_setup(struct kvm_vcpu
*vcpu
)
1181 return kvm_mips_callbacks
->vcpu_setup(vcpu
);
1184 static void kvm_mips_set_c0_status(void)
1186 u32 status
= read_c0_status();
1191 write_c0_status(status
);
1196 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1198 int kvm_mips_handle_exit(struct kvm_run
*run
, struct kvm_vcpu
*vcpu
)
1200 u32 cause
= vcpu
->arch
.host_cp0_cause
;
1201 u32 exccode
= (cause
>> CAUSEB_EXCCODE
) & 0x1f;
1202 u32 __user
*opc
= (u32 __user
*) vcpu
->arch
.pc
;
1203 unsigned long badvaddr
= vcpu
->arch
.host_cp0_badvaddr
;
1204 enum emulation_result er
= EMULATE_DONE
;
1206 int ret
= RESUME_GUEST
;
1208 vcpu
->mode
= OUTSIDE_GUEST_MODE
;
1210 /* re-enable HTW before enabling interrupts */
1213 /* Set a default exit reason */
1214 run
->exit_reason
= KVM_EXIT_UNKNOWN
;
1215 run
->ready_for_interrupt_injection
= 1;
1218 * Set the appropriate status bits based on host CPU features,
1219 * before we hit the scheduler
1221 kvm_mips_set_c0_status();
1225 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1226 cause
, opc
, run
, vcpu
);
1227 trace_kvm_exit(vcpu
, exccode
);
1230 * Do a privilege check, if in UM most of these exit conditions end up
1231 * causing an exception to be delivered to the Guest Kernel
1233 er
= kvm_mips_check_privilege(cause
, opc
, run
, vcpu
);
1234 if (er
== EMULATE_PRIV_FAIL
) {
1236 } else if (er
== EMULATE_FAIL
) {
1237 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1244 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu
->vcpu_id
, opc
);
1246 ++vcpu
->stat
.int_exits
;
1255 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc
);
1257 ++vcpu
->stat
.cop_unusable_exits
;
1258 ret
= kvm_mips_callbacks
->handle_cop_unusable(vcpu
);
1259 /* XXXKYMA: Might need to return to user space */
1260 if (run
->exit_reason
== KVM_EXIT_IRQ_WINDOW_OPEN
)
1265 ++vcpu
->stat
.tlbmod_exits
;
1266 ret
= kvm_mips_callbacks
->handle_tlb_mod(vcpu
);
1270 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1271 cause
, kvm_read_c0_guest_status(vcpu
->arch
.cop0
), opc
,
1274 ++vcpu
->stat
.tlbmiss_st_exits
;
1275 ret
= kvm_mips_callbacks
->handle_tlb_st_miss(vcpu
);
1279 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1280 cause
, opc
, badvaddr
);
1282 ++vcpu
->stat
.tlbmiss_ld_exits
;
1283 ret
= kvm_mips_callbacks
->handle_tlb_ld_miss(vcpu
);
1287 ++vcpu
->stat
.addrerr_st_exits
;
1288 ret
= kvm_mips_callbacks
->handle_addr_err_st(vcpu
);
1292 ++vcpu
->stat
.addrerr_ld_exits
;
1293 ret
= kvm_mips_callbacks
->handle_addr_err_ld(vcpu
);
1297 ++vcpu
->stat
.syscall_exits
;
1298 ret
= kvm_mips_callbacks
->handle_syscall(vcpu
);
1302 ++vcpu
->stat
.resvd_inst_exits
;
1303 ret
= kvm_mips_callbacks
->handle_res_inst(vcpu
);
1307 ++vcpu
->stat
.break_inst_exits
;
1308 ret
= kvm_mips_callbacks
->handle_break(vcpu
);
1312 ++vcpu
->stat
.trap_inst_exits
;
1313 ret
= kvm_mips_callbacks
->handle_trap(vcpu
);
1316 case EXCCODE_MSAFPE
:
1317 ++vcpu
->stat
.msa_fpe_exits
;
1318 ret
= kvm_mips_callbacks
->handle_msa_fpe(vcpu
);
1322 ++vcpu
->stat
.fpe_exits
;
1323 ret
= kvm_mips_callbacks
->handle_fpe(vcpu
);
1326 case EXCCODE_MSADIS
:
1327 ++vcpu
->stat
.msa_disabled_exits
;
1328 ret
= kvm_mips_callbacks
->handle_msa_disabled(vcpu
);
1332 if (cause
& CAUSEF_BD
)
1335 kvm_get_badinstr(opc
, vcpu
, &inst
);
1336 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1337 exccode
, opc
, inst
, badvaddr
,
1338 kvm_read_c0_guest_status(vcpu
->arch
.cop0
));
1339 kvm_arch_vcpu_dump_regs(vcpu
);
1340 run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
1347 local_irq_disable();
1349 if (er
== EMULATE_DONE
&& !(ret
& RESUME_HOST
))
1350 kvm_mips_deliver_interrupts(vcpu
, cause
);
1352 if (!(ret
& RESUME_HOST
)) {
1353 /* Only check for signals if not already exiting to userspace */
1354 if (signal_pending(current
)) {
1355 run
->exit_reason
= KVM_EXIT_INTR
;
1356 ret
= (-EINTR
<< 2) | RESUME_HOST
;
1357 ++vcpu
->stat
.signal_exits
;
1358 trace_kvm_exit(vcpu
, KVM_TRACE_EXIT_SIGNAL
);
1362 if (ret
== RESUME_GUEST
) {
1363 trace_kvm_reenter(vcpu
);
1366 * Make sure the read of VCPU requests in vcpu_reenter()
1367 * callback is not reordered ahead of the write to vcpu->mode,
1368 * or we could miss a TLB flush request while the requester sees
1369 * the VCPU as outside of guest mode and not needing an IPI.
1371 smp_store_mb(vcpu
->mode
, IN_GUEST_MODE
);
1373 kvm_mips_callbacks
->vcpu_reenter(run
, vcpu
);
1376 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1377 * is live), restore FCR31 / MSACSR.
1379 * This should be before returning to the guest exception
1380 * vector, as it may well cause an [MSA] FP exception if there
1381 * are pending exception bits unmasked. (see
1382 * kvm_mips_csr_die_notifier() for how that is handled).
1384 if (kvm_mips_guest_has_fpu(&vcpu
->arch
) &&
1385 read_c0_status() & ST0_CU1
)
1386 __kvm_restore_fcsr(&vcpu
->arch
);
1388 if (kvm_mips_guest_has_msa(&vcpu
->arch
) &&
1389 read_c0_config5() & MIPS_CONF5_MSAEN
)
1390 __kvm_restore_msacsr(&vcpu
->arch
);
1393 /* Disable HTW before returning to guest or host */
1399 /* Enable FPU for guest and restore context */
1400 void kvm_own_fpu(struct kvm_vcpu
*vcpu
)
1402 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1403 unsigned int sr
, cfg5
;
1407 sr
= kvm_read_c0_guest_status(cop0
);
1410 * If MSA state is already live, it is undefined how it interacts with
1411 * FR=0 FPU state, and we don't want to hit reserved instruction
1412 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1413 * play it safe and save it first.
1415 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1416 * get called when guest CU1 is set, however we can't trust the guest
1417 * not to clobber the status register directly via the commpage.
1419 if (cpu_has_msa
&& sr
& ST0_CU1
&& !(sr
& ST0_FR
) &&
1420 vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
)
1424 * Enable FPU for guest
1425 * We set FR and FRE according to guest context
1427 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1429 cfg5
= kvm_read_c0_guest_config5(cop0
);
1430 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1432 enable_fpu_hazard();
1434 /* If guest FPU state not active, restore it now */
1435 if (!(vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
)) {
1436 __kvm_restore_fpu(&vcpu
->arch
);
1437 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_FPU
;
1438 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
, KVM_TRACE_AUX_FPU
);
1440 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_ENABLE
, KVM_TRACE_AUX_FPU
);
1446 #ifdef CONFIG_CPU_HAS_MSA
1447 /* Enable MSA for guest and restore context */
1448 void kvm_own_msa(struct kvm_vcpu
*vcpu
)
1450 struct mips_coproc
*cop0
= vcpu
->arch
.cop0
;
1451 unsigned int sr
, cfg5
;
1456 * Enable FPU if enabled in guest, since we're restoring FPU context
1457 * anyway. We set FR and FRE according to guest context.
1459 if (kvm_mips_guest_has_fpu(&vcpu
->arch
)) {
1460 sr
= kvm_read_c0_guest_status(cop0
);
1463 * If FR=0 FPU state is already live, it is undefined how it
1464 * interacts with MSA state, so play it safe and save it first.
1466 if (!(sr
& ST0_FR
) &&
1467 (vcpu
->arch
.aux_inuse
& (KVM_MIPS_AUX_FPU
|
1468 KVM_MIPS_AUX_MSA
)) == KVM_MIPS_AUX_FPU
)
1471 change_c0_status(ST0_CU1
| ST0_FR
, sr
);
1472 if (sr
& ST0_CU1
&& cpu_has_fre
) {
1473 cfg5
= kvm_read_c0_guest_config5(cop0
);
1474 change_c0_config5(MIPS_CONF5_FRE
, cfg5
);
1478 /* Enable MSA for guest */
1479 set_c0_config5(MIPS_CONF5_MSAEN
);
1480 enable_fpu_hazard();
1482 switch (vcpu
->arch
.aux_inuse
& (KVM_MIPS_AUX_FPU
| KVM_MIPS_AUX_MSA
)) {
1483 case KVM_MIPS_AUX_FPU
:
1485 * Guest FPU state already loaded, only restore upper MSA state
1487 __kvm_restore_msa_upper(&vcpu
->arch
);
1488 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_MSA
;
1489 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
, KVM_TRACE_AUX_MSA
);
1492 /* Neither FPU or MSA already active, restore full MSA state */
1493 __kvm_restore_msa(&vcpu
->arch
);
1494 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_MSA
;
1495 if (kvm_mips_guest_has_fpu(&vcpu
->arch
))
1496 vcpu
->arch
.aux_inuse
|= KVM_MIPS_AUX_FPU
;
1497 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_RESTORE
,
1498 KVM_TRACE_AUX_FPU_MSA
);
1501 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_ENABLE
, KVM_TRACE_AUX_MSA
);
1509 /* Drop FPU & MSA without saving it */
1510 void kvm_drop_fpu(struct kvm_vcpu
*vcpu
)
1513 if (cpu_has_msa
&& vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
) {
1515 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_DISCARD
, KVM_TRACE_AUX_MSA
);
1516 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_MSA
;
1518 if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1519 clear_c0_status(ST0_CU1
| ST0_FR
);
1520 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_DISCARD
, KVM_TRACE_AUX_FPU
);
1521 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_FPU
;
1526 /* Save and disable FPU & MSA */
1527 void kvm_lose_fpu(struct kvm_vcpu
*vcpu
)
1530 * FPU & MSA get disabled in root context (hardware) when it is disabled
1531 * in guest context (software), but the register state in the hardware
1532 * may still be in use. This is why we explicitly re-enable the hardware
1537 if (cpu_has_msa
&& vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_MSA
) {
1538 set_c0_config5(MIPS_CONF5_MSAEN
);
1539 enable_fpu_hazard();
1541 __kvm_save_msa(&vcpu
->arch
);
1542 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_SAVE
, KVM_TRACE_AUX_FPU_MSA
);
1544 /* Disable MSA & FPU */
1546 if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1547 clear_c0_status(ST0_CU1
| ST0_FR
);
1548 disable_fpu_hazard();
1550 vcpu
->arch
.aux_inuse
&= ~(KVM_MIPS_AUX_FPU
| KVM_MIPS_AUX_MSA
);
1551 } else if (vcpu
->arch
.aux_inuse
& KVM_MIPS_AUX_FPU
) {
1552 set_c0_status(ST0_CU1
);
1553 enable_fpu_hazard();
1555 __kvm_save_fpu(&vcpu
->arch
);
1556 vcpu
->arch
.aux_inuse
&= ~KVM_MIPS_AUX_FPU
;
1557 trace_kvm_aux(vcpu
, KVM_TRACE_AUX_SAVE
, KVM_TRACE_AUX_FPU
);
1560 clear_c0_status(ST0_CU1
| ST0_FR
);
1561 disable_fpu_hazard();
1567 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1568 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1569 * exception if cause bits are set in the value being written.
1571 static int kvm_mips_csr_die_notify(struct notifier_block
*self
,
1572 unsigned long cmd
, void *ptr
)
1574 struct die_args
*args
= (struct die_args
*)ptr
;
1575 struct pt_regs
*regs
= args
->regs
;
1578 /* Only interested in FPE and MSAFPE */
1579 if (cmd
!= DIE_FP
&& cmd
!= DIE_MSAFP
)
1582 /* Return immediately if guest context isn't active */
1583 if (!(current
->flags
& PF_VCPU
))
1586 /* Should never get here from user mode */
1587 BUG_ON(user_mode(regs
));
1589 pc
= instruction_pointer(regs
);
1592 /* match 2nd instruction in __kvm_restore_fcsr */
1593 if (pc
!= (unsigned long)&__kvm_restore_fcsr
+ 4)
1597 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1599 pc
< (unsigned long)&__kvm_restore_msacsr
+ 4 ||
1600 pc
> (unsigned long)&__kvm_restore_msacsr
+ 8)
1605 /* Move PC forward a little and continue executing */
1606 instruction_pointer(regs
) += 4;
1611 static struct notifier_block kvm_mips_csr_die_notifier
= {
1612 .notifier_call
= kvm_mips_csr_die_notify
,
1615 static int __init
kvm_mips_init(void)
1619 ret
= kvm_mips_entry_setup();
1623 ret
= kvm_init(NULL
, sizeof(struct kvm_vcpu
), 0, THIS_MODULE
);
1628 register_die_notifier(&kvm_mips_csr_die_notifier
);
1633 static void __exit
kvm_mips_exit(void)
1637 unregister_die_notifier(&kvm_mips_csr_die_notifier
);
1640 module_init(kvm_mips_init
);
1641 module_exit(kvm_mips_exit
);
1643 EXPORT_TRACEPOINT_SYMBOL(kvm_exit
);