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powerpc/64s: Add support for a store forwarding barrier at kernel entry/exit
[mirror_ubuntu-artful-kernel.git] / arch / powerpc / include / asm / exception-64s.h
1 #ifndef _ASM_POWERPC_EXCEPTION_H
2 #define _ASM_POWERPC_EXCEPTION_H
3 /*
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27 /*
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
32 *
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
36 */
37 #include <asm/head-64.h>
38 #include <asm/bug.h>
39
40 /* PACA save area offsets (exgen, exmc, etc) */
41 #define EX_R9 0
42 #define EX_R10 8
43 #define EX_R11 16
44 #define EX_R12 24
45 #define EX_R13 32
46 #define EX_DAR 40
47 #define EX_DSISR 48
48 #define EX_CCR 52
49 #define EX_CFAR 56
50 #define EX_PPR 64
51 #if defined(CONFIG_RELOCATABLE)
52 #define EX_CTR 72
53 #define EX_SIZE 10 /* size in u64 units */
54 #else
55 #define EX_SIZE 9 /* size in u64 units */
56 #endif
57
58 /*
59 * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR
60 * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole
61 * in the save area so it's not necessary to overlap them. Could be used
62 * for future savings though if another 4 byte register was to be saved.
63 */
64 #define EX_LR EX_DAR
65
66 /*
67 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and
68 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap
69 * with EX_DAR.
70 */
71 #define EX_R3 EX_DAR
72
73 #define STF_ENTRY_BARRIER_SLOT \
74 STF_ENTRY_BARRIER_FIXUP_SECTION; \
75 mflr r10; \
76 bl stf_barrier_fallback; \
77 mtlr r10
78
79 #define STF_EXIT_BARRIER_SLOT \
80 STF_EXIT_BARRIER_FIXUP_SECTION; \
81 nop; \
82 nop; \
83 nop; \
84 nop; \
85 nop; \
86 nop
87
88 /*
89 * r10 must be free to use, r13 must be paca
90 */
91 #define INTERRUPT_TO_KERNEL \
92 STF_ENTRY_BARRIER_SLOT
93
94 /*
95 * The nop instructions allow us to insert one or more instructions to flush the
96 * L1-D cache when return to userspace or a guest.
97 */
98 #define RFI_FLUSH_SLOT \
99 RFI_FLUSH_FIXUP_SECTION; \
100 nop; \
101 nop; \
102 nop
103
104 #ifdef CONFIG_PPC_DEBUG_RFI
105 #define CHECK_TARGET_MSR_PR(srr_reg, expected_pr) \
106 SET_SCRATCH0(r3); \
107 mfspr r3,srr_reg; \
108 extrdi r3,r3,1,63-MSR_PR_LG; \
109 666: tdnei r3,expected_pr; \
110 EMIT_BUG_ENTRY 666b,__FILE__,__LINE__,0; \
111 GET_SCRATCH0(r3);
112 #else
113 #define CHECK_TARGET_MSR_PR(srr_reg, expected_pr)
114 #endif
115
116 #define RFI_TO_KERNEL \
117 CHECK_TARGET_MSR_PR(SPRN_SRR1, 0); \
118 rfid
119
120 #define RFI_TO_USER \
121 CHECK_TARGET_MSR_PR(SPRN_SRR1, 1); \
122 STF_EXIT_BARRIER_SLOT; \
123 RFI_FLUSH_SLOT; \
124 rfid; \
125 b rfi_flush_fallback
126
127 #define RFI_TO_USER_OR_KERNEL \
128 STF_EXIT_BARRIER_SLOT; \
129 RFI_FLUSH_SLOT; \
130 rfid; \
131 b rfi_flush_fallback
132
133 #define RFI_TO_GUEST \
134 STF_EXIT_BARRIER_SLOT; \
135 RFI_FLUSH_SLOT; \
136 rfid; \
137 b rfi_flush_fallback
138
139 #define HRFI_TO_KERNEL \
140 CHECK_TARGET_MSR_PR(SPRN_HSRR1, 0); \
141 hrfid
142
143 #define HRFI_TO_USER \
144 CHECK_TARGET_MSR_PR(SPRN_HSRR1, 1); \
145 STF_EXIT_BARRIER_SLOT; \
146 RFI_FLUSH_SLOT; \
147 hrfid; \
148 b hrfi_flush_fallback
149
150 #define HRFI_TO_USER_OR_KERNEL \
151 STF_EXIT_BARRIER_SLOT; \
152 RFI_FLUSH_SLOT; \
153 hrfid; \
154 b hrfi_flush_fallback
155
156 #define HRFI_TO_GUEST \
157 STF_EXIT_BARRIER_SLOT; \
158 RFI_FLUSH_SLOT; \
159 hrfid; \
160 b hrfi_flush_fallback
161
162 #define HRFI_TO_UNKNOWN \
163 STF_EXIT_BARRIER_SLOT; \
164 RFI_FLUSH_SLOT; \
165 hrfid; \
166 b hrfi_flush_fallback
167
168 #ifdef CONFIG_RELOCATABLE
169 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
170 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
171 LOAD_HANDLER(r12,label); \
172 mtctr r12; \
173 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
174 li r10,MSR_RI; \
175 mtmsrd r10,1; /* Set RI (EE=0) */ \
176 bctr;
177 #else
178 /* If not relocatable, we can jump directly -- and save messing with LR */
179 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
180 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
181 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
182 li r10,MSR_RI; \
183 mtmsrd r10,1; /* Set RI (EE=0) */ \
184 b label;
185 #endif
186 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
187 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
188
189 /*
190 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on
191 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which
192 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr.
193 */
194 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \
195 EXCEPTION_PROLOG_0(area); \
196 EXCEPTION_PROLOG_1(area, extra, vec); \
197 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
198
199 /*
200 * We're short on space and time in the exception prolog, so we can't
201 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
202 * Instead we get the base of the kernel from paca->kernelbase and or in the low
203 * part of label. This requires that the label be within 64KB of kernelbase, and
204 * that kernelbase be 64K aligned.
205 */
206 #define LOAD_HANDLER(reg, label) \
207 ld reg,PACAKBASE(r13); /* get high part of &label */ \
208 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label);
209
210 #define __LOAD_HANDLER(reg, label) \
211 ld reg,PACAKBASE(r13); \
212 ori reg,reg,(ABS_ADDR(label))@l;
213
214 /*
215 * Branches from unrelocated code (e.g., interrupts) to labels outside
216 * head-y require >64K offsets.
217 */
218 #define __LOAD_FAR_HANDLER(reg, label) \
219 ld reg,PACAKBASE(r13); \
220 ori reg,reg,(ABS_ADDR(label))@l; \
221 addis reg,reg,(ABS_ADDR(label))@h;
222
223 /* Exception register prefixes */
224 #define EXC_HV H
225 #define EXC_STD
226
227 #if defined(CONFIG_RELOCATABLE)
228 /*
229 * If we support interrupts with relocation on AND we're a relocatable kernel,
230 * we need to use CTR to get to the 2nd level handler. So, save/restore it
231 * when required.
232 */
233 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
234 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
235 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
236 #else
237 /* ...else CTR is unused and in register. */
238 #define SAVE_CTR(reg, area)
239 #define GET_CTR(reg, area) mfctr reg
240 #define RESTORE_CTR(reg, area)
241 #endif
242
243 /*
244 * PPR save/restore macros used in exceptions_64s.S
245 * Used for P7 or later processors
246 */
247 #define SAVE_PPR(area, ra, rb) \
248 BEGIN_FTR_SECTION_NESTED(940) \
249 ld ra,PACACURRENT(r13); \
250 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \
251 std rb,TASKTHREADPPR(ra); \
252 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
253
254 #define RESTORE_PPR_PACA(area, ra) \
255 BEGIN_FTR_SECTION_NESTED(941) \
256 ld ra,area+EX_PPR(r13); \
257 mtspr SPRN_PPR,ra; \
258 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
259
260 /*
261 * Get an SPR into a register if the CPU has the given feature
262 */
263 #define OPT_GET_SPR(ra, spr, ftr) \
264 BEGIN_FTR_SECTION_NESTED(943) \
265 mfspr ra,spr; \
266 END_FTR_SECTION_NESTED(ftr,ftr,943)
267
268 /*
269 * Set an SPR from a register if the CPU has the given feature
270 */
271 #define OPT_SET_SPR(ra, spr, ftr) \
272 BEGIN_FTR_SECTION_NESTED(943) \
273 mtspr spr,ra; \
274 END_FTR_SECTION_NESTED(ftr,ftr,943)
275
276 /*
277 * Save a register to the PACA if the CPU has the given feature
278 */
279 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
280 BEGIN_FTR_SECTION_NESTED(943) \
281 std ra,offset(r13); \
282 END_FTR_SECTION_NESTED(ftr,ftr,943)
283
284 #define EXCEPTION_PROLOG_0(area) \
285 GET_PACA(r13); \
286 std r9,area+EX_R9(r13); /* save r9 */ \
287 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
288 HMT_MEDIUM; \
289 std r10,area+EX_R10(r13); /* save r10 - r12 */ \
290 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
291
292 #define __EXCEPTION_PROLOG_1(area, extra, vec) \
293 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
294 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
295 INTERRUPT_TO_KERNEL; \
296 SAVE_CTR(r10, area); \
297 mfcr r9; \
298 extra(vec); \
299 std r11,area+EX_R11(r13); \
300 std r12,area+EX_R12(r13); \
301 GET_SCRATCH0(r10); \
302 std r10,area+EX_R13(r13)
303 #define EXCEPTION_PROLOG_1(area, extra, vec) \
304 __EXCEPTION_PROLOG_1(area, extra, vec)
305
306 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \
307 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
308 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
309 LOAD_HANDLER(r12,label) \
310 mtspr SPRN_##h##SRR0,r12; \
311 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
312 mtspr SPRN_##h##SRR1,r10; \
313 h##RFI_TO_KERNEL; \
314 b . /* prevent speculative execution */
315 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \
316 __EXCEPTION_PROLOG_PSERIES_1(label, h)
317
318 /* _NORI variant keeps MSR_RI clear */
319 #define __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \
320 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
321 xori r10,r10,MSR_RI; /* Clear MSR_RI */ \
322 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
323 LOAD_HANDLER(r12,label) \
324 mtspr SPRN_##h##SRR0,r12; \
325 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
326 mtspr SPRN_##h##SRR1,r10; \
327 h##RFI_TO_KERNEL; \
328 b . /* prevent speculative execution */
329
330 #define EXCEPTION_PROLOG_PSERIES_1_NORI(label, h) \
331 __EXCEPTION_PROLOG_PSERIES_1_NORI(label, h)
332
333 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \
334 EXCEPTION_PROLOG_0(area); \
335 EXCEPTION_PROLOG_1(area, extra, vec); \
336 EXCEPTION_PROLOG_PSERIES_1(label, h);
337
338 #define __KVMTEST(h, n) \
339 lbz r10,HSTATE_IN_GUEST(r13); \
340 cmpwi r10,0; \
341 bne do_kvm_##h##n
342
343 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
344 /*
345 * If hv is possible, interrupts come into to the hv version
346 * of the kvmppc_interrupt code, which then jumps to the PR handler,
347 * kvmppc_interrupt_pr, if the guest is a PR guest.
348 */
349 #define kvmppc_interrupt kvmppc_interrupt_hv
350 #else
351 #define kvmppc_interrupt kvmppc_interrupt_pr
352 #endif
353
354 /*
355 * Branch to label using its 0xC000 address. This results in instruction
356 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
357 * on using mtmsr rather than rfid.
358 *
359 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
360 * load KBASE for a slight optimisation.
361 */
362 #define BRANCH_TO_C000(reg, label) \
363 __LOAD_HANDLER(reg, label); \
364 mtctr reg; \
365 bctr
366
367 #ifdef CONFIG_RELOCATABLE
368 #define BRANCH_TO_COMMON(reg, label) \
369 __LOAD_HANDLER(reg, label); \
370 mtctr reg; \
371 bctr
372
373 #define BRANCH_LINK_TO_FAR(label) \
374 __LOAD_FAR_HANDLER(r12, label); \
375 mtctr r12; \
376 bctrl
377
378 /*
379 * KVM requires __LOAD_FAR_HANDLER.
380 *
381 * __BRANCH_TO_KVM_EXIT branches are also a special case because they
382 * explicitly use r9 then reload it from PACA before branching. Hence
383 * the double-underscore.
384 */
385 #define __BRANCH_TO_KVM_EXIT(area, label) \
386 mfctr r9; \
387 std r9,HSTATE_SCRATCH1(r13); \
388 __LOAD_FAR_HANDLER(r9, label); \
389 mtctr r9; \
390 ld r9,area+EX_R9(r13); \
391 bctr
392
393 #else
394 #define BRANCH_TO_COMMON(reg, label) \
395 b label
396
397 #define BRANCH_LINK_TO_FAR(label) \
398 bl label
399
400 #define __BRANCH_TO_KVM_EXIT(area, label) \
401 ld r9,area+EX_R9(r13); \
402 b label
403
404 #endif
405
406 /* Do not enable RI */
407 #define EXCEPTION_PROLOG_PSERIES_NORI(area, label, h, extra, vec) \
408 EXCEPTION_PROLOG_0(area); \
409 EXCEPTION_PROLOG_1(area, extra, vec); \
410 EXCEPTION_PROLOG_PSERIES_1_NORI(label, h);
411
412
413 #define __KVM_HANDLER(area, h, n) \
414 BEGIN_FTR_SECTION_NESTED(947) \
415 ld r10,area+EX_CFAR(r13); \
416 std r10,HSTATE_CFAR(r13); \
417 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
418 BEGIN_FTR_SECTION_NESTED(948) \
419 ld r10,area+EX_PPR(r13); \
420 std r10,HSTATE_PPR(r13); \
421 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
422 ld r10,area+EX_R10(r13); \
423 std r12,HSTATE_SCRATCH0(r13); \
424 sldi r12,r9,32; \
425 ori r12,r12,(n); \
426 /* This reloads r9 before branching to kvmppc_interrupt */ \
427 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt)
428
429 #define __KVM_HANDLER_SKIP(area, h, n) \
430 cmpwi r10,KVM_GUEST_MODE_SKIP; \
431 beq 89f; \
432 BEGIN_FTR_SECTION_NESTED(948) \
433 ld r10,area+EX_PPR(r13); \
434 std r10,HSTATE_PPR(r13); \
435 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \
436 ld r10,area+EX_R10(r13); \
437 std r12,HSTATE_SCRATCH0(r13); \
438 sldi r12,r9,32; \
439 ori r12,r12,(n); \
440 /* This reloads r9 before branching to kvmppc_interrupt */ \
441 __BRANCH_TO_KVM_EXIT(area, kvmppc_interrupt); \
442 89: mtocrf 0x80,r9; \
443 ld r9,area+EX_R9(r13); \
444 ld r10,area+EX_R10(r13); \
445 b kvmppc_skip_##h##interrupt
446
447 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
448 #define KVMTEST(h, n) __KVMTEST(h, n)
449 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n)
450 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n)
451
452 #else
453 #define KVMTEST(h, n)
454 #define KVM_HANDLER(area, h, n)
455 #define KVM_HANDLER_SKIP(area, h, n)
456 #endif
457
458 #define NOTEST(n)
459
460 #define EXCEPTION_PROLOG_COMMON_1() \
461 std r9,_CCR(r1); /* save CR in stackframe */ \
462 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
463 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
464 std r10,0(r1); /* make stack chain pointer */ \
465 std r0,GPR0(r1); /* save r0 in stackframe */ \
466 std r10,GPR1(r1); /* save r1 in stackframe */ \
467
468
469 /*
470 * The common exception prolog is used for all except a few exceptions
471 * such as a segment miss on a kernel address. We have to be prepared
472 * to take another exception from the point where we first touch the
473 * kernel stack onwards.
474 *
475 * On entry r13 points to the paca, r9-r13 are saved in the paca,
476 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
477 * SRR1, and relocation is on.
478 */
479 #define EXCEPTION_PROLOG_COMMON(n, area) \
480 andi. r10,r12,MSR_PR; /* See if coming from user */ \
481 mr r10,r1; /* Save r1 */ \
482 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
483 beq- 1f; \
484 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
485 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
486 blt+ cr1,3f; /* abort if it is */ \
487 li r1,(n); /* will be reloaded later */ \
488 sth r1,PACA_TRAP_SAVE(r13); \
489 std r3,area+EX_R3(r13); \
490 addi r3,r13,area; /* r3 -> where regs are saved*/ \
491 RESTORE_CTR(r1, area); \
492 b bad_stack; \
493 3: EXCEPTION_PROLOG_COMMON_1(); \
494 beq 4f; /* if from kernel mode */ \
495 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
496 SAVE_PPR(area, r9, r10); \
497 4: EXCEPTION_PROLOG_COMMON_2(area) \
498 EXCEPTION_PROLOG_COMMON_3(n) \
499 ACCOUNT_STOLEN_TIME
500
501 /* Save original regs values from save area to stack frame. */
502 #define EXCEPTION_PROLOG_COMMON_2(area) \
503 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
504 ld r10,area+EX_R10(r13); \
505 std r9,GPR9(r1); \
506 std r10,GPR10(r1); \
507 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
508 ld r10,area+EX_R12(r13); \
509 ld r11,area+EX_R13(r13); \
510 std r9,GPR11(r1); \
511 std r10,GPR12(r1); \
512 std r11,GPR13(r1); \
513 BEGIN_FTR_SECTION_NESTED(66); \
514 ld r10,area+EX_CFAR(r13); \
515 std r10,ORIG_GPR3(r1); \
516 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
517 GET_CTR(r10, area); \
518 std r10,_CTR(r1);
519
520 #define EXCEPTION_PROLOG_COMMON_3(n) \
521 std r2,GPR2(r1); /* save r2 in stackframe */ \
522 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
523 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
524 mflr r9; /* Get LR, later save to stack */ \
525 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
526 std r9,_LINK(r1); \
527 lbz r10,PACASOFTIRQEN(r13); \
528 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
529 std r10,SOFTE(r1); \
530 std r11,_XER(r1); \
531 li r9,(n)+1; \
532 std r9,_TRAP(r1); /* set trap number */ \
533 li r10,0; \
534 ld r11,exception_marker@toc(r2); \
535 std r10,RESULT(r1); /* clear regs->result */ \
536 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
537
538 /*
539 * Exception vectors.
540 */
541 #define STD_EXCEPTION_PSERIES(vec, label) \
542 SET_SCRATCH0(r13); /* save r13 */ \
543 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \
544 EXC_STD, KVMTEST_PR, vec); \
545
546 /* Version of above for when we have to branch out-of-line */
547 #define __OOL_EXCEPTION(vec, label, hdlr) \
548 SET_SCRATCH0(r13) \
549 EXCEPTION_PROLOG_0(PACA_EXGEN) \
550 b hdlr;
551
552 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \
553 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
554 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD)
555
556 #define STD_EXCEPTION_HV(loc, vec, label) \
557 SET_SCRATCH0(r13); /* save r13 */ \
558 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \
559 EXC_HV, KVMTEST_HV, vec);
560
561 #define STD_EXCEPTION_HV_OOL(vec, label) \
562 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
563 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV)
564
565 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \
566 /* No guest interrupts come through here */ \
567 SET_SCRATCH0(r13); /* save r13 */ \
568 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec);
569
570 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \
571 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \
572 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD)
573
574 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \
575 SET_SCRATCH0(r13); /* save r13 */ \
576 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, \
577 EXC_HV, KVMTEST_HV, vec);
578
579 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
580 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
581 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV)
582
583 /* This associate vector numbers with bits in paca->irq_happened */
584 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE
585 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC
586 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC
587 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL
588 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL
589 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI
590 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE
591
592 #define __SOFTEN_TEST(h, vec) \
593 lbz r10,PACASOFTIRQEN(r13); \
594 cmpwi r10,0; \
595 li r10,SOFTEN_VALUE_##vec; \
596 beq masked_##h##interrupt
597
598 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec)
599
600 #define SOFTEN_TEST_PR(vec) \
601 KVMTEST(EXC_STD, vec); \
602 _SOFTEN_TEST(EXC_STD, vec)
603
604 #define SOFTEN_TEST_HV(vec) \
605 KVMTEST(EXC_HV, vec); \
606 _SOFTEN_TEST(EXC_HV, vec)
607
608 #define KVMTEST_PR(vec) \
609 KVMTEST(EXC_STD, vec)
610
611 #define KVMTEST_HV(vec) \
612 KVMTEST(EXC_HV, vec)
613
614 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec)
615 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec)
616
617 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
618 SET_SCRATCH0(r13); /* save r13 */ \
619 EXCEPTION_PROLOG_0(PACA_EXGEN); \
620 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
621 EXCEPTION_PROLOG_PSERIES_1(label, h);
622
623 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
624 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)
625
626 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \
627 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
628 EXC_STD, SOFTEN_TEST_PR)
629
630 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \
631 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \
632 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD)
633
634 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \
635 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
636 EXC_HV, SOFTEN_TEST_HV)
637
638 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \
639 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
640 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV)
641
642 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
643 SET_SCRATCH0(r13); /* save r13 */ \
644 EXCEPTION_PROLOG_0(PACA_EXGEN); \
645 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
646 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
647
648 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
649 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra)
650
651 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \
652 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
653 EXC_STD, SOFTEN_NOTEST_PR)
654
655 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \
656 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
657 EXC_HV, SOFTEN_TEST_HV)
658
659 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \
660 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
661 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV)
662
663 /*
664 * Our exception common code can be passed various "additions"
665 * to specify the behaviour of interrupts, whether to kick the
666 * runlatch, etc...
667 */
668
669 /*
670 * This addition reconciles our actual IRQ state with the various software
671 * flags that track it. This may call C code.
672 */
673 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11)
674
675 #define ADD_NVGPRS \
676 bl save_nvgprs
677
678 #define RUNLATCH_ON \
679 BEGIN_FTR_SECTION \
680 CURRENT_THREAD_INFO(r3, r1); \
681 ld r4,TI_LOCAL_FLAGS(r3); \
682 andi. r0,r4,_TLF_RUNLATCH; \
683 beql ppc64_runlatch_on_trampoline; \
684 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
685
686 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \
687 EXCEPTION_PROLOG_COMMON(trap, area); \
688 /* Volatile regs are potentially clobbered here */ \
689 additions; \
690 addi r3,r1,STACK_FRAME_OVERHEAD; \
691 bl hdlr; \
692 b ret
693
694 /*
695 * Exception where stack is already set in r1, r1 is saved in r10, and it
696 * continues rather than returns.
697 */
698 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \
699 EXCEPTION_PROLOG_COMMON_1(); \
700 EXCEPTION_PROLOG_COMMON_2(area); \
701 EXCEPTION_PROLOG_COMMON_3(trap); \
702 /* Volatile regs are potentially clobbered here */ \
703 additions; \
704 addi r3,r1,STACK_FRAME_OVERHEAD; \
705 bl hdlr
706
707 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
708 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \
709 ret_from_except, ADD_NVGPRS;ADD_RECONCILE)
710
711 /*
712 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
713 * in the idle task and therefore need the special idle handling
714 * (finish nap and runlatch)
715 */
716 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
717 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \
718 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON)
719
720 /*
721 * When the idle code in power4_idle puts the CPU into NAP mode,
722 * it has to do so in a loop, and relies on the external interrupt
723 * and decrementer interrupt entry code to get it out of the loop.
724 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
725 * to signal that it is in the loop and needs help to get out.
726 */
727 #ifdef CONFIG_PPC_970_NAP
728 #define FINISH_NAP \
729 BEGIN_FTR_SECTION \
730 CURRENT_THREAD_INFO(r11, r1); \
731 ld r9,TI_LOCAL_FLAGS(r11); \
732 andi. r10,r9,_TLF_NAPPING; \
733 bnel power4_fixup_nap; \
734 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
735 #else
736 #define FINISH_NAP
737 #endif
738
739 #endif /* _ASM_POWERPC_EXCEPTION_H */
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