arch/x86/include/asm/spec-ctrl.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_SPECCTRL_H_
   3 #define _ASM_X86_SPECCTRL_H_
   4
   5 #include <linux/thread_info.h>
   6 #include <asm/nospec-branch.h>
   7
   8 /*
   9  * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
  10  * the guest has, while on VMEXIT we restore the host view. This
  11  * would be easier if SPEC_CTRL were architecturally maskable or
  12  * shadowable for guests but this is not (currently) the case.
  13  * Takes the guest view of SPEC_CTRL MSR as a parameter and also
  14  * the guest's version of VIRT_SPEC_CTRL, if emulated.
  15  */
  16 extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);
  17
  18 /**
  19  * x86_spec_ctrl_set_guest - Set speculation control registers for the guest
  20  * @guest_spec_ctrl:            The guest content of MSR_SPEC_CTRL
  21  * @guest_virt_spec_ctrl:       The guest controlled bits of MSR_VIRT_SPEC_CTRL
  22  *                              (may get translated to MSR_AMD64_LS_CFG bits)
  23  *
  24  * Avoids writing to the MSR if the content/bits are the same
  25  */
  26 static inline
  27 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
  28 {
  29         x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true);
  30 }
  31
  32 /**
  33  * x86_spec_ctrl_restore_host - Restore host speculation control registers
  34  * @guest_spec_ctrl:            The guest content of MSR_SPEC_CTRL
  35  * @guest_virt_spec_ctrl:       The guest controlled bits of MSR_VIRT_SPEC_CTRL
  36  *                              (may get translated to MSR_AMD64_LS_CFG bits)
  37  *
  38  * Avoids writing to the MSR if the content/bits are the same
  39  */
  40 static inline
  41 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
  42 {
  43         x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false);
  44 }
  45
  46 /*
  47  * On VMEXIT we must ensure that no RSB predictions learned in the guest
  48  * can be followed in the host, by overwriting the RSB completely. Both
  49  * retpoline and IBRS mitigations for Spectre v2 need this; only on future
  50  * CPUs with IBRS_ATT *might* it be avoided.
  51  */
  52 static inline void vmexit_fill_RSB(void)
  53 {
  54 #ifdef CONFIG_RETPOLINE
  55         alternative_input("",
  56                           "call __fill_rsb",
  57                           X86_FEATURE_RETPOLINE,
  58                           ASM_NO_INPUT_CLOBBER(_ASM_BX, "memory"));
  59 #endif
  60 }
  61
  62 /* AMD specific Speculative Store Bypass MSR data */
  63 extern u64 x86_amd_ls_cfg_base;
  64 extern u64 x86_amd_ls_cfg_ssbd_mask;
  65
  66 static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
  67 {
  68         BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
  69         return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
  70 }
  71
  72 static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
  73 {
  74         return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
  75 }
  76
  77 #ifdef CONFIG_SMP
  78 extern void speculative_store_bypass_ht_init(void);
  79 #else
  80 static inline void speculative_store_bypass_ht_init(void) { }
  81 #endif
  82
  83 extern void speculative_store_bypass_update(unsigned long tif);
  84
  85 static inline void speculative_store_bypass_update_current(void)
  86 {
  87         speculative_store_bypass_update(current_thread_info()->flags);
  88 }
  89
  90 #endif