arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/smp.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16
  17 #include <asm/spec-ctrl.h>
  18 #include <asm/cmdline.h>
  19 #include <asm/bugs.h>
  20 #include <asm/processor.h>
  21 #include <asm/processor-flags.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/msr.h>
  24 #include <asm/paravirt.h>
  25 #include <asm/alternative.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/set_memory.h>
  28 #include <asm/intel-family.h>
  29
  30 static void __init spectre_v2_select_mitigation(void);
  31 static void __init ssb_select_mitigation(void);
  32
  33 /*
  34  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  35  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  36  */
  37 u64 __ro_after_init x86_spec_ctrl_base;
  38
  39 /*
  40  * The vendor and possibly platform specific bits which can be modified in
  41  * x86_spec_ctrl_base.
  42  */
  43 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  44
  45 /*
  46  * AMD specific MSR info for Speculative Store Bypass control.
  47  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  48  */
  49 u64 __ro_after_init x86_amd_ls_cfg_base;
  50 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  51
  52 void __init check_bugs(void)
  53 {
  54         identify_boot_cpu();
  55
  56         if (!IS_ENABLED(CONFIG_SMP)) {
  57                 pr_info("CPU: ");
  58                 print_cpu_info(&boot_cpu_data);
  59         }
  60
  61         /*
  62          * Read the SPEC_CTRL MSR to account for reserved bits which may
  63          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  64          * init code as it is not enumerated and depends on the family.
  65          */
  66         if (ibrs_inuse)
  67                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  68
  69         /* Select the proper spectre mitigation before patching alternatives */
  70         spectre_v2_select_mitigation();
  71
  72         /*
  73          * Select proper mitigation for any exposure to the Speculative Store
  74          * Bypass vulnerability.
  75          */
  76         ssb_select_mitigation();
  77
  78 #ifdef CONFIG_X86_32
  79         /*
  80          * Check whether we are able to run this kernel safely on SMP.
  81          *
  82          * - i386 is no longer supported.
  83          * - In order to run on anything without a TSC, we need to be
  84          *   compiled for a i486.
  85          */
  86         if (boot_cpu_data.x86 < 4)
  87                 panic("Kernel requires i486+ for 'invlpg' and other features");
  88
  89         init_utsname()->machine[1] =
  90                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  91         alternative_instructions();
  92
  93         fpu__init_check_bugs();
  94 #else /* CONFIG_X86_64 */
  95         alternative_instructions();
  96
  97         /*
  98          * Make sure the first 2MB area is not mapped by huge pages
  99          * There are typically fixed size MTRRs in there and overlapping
 100          * MTRRs into large pages causes slow downs.
 101          *
 102          * Right now we don't do that with gbpages because there seems
 103          * very little benefit for that case.
 104          */
 105         if (!direct_gbpages)
 106                 set_memory_4k((unsigned long)__va(0), 1);
 107 #endif
 108 }
 109
 110 /* The kernel command line selection */
 111 enum spectre_v2_mitigation_cmd {
 112         SPECTRE_V2_CMD_NONE,
 113         SPECTRE_V2_CMD_AUTO,
 114         SPECTRE_V2_CMD_FORCE,
 115         SPECTRE_V2_CMD_RETPOLINE,
 116         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 117         SPECTRE_V2_CMD_RETPOLINE_AMD,
 118 };
 119
 120 static const char *spectre_v2_strings[] = {
 121         [SPECTRE_V2_NONE]                       = "Vulnerable",
 122         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 125         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 126 };
 127
 128 #undef pr_fmt
 129 #define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt
 130
 131 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 132         SPECTRE_V2_NONE;
 133
 134 void x86_spec_ctrl_set(u64 val)
 135 {
 136         if (val & x86_spec_ctrl_mask)
 137                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 138         else
 139                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 140 }
 141 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 142
 143 u64 x86_spec_ctrl_get_default(void)
 144 {
 145         u64 msrval = x86_spec_ctrl_base;
 146
 147         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 148                 msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 149         return msrval;
 150 }
 151 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
 152
 153 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
 154 {
 155         u64 host = x86_spec_ctrl_base;
 156
 157         if (!ibrs_inuse)
 158                 return;
 159
 160         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 161                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 162
 163         if (host != guest_spec_ctrl)
 164                 wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
 165 }
 166 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
 167
 168 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
 169 {
 170         u64 host = x86_spec_ctrl_base;
 171
 172         if (!ibrs_inuse)
 173                 return;
 174
 175         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
 176                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 177
 178         if (host != guest_spec_ctrl)
 179                 wrmsrl(MSR_IA32_SPEC_CTRL, host);
 180 }
 181 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
 182
 183 static void x86_amd_ssb_disable(void)
 184 {
 185         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 186
 187         if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
 188                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 189 }
 190
 191 static void __init spec2_print_if_insecure(const char *reason)
 192 {
 193         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 194                 pr_info("%s\n", reason);
 195 }
 196
 197 static void __init spec2_print_if_secure(const char *reason)
 198 {
 199         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 200                 pr_info("%s\n", reason);
 201 }
 202
 203 static inline bool retp_compiler(void)
 204 {
 205         return __is_defined(RETPOLINE);
 206 }
 207
 208 static inline bool match_option(const char *arg, int arglen, const char *opt)
 209 {
 210         int len = strlen(opt);
 211
 212         return len == arglen && !strncmp(arg, opt, len);
 213 }
 214
 215 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 216 {
 217         char arg[20];
 218         int ret;
 219
 220         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
 221                                   sizeof(arg));
 222         if (ret > 0)  {
 223                 if (match_option(arg, ret, "off")) {
 224                         goto disable;
 225                 } else if (match_option(arg, ret, "on")) {
 226                         spec2_print_if_secure("force enabled on command line.");
 227                         return SPECTRE_V2_CMD_FORCE;
 228                 } else if (match_option(arg, ret, "retpoline")) {
 229                         spec2_print_if_insecure("retpoline selected on command line.");
 230                         return SPECTRE_V2_CMD_RETPOLINE;
 231                 } else if (match_option(arg, ret, "retpoline,amd")) {
 232                         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 233                                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 234                                 return SPECTRE_V2_CMD_AUTO;
 235                         }
 236                         spec2_print_if_insecure("AMD retpoline selected on command line.");
 237                         return SPECTRE_V2_CMD_RETPOLINE_AMD;
 238                 } else if (match_option(arg, ret, "retpoline,generic")) {
 239                         spec2_print_if_insecure("generic retpoline selected on command line.");
 240                         return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
 241                 } else if (match_option(arg, ret, "auto")) {
 242                         return SPECTRE_V2_CMD_AUTO;
 243                 }
 244         }
 245
 246         if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 247                 return SPECTRE_V2_CMD_AUTO;
 248 disable:
 249         spec2_print_if_insecure("disabled on command line.");
 250         return SPECTRE_V2_CMD_NONE;
 251 }
 252
 253 /* Check for Skylake-like CPUs (for RSB handling) */
 254 static bool __init is_skylake_era(void)
 255 {
 256         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 257             boot_cpu_data.x86 == 6) {
 258                 switch (boot_cpu_data.x86_model) {
 259                 case INTEL_FAM6_SKYLAKE_MOBILE:
 260                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 261                 case INTEL_FAM6_SKYLAKE_X:
 262                 case INTEL_FAM6_KABYLAKE_MOBILE:
 263                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 264                         return true;
 265                 }
 266         }
 267         return false;
 268 }
 269
 270 static void __init spectre_v2_select_mitigation(void)
 271 {
 272         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 273         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 274
 275         /*
 276          * If the CPU is not affected and the command line mode is NONE or AUTO
 277          * then nothing to do.
 278          */
 279         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 280             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 281                 return;
 282
 283         switch (cmd) {
 284         case SPECTRE_V2_CMD_NONE:
 285                 return;
 286
 287         case SPECTRE_V2_CMD_FORCE:
 288                 /* FALLTRHU */
 289         case SPECTRE_V2_CMD_AUTO:
 290                 goto retpoline_auto;
 291
 292         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 293                 if (IS_ENABLED(CONFIG_RETPOLINE))
 294                         goto retpoline_amd;
 295                 break;
 296         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 297                 if (IS_ENABLED(CONFIG_RETPOLINE))
 298                         goto retpoline_generic;
 299                 break;
 300         case SPECTRE_V2_CMD_RETPOLINE:
 301                 if (IS_ENABLED(CONFIG_RETPOLINE))
 302                         goto retpoline_auto;
 303                 break;
 304         }
 305         pr_err("kernel not compiled with retpoline; no mitigation available!");
 306         return;
 307
 308 retpoline_auto:
 309         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 310         retpoline_amd:
 311                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 312                         pr_err("LFENCE not serializing. Switching to generic retpoline\n");
 313                         goto retpoline_generic;
 314                 }
 315                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 316                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 317                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 318                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 319         } else {
 320         retpoline_generic:
 321                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 322                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 323                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 324         }
 325
 326         spectre_v2_enabled = mode;
 327         pr_info("%s\n", spectre_v2_strings[mode]);
 328
 329         pr_info("Speculation control IBPB %s IBRS %s",
 330                 ibpb_supported ? "supported" : "not-supported",
 331                 ibrs_supported ? "supported" : "not-supported");
 332
 333         /*
 334          * If we have a full retpoline mode and then disable IBPB in kernel mode
 335          * we do not require both.
 336          */
 337         if (mode == SPECTRE_V2_RETPOLINE_AMD ||
 338             mode == SPECTRE_V2_RETPOLINE_GENERIC)
 339         {
 340                 if (ibrs_supported) {
 341                         pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
 342                         set_ibrs_disabled();
 343                         if (!ibrs_inuse)
 344                                 sysctl_ibrs_enabled = 0;
 345                 }
 346         }
 347
 348         /*
 349          * If neither SMEP or KPTI are available, there is a risk of
 350          * hitting userspace addresses in the RSB after a context switch
 351          * from a shallow call stack to a deeper one. To prevent this fill
 352          * the entire RSB, even when using IBRS.
 353          *
 354          * Skylake era CPUs have a separate issue with *underflow* of the
 355          * RSB, when they will predict 'ret' targets from the generic BTB.
 356          * The proper mitigation for this is IBRS. If IBRS is not supported
 357          * or deactivated in favour of retpolines the RSB fill on context
 358          * switch is required.
 359          */
 360         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 361              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 362                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 363                 pr_info("Filling RSB on context switch\n");
 364         }
 365 }
 366
 367 #undef pr_fmt
 368 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 369
 370 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 371
 372 /* The kernel command line selection */
 373 enum ssb_mitigation_cmd {
 374         SPEC_STORE_BYPASS_CMD_NONE,
 375         SPEC_STORE_BYPASS_CMD_AUTO,
 376         SPEC_STORE_BYPASS_CMD_ON,
 377         SPEC_STORE_BYPASS_CMD_PRCTL,
 378         SPEC_STORE_BYPASS_CMD_SECCOMP,
 379 };
 380
 381 static const char *ssb_strings[] = {
 382         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 383         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 384         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 385         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 386 };
 387
 388 static const struct {
 389         const char *option;
 390         enum ssb_mitigation_cmd cmd;
 391 } ssb_mitigation_options[] = {
 392         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 393         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 394         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 395         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 396         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 397 };
 398
 399 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 400 {
 401         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 402         char arg[20];
 403         int ret, i;
 404
 405         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 406                 return SPEC_STORE_BYPASS_CMD_NONE;
 407         } else {
 408                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 409                                           arg, sizeof(arg));
 410                 if (ret < 0)
 411                         return SPEC_STORE_BYPASS_CMD_AUTO;
 412
 413                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 414                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 415                                 continue;
 416
 417                         cmd = ssb_mitigation_options[i].cmd;
 418                         break;
 419                 }
 420
 421                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 422                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 423                         return SPEC_STORE_BYPASS_CMD_AUTO;
 424                 }
 425         }
 426
 427         return cmd;
 428 }
 429
 430 static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
 431 {
 432         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 433         enum ssb_mitigation_cmd cmd;
 434
 435         if (!boot_cpu_has(X86_FEATURE_SSBD))
 436                 return mode;
 437
 438         cmd = ssb_parse_cmdline();
 439         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 440             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 441              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 442                 return mode;
 443
 444         switch (cmd) {
 445         case SPEC_STORE_BYPASS_CMD_AUTO:
 446         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 447                 /*
 448                  * Choose prctl+seccomp as the default mode if seccomp is
 449                  * enabled.
 450                  */
 451                 if (IS_ENABLED(CONFIG_SECCOMP))
 452                         mode = SPEC_STORE_BYPASS_SECCOMP;
 453                 else
 454                         mode = SPEC_STORE_BYPASS_PRCTL;
 455                 break;
 456         case SPEC_STORE_BYPASS_CMD_ON:
 457                 mode = SPEC_STORE_BYPASS_DISABLE;
 458                 break;
 459         case SPEC_STORE_BYPASS_CMD_PRCTL:
 460                 mode = SPEC_STORE_BYPASS_PRCTL;
 461                 break;
 462         case SPEC_STORE_BYPASS_CMD_NONE:
 463                 break;
 464         }
 465
 466         /*
 467          * We have three CPU feature flags that are in play here:
 468          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 469          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 470          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 471          */
 472         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 473                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 474                 /*
 475                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 476                  * a completely different MSR and bit dependent on family.
 477                  */
 478                 switch (boot_cpu_data.x86_vendor) {
 479                 case X86_VENDOR_INTEL:
 480                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 481                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 482                         x86_spec_ctrl_set(SPEC_CTRL_SSBD);
 483                         break;
 484                 case X86_VENDOR_AMD:
 485                         x86_amd_ssb_disable();
 486                         break;
 487                 }
 488         }
 489
 490         return mode;
 491 }
 492
 493 static void ssb_select_mitigation()
 494 {
 495         ssb_mode = __ssb_select_mitigation();
 496
 497         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 498                 pr_info("%s\n", ssb_strings[ssb_mode]);
 499 }
 500
 501 #undef pr_fmt
 502 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 503
 504 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 505 {
 506         bool update;
 507
 508         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 509             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 510                 return -ENXIO;
 511
 512         switch (ctrl) {
 513         case PR_SPEC_ENABLE:
 514                 /* If speculation is force disabled, enable is not allowed */
 515                 if (task_spec_ssb_force_disable(task))
 516                         return -EPERM;
 517                 task_clear_spec_ssb_disable(task);
 518                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 519                 break;
 520         case PR_SPEC_DISABLE:
 521                 task_set_spec_ssb_disable(task);
 522                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 523                 break;
 524         case PR_SPEC_FORCE_DISABLE:
 525                 task_set_spec_ssb_disable(task);
 526                 task_set_spec_ssb_force_disable(task);
 527                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 528                 break;
 529         default:
 530                 return -ERANGE;
 531         }
 532
 533         /*
 534          * If being set on non-current task, delay setting the CPU
 535          * mitigation until it is next scheduled.
 536          */
 537         if (task == current && update)
 538                 speculative_store_bypass_update();
 539
 540         return 0;
 541 }
 542
 543 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 544                              unsigned long ctrl)
 545 {
 546         switch (which) {
 547         case PR_SPEC_STORE_BYPASS:
 548                 return ssb_prctl_set(task, ctrl);
 549         default:
 550                 return -ENODEV;
 551         }
 552 }
 553
 554 #ifdef CONFIG_SECCOMP
 555 void arch_seccomp_spec_mitigate(struct task_struct *task)
 556 {
 557         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 558                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 559 }
 560 #endif
 561
 562 static int ssb_prctl_get(struct task_struct *task)
 563 {
 564         switch (ssb_mode) {
 565         case SPEC_STORE_BYPASS_DISABLE:
 566                 return PR_SPEC_DISABLE;
 567         case SPEC_STORE_BYPASS_SECCOMP:
 568         case SPEC_STORE_BYPASS_PRCTL:
 569                 if (task_spec_ssb_force_disable(task))
 570                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 571                 if (task_spec_ssb_disable(task))
 572                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 573                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 574         default:
 575                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 576                         return PR_SPEC_ENABLE;
 577                 return PR_SPEC_NOT_AFFECTED;
 578         }
 579 }
 580
 581 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 582 {
 583         switch (which) {
 584         case PR_SPEC_STORE_BYPASS:
 585                 return ssb_prctl_get(task);
 586         default:
 587                 return -ENODEV;
 588         }
 589 }
 590
 591 void x86_spec_ctrl_setup_ap(void)
 592 {
 593         if (ibrs_inuse)
 594                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 595
 596         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 597                 x86_amd_ssb_disable();
 598 }
 599
 600 #ifdef CONFIG_SYSFS
 601 ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 602                         char *buf, unsigned int bug)
 603 {
 604         if (!boot_cpu_has_bug(bug))
 605                 return sprintf(buf, "Not affected\n");
 606
 607         switch (bug) {
 608         case X86_BUG_CPU_MELTDOWN:
 609                 if (boot_cpu_has(X86_FEATURE_PTI))
 610                         return sprintf(buf, "Mitigation: PTI\n");
 611                 break;
 612
 613         case X86_BUG_SPECTRE_V1:
 614                 if (osb_is_enabled)
 615                         return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
 616
 617         case X86_BUG_SPECTRE_V2:
 618                 return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
 619
 620         case X86_BUG_SPEC_STORE_BYPASS:
 621                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 622
 623         default:
 624                 break;
 625         }
 626
 627         return sprintf(buf, "Vulnerable\n");
 628 }
 629
 630 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
 631                           char *buf)
 632 {
 633         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 634 }
 635
 636 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 637                             char *buf)
 638 {
 639         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 640 }
 641
 642 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 643                             char *buf)
 644 {
 645         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 646 }
 647
 648 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 649 {
 650         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 651 }
 652 #endif