arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/smp.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16
  17 #include <asm/spec-ctrl.h>
  18 #include <asm/cmdline.h>
  19 #include <asm/bugs.h>
  20 #include <asm/processor.h>
  21 #include <asm/processor-flags.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/msr.h>
  24 #include <asm/paravirt.h>
  25 #include <asm/alternative.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/set_memory.h>
  28 #include <asm/intel-family.h>
  29
  30 static void __init spectre_v2_select_mitigation(void);
  31 static void __init ssb_select_mitigation(void);
  32
  33 /*
  34  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  35  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  36  */
  37 u64 __ro_after_init x86_spec_ctrl_base;
  38 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 133         SPECTRE_V2_NONE;
 134
 135 void
 136 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 137 {
 138         struct thread_info *ti = current_thread_info();
 139         u64 msr, host = x86_spec_ctrl_base;
 140
 141         /* Is MSR_SPEC_CTRL implemented ? */
 142         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 143                 /* SSBD controlled in MSR_SPEC_CTRL */
 144                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 145                         host |= ssbd_tif_to_spec_ctrl(ti->flags);
 146
 147                 if (host != guest_spec_ctrl) {
 148                         msr = setguest ? guest_spec_ctrl : host;
 149                         wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 150                 }
 151         }
 152 }
 153 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 154
 155 static void x86_amd_ssb_disable(void)
 156 {
 157         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 158
 159         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 160                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 161         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 162                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 163 }
 164
 165 static void __init spec2_print_if_insecure(const char *reason)
 166 {
 167         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 168                 pr_info("%s\n", reason);
 169 }
 170
 171 static void __init spec2_print_if_secure(const char *reason)
 172 {
 173         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 174                 pr_info("%s\n", reason);
 175 }
 176
 177 static inline bool retp_compiler(void)
 178 {
 179         return __is_defined(RETPOLINE);
 180 }
 181
 182 static inline bool match_option(const char *arg, int arglen, const char *opt)
 183 {
 184         int len = strlen(opt);
 185
 186         return len == arglen && !strncmp(arg, opt, len);
 187 }
 188
 189 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 190 {
 191         char arg[20];
 192         int ret;
 193
 194         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
 195                                   sizeof(arg));
 196         if (ret > 0)  {
 197                 if (match_option(arg, ret, "off")) {
 198                         goto disable;
 199                 } else if (match_option(arg, ret, "on")) {
 200                         spec2_print_if_secure("force enabled on command line.");
 201                         return SPECTRE_V2_CMD_FORCE;
 202                 } else if (match_option(arg, ret, "retpoline")) {
 203                         spec2_print_if_insecure("retpoline selected on command line.");
 204                         return SPECTRE_V2_CMD_RETPOLINE;
 205                 } else if (match_option(arg, ret, "retpoline,amd")) {
 206                         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 207                                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 208                                 return SPECTRE_V2_CMD_AUTO;
 209                         }
 210                         spec2_print_if_insecure("AMD retpoline selected on command line.");
 211                         return SPECTRE_V2_CMD_RETPOLINE_AMD;
 212                 } else if (match_option(arg, ret, "retpoline,generic")) {
 213                         spec2_print_if_insecure("generic retpoline selected on command line.");
 214                         return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
 215                 } else if (match_option(arg, ret, "auto")) {
 216                         return SPECTRE_V2_CMD_AUTO;
 217                 }
 218         }
 219
 220         if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 221                 return SPECTRE_V2_CMD_AUTO;
 222 disable:
 223         spec2_print_if_insecure("disabled on command line.");
 224         return SPECTRE_V2_CMD_NONE;
 225 }
 226
 227 /* Check for Skylake-like CPUs (for RSB handling) */
 228 static bool __init is_skylake_era(void)
 229 {
 230         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 231             boot_cpu_data.x86 == 6) {
 232                 switch (boot_cpu_data.x86_model) {
 233                 case INTEL_FAM6_SKYLAKE_MOBILE:
 234                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 235                 case INTEL_FAM6_SKYLAKE_X:
 236                 case INTEL_FAM6_KABYLAKE_MOBILE:
 237                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 238                         return true;
 239                 }
 240         }
 241         return false;
 242 }
 243
 244 static void __init spectre_v2_select_mitigation(void)
 245 {
 246         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 247         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 248
 249         /*
 250          * If the CPU is not affected and the command line mode is NONE or AUTO
 251          * then nothing to do.
 252          */
 253         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 254             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 255                 return;
 256
 257         switch (cmd) {
 258         case SPECTRE_V2_CMD_NONE:
 259                 return;
 260
 261         case SPECTRE_V2_CMD_FORCE:
 262                 /* FALLTRHU */
 263         case SPECTRE_V2_CMD_AUTO:
 264                 goto retpoline_auto;
 265
 266         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 267                 if (IS_ENABLED(CONFIG_RETPOLINE))
 268                         goto retpoline_amd;
 269                 break;
 270         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 271                 if (IS_ENABLED(CONFIG_RETPOLINE))
 272                         goto retpoline_generic;
 273                 break;
 274         case SPECTRE_V2_CMD_RETPOLINE:
 275                 if (IS_ENABLED(CONFIG_RETPOLINE))
 276                         goto retpoline_auto;
 277                 break;
 278         }
 279         pr_err("kernel not compiled with retpoline; no mitigation available!");
 280         return;
 281
 282 retpoline_auto:
 283         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 284         retpoline_amd:
 285                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 286                         pr_err("LFENCE not serializing. Switching to generic retpoline\n");
 287                         goto retpoline_generic;
 288                 }
 289                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 290                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 291                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 292                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 293         } else {
 294         retpoline_generic:
 295                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 296                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 297                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 298         }
 299
 300         spectre_v2_enabled = mode;
 301         pr_info("%s\n", spectre_v2_strings[mode]);
 302
 303         pr_info("Speculation control IBPB %s IBRS %s",
 304                 ibpb_supported ? "supported" : "not-supported",
 305                 ibrs_supported ? "supported" : "not-supported");
 306
 307         /*
 308          * If we have a full retpoline mode and then disable IBPB in kernel mode
 309          * we do not require both.
 310          */
 311         if (mode == SPECTRE_V2_RETPOLINE_AMD ||
 312             mode == SPECTRE_V2_RETPOLINE_GENERIC)
 313         {
 314                 if (ibrs_supported) {
 315                         pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
 316                         set_ibrs_disabled();
 317                         if (!ibrs_inuse)
 318                                 sysctl_ibrs_enabled = 0;
 319                 }
 320         }
 321
 322         /*
 323          * If neither SMEP or KPTI are available, there is a risk of
 324          * hitting userspace addresses in the RSB after a context switch
 325          * from a shallow call stack to a deeper one. To prevent this fill
 326          * the entire RSB, even when using IBRS.
 327          *
 328          * Skylake era CPUs have a separate issue with *underflow* of the
 329          * RSB, when they will predict 'ret' targets from the generic BTB.
 330          * The proper mitigation for this is IBRS. If IBRS is not supported
 331          * or deactivated in favour of retpolines the RSB fill on context
 332          * switch is required.
 333          */
 334         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 335              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 336                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 337                 pr_info("Filling RSB on context switch\n");
 338         }
 339 }
 340
 341 #undef pr_fmt
 342 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 343
 344 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 345
 346 /* The kernel command line selection */
 347 enum ssb_mitigation_cmd {
 348         SPEC_STORE_BYPASS_CMD_NONE,
 349         SPEC_STORE_BYPASS_CMD_AUTO,
 350         SPEC_STORE_BYPASS_CMD_ON,
 351         SPEC_STORE_BYPASS_CMD_PRCTL,
 352         SPEC_STORE_BYPASS_CMD_SECCOMP,
 353 };
 354
 355 static const char *ssb_strings[] = {
 356         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 357         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 358         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 359         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 360 };
 361
 362 static const struct {
 363         const char *option;
 364         enum ssb_mitigation_cmd cmd;
 365 } ssb_mitigation_options[] = {
 366         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 367         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 368         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 369         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 370         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 371 };
 372
 373 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 374 {
 375         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 376         char arg[20];
 377         int ret, i;
 378
 379         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 380                 return SPEC_STORE_BYPASS_CMD_NONE;
 381         } else {
 382                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 383                                           arg, sizeof(arg));
 384                 if (ret < 0)
 385                         return SPEC_STORE_BYPASS_CMD_AUTO;
 386
 387                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 388                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 389                                 continue;
 390
 391                         cmd = ssb_mitigation_options[i].cmd;
 392                         break;
 393                 }
 394
 395                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 396                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 397                         return SPEC_STORE_BYPASS_CMD_AUTO;
 398                 }
 399         }
 400
 401         return cmd;
 402 }
 403
 404 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 405 {
 406         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 407         enum ssb_mitigation_cmd cmd;
 408
 409         if (!boot_cpu_has(X86_FEATURE_SSBD))
 410                 return mode;
 411
 412         cmd = ssb_parse_cmdline();
 413         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 414             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 415              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 416                 return mode;
 417
 418         switch (cmd) {
 419         case SPEC_STORE_BYPASS_CMD_AUTO:
 420         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 421                 /*
 422                  * Choose prctl+seccomp as the default mode if seccomp is
 423                  * enabled.
 424                  */
 425                 if (IS_ENABLED(CONFIG_SECCOMP))
 426                         mode = SPEC_STORE_BYPASS_SECCOMP;
 427                 else
 428                         mode = SPEC_STORE_BYPASS_PRCTL;
 429                 break;
 430         case SPEC_STORE_BYPASS_CMD_ON:
 431                 mode = SPEC_STORE_BYPASS_DISABLE;
 432                 break;
 433         case SPEC_STORE_BYPASS_CMD_PRCTL:
 434                 mode = SPEC_STORE_BYPASS_PRCTL;
 435                 break;
 436         case SPEC_STORE_BYPASS_CMD_NONE:
 437                 break;
 438         }
 439
 440         /*
 441          * We have three CPU feature flags that are in play here:
 442          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 443          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 444          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 445          */
 446         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 447                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 448                 /*
 449                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 450                  * a completely different MSR and bit dependent on family.
 451                  */
 452                 switch (boot_cpu_data.x86_vendor) {
 453                 case X86_VENDOR_INTEL:
 454                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 455                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 456                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 457                         break;
 458                 case X86_VENDOR_AMD:
 459                         x86_amd_ssb_disable();
 460                         break;
 461                 }
 462         }
 463
 464         return mode;
 465 }
 466
 467 static void ssb_select_mitigation(void)
 468 {
 469         ssb_mode = __ssb_select_mitigation();
 470
 471         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 472                 pr_info("%s\n", ssb_strings[ssb_mode]);
 473 }
 474
 475 #undef pr_fmt
 476 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 477
 478 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 479 {
 480         bool update;
 481
 482         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 483             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 484                 return -ENXIO;
 485
 486         switch (ctrl) {
 487         case PR_SPEC_ENABLE:
 488                 /* If speculation is force disabled, enable is not allowed */
 489                 if (task_spec_ssb_force_disable(task))
 490                         return -EPERM;
 491                 task_clear_spec_ssb_disable(task);
 492                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 493                 break;
 494         case PR_SPEC_DISABLE:
 495                 task_set_spec_ssb_disable(task);
 496                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 497                 break;
 498         case PR_SPEC_FORCE_DISABLE:
 499                 task_set_spec_ssb_disable(task);
 500                 task_set_spec_ssb_force_disable(task);
 501                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 502                 break;
 503         default:
 504                 return -ERANGE;
 505         }
 506
 507         /*
 508          * If being set on non-current task, delay setting the CPU
 509          * mitigation until it is next scheduled.
 510          */
 511         if (task == current && update)
 512                 speculative_store_bypass_update_current();
 513
 514         return 0;
 515 }
 516
 517 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 518                              unsigned long ctrl)
 519 {
 520         switch (which) {
 521         case PR_SPEC_STORE_BYPASS:
 522                 return ssb_prctl_set(task, ctrl);
 523         default:
 524                 return -ENODEV;
 525         }
 526 }
 527
 528 #ifdef CONFIG_SECCOMP
 529 void arch_seccomp_spec_mitigate(struct task_struct *task)
 530 {
 531         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 532                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 533 }
 534 #endif
 535
 536 static int ssb_prctl_get(struct task_struct *task)
 537 {
 538         switch (ssb_mode) {
 539         case SPEC_STORE_BYPASS_DISABLE:
 540                 return PR_SPEC_DISABLE;
 541         case SPEC_STORE_BYPASS_SECCOMP:
 542         case SPEC_STORE_BYPASS_PRCTL:
 543                 if (task_spec_ssb_force_disable(task))
 544                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 545                 if (task_spec_ssb_disable(task))
 546                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 547                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 548         default:
 549                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 550                         return PR_SPEC_ENABLE;
 551                 return PR_SPEC_NOT_AFFECTED;
 552         }
 553 }
 554
 555 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 556 {
 557         switch (which) {
 558         case PR_SPEC_STORE_BYPASS:
 559                 return ssb_prctl_get(task);
 560         default:
 561                 return -ENODEV;
 562         }
 563 }
 564
 565 void x86_spec_ctrl_setup_ap(void)
 566 {
 567         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 568                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 569
 570         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 571                 x86_amd_ssb_disable();
 572 }
 573
 574 #ifdef CONFIG_SYSFS
 575 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 576                                char *buf, unsigned int bug)
 577 {
 578         if (!boot_cpu_has_bug(bug))
 579                 return sprintf(buf, "Not affected\n");
 580
 581         switch (bug) {
 582         case X86_BUG_CPU_MELTDOWN:
 583                 if (boot_cpu_has(X86_FEATURE_PTI))
 584                         return sprintf(buf, "Mitigation: PTI\n");
 585                 break;
 586
 587         case X86_BUG_SPECTRE_V1:
 588                 if (osb_is_enabled)
 589                         return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
 590
 591         case X86_BUG_SPECTRE_V2:
 592                 return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
 593
 594         case X86_BUG_SPEC_STORE_BYPASS:
 595                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 596
 597         default:
 598                 break;
 599         }
 600
 601         return sprintf(buf, "Vulnerable\n");
 602 }
 603
 604 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
 605                           char *buf)
 606 {
 607         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 608 }
 609
 610 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 611                             char *buf)
 612 {
 613         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 614 }
 615
 616 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 617                             char *buf)
 618 {
 619         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 620 }
 621
 622 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 623 {
 624         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 625 }
 626 #endif