arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/smp.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16
  17 #include <asm/spec-ctrl.h>
  18 #include <asm/cmdline.h>
  19 #include <asm/bugs.h>
  20 #include <asm/processor.h>
  21 #include <asm/processor-flags.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/msr.h>
  24 #include <asm/paravirt.h>
  25 #include <asm/alternative.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/set_memory.h>
  28 #include <asm/intel-family.h>
  29
  30 static void __init spectre_v2_select_mitigation(void);
  31 static void __init ssb_select_mitigation(void);
  32
  33 /*
  34  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  35  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  36  */
  37 u64 __ro_after_init x86_spec_ctrl_base;
  38 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  39
  40 /*
  41  * The vendor and possibly platform specific bits which can be modified in
  42  * x86_spec_ctrl_base.
  43  */
  44 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  45
  46 /*
  47  * AMD specific MSR info for Speculative Store Bypass control.
  48  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  49  */
  50 u64 __ro_after_init x86_amd_ls_cfg_base;
  51 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  52
  53 void __init check_bugs(void)
  54 {
  55         identify_boot_cpu();
  56
  57         if (!IS_ENABLED(CONFIG_SMP)) {
  58                 pr_info("CPU: ");
  59                 print_cpu_info(&boot_cpu_data);
  60         }
  61
  62         /*
  63          * Read the SPEC_CTRL MSR to account for reserved bits which may
  64          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  65          * init code as it is not enumerated and depends on the family.
  66          */
  67         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  68                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  69
  70         /* Select the proper spectre mitigation before patching alternatives */
  71         spectre_v2_select_mitigation();
  72
  73         /*
  74          * Select proper mitigation for any exposure to the Speculative Store
  75          * Bypass vulnerability.
  76          */
  77         ssb_select_mitigation();
  78
  79 #ifdef CONFIG_X86_32
  80         /*
  81          * Check whether we are able to run this kernel safely on SMP.
  82          *
  83          * - i386 is no longer supported.
  84          * - In order to run on anything without a TSC, we need to be
  85          *   compiled for a i486.
  86          */
  87         if (boot_cpu_data.x86 < 4)
  88                 panic("Kernel requires i486+ for 'invlpg' and other features");
  89
  90         init_utsname()->machine[1] =
  91                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  92         alternative_instructions();
  93
  94         fpu__init_check_bugs();
  95 #else /* CONFIG_X86_64 */
  96         alternative_instructions();
  97
  98         /*
  99          * Make sure the first 2MB area is not mapped by huge pages
 100          * There are typically fixed size MTRRs in there and overlapping
 101          * MTRRs into large pages causes slow downs.
 102          *
 103          * Right now we don't do that with gbpages because there seems
 104          * very little benefit for that case.
 105          */
 106         if (!direct_gbpages)
 107                 set_memory_4k((unsigned long)__va(0), 1);
 108 #endif
 109 }
 110
 111 /* The kernel command line selection */
 112 enum spectre_v2_mitigation_cmd {
 113         SPECTRE_V2_CMD_NONE,
 114         SPECTRE_V2_CMD_AUTO,
 115         SPECTRE_V2_CMD_FORCE,
 116         SPECTRE_V2_CMD_RETPOLINE,
 117         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 118         SPECTRE_V2_CMD_RETPOLINE_AMD,
 119 };
 120
 121 static const char *spectre_v2_strings[] = {
 122         [SPECTRE_V2_NONE]                       = "Vulnerable",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 125         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 126         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 127 };
 128
 129 #undef pr_fmt
 130 #define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt
 131
 132 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 133         SPECTRE_V2_NONE;
 134
 135 void x86_spec_ctrl_set(u64 val)
 136 {
 137         if (val & x86_spec_ctrl_mask)
 138                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 139         else
 140                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 141 }
 142 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 143
 144 void
 145 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 146 {
 147         struct thread_info *ti = current_thread_info();
 148         u64 msr, host = x86_spec_ctrl_base;
 149
 150         /* Is MSR_SPEC_CTRL implemented ? */
 151         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 152                 /* SSBD controlled in MSR_SPEC_CTRL */
 153                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 154                         host |= ssbd_tif_to_spec_ctrl(ti->flags);
 155
 156                 if (host != guest_spec_ctrl) {
 157                         msr = setguest ? guest_spec_ctrl : host;
 158                         wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 159                 }
 160         }
 161 }
 162 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 163
 164 static void x86_amd_ssb_disable(void)
 165 {
 166         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 167
 168         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 169                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 170         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 171                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 172 }
 173
 174 static void __init spec2_print_if_insecure(const char *reason)
 175 {
 176         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 177                 pr_info("%s\n", reason);
 178 }
 179
 180 static void __init spec2_print_if_secure(const char *reason)
 181 {
 182         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 183                 pr_info("%s\n", reason);
 184 }
 185
 186 static inline bool retp_compiler(void)
 187 {
 188         return __is_defined(RETPOLINE);
 189 }
 190
 191 static inline bool match_option(const char *arg, int arglen, const char *opt)
 192 {
 193         int len = strlen(opt);
 194
 195         return len == arglen && !strncmp(arg, opt, len);
 196 }
 197
 198 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 199 {
 200         char arg[20];
 201         int ret;
 202
 203         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
 204                                   sizeof(arg));
 205         if (ret > 0)  {
 206                 if (match_option(arg, ret, "off")) {
 207                         goto disable;
 208                 } else if (match_option(arg, ret, "on")) {
 209                         spec2_print_if_secure("force enabled on command line.");
 210                         return SPECTRE_V2_CMD_FORCE;
 211                 } else if (match_option(arg, ret, "retpoline")) {
 212                         spec2_print_if_insecure("retpoline selected on command line.");
 213                         return SPECTRE_V2_CMD_RETPOLINE;
 214                 } else if (match_option(arg, ret, "retpoline,amd")) {
 215                         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 216                                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 217                                 return SPECTRE_V2_CMD_AUTO;
 218                         }
 219                         spec2_print_if_insecure("AMD retpoline selected on command line.");
 220                         return SPECTRE_V2_CMD_RETPOLINE_AMD;
 221                 } else if (match_option(arg, ret, "retpoline,generic")) {
 222                         spec2_print_if_insecure("generic retpoline selected on command line.");
 223                         return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
 224                 } else if (match_option(arg, ret, "auto")) {
 225                         return SPECTRE_V2_CMD_AUTO;
 226                 }
 227         }
 228
 229         if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 230                 return SPECTRE_V2_CMD_AUTO;
 231 disable:
 232         spec2_print_if_insecure("disabled on command line.");
 233         return SPECTRE_V2_CMD_NONE;
 234 }
 235
 236 /* Check for Skylake-like CPUs (for RSB handling) */
 237 static bool __init is_skylake_era(void)
 238 {
 239         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 240             boot_cpu_data.x86 == 6) {
 241                 switch (boot_cpu_data.x86_model) {
 242                 case INTEL_FAM6_SKYLAKE_MOBILE:
 243                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 244                 case INTEL_FAM6_SKYLAKE_X:
 245                 case INTEL_FAM6_KABYLAKE_MOBILE:
 246                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 247                         return true;
 248                 }
 249         }
 250         return false;
 251 }
 252
 253 static void __init spectre_v2_select_mitigation(void)
 254 {
 255         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 256         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 257
 258         /*
 259          * If the CPU is not affected and the command line mode is NONE or AUTO
 260          * then nothing to do.
 261          */
 262         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 263             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 264                 return;
 265
 266         switch (cmd) {
 267         case SPECTRE_V2_CMD_NONE:
 268                 return;
 269
 270         case SPECTRE_V2_CMD_FORCE:
 271                 /* FALLTRHU */
 272         case SPECTRE_V2_CMD_AUTO:
 273                 goto retpoline_auto;
 274
 275         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 276                 if (IS_ENABLED(CONFIG_RETPOLINE))
 277                         goto retpoline_amd;
 278                 break;
 279         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 280                 if (IS_ENABLED(CONFIG_RETPOLINE))
 281                         goto retpoline_generic;
 282                 break;
 283         case SPECTRE_V2_CMD_RETPOLINE:
 284                 if (IS_ENABLED(CONFIG_RETPOLINE))
 285                         goto retpoline_auto;
 286                 break;
 287         }
 288         pr_err("kernel not compiled with retpoline; no mitigation available!");
 289         return;
 290
 291 retpoline_auto:
 292         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 293         retpoline_amd:
 294                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 295                         pr_err("LFENCE not serializing. Switching to generic retpoline\n");
 296                         goto retpoline_generic;
 297                 }
 298                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 299                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 300                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 301                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 302         } else {
 303         retpoline_generic:
 304                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 305                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 306                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 307         }
 308
 309         spectre_v2_enabled = mode;
 310         pr_info("%s\n", spectre_v2_strings[mode]);
 311
 312         pr_info("Speculation control IBPB %s IBRS %s",
 313                 ibpb_supported ? "supported" : "not-supported",
 314                 ibrs_supported ? "supported" : "not-supported");
 315
 316         /*
 317          * If we have a full retpoline mode and then disable IBPB in kernel mode
 318          * we do not require both.
 319          */
 320         if (mode == SPECTRE_V2_RETPOLINE_AMD ||
 321             mode == SPECTRE_V2_RETPOLINE_GENERIC)
 322         {
 323                 if (ibrs_supported) {
 324                         pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
 325                         set_ibrs_disabled();
 326                         if (!ibrs_inuse)
 327                                 sysctl_ibrs_enabled = 0;
 328                 }
 329         }
 330
 331         /*
 332          * If neither SMEP or KPTI are available, there is a risk of
 333          * hitting userspace addresses in the RSB after a context switch
 334          * from a shallow call stack to a deeper one. To prevent this fill
 335          * the entire RSB, even when using IBRS.
 336          *
 337          * Skylake era CPUs have a separate issue with *underflow* of the
 338          * RSB, when they will predict 'ret' targets from the generic BTB.
 339          * The proper mitigation for this is IBRS. If IBRS is not supported
 340          * or deactivated in favour of retpolines the RSB fill on context
 341          * switch is required.
 342          */
 343         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 344              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 345                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 346                 pr_info("Filling RSB on context switch\n");
 347         }
 348 }
 349
 350 #undef pr_fmt
 351 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 352
 353 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 354
 355 /* The kernel command line selection */
 356 enum ssb_mitigation_cmd {
 357         SPEC_STORE_BYPASS_CMD_NONE,
 358         SPEC_STORE_BYPASS_CMD_AUTO,
 359         SPEC_STORE_BYPASS_CMD_ON,
 360         SPEC_STORE_BYPASS_CMD_PRCTL,
 361         SPEC_STORE_BYPASS_CMD_SECCOMP,
 362 };
 363
 364 static const char *ssb_strings[] = {
 365         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 366         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 367         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 368         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 369 };
 370
 371 static const struct {
 372         const char *option;
 373         enum ssb_mitigation_cmd cmd;
 374 } ssb_mitigation_options[] = {
 375         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 376         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 377         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 378         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 379         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 380 };
 381
 382 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 383 {
 384         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 385         char arg[20];
 386         int ret, i;
 387
 388         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 389                 return SPEC_STORE_BYPASS_CMD_NONE;
 390         } else {
 391                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 392                                           arg, sizeof(arg));
 393                 if (ret < 0)
 394                         return SPEC_STORE_BYPASS_CMD_AUTO;
 395
 396                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 397                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 398                                 continue;
 399
 400                         cmd = ssb_mitigation_options[i].cmd;
 401                         break;
 402                 }
 403
 404                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 405                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 406                         return SPEC_STORE_BYPASS_CMD_AUTO;
 407                 }
 408         }
 409
 410         return cmd;
 411 }
 412
 413 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 414 {
 415         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 416         enum ssb_mitigation_cmd cmd;
 417
 418         if (!boot_cpu_has(X86_FEATURE_SSBD))
 419                 return mode;
 420
 421         cmd = ssb_parse_cmdline();
 422         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 423             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 424              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 425                 return mode;
 426
 427         switch (cmd) {
 428         case SPEC_STORE_BYPASS_CMD_AUTO:
 429         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 430                 /*
 431                  * Choose prctl+seccomp as the default mode if seccomp is
 432                  * enabled.
 433                  */
 434                 if (IS_ENABLED(CONFIG_SECCOMP))
 435                         mode = SPEC_STORE_BYPASS_SECCOMP;
 436                 else
 437                         mode = SPEC_STORE_BYPASS_PRCTL;
 438                 break;
 439         case SPEC_STORE_BYPASS_CMD_ON:
 440                 mode = SPEC_STORE_BYPASS_DISABLE;
 441                 break;
 442         case SPEC_STORE_BYPASS_CMD_PRCTL:
 443                 mode = SPEC_STORE_BYPASS_PRCTL;
 444                 break;
 445         case SPEC_STORE_BYPASS_CMD_NONE:
 446                 break;
 447         }
 448
 449         /*
 450          * We have three CPU feature flags that are in play here:
 451          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 452          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 453          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 454          */
 455         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 456                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 457                 /*
 458                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 459                  * a completely different MSR and bit dependent on family.
 460                  */
 461                 switch (boot_cpu_data.x86_vendor) {
 462                 case X86_VENDOR_INTEL:
 463                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 464                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 465                         x86_spec_ctrl_set(SPEC_CTRL_SSBD);
 466                         break;
 467                 case X86_VENDOR_AMD:
 468                         x86_amd_ssb_disable();
 469                         break;
 470                 }
 471         }
 472
 473         return mode;
 474 }
 475
 476 static void ssb_select_mitigation(void)
 477 {
 478         ssb_mode = __ssb_select_mitigation();
 479
 480         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 481                 pr_info("%s\n", ssb_strings[ssb_mode]);
 482 }
 483
 484 #undef pr_fmt
 485 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 486
 487 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 488 {
 489         bool update;
 490
 491         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 492             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 493                 return -ENXIO;
 494
 495         switch (ctrl) {
 496         case PR_SPEC_ENABLE:
 497                 /* If speculation is force disabled, enable is not allowed */
 498                 if (task_spec_ssb_force_disable(task))
 499                         return -EPERM;
 500                 task_clear_spec_ssb_disable(task);
 501                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 502                 break;
 503         case PR_SPEC_DISABLE:
 504                 task_set_spec_ssb_disable(task);
 505                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 506                 break;
 507         case PR_SPEC_FORCE_DISABLE:
 508                 task_set_spec_ssb_disable(task);
 509                 task_set_spec_ssb_force_disable(task);
 510                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 511                 break;
 512         default:
 513                 return -ERANGE;
 514         }
 515
 516         /*
 517          * If being set on non-current task, delay setting the CPU
 518          * mitigation until it is next scheduled.
 519          */
 520         if (task == current && update)
 521                 speculative_store_bypass_update_current();
 522
 523         return 0;
 524 }
 525
 526 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 527                              unsigned long ctrl)
 528 {
 529         switch (which) {
 530         case PR_SPEC_STORE_BYPASS:
 531                 return ssb_prctl_set(task, ctrl);
 532         default:
 533                 return -ENODEV;
 534         }
 535 }
 536
 537 #ifdef CONFIG_SECCOMP
 538 void arch_seccomp_spec_mitigate(struct task_struct *task)
 539 {
 540         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 541                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 542 }
 543 #endif
 544
 545 static int ssb_prctl_get(struct task_struct *task)
 546 {
 547         switch (ssb_mode) {
 548         case SPEC_STORE_BYPASS_DISABLE:
 549                 return PR_SPEC_DISABLE;
 550         case SPEC_STORE_BYPASS_SECCOMP:
 551         case SPEC_STORE_BYPASS_PRCTL:
 552                 if (task_spec_ssb_force_disable(task))
 553                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 554                 if (task_spec_ssb_disable(task))
 555                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 556                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 557         default:
 558                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 559                         return PR_SPEC_ENABLE;
 560                 return PR_SPEC_NOT_AFFECTED;
 561         }
 562 }
 563
 564 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 565 {
 566         switch (which) {
 567         case PR_SPEC_STORE_BYPASS:
 568                 return ssb_prctl_get(task);
 569         default:
 570                 return -ENODEV;
 571         }
 572 }
 573
 574 void x86_spec_ctrl_setup_ap(void)
 575 {
 576         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 577                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 578
 579         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 580                 x86_amd_ssb_disable();
 581 }
 582
 583 #ifdef CONFIG_SYSFS
 584 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 585                                char *buf, unsigned int bug)
 586 {
 587         if (!boot_cpu_has_bug(bug))
 588                 return sprintf(buf, "Not affected\n");
 589
 590         switch (bug) {
 591         case X86_BUG_CPU_MELTDOWN:
 592                 if (boot_cpu_has(X86_FEATURE_PTI))
 593                         return sprintf(buf, "Mitigation: PTI\n");
 594                 break;
 595
 596         case X86_BUG_SPECTRE_V1:
 597                 if (osb_is_enabled)
 598                         return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
 599
 600         case X86_BUG_SPECTRE_V2:
 601                 return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
 602
 603         case X86_BUG_SPEC_STORE_BYPASS:
 604                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 605
 606         default:
 607                 break;
 608         }
 609
 610         return sprintf(buf, "Vulnerable\n");
 611 }
 612
 613 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
 614                           char *buf)
 615 {
 616         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 617 }
 618
 619 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 620                             char *buf)
 621 {
 622         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 623 }
 624
 625 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 626                             char *buf)
 627 {
 628         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 629 }
 630
 631 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 632 {
 633         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 634 }
 635 #endif