2 * Copyright (C) 1994 Linus Torvalds
4 * Cyrix stuff, June 1998 by:
5 * - Rafael R. Reilova (moved everything from head.S),
6 * <rreilova@ececs.uc.edu>
7 * - Channing Corn (tests & fixes),
8 * - Andrew D. Balsa (code cleanup).
10 #include <linux/init.h>
11 #include <linux/utsname.h>
12 #include <linux/cpu.h>
13 #include <linux/smp.h>
14 #include <linux/nospec.h>
15 #include <linux/prctl.h>
17 #include <asm/spec-ctrl.h>
18 #include <asm/cmdline.h>
20 #include <asm/processor.h>
21 #include <asm/processor-flags.h>
22 #include <asm/fpu/internal.h>
24 #include <asm/paravirt.h>
25 #include <asm/alternative.h>
26 #include <asm/pgtable.h>
27 #include <asm/set_memory.h>
28 #include <asm/intel-family.h>
30 static void __init
spectre_v2_select_mitigation(void);
31 static void __init
ssb_select_mitigation(void);
34 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
35 * writes to SPEC_CTRL contain whatever reserved bits have been set.
37 u64 __ro_after_init x86_spec_ctrl_base
;
40 * The vendor and possibly platform specific bits which can be modified in
43 static u64 __ro_after_init x86_spec_ctrl_mask
= ~SPEC_CTRL_IBRS
;
46 * AMD specific MSR info for Speculative Store Bypass control.
47 * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
49 u64 __ro_after_init x86_amd_ls_cfg_base
;
50 u64 __ro_after_init x86_amd_ls_cfg_rds_mask
;
52 void __init
check_bugs(void)
56 if (!IS_ENABLED(CONFIG_SMP
)) {
58 print_cpu_info(&boot_cpu_data
);
62 * Read the SPEC_CTRL MSR to account for reserved bits which may
63 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
64 * init code as it is not enumerated and depends on the family.
67 rdmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
);
69 /* Select the proper spectre mitigation before patching alternatives */
70 spectre_v2_select_mitigation();
73 * Select proper mitigation for any exposure to the Speculative Store
74 * Bypass vulnerability.
76 ssb_select_mitigation();
80 * Check whether we are able to run this kernel safely on SMP.
82 * - i386 is no longer supported.
83 * - In order to run on anything without a TSC, we need to be
84 * compiled for a i486.
86 if (boot_cpu_data
.x86
< 4)
87 panic("Kernel requires i486+ for 'invlpg' and other features");
89 init_utsname()->machine
[1] =
90 '0' + (boot_cpu_data
.x86
> 6 ? 6 : boot_cpu_data
.x86
);
91 alternative_instructions();
93 fpu__init_check_bugs();
94 #else /* CONFIG_X86_64 */
95 alternative_instructions();
98 * Make sure the first 2MB area is not mapped by huge pages
99 * There are typically fixed size MTRRs in there and overlapping
100 * MTRRs into large pages causes slow downs.
102 * Right now we don't do that with gbpages because there seems
103 * very little benefit for that case.
106 set_memory_4k((unsigned long)__va(0), 1);
110 /* The kernel command line selection */
111 enum spectre_v2_mitigation_cmd
{
114 SPECTRE_V2_CMD_FORCE
,
115 SPECTRE_V2_CMD_RETPOLINE
,
116 SPECTRE_V2_CMD_RETPOLINE_GENERIC
,
117 SPECTRE_V2_CMD_RETPOLINE_AMD
,
120 static const char *spectre_v2_strings
[] = {
121 [SPECTRE_V2_NONE
] = "Vulnerable",
122 [SPECTRE_V2_RETPOLINE_MINIMAL
] = "Vulnerable: Minimal generic ASM retpoline",
123 [SPECTRE_V2_RETPOLINE_MINIMAL_AMD
] = "Vulnerable: Minimal AMD ASM retpoline",
124 [SPECTRE_V2_RETPOLINE_GENERIC
] = "Mitigation: Full generic retpoline",
125 [SPECTRE_V2_RETPOLINE_AMD
] = "Mitigation: Full AMD retpoline",
129 #define pr_fmt(fmt) "Spectre V2 mitigation: " fmt
131 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init
=
134 void x86_spec_ctrl_set(u64 val
)
136 if (val
& x86_spec_ctrl_mask
)
137 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val
);
139 wrmsrl(MSR_IA32_SPEC_CTRL
, x86_spec_ctrl_base
| val
);
141 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set
);
143 u64
x86_spec_ctrl_get_default(void)
145 u64 msrval
= x86_spec_ctrl_base
;
147 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
148 msrval
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
151 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default
);
153 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl
)
155 u64 host
= x86_spec_ctrl_base
;
160 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
161 host
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
163 if (host
!= guest_spec_ctrl
)
164 wrmsrl(MSR_IA32_SPEC_CTRL
, guest_spec_ctrl
);
166 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest
);
168 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl
)
170 u64 host
= x86_spec_ctrl_base
;
175 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
176 host
|= rds_tif_to_spec_ctrl(current_thread_info()->flags
);
178 if (host
!= guest_spec_ctrl
)
179 wrmsrl(MSR_IA32_SPEC_CTRL
, host
);
181 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host
);
183 static void x86_amd_rds_enable(void)
185 u64 msrval
= x86_amd_ls_cfg_base
| x86_amd_ls_cfg_rds_mask
;
187 if (boot_cpu_has(X86_FEATURE_AMD_RDS
))
188 wrmsrl(MSR_AMD64_LS_CFG
, msrval
);
191 static void __init
spec2_print_if_insecure(const char *reason
)
193 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
194 pr_info("%s\n", reason
);
197 static void __init
spec2_print_if_secure(const char *reason
)
199 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
))
200 pr_info("%s\n", reason
);
203 static inline bool retp_compiler(void)
205 return __is_defined(RETPOLINE
);
208 static inline bool match_option(const char *arg
, int arglen
, const char *opt
)
210 int len
= strlen(opt
);
212 return len
== arglen
&& !strncmp(arg
, opt
, len
);
215 static enum spectre_v2_mitigation_cmd __init
spectre_v2_parse_cmdline(void)
220 ret
= cmdline_find_option(boot_command_line
, "spectre_v2", arg
,
223 if (match_option(arg
, ret
, "off")) {
225 } else if (match_option(arg
, ret
, "on")) {
226 spec2_print_if_secure("force enabled on command line.");
227 return SPECTRE_V2_CMD_FORCE
;
228 } else if (match_option(arg
, ret
, "retpoline")) {
229 spec2_print_if_insecure("retpoline selected on command line.");
230 return SPECTRE_V2_CMD_RETPOLINE
;
231 } else if (match_option(arg
, ret
, "retpoline,amd")) {
232 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
) {
233 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
234 return SPECTRE_V2_CMD_AUTO
;
236 spec2_print_if_insecure("AMD retpoline selected on command line.");
237 return SPECTRE_V2_CMD_RETPOLINE_AMD
;
238 } else if (match_option(arg
, ret
, "retpoline,generic")) {
239 spec2_print_if_insecure("generic retpoline selected on command line.");
240 return SPECTRE_V2_CMD_RETPOLINE_GENERIC
;
241 } else if (match_option(arg
, ret
, "auto")) {
242 return SPECTRE_V2_CMD_AUTO
;
246 if (!cmdline_find_option_bool(boot_command_line
, "nospectre_v2"))
247 return SPECTRE_V2_CMD_AUTO
;
249 spec2_print_if_insecure("disabled on command line.");
250 return SPECTRE_V2_CMD_NONE
;
253 /* Check for Skylake-like CPUs (for RSB handling) */
254 static bool __init
is_skylake_era(void)
256 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
257 boot_cpu_data
.x86
== 6) {
258 switch (boot_cpu_data
.x86_model
) {
259 case INTEL_FAM6_SKYLAKE_MOBILE
:
260 case INTEL_FAM6_SKYLAKE_DESKTOP
:
261 case INTEL_FAM6_SKYLAKE_X
:
262 case INTEL_FAM6_KABYLAKE_MOBILE
:
263 case INTEL_FAM6_KABYLAKE_DESKTOP
:
270 static void __init
spectre_v2_select_mitigation(void)
272 enum spectre_v2_mitigation_cmd cmd
= spectre_v2_parse_cmdline();
273 enum spectre_v2_mitigation mode
= SPECTRE_V2_NONE
;
276 * If the CPU is not affected and the command line mode is NONE or AUTO
277 * then nothing to do.
279 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2
) &&
280 (cmd
== SPECTRE_V2_CMD_NONE
|| cmd
== SPECTRE_V2_CMD_AUTO
))
284 case SPECTRE_V2_CMD_NONE
:
287 case SPECTRE_V2_CMD_FORCE
:
289 case SPECTRE_V2_CMD_AUTO
:
292 case SPECTRE_V2_CMD_RETPOLINE_AMD
:
293 if (IS_ENABLED(CONFIG_RETPOLINE
))
296 case SPECTRE_V2_CMD_RETPOLINE_GENERIC
:
297 if (IS_ENABLED(CONFIG_RETPOLINE
))
298 goto retpoline_generic
;
300 case SPECTRE_V2_CMD_RETPOLINE
:
301 if (IS_ENABLED(CONFIG_RETPOLINE
))
305 pr_err("kernel not compiled with retpoline; no mitigation available!");
309 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) {
311 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
)) {
312 pr_err("LFENCE not serializing. Switching to generic retpoline\n");
313 goto retpoline_generic
;
315 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD
:
316 SPECTRE_V2_RETPOLINE_MINIMAL_AMD
;
317 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD
);
318 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
321 mode
= retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC
:
322 SPECTRE_V2_RETPOLINE_MINIMAL
;
323 setup_force_cpu_cap(X86_FEATURE_RETPOLINE
);
326 spectre_v2_enabled
= mode
;
327 pr_info("%s\n", spectre_v2_strings
[mode
]);
329 pr_info("Speculation control IBPB %s IBRS %s",
330 ibpb_supported
? "supported" : "not-supported",
331 ibrs_supported
? "supported" : "not-supported");
334 * If we have a full retpoline mode and then disable IBPB in kernel mode
335 * we do not require both.
337 if (mode
== SPECTRE_V2_RETPOLINE_AMD
||
338 mode
== SPECTRE_V2_RETPOLINE_GENERIC
)
340 if (ibrs_supported
) {
341 pr_info("Retpoline compiled kernel. Defaulting IBRS to disabled");
344 sysctl_ibrs_enabled
= 0;
349 * If neither SMEP or KPTI are available, there is a risk of
350 * hitting userspace addresses in the RSB after a context switch
351 * from a shallow call stack to a deeper one. To prevent this fill
352 * the entire RSB, even when using IBRS.
354 * Skylake era CPUs have a separate issue with *underflow* of the
355 * RSB, when they will predict 'ret' targets from the generic BTB.
356 * The proper mitigation for this is IBRS. If IBRS is not supported
357 * or deactivated in favour of retpolines the RSB fill on context
358 * switch is required.
360 if ((!boot_cpu_has(X86_FEATURE_PTI
) &&
361 !boot_cpu_has(X86_FEATURE_SMEP
)) || is_skylake_era()) {
362 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW
);
363 pr_info("Filling RSB on context switch\n");
368 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
370 static enum ssb_mitigation ssb_mode __ro_after_init
= SPEC_STORE_BYPASS_NONE
;
372 /* The kernel command line selection */
373 enum ssb_mitigation_cmd
{
374 SPEC_STORE_BYPASS_CMD_NONE
,
375 SPEC_STORE_BYPASS_CMD_AUTO
,
376 SPEC_STORE_BYPASS_CMD_ON
,
377 SPEC_STORE_BYPASS_CMD_PRCTL
,
380 static const char *ssb_strings
[] = {
381 [SPEC_STORE_BYPASS_NONE
] = "Vulnerable",
382 [SPEC_STORE_BYPASS_DISABLE
] = "Mitigation: Speculative Store Bypass disabled",
383 [SPEC_STORE_BYPASS_PRCTL
] = "Mitigation: Speculative Store Bypass disabled via prctl"
386 static const struct {
388 enum ssb_mitigation_cmd cmd
;
389 } ssb_mitigation_options
[] = {
390 { "auto", SPEC_STORE_BYPASS_CMD_AUTO
}, /* Platform decides */
391 { "on", SPEC_STORE_BYPASS_CMD_ON
}, /* Disable Speculative Store Bypass */
392 { "off", SPEC_STORE_BYPASS_CMD_NONE
}, /* Don't touch Speculative Store Bypass */
393 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL
}, /* Disable Speculative Store Bypass via prctl */
396 static enum ssb_mitigation_cmd __init
ssb_parse_cmdline(void)
398 enum ssb_mitigation_cmd cmd
= SPEC_STORE_BYPASS_CMD_AUTO
;
402 if (cmdline_find_option_bool(boot_command_line
, "nospec_store_bypass_disable")) {
403 return SPEC_STORE_BYPASS_CMD_NONE
;
405 ret
= cmdline_find_option(boot_command_line
, "spec_store_bypass_disable",
408 return SPEC_STORE_BYPASS_CMD_AUTO
;
410 for (i
= 0; i
< ARRAY_SIZE(ssb_mitigation_options
); i
++) {
411 if (!match_option(arg
, ret
, ssb_mitigation_options
[i
].option
))
414 cmd
= ssb_mitigation_options
[i
].cmd
;
418 if (i
>= ARRAY_SIZE(ssb_mitigation_options
)) {
419 pr_err("unknown option (%s). Switching to AUTO select\n", arg
);
420 return SPEC_STORE_BYPASS_CMD_AUTO
;
427 static enum ssb_mitigation_cmd __init
__ssb_select_mitigation(void)
429 enum ssb_mitigation mode
= SPEC_STORE_BYPASS_NONE
;
430 enum ssb_mitigation_cmd cmd
;
432 if (!boot_cpu_has(X86_FEATURE_RDS
))
435 cmd
= ssb_parse_cmdline();
436 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
) &&
437 (cmd
== SPEC_STORE_BYPASS_CMD_NONE
||
438 cmd
== SPEC_STORE_BYPASS_CMD_AUTO
))
442 case SPEC_STORE_BYPASS_CMD_AUTO
:
443 /* Choose prctl as the default mode */
444 mode
= SPEC_STORE_BYPASS_PRCTL
;
446 case SPEC_STORE_BYPASS_CMD_ON
:
447 mode
= SPEC_STORE_BYPASS_DISABLE
;
449 case SPEC_STORE_BYPASS_CMD_PRCTL
:
450 mode
= SPEC_STORE_BYPASS_PRCTL
;
452 case SPEC_STORE_BYPASS_CMD_NONE
:
457 * We have three CPU feature flags that are in play here:
458 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
459 * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
460 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
462 if (mode
== SPEC_STORE_BYPASS_DISABLE
) {
463 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE
);
465 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
466 * a completely different MSR and bit dependent on family.
468 switch (boot_cpu_data
.x86_vendor
) {
469 case X86_VENDOR_INTEL
:
470 x86_spec_ctrl_base
|= SPEC_CTRL_RDS
;
471 x86_spec_ctrl_mask
&= ~SPEC_CTRL_RDS
;
472 x86_spec_ctrl_set(SPEC_CTRL_RDS
);
475 x86_amd_rds_enable();
483 static void ssb_select_mitigation()
485 ssb_mode
= __ssb_select_mitigation();
487 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
488 pr_info("%s\n", ssb_strings
[ssb_mode
]);
493 static int ssb_prctl_set(struct task_struct
*task
, unsigned long ctrl
)
497 if (ssb_mode
!= SPEC_STORE_BYPASS_PRCTL
)
502 /* If speculation is force disabled, enable is not allowed */
503 if (task_spec_ssb_force_disable(task
))
505 task_clear_spec_ssb_disable(task
);
506 update
= test_and_clear_tsk_thread_flag(task
, TIF_RDS
);
508 case PR_SPEC_DISABLE
:
509 task_set_spec_ssb_disable(task
);
510 update
= !test_and_set_tsk_thread_flag(task
, TIF_RDS
);
512 case PR_SPEC_FORCE_DISABLE
:
513 task_set_spec_ssb_disable(task
);
514 task_set_spec_ssb_force_disable(task
);
515 update
= !test_and_set_tsk_thread_flag(task
, TIF_RDS
);
522 * If being set on non-current task, delay setting the CPU
523 * mitigation until it is next scheduled.
525 if (task
== current
&& update
)
526 speculative_store_bypass_update();
531 static int ssb_prctl_get(struct task_struct
*task
)
534 case SPEC_STORE_BYPASS_DISABLE
:
535 return PR_SPEC_DISABLE
;
536 case SPEC_STORE_BYPASS_PRCTL
:
537 if (task_spec_ssb_force_disable(task
))
538 return PR_SPEC_PRCTL
| PR_SPEC_FORCE_DISABLE
;
539 if (task_spec_ssb_disable(task
))
540 return PR_SPEC_PRCTL
| PR_SPEC_DISABLE
;
541 return PR_SPEC_PRCTL
| PR_SPEC_ENABLE
;
543 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS
))
544 return PR_SPEC_ENABLE
;
545 return PR_SPEC_NOT_AFFECTED
;
549 int arch_prctl_spec_ctrl_set(struct task_struct
*task
, unsigned long which
,
553 case PR_SPEC_STORE_BYPASS
:
554 return ssb_prctl_set(task
, ctrl
);
560 int arch_prctl_spec_ctrl_get(struct task_struct
*task
, unsigned long which
)
563 case PR_SPEC_STORE_BYPASS
:
564 return ssb_prctl_get(task
);
570 void x86_spec_ctrl_setup_ap(void)
573 x86_spec_ctrl_set(x86_spec_ctrl_base
& ~x86_spec_ctrl_mask
);
575 if (ssb_mode
== SPEC_STORE_BYPASS_DISABLE
)
576 x86_amd_rds_enable();
580 ssize_t
cpu_show_common(struct device
*dev
, struct device_attribute
*attr
,
581 char *buf
, unsigned int bug
)
583 if (!boot_cpu_has_bug(bug
))
584 return sprintf(buf
, "Not affected\n");
587 case X86_BUG_CPU_MELTDOWN
:
588 if (boot_cpu_has(X86_FEATURE_PTI
))
589 return sprintf(buf
, "Mitigation: PTI\n");
592 case X86_BUG_SPECTRE_V1
:
594 return sprintf(buf
, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
596 case X86_BUG_SPECTRE_V2
:
597 return sprintf(buf
, "%s%s\n", spectre_v2_strings
[spectre_v2_enabled
], ibpb_inuse
? ", IBPB (Intel v4)" : "");
599 case X86_BUG_SPEC_STORE_BYPASS
:
600 return sprintf(buf
, "%s\n", ssb_strings
[ssb_mode
]);
606 return sprintf(buf
, "Vulnerable\n");
609 ssize_t
cpu_show_meltdown(struct device
*dev
, struct device_attribute
*attr
,
612 return cpu_show_common(dev
, attr
, buf
, X86_BUG_CPU_MELTDOWN
);
615 ssize_t
cpu_show_spectre_v1(struct device
*dev
, struct device_attribute
*attr
,
618 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V1
);
621 ssize_t
cpu_show_spectre_v2(struct device
*dev
, struct device_attribute
*attr
,
624 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPECTRE_V2
);
627 ssize_t
cpu_show_spec_store_bypass(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
629 return cpu_show_common(dev
, attr
, buf
, X86_BUG_SPEC_STORE_BYPASS
);