arch/x86/kernel/cpu/bugs.c

   1 /*
   2  *  Copyright (C) 1994  Linus Torvalds
   3  *
   4  *  Cyrix stuff, June 1998 by:
   5  *      - Rafael R. Reilova (moved everything from head.S),
   6  *        <rreilova@ececs.uc.edu>
   7  *      - Channing Corn (tests & fixes),
   8  *      - Andrew D. Balsa (code cleanup).
   9  */
  10 #include <linux/init.h>
  11 #include <linux/utsname.h>
  12 #include <linux/cpu.h>
  13 #include <linux/smp.h>
  14 #include <linux/nospec.h>
  15 #include <linux/prctl.h>
  16
  17 #include <asm/spec-ctrl.h>
  18 #include <asm/cmdline.h>
  19 #include <asm/bugs.h>
  20 #include <asm/processor.h>
  21 #include <asm/processor-flags.h>
  22 #include <asm/fpu/internal.h>
  23 #include <asm/msr.h>
  24 #include <asm/paravirt.h>
  25 #include <asm/alternative.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/set_memory.h>
  28 #include <asm/intel-family.h>
  29
  30 static void __init spectre_v2_select_mitigation(void);
  31 static void __init ssb_select_mitigation(void);
  32
  33 /*
  34  * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
  35  * writes to SPEC_CTRL contain whatever reserved bits have been set.
  36  */
  37 u64 __ro_after_init x86_spec_ctrl_base;
  38
  39 /*
  40  * The vendor and possibly platform specific bits which can be modified in
  41  * x86_spec_ctrl_base.
  42  */
  43 static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
  44
  45 /*
  46  * AMD specific MSR info for Speculative Store Bypass control.
  47  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  48  */
  49 u64 __ro_after_init x86_amd_ls_cfg_base;
  50 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
  51
  52 void __init check_bugs(void)
  53 {
  54         identify_boot_cpu();
  55
  56         if (!IS_ENABLED(CONFIG_SMP)) {
  57                 pr_info("CPU: ");
  58                 print_cpu_info(&boot_cpu_data);
  59         }
  60
  61         /*
  62          * Read the SPEC_CTRL MSR to account for reserved bits which may
  63          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
  64          * init code as it is not enumerated and depends on the family.
  65          */
  66         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  67                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
  68
  69         /* Select the proper spectre mitigation before patching alternatives */
  70         spectre_v2_select_mitigation();
  71
  72         /*
  73          * Select proper mitigation for any exposure to the Speculative Store
  74          * Bypass vulnerability.
  75          */
  76         ssb_select_mitigation();
  77
  78 #ifdef CONFIG_X86_32
  79         /*
  80          * Check whether we are able to run this kernel safely on SMP.
  81          *
  82          * - i386 is no longer supported.
  83          * - In order to run on anything without a TSC, we need to be
  84          *   compiled for a i486.
  85          */
  86         if (boot_cpu_data.x86 < 4)
  87                 panic("Kernel requires i486+ for 'invlpg' and other features");
  88
  89         init_utsname()->machine[1] =
  90                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
  91         alternative_instructions();
  92
  93         fpu__init_check_bugs();
  94 #else /* CONFIG_X86_64 */
  95         alternative_instructions();
  96
  97         /*
  98          * Make sure the first 2MB area is not mapped by huge pages
  99          * There are typically fixed size MTRRs in there and overlapping
 100          * MTRRs into large pages causes slow downs.
 101          *
 102          * Right now we don't do that with gbpages because there seems
 103          * very little benefit for that case.
 104          */
 105         if (!direct_gbpages)
 106                 set_memory_4k((unsigned long)__va(0), 1);
 107 #endif
 108 }
 109
 110 /* The kernel command line selection */
 111 enum spectre_v2_mitigation_cmd {
 112         SPECTRE_V2_CMD_NONE,
 113         SPECTRE_V2_CMD_AUTO,
 114         SPECTRE_V2_CMD_FORCE,
 115         SPECTRE_V2_CMD_RETPOLINE,
 116         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
 117         SPECTRE_V2_CMD_RETPOLINE_AMD,
 118 };
 119
 120 static const char *spectre_v2_strings[] = {
 121         [SPECTRE_V2_NONE]                       = "Vulnerable",
 122         [SPECTRE_V2_RETPOLINE_MINIMAL]          = "Vulnerable: Minimal generic ASM retpoline",
 123         [SPECTRE_V2_RETPOLINE_MINIMAL_AMD]      = "Vulnerable: Minimal AMD ASM retpoline",
 124         [SPECTRE_V2_RETPOLINE_GENERIC]          = "Mitigation: Full generic retpoline",
 125         [SPECTRE_V2_RETPOLINE_AMD]              = "Mitigation: Full AMD retpoline",
 126 };
 127
 128 #undef pr_fmt
 129 #define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt
 130
 131 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 132         SPECTRE_V2_NONE;
 133
 134 void x86_spec_ctrl_set(u64 val)
 135 {
 136         if (val & x86_spec_ctrl_mask)
 137                 WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
 138         else
 139                 wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
 140 }
 141 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
 142
 143 u64 x86_spec_ctrl_get_default(void)
 144 {
 145         u64 msrval = x86_spec_ctrl_base;
 146
 147         if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
 148                 msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 149         return msrval;
 150 }
 151 EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
 152
 153 void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
 154 {
 155         u64 host = x86_spec_ctrl_base;
 156
 157         /* Is MSR_SPEC_CTRL implemented ? */
 158         if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 159                 return;
 160
 161         /* SSBD controlled in MSR_SPEC_CTRL */
 162         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 163                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 164
 165         if (host != guest_spec_ctrl)
 166                 wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
 167 }
 168 EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
 169
 170 void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
 171 {
 172         u64 host = x86_spec_ctrl_base;
 173
 174         /* Is MSR_SPEC_CTRL implemented ? */
 175         if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 176                 return;
 177
 178         /* SSBD controlled in MSR_SPEC_CTRL */
 179         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
 180                 host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
 181
 182         if (host != guest_spec_ctrl)
 183                 wrmsrl(MSR_IA32_SPEC_CTRL, host);
 184 }
 185 EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
 186
 187 static void x86_amd_ssb_disable(void)
 188 {
 189         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 190
 191         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 192                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 193 }
 194
 195 static void __init spec2_print_if_insecure(const char *reason)
 196 {
 197         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 198                 pr_info("%s\n", reason);
 199 }
 200
 201 static void __init spec2_print_if_secure(const char *reason)
 202 {
 203         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
 204                 pr_info("%s\n", reason);
 205 }
 206
 207 static inline bool retp_compiler(void)
 208 {
 209         return __is_defined(RETPOLINE);
 210 }
 211
 212 static inline bool match_option(const char *arg, int arglen, const char *opt)
 213 {
 214         int len = strlen(opt);
 215
 216         return len == arglen && !strncmp(arg, opt, len);
 217 }
 218
 219 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
 220 {
 221         char arg[20];
 222         int ret;
 223
 224         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
 225                                   sizeof(arg));
 226         if (ret > 0)  {
 227                 if (match_option(arg, ret, "off")) {
 228                         goto disable;
 229                 } else if (match_option(arg, ret, "on")) {
 230                         spec2_print_if_secure("force enabled on command line.");
 231                         return SPECTRE_V2_CMD_FORCE;
 232                 } else if (match_option(arg, ret, "retpoline")) {
 233                         spec2_print_if_insecure("retpoline selected on command line.");
 234                         return SPECTRE_V2_CMD_RETPOLINE;
 235                 } else if (match_option(arg, ret, "retpoline,amd")) {
 236                         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 237                                 pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
 238                                 return SPECTRE_V2_CMD_AUTO;
 239                         }
 240                         spec2_print_if_insecure("AMD retpoline selected on command line.");
 241                         return SPECTRE_V2_CMD_RETPOLINE_AMD;
 242                 } else if (match_option(arg, ret, "retpoline,generic")) {
 243                         spec2_print_if_insecure("generic retpoline selected on command line.");
 244                         return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
 245                 } else if (match_option(arg, ret, "auto")) {
 246                         return SPECTRE_V2_CMD_AUTO;
 247                 }
 248         }
 249
 250         if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
 251                 return SPECTRE_V2_CMD_AUTO;
 252 disable:
 253         spec2_print_if_insecure("disabled on command line.");
 254         return SPECTRE_V2_CMD_NONE;
 255 }
 256
 257 /* Check for Skylake-like CPUs (for RSB handling) */
 258 static bool __init is_skylake_era(void)
 259 {
 260         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 261             boot_cpu_data.x86 == 6) {
 262                 switch (boot_cpu_data.x86_model) {
 263                 case INTEL_FAM6_SKYLAKE_MOBILE:
 264                 case INTEL_FAM6_SKYLAKE_DESKTOP:
 265                 case INTEL_FAM6_SKYLAKE_X:
 266                 case INTEL_FAM6_KABYLAKE_MOBILE:
 267                 case INTEL_FAM6_KABYLAKE_DESKTOP:
 268                         return true;
 269                 }
 270         }
 271         return false;
 272 }
 273
 274 static void __init spectre_v2_select_mitigation(void)
 275 {
 276         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
 277         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
 278
 279         /*
 280          * If the CPU is not affected and the command line mode is NONE or AUTO
 281          * then nothing to do.
 282          */
 283         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
 284             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
 285                 return;
 286
 287         switch (cmd) {
 288         case SPECTRE_V2_CMD_NONE:
 289                 return;
 290
 291         case SPECTRE_V2_CMD_FORCE:
 292                 /* FALLTRHU */
 293         case SPECTRE_V2_CMD_AUTO:
 294                 goto retpoline_auto;
 295
 296         case SPECTRE_V2_CMD_RETPOLINE_AMD:
 297                 if (IS_ENABLED(CONFIG_RETPOLINE))
 298                         goto retpoline_amd;
 299                 break;
 300         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
 301                 if (IS_ENABLED(CONFIG_RETPOLINE))
 302                         goto retpoline_generic;
 303                 break;
 304         case SPECTRE_V2_CMD_RETPOLINE:
 305                 if (IS_ENABLED(CONFIG_RETPOLINE))
 306                         goto retpoline_auto;
 307                 break;
 308         }
 309         pr_err("kernel not compiled with retpoline; no mitigation available!");
 310         return;
 311
 312 retpoline_auto:
 313         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
 314         retpoline_amd:
 315                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
 316                         pr_err("LFENCE not serializing. Switching to generic retpoline\n");
 317                         goto retpoline_generic;
 318                 }
 319                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
 320                                          SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
 321                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
 322                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 323         } else {
 324         retpoline_generic:
 325                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
 326                                          SPECTRE_V2_RETPOLINE_MINIMAL;
 327                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
 328         }
 329
 330         spectre_v2_enabled = mode;
 331         pr_info("%s\n", spectre_v2_strings[mode]);
 332
 333         pr_info("Speculation control IBPB %s IBRS %s",
 334                 ibpb_supported ? "supported" : "not-supported",
 335                 ibrs_supported ? "supported" : "not-supported");
 336
 337         /*
 338          * If we have a full retpoline mode and then disable IBPB in kernel mode
 339          * we do not require both.
 340          */
 341         if (mode == SPECTRE_V2_RETPOLINE_AMD ||
 342             mode == SPECTRE_V2_RETPOLINE_GENERIC)
 343         {
 344                 if (ibrs_supported) {
 345                         pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
 346                         set_ibrs_disabled();
 347                         if (!ibrs_inuse)
 348                                 sysctl_ibrs_enabled = 0;
 349                 }
 350         }
 351
 352         /*
 353          * If neither SMEP or KPTI are available, there is a risk of
 354          * hitting userspace addresses in the RSB after a context switch
 355          * from a shallow call stack to a deeper one. To prevent this fill
 356          * the entire RSB, even when using IBRS.
 357          *
 358          * Skylake era CPUs have a separate issue with *underflow* of the
 359          * RSB, when they will predict 'ret' targets from the generic BTB.
 360          * The proper mitigation for this is IBRS. If IBRS is not supported
 361          * or deactivated in favour of retpolines the RSB fill on context
 362          * switch is required.
 363          */
 364         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
 365              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
 366                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
 367                 pr_info("Filling RSB on context switch\n");
 368         }
 369 }
 370
 371 #undef pr_fmt
 372 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
 373
 374 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
 375
 376 /* The kernel command line selection */
 377 enum ssb_mitigation_cmd {
 378         SPEC_STORE_BYPASS_CMD_NONE,
 379         SPEC_STORE_BYPASS_CMD_AUTO,
 380         SPEC_STORE_BYPASS_CMD_ON,
 381         SPEC_STORE_BYPASS_CMD_PRCTL,
 382         SPEC_STORE_BYPASS_CMD_SECCOMP,
 383 };
 384
 385 static const char *ssb_strings[] = {
 386         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
 387         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
 388         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
 389         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
 390 };
 391
 392 static const struct {
 393         const char *option;
 394         enum ssb_mitigation_cmd cmd;
 395 } ssb_mitigation_options[] = {
 396         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
 397         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
 398         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
 399         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
 400         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
 401 };
 402
 403 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
 404 {
 405         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
 406         char arg[20];
 407         int ret, i;
 408
 409         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
 410                 return SPEC_STORE_BYPASS_CMD_NONE;
 411         } else {
 412                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
 413                                           arg, sizeof(arg));
 414                 if (ret < 0)
 415                         return SPEC_STORE_BYPASS_CMD_AUTO;
 416
 417                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
 418                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
 419                                 continue;
 420
 421                         cmd = ssb_mitigation_options[i].cmd;
 422                         break;
 423                 }
 424
 425                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
 426                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
 427                         return SPEC_STORE_BYPASS_CMD_AUTO;
 428                 }
 429         }
 430
 431         return cmd;
 432 }
 433
 434 static enum ssb_mitigation __init __ssb_select_mitigation(void)
 435 {
 436         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
 437         enum ssb_mitigation_cmd cmd;
 438
 439         if (!boot_cpu_has(X86_FEATURE_SSBD))
 440                 return mode;
 441
 442         cmd = ssb_parse_cmdline();
 443         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
 444             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
 445              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
 446                 return mode;
 447
 448         switch (cmd) {
 449         case SPEC_STORE_BYPASS_CMD_AUTO:
 450         case SPEC_STORE_BYPASS_CMD_SECCOMP:
 451                 /*
 452                  * Choose prctl+seccomp as the default mode if seccomp is
 453                  * enabled.
 454                  */
 455                 if (IS_ENABLED(CONFIG_SECCOMP))
 456                         mode = SPEC_STORE_BYPASS_SECCOMP;
 457                 else
 458                         mode = SPEC_STORE_BYPASS_PRCTL;
 459                 break;
 460         case SPEC_STORE_BYPASS_CMD_ON:
 461                 mode = SPEC_STORE_BYPASS_DISABLE;
 462                 break;
 463         case SPEC_STORE_BYPASS_CMD_PRCTL:
 464                 mode = SPEC_STORE_BYPASS_PRCTL;
 465                 break;
 466         case SPEC_STORE_BYPASS_CMD_NONE:
 467                 break;
 468         }
 469
 470         /*
 471          * We have three CPU feature flags that are in play here:
 472          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
 473          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
 474          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
 475          */
 476         if (mode == SPEC_STORE_BYPASS_DISABLE) {
 477                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
 478                 /*
 479                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
 480                  * a completely different MSR and bit dependent on family.
 481                  */
 482                 switch (boot_cpu_data.x86_vendor) {
 483                 case X86_VENDOR_INTEL:
 484                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 485                         x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD;
 486                         x86_spec_ctrl_set(SPEC_CTRL_SSBD);
 487                         break;
 488                 case X86_VENDOR_AMD:
 489                         x86_amd_ssb_disable();
 490                         break;
 491                 }
 492         }
 493
 494         return mode;
 495 }
 496
 497 static void ssb_select_mitigation(void)
 498 {
 499         ssb_mode = __ssb_select_mitigation();
 500
 501         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 502                 pr_info("%s\n", ssb_strings[ssb_mode]);
 503 }
 504
 505 #undef pr_fmt
 506 #define pr_fmt(fmt)     "Speculation prctl: " fmt
 507
 508 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 509 {
 510         bool update;
 511
 512         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
 513             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
 514                 return -ENXIO;
 515
 516         switch (ctrl) {
 517         case PR_SPEC_ENABLE:
 518                 /* If speculation is force disabled, enable is not allowed */
 519                 if (task_spec_ssb_force_disable(task))
 520                         return -EPERM;
 521                 task_clear_spec_ssb_disable(task);
 522                 update = test_and_clear_tsk_thread_flag(task, TIF_SSBD);
 523                 break;
 524         case PR_SPEC_DISABLE:
 525                 task_set_spec_ssb_disable(task);
 526                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 527                 break;
 528         case PR_SPEC_FORCE_DISABLE:
 529                 task_set_spec_ssb_disable(task);
 530                 task_set_spec_ssb_force_disable(task);
 531                 update = !test_and_set_tsk_thread_flag(task, TIF_SSBD);
 532                 break;
 533         default:
 534                 return -ERANGE;
 535         }
 536
 537         /*
 538          * If being set on non-current task, delay setting the CPU
 539          * mitigation until it is next scheduled.
 540          */
 541         if (task == current && update)
 542                 speculative_store_bypass_update();
 543
 544         return 0;
 545 }
 546
 547 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
 548                              unsigned long ctrl)
 549 {
 550         switch (which) {
 551         case PR_SPEC_STORE_BYPASS:
 552                 return ssb_prctl_set(task, ctrl);
 553         default:
 554                 return -ENODEV;
 555         }
 556 }
 557
 558 #ifdef CONFIG_SECCOMP
 559 void arch_seccomp_spec_mitigate(struct task_struct *task)
 560 {
 561         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
 562                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
 563 }
 564 #endif
 565
 566 static int ssb_prctl_get(struct task_struct *task)
 567 {
 568         switch (ssb_mode) {
 569         case SPEC_STORE_BYPASS_DISABLE:
 570                 return PR_SPEC_DISABLE;
 571         case SPEC_STORE_BYPASS_SECCOMP:
 572         case SPEC_STORE_BYPASS_PRCTL:
 573                 if (task_spec_ssb_force_disable(task))
 574                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 575                 if (task_spec_ssb_disable(task))
 576                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 577                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
 578         default:
 579                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
 580                         return PR_SPEC_ENABLE;
 581                 return PR_SPEC_NOT_AFFECTED;
 582         }
 583 }
 584
 585 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
 586 {
 587         switch (which) {
 588         case PR_SPEC_STORE_BYPASS:
 589                 return ssb_prctl_get(task);
 590         default:
 591                 return -ENODEV;
 592         }
 593 }
 594
 595 void x86_spec_ctrl_setup_ap(void)
 596 {
 597         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 598                 x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
 599
 600         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
 601                 x86_amd_ssb_disable();
 602 }
 603
 604 #ifdef CONFIG_SYSFS
 605 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
 606                                char *buf, unsigned int bug)
 607 {
 608         if (!boot_cpu_has_bug(bug))
 609                 return sprintf(buf, "Not affected\n");
 610
 611         switch (bug) {
 612         case X86_BUG_CPU_MELTDOWN:
 613                 if (boot_cpu_has(X86_FEATURE_PTI))
 614                         return sprintf(buf, "Mitigation: PTI\n");
 615                 break;
 616
 617         case X86_BUG_SPECTRE_V1:
 618                 if (osb_is_enabled)
 619                         return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
 620
 621         case X86_BUG_SPECTRE_V2:
 622                 return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
 623
 624         case X86_BUG_SPEC_STORE_BYPASS:
 625                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
 626
 627         default:
 628                 break;
 629         }
 630
 631         return sprintf(buf, "Vulnerable\n");
 632 }
 633
 634 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
 635                           char *buf)
 636 {
 637         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
 638 }
 639
 640 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 641                             char *buf)
 642 {
 643         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
 644 }
 645
 646 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
 647                             char *buf)
 648 {
 649         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
 650 }
 651
 652 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
 653 {
 654         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
 655 }
 656 #endif