arch/x86/kernel/irqinit.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/random.h>
   9 #include <linux/kprobes.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel_stat.h>
  12 #include <linux/device.h>
  13 #include <linux/bitops.h>
  14 #include <linux/acpi.h>
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17
  18 #include <linux/atomic.h>
  19 #include <asm/timer.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/desc.h>
  23 #include <asm/apic.h>
  24 #include <asm/setup.h>
  25 #include <asm/i8259.h>
  26 #include <asm/traps.h>
  27 #include <asm/prom.h>
  28
  29 /*
  30  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  31  * (these are usually mapped to vectors 0x30-0x3f)
  32  */
  33
  34 /*
  35  * The IO-APIC gives us many more interrupt sources. Most of these
  36  * are unused but an SMP system is supposed to have enough memory ...
  37  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  38  * across the spectrum, so we really want to be prepared to get all
  39  * of these. Plus, more powerful systems might have more than 64
  40  * IO-APIC registers.
  41  *
  42  * (these are usually mapped into the 0x30-0xff vector range)
  43  */
  44
  45 /*
  46  * IRQ2 is cascade interrupt to second interrupt controller
  47  */
  48 static struct irqaction irq2 = {
  49         .handler = no_action,
  50         .name = "cascade",
  51         .flags = IRQF_NO_THREAD,
  52 };
  53
  54 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  55         [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
  56 };
  57
  58 int vector_used_by_percpu_irq(unsigned int vector)
  59 {
  60         int cpu;
  61
  62         for_each_online_cpu(cpu) {
  63                 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector]))
  64                         return 1;
  65         }
  66
  67         return 0;
  68 }
  69
  70 void __init init_ISA_irqs(void)
  71 {
  72         struct irq_chip *chip = legacy_pic->chip;
  73         int i;
  74
  75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
  76         init_bsp_APIC();
  77 #endif
  78         legacy_pic->init(0);
  79
  80         for (i = 0; i < nr_legacy_irqs(); i++)
  81                 irq_set_chip_and_handler(i, chip, handle_level_irq);
  82 }
  83
  84 void __init init_IRQ(void)
  85 {
  86         int i;
  87
  88         /*
  89          * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
  90          * If these IRQ's are handled by legacy interrupt-controllers like PIC,
  91          * then this configuration will likely be static after the boot. If
  92          * these IRQ's are handled by more mordern controllers like IO-APIC,
  93          * then this vector space can be freed and re-used dynamically as the
  94          * irq's migrate etc.
  95          */
  96         for (i = 0; i < nr_legacy_irqs(); i++)
  97                 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
  98
  99         x86_init.irqs.intr_init();
 100 }
 101
 102 static void __init smp_intr_init(void)
 103 {
 104 #ifdef CONFIG_SMP
 105         /*
 106          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 107          * IPI, driven by wakeup.
 108          */
 109         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 110
 111         /* IPI for generic function call */
 112         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 113
 114         /* IPI for generic single function call */
 115         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 116                         call_function_single_interrupt);
 117
 118         /* Low priority IPI to cleanup after moving an irq */
 119         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 120         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 121
 122         /* IPI used for rebooting/stopping */
 123         alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
 124 #endif /* CONFIG_SMP */
 125 }
 126
 127 static void __init apic_intr_init(void)
 128 {
 129         smp_intr_init();
 130
 131 #ifdef CONFIG_X86_THERMAL_VECTOR
 132         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 133 #endif
 134 #ifdef CONFIG_X86_MCE_THRESHOLD
 135         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 136 #endif
 137
 138 #ifdef CONFIG_X86_MCE_AMD
 139         alloc_intr_gate(DEFERRED_ERROR_VECTOR, deferred_error_interrupt);
 140 #endif
 141
 142 #ifdef CONFIG_X86_LOCAL_APIC
 143         /* self generated IPI for local APIC timer */
 144         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 145
 146         /* IPI for X86 platform specific use */
 147         alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
 148 #ifdef CONFIG_HAVE_KVM
 149         /* IPI for KVM to deliver posted interrupt */
 150         alloc_intr_gate(POSTED_INTR_VECTOR, kvm_posted_intr_ipi);
 151         /* IPI for KVM to deliver interrupt to wake up tasks */
 152         alloc_intr_gate(POSTED_INTR_WAKEUP_VECTOR, kvm_posted_intr_wakeup_ipi);
 153         /* IPI for KVM to deliver nested posted interrupt */
 154         alloc_intr_gate(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi);
 155 #endif
 156
 157         /* IPI vectors for APIC spurious and error interrupts */
 158         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 159         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 160
 161         /* IRQ work interrupts: */
 162 # ifdef CONFIG_IRQ_WORK
 163         alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
 164 # endif
 165
 166 #endif
 167 }
 168
 169 void __init native_init_IRQ(void)
 170 {
 171         int i;
 172
 173         /* Execute any quirks before the call gates are initialised: */
 174         x86_init.irqs.pre_vector_init();
 175
 176         apic_intr_init();
 177
 178         /*
 179          * Cover the whole vector space, no vector can escape
 180          * us. (some of these will be overridden and become
 181          * 'special' SMP interrupts)
 182          */
 183         i = FIRST_EXTERNAL_VECTOR;
 184 #ifndef CONFIG_X86_LOCAL_APIC
 185 #define first_system_vector NR_VECTORS
 186 #endif
 187         for_each_clear_bit_from(i, used_vectors, first_system_vector) {
 188                 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
 189                 set_intr_gate(i, irq_entries_start +
 190                                 8 * (i - FIRST_EXTERNAL_VECTOR));
 191         }
 192 #ifdef CONFIG_X86_LOCAL_APIC
 193         for_each_clear_bit_from(i, used_vectors, NR_VECTORS)
 194                 set_intr_gate(i, spurious_interrupt);
 195 #endif
 196
 197         if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
 198                 setup_irq(2, &irq2);
 199
 200         irq_ctx_init(smp_processor_id());
 201 }