arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/sched/idle.h>
  11 #include <linux/sched/debug.h>
  12 #include <linux/sched/task.h>
  13 #include <linux/sched/task_stack.h>
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/pm.h>
  17 #include <linux/tick.h>
  18 #include <linux/random.h>
  19 #include <linux/user-return-notifier.h>
  20 #include <linux/dmi.h>
  21 #include <linux/utsname.h>
  22 #include <linux/stackprotector.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <trace/events/power.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <asm/cpu.h>
  28 #include <asm/apic.h>
  29 #include <asm/syscalls.h>
  30 #include <linux/uaccess.h>
  31 #include <asm/mwait.h>
  32 #include <asm/fpu/internal.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/nmi.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/mce.h>
  37 #include <asm/vm86.h>
  38 #include <asm/switch_to.h>
  39 #include <asm/desc.h>
  40 #include <asm/prctl.h>
  41
  42 /*
  43  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  44  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  45  * so they are allowed to end up in the .data..cacheline_aligned
  46  * section. Since TSS's are completely CPU-local, we want them
  47  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  48  */
  49 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
  50         .x86_tss = {
  51                 /*
  52                  * .sp0 is only used when entering ring 0 from a lower
  53                  * privilege level.  Since the init task never runs anything
  54                  * but ring 0 code, there is no need for a valid value here.
  55                  * Poison it.
  56                  */
  57                 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
  58
  59 #ifdef CONFIG_X86_64
  60                 /*
  61                  * .sp1 is cpu_current_top_of_stack.  The init task never
  62                  * runs user code, but cpu_current_top_of_stack should still
  63                  * be well defined before the first context switch.
  64                  */
  65                 .sp1 = TOP_OF_INIT_STACK,
  66 #endif
  67
  68 #ifdef CONFIG_X86_32
  69                 .ss0 = __KERNEL_DS,
  70                 .ss1 = __KERNEL_CS,
  71                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  72 #endif
  73          },
  74 #ifdef CONFIG_X86_32
  75          /*
  76           * Note that the .io_bitmap member must be extra-big. This is because
  77           * the CPU will access an additional byte beyond the end of the IO
  78           * permission bitmap. The extra byte must be all 1 bits, and must
  79           * be within the limit.
  80           */
  81         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  82 #endif
  83 };
  84 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
  85
  86 DEFINE_PER_CPU(bool, __tss_limit_invalid);
  87 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  88
  89 /*
  90  * this gets called so that we can store lazy state into memory and copy the
  91  * current task into the new thread.
  92  */
  93 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  94 {
  95         memcpy(dst, src, arch_task_struct_size);
  96 #ifdef CONFIG_VM86
  97         dst->thread.vm86 = NULL;
  98 #endif
  99
 100         return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
 101 }
 102
 103 /*
 104  * Free current thread data structures etc..
 105  */
 106 void exit_thread(struct task_struct *tsk)
 107 {
 108         struct thread_struct *t = &tsk->thread;
 109         unsigned long *bp = t->io_bitmap_ptr;
 110         struct fpu *fpu = &t->fpu;
 111
 112         if (bp) {
 113                 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
 114
 115                 t->io_bitmap_ptr = NULL;
 116                 clear_thread_flag(TIF_IO_BITMAP);
 117                 /*
 118                  * Careful, clear this in the TSS too:
 119                  */
 120                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 121                 t->io_bitmap_max = 0;
 122                 put_cpu();
 123                 kfree(bp);
 124         }
 125
 126         free_vm86(t);
 127
 128         fpu__drop(fpu);
 129 }
 130
 131 void flush_thread(void)
 132 {
 133         struct task_struct *tsk = current;
 134
 135         flush_ptrace_hw_breakpoint(tsk);
 136         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 137
 138         fpu__clear(&tsk->thread.fpu);
 139 }
 140
 141 void disable_TSC(void)
 142 {
 143         preempt_disable();
 144         if (!test_and_set_thread_flag(TIF_NOTSC))
 145                 /*
 146                  * Must flip the CPU state synchronously with
 147                  * TIF_NOTSC in the current running context.
 148                  */
 149                 cr4_set_bits(X86_CR4_TSD);
 150         preempt_enable();
 151 }
 152
 153 static void enable_TSC(void)
 154 {
 155         preempt_disable();
 156         if (test_and_clear_thread_flag(TIF_NOTSC))
 157                 /*
 158                  * Must flip the CPU state synchronously with
 159                  * TIF_NOTSC in the current running context.
 160                  */
 161                 cr4_clear_bits(X86_CR4_TSD);
 162         preempt_enable();
 163 }
 164
 165 int get_tsc_mode(unsigned long adr)
 166 {
 167         unsigned int val;
 168
 169         if (test_thread_flag(TIF_NOTSC))
 170                 val = PR_TSC_SIGSEGV;
 171         else
 172                 val = PR_TSC_ENABLE;
 173
 174         return put_user(val, (unsigned int __user *)adr);
 175 }
 176
 177 int set_tsc_mode(unsigned int val)
 178 {
 179         if (val == PR_TSC_SIGSEGV)
 180                 disable_TSC();
 181         else if (val == PR_TSC_ENABLE)
 182                 enable_TSC();
 183         else
 184                 return -EINVAL;
 185
 186         return 0;
 187 }
 188
 189 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 190
 191 static void set_cpuid_faulting(bool on)
 192 {
 193         u64 msrval;
 194
 195         msrval = this_cpu_read(msr_misc_features_shadow);
 196         msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 197         msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 198         this_cpu_write(msr_misc_features_shadow, msrval);
 199         wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 200 }
 201
 202 static void disable_cpuid(void)
 203 {
 204         preempt_disable();
 205         if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 206                 /*
 207                  * Must flip the CPU state synchronously with
 208                  * TIF_NOCPUID in the current running context.
 209                  */
 210                 set_cpuid_faulting(true);
 211         }
 212         preempt_enable();
 213 }
 214
 215 static void enable_cpuid(void)
 216 {
 217         preempt_disable();
 218         if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 219                 /*
 220                  * Must flip the CPU state synchronously with
 221                  * TIF_NOCPUID in the current running context.
 222                  */
 223                 set_cpuid_faulting(false);
 224         }
 225         preempt_enable();
 226 }
 227
 228 static int get_cpuid_mode(void)
 229 {
 230         return !test_thread_flag(TIF_NOCPUID);
 231 }
 232
 233 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 234 {
 235         if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
 236                 return -ENODEV;
 237
 238         if (cpuid_enabled)
 239                 enable_cpuid();
 240         else
 241                 disable_cpuid();
 242
 243         return 0;
 244 }
 245
 246 /*
 247  * Called immediately after a successful exec.
 248  */
 249 void arch_setup_new_exec(void)
 250 {
 251         /* If cpuid was previously disabled for this task, re-enable it. */
 252         if (test_thread_flag(TIF_NOCPUID))
 253                 enable_cpuid();
 254 }
 255
 256 static inline void switch_to_bitmap(struct tss_struct *tss,
 257                                     struct thread_struct *prev,
 258                                     struct thread_struct *next,
 259                                     unsigned long tifp, unsigned long tifn)
 260 {
 261         if (tifn & _TIF_IO_BITMAP) {
 262                 /*
 263                  * Copy the relevant range of the IO bitmap.
 264                  * Normally this is 128 bytes or less:
 265                  */
 266                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 267                        max(prev->io_bitmap_max, next->io_bitmap_max));
 268                 /*
 269                  * Make sure that the TSS limit is correct for the CPU
 270                  * to notice the IO bitmap.
 271                  */
 272                 refresh_tss_limit();
 273         } else if (tifp & _TIF_IO_BITMAP) {
 274                 /*
 275                  * Clear any possible leftover bits:
 276                  */
 277                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 278         }
 279 }
 280
 281 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 282                       struct tss_struct *tss)
 283 {
 284         struct thread_struct *prev, *next;
 285         unsigned long tifp, tifn;
 286
 287         prev = &prev_p->thread;
 288         next = &next_p->thread;
 289
 290         tifn = READ_ONCE(task_thread_info(next_p)->flags);
 291         tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 292         switch_to_bitmap(tss, prev, next, tifp, tifn);
 293
 294         propagate_user_return_notify(prev_p, next_p);
 295
 296         if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 297             arch_has_block_step()) {
 298                 unsigned long debugctl, msk;
 299
 300                 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 301                 debugctl &= ~DEBUGCTLMSR_BTF;
 302                 msk = tifn & _TIF_BLOCKSTEP;
 303                 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 304                 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 305         }
 306
 307         if ((tifp ^ tifn) & _TIF_NOTSC)
 308                 cr4_toggle_bits(X86_CR4_TSD);
 309
 310         if ((tifp ^ tifn) & _TIF_NOCPUID)
 311                 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 312 }
 313
 314 /*
 315  * Idle related variables and functions
 316  */
 317 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 318 EXPORT_SYMBOL(boot_option_idle_override);
 319
 320 static void (*x86_idle)(void);
 321
 322 #ifndef CONFIG_SMP
 323 static inline void play_dead(void)
 324 {
 325         BUG();
 326 }
 327 #endif
 328
 329 void arch_cpu_idle_enter(void)
 330 {
 331         tsc_verify_tsc_adjust(false);
 332         local_touch_nmi();
 333 }
 334
 335 void arch_cpu_idle_dead(void)
 336 {
 337         play_dead();
 338 }
 339
 340 /*
 341  * Called from the generic idle code.
 342  */
 343 void arch_cpu_idle(void)
 344 {
 345         x86_idle();
 346 }
 347
 348 /*
 349  * We use this if we don't have any better idle routine..
 350  */
 351 void __cpuidle default_idle(void)
 352 {
 353         trace_cpu_idle_rcuidle(1, smp_processor_id());
 354         safe_halt();
 355         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 356 }
 357 #ifdef CONFIG_APM_MODULE
 358 EXPORT_SYMBOL(default_idle);
 359 #endif
 360
 361 #ifdef CONFIG_XEN
 362 bool xen_set_default_idle(void)
 363 {
 364         bool ret = !!x86_idle;
 365
 366         x86_idle = default_idle;
 367
 368         return ret;
 369 }
 370 #endif
 371 void stop_this_cpu(void *dummy)
 372 {
 373         local_irq_disable();
 374         /*
 375          * Remove this CPU:
 376          */
 377         set_cpu_online(smp_processor_id(), false);
 378         disable_local_APIC();
 379         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 380
 381         for (;;)
 382                 halt();
 383 }
 384
 385 /*
 386  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 387  * states (local apic timer and TSC stop).
 388  */
 389 static void amd_e400_idle(void)
 390 {
 391         /*
 392          * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 393          * gets set after static_cpu_has() places have been converted via
 394          * alternatives.
 395          */
 396         if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 397                 default_idle();
 398                 return;
 399         }
 400
 401         tick_broadcast_enter();
 402
 403         default_idle();
 404
 405         /*
 406          * The switch back from broadcast mode needs to be called with
 407          * interrupts disabled.
 408          */
 409         local_irq_disable();
 410         tick_broadcast_exit();
 411         local_irq_enable();
 412 }
 413
 414 /*
 415  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 416  * We can't rely on cpuidle installing MWAIT, because it will not load
 417  * on systems that support only C1 -- so the boot default must be MWAIT.
 418  *
 419  * Some AMD machines are the opposite, they depend on using HALT.
 420  *
 421  * So for default C1, which is used during boot until cpuidle loads,
 422  * use MWAIT-C1 on Intel HW that has it, else use HALT.
 423  */
 424 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 425 {
 426         if (c->x86_vendor != X86_VENDOR_INTEL)
 427                 return 0;
 428
 429         if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
 430                 return 0;
 431
 432         return 1;
 433 }
 434
 435 /*
 436  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 437  * with interrupts enabled and no flags, which is backwards compatible with the
 438  * original MWAIT implementation.
 439  */
 440 static __cpuidle void mwait_idle(void)
 441 {
 442         if (!current_set_polling_and_test()) {
 443                 trace_cpu_idle_rcuidle(1, smp_processor_id());
 444                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 445                         mb(); /* quirk */
 446                         clflush((void *)&current_thread_info()->flags);
 447                         mb(); /* quirk */
 448                 }
 449
 450                 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
 451                         native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
 452
 453                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 454                 if (!need_resched()) {
 455                         __sti_mwait(0, 0);
 456                         if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
 457                                 native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
 458                 } else {
 459                         if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
 460                                 native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
 461                         local_irq_enable();
 462                 }
 463                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 464         } else {
 465                 local_irq_enable();
 466         }
 467         __current_clr_polling();
 468 }
 469
 470 void select_idle_routine(const struct cpuinfo_x86 *c)
 471 {
 472 #ifdef CONFIG_SMP
 473         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 474                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 475 #endif
 476         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 477                 return;
 478
 479         if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 480                 pr_info("using AMD E400 aware idle routine\n");
 481                 x86_idle = amd_e400_idle;
 482         } else if (prefer_mwait_c1_over_halt(c)) {
 483                 pr_info("using mwait in idle threads\n");
 484                 x86_idle = mwait_idle;
 485         } else
 486                 x86_idle = default_idle;
 487 }
 488
 489 void amd_e400_c1e_apic_setup(void)
 490 {
 491         if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 492                 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 493                 local_irq_disable();
 494                 tick_broadcast_force();
 495                 local_irq_enable();
 496         }
 497 }
 498
 499 void __init arch_post_acpi_subsys_init(void)
 500 {
 501         u32 lo, hi;
 502
 503         if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 504                 return;
 505
 506         /*
 507          * AMD E400 detection needs to happen after ACPI has been enabled. If
 508          * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 509          * MSR_K8_INT_PENDING_MSG.
 510          */
 511         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 512         if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 513                 return;
 514
 515         boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 516
 517         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 518                 mark_tsc_unstable("TSC halt in AMD C1E");
 519         pr_info("System has AMD C1E enabled\n");
 520 }
 521
 522 static int __init idle_setup(char *str)
 523 {
 524         if (!str)
 525                 return -EINVAL;
 526
 527         if (!strcmp(str, "poll")) {
 528                 pr_info("using polling idle threads\n");
 529                 boot_option_idle_override = IDLE_POLL;
 530                 cpu_idle_poll_ctrl(true);
 531         } else if (!strcmp(str, "halt")) {
 532                 /*
 533                  * When the boot option of idle=halt is added, halt is
 534                  * forced to be used for CPU idle. In such case CPU C2/C3
 535                  * won't be used again.
 536                  * To continue to load the CPU idle driver, don't touch
 537                  * the boot_option_idle_override.
 538                  */
 539                 x86_idle = default_idle;
 540                 boot_option_idle_override = IDLE_HALT;
 541         } else if (!strcmp(str, "nomwait")) {
 542                 /*
 543                  * If the boot option of "idle=nomwait" is added,
 544                  * it means that mwait will be disabled for CPU C2/C3
 545                  * states. In such case it won't touch the variable
 546                  * of boot_option_idle_override.
 547                  */
 548                 boot_option_idle_override = IDLE_NOMWAIT;
 549         } else
 550                 return -1;
 551
 552         return 0;
 553 }
 554 early_param("idle", idle_setup);
 555
 556 unsigned long arch_align_stack(unsigned long sp)
 557 {
 558         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 559                 sp -= get_random_int() % 8192;
 560         return sp & ~0xf;
 561 }
 562
 563 unsigned long arch_randomize_brk(struct mm_struct *mm)
 564 {
 565         return randomize_page(mm->brk, 0x02000000);
 566 }
 567
 568 /*
 569  * Called from fs/proc with a reference on @p to find the function
 570  * which called into schedule(). This needs to be done carefully
 571  * because the task might wake up and we might look at a stack
 572  * changing under us.
 573  */
 574 unsigned long get_wchan(struct task_struct *p)
 575 {
 576         unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 577         int count = 0;
 578
 579         if (!p || p == current || p->state == TASK_RUNNING)
 580                 return 0;
 581
 582         if (!try_get_task_stack(p))
 583                 return 0;
 584
 585         start = (unsigned long)task_stack_page(p);
 586         if (!start)
 587                 goto out;
 588
 589         /*
 590          * Layout of the stack page:
 591          *
 592          * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 593          * PADDING
 594          * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 595          * stack
 596          * ----------- bottom = start
 597          *
 598          * The tasks stack pointer points at the location where the
 599          * framepointer is stored. The data on the stack is:
 600          * ... IP FP ... IP FP
 601          *
 602          * We need to read FP and IP, so we need to adjust the upper
 603          * bound by another unsigned long.
 604          */
 605         top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 606         top -= 2 * sizeof(unsigned long);
 607         bottom = start;
 608
 609         sp = READ_ONCE(p->thread.sp);
 610         if (sp < bottom || sp > top)
 611                 goto out;
 612
 613         fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 614         do {
 615                 if (fp < bottom || fp > top)
 616                         goto out;
 617                 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 618                 if (!in_sched_functions(ip)) {
 619                         ret = ip;
 620                         goto out;
 621                 }
 622                 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 623         } while (count++ < 16 && p->state != TASK_RUNNING);
 624
 625 out:
 626         put_task_stack(p);
 627         return ret;
 628 }
 629
 630 long do_arch_prctl_common(struct task_struct *task, int option,
 631                           unsigned long cpuid_enabled)
 632 {
 633         switch (option) {
 634         case ARCH_GET_CPUID:
 635                 return get_cpuid_mode();
 636         case ARCH_SET_CPUID:
 637                 return set_cpuid_mode(task, cpuid_enabled);
 638         }
 639
 640         return -EINVAL;
 641 }