arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/sched/idle.h>
  11 #include <linux/sched/debug.h>
  12 #include <linux/sched/task.h>
  13 #include <linux/sched/task_stack.h>
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/pm.h>
  17 #include <linux/tick.h>
  18 #include <linux/random.h>
  19 #include <linux/user-return-notifier.h>
  20 #include <linux/dmi.h>
  21 #include <linux/utsname.h>
  22 #include <linux/stackprotector.h>
  23 #include <linux/tick.h>
  24 #include <linux/cpuidle.h>
  25 #include <trace/events/power.h>
  26 #include <linux/hw_breakpoint.h>
  27 #include <asm/cpu.h>
  28 #include <asm/apic.h>
  29 #include <asm/syscalls.h>
  30 #include <linux/uaccess.h>
  31 #include <asm/mwait.h>
  32 #include <asm/fpu/internal.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/nmi.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/mce.h>
  37 #include <asm/vm86.h>
  38 #include <asm/switch_to.h>
  39 #include <asm/desc.h>
  40 #include <asm/prctl.h>
  41
  42 /*
  43  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  44  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  45  * so they are allowed to end up in the .data..cacheline_aligned
  46  * section. Since TSS's are completely CPU-local, we want them
  47  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  48  */
  49 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
  50         .x86_tss = {
  51                 .sp0 = TOP_OF_INIT_STACK,
  52 #ifdef CONFIG_X86_32
  53                 .ss0 = __KERNEL_DS,
  54                 .ss1 = __KERNEL_CS,
  55                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
  56 #endif
  57          },
  58 #ifdef CONFIG_X86_32
  59          /*
  60           * Note that the .io_bitmap member must be extra-big. This is because
  61           * the CPU will access an additional byte beyond the end of the IO
  62           * permission bitmap. The extra byte must be all 1 bits, and must
  63           * be within the limit.
  64           */
  65         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },
  66 #endif
  67 #ifdef CONFIG_X86_32
  68         .SYSENTER_stack_canary  = STACK_END_MAGIC,
  69 #endif
  70 };
  71 EXPORT_PER_CPU_SYMBOL(cpu_tss);
  72
  73 DEFINE_PER_CPU(bool, __tss_limit_invalid);
  74 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  75
  76 /*
  77  * this gets called so that we can store lazy state into memory and copy the
  78  * current task into the new thread.
  79  */
  80 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  81 {
  82         memcpy(dst, src, arch_task_struct_size);
  83 #ifdef CONFIG_VM86
  84         dst->thread.vm86 = NULL;
  85 #endif
  86
  87         return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
  88 }
  89
  90 /*
  91  * Free current thread data structures etc..
  92  */
  93 void exit_thread(struct task_struct *tsk)
  94 {
  95         struct thread_struct *t = &tsk->thread;
  96         unsigned long *bp = t->io_bitmap_ptr;
  97         struct fpu *fpu = &t->fpu;
  98
  99         if (bp) {
 100                 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
 101
 102                 t->io_bitmap_ptr = NULL;
 103                 clear_thread_flag(TIF_IO_BITMAP);
 104                 /*
 105                  * Careful, clear this in the TSS too:
 106                  */
 107                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 108                 t->io_bitmap_max = 0;
 109                 put_cpu();
 110                 kfree(bp);
 111         }
 112
 113         free_vm86(t);
 114
 115         fpu__drop(fpu);
 116 }
 117
 118 void flush_thread(void)
 119 {
 120         struct task_struct *tsk = current;
 121
 122         flush_ptrace_hw_breakpoint(tsk);
 123         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 124
 125         fpu__clear(&tsk->thread.fpu);
 126 }
 127
 128 void disable_TSC(void)
 129 {
 130         preempt_disable();
 131         if (!test_and_set_thread_flag(TIF_NOTSC))
 132                 /*
 133                  * Must flip the CPU state synchronously with
 134                  * TIF_NOTSC in the current running context.
 135                  */
 136                 cr4_set_bits(X86_CR4_TSD);
 137         preempt_enable();
 138 }
 139
 140 static void enable_TSC(void)
 141 {
 142         preempt_disable();
 143         if (test_and_clear_thread_flag(TIF_NOTSC))
 144                 /*
 145                  * Must flip the CPU state synchronously with
 146                  * TIF_NOTSC in the current running context.
 147                  */
 148                 cr4_clear_bits(X86_CR4_TSD);
 149         preempt_enable();
 150 }
 151
 152 int get_tsc_mode(unsigned long adr)
 153 {
 154         unsigned int val;
 155
 156         if (test_thread_flag(TIF_NOTSC))
 157                 val = PR_TSC_SIGSEGV;
 158         else
 159                 val = PR_TSC_ENABLE;
 160
 161         return put_user(val, (unsigned int __user *)adr);
 162 }
 163
 164 int set_tsc_mode(unsigned int val)
 165 {
 166         if (val == PR_TSC_SIGSEGV)
 167                 disable_TSC();
 168         else if (val == PR_TSC_ENABLE)
 169                 enable_TSC();
 170         else
 171                 return -EINVAL;
 172
 173         return 0;
 174 }
 175
 176 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 177
 178 static void set_cpuid_faulting(bool on)
 179 {
 180         u64 msrval;
 181
 182         msrval = this_cpu_read(msr_misc_features_shadow);
 183         msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 184         msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 185         this_cpu_write(msr_misc_features_shadow, msrval);
 186         wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 187 }
 188
 189 static void disable_cpuid(void)
 190 {
 191         preempt_disable();
 192         if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 193                 /*
 194                  * Must flip the CPU state synchronously with
 195                  * TIF_NOCPUID in the current running context.
 196                  */
 197                 set_cpuid_faulting(true);
 198         }
 199         preempt_enable();
 200 }
 201
 202 static void enable_cpuid(void)
 203 {
 204         preempt_disable();
 205         if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 206                 /*
 207                  * Must flip the CPU state synchronously with
 208                  * TIF_NOCPUID in the current running context.
 209                  */
 210                 set_cpuid_faulting(false);
 211         }
 212         preempt_enable();
 213 }
 214
 215 static int get_cpuid_mode(void)
 216 {
 217         return !test_thread_flag(TIF_NOCPUID);
 218 }
 219
 220 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 221 {
 222         if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
 223                 return -ENODEV;
 224
 225         if (cpuid_enabled)
 226                 enable_cpuid();
 227         else
 228                 disable_cpuid();
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * Called immediately after a successful exec.
 235  */
 236 void arch_setup_new_exec(void)
 237 {
 238         /* If cpuid was previously disabled for this task, re-enable it. */
 239         if (test_thread_flag(TIF_NOCPUID))
 240                 enable_cpuid();
 241 }
 242
 243 static inline void switch_to_bitmap(struct tss_struct *tss,
 244                                     struct thread_struct *prev,
 245                                     struct thread_struct *next,
 246                                     unsigned long tifp, unsigned long tifn)
 247 {
 248         if (tifn & _TIF_IO_BITMAP) {
 249                 /*
 250                  * Copy the relevant range of the IO bitmap.
 251                  * Normally this is 128 bytes or less:
 252                  */
 253                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 254                        max(prev->io_bitmap_max, next->io_bitmap_max));
 255                 /*
 256                  * Make sure that the TSS limit is correct for the CPU
 257                  * to notice the IO bitmap.
 258                  */
 259                 refresh_tss_limit();
 260         } else if (tifp & _TIF_IO_BITMAP) {
 261                 /*
 262                  * Clear any possible leftover bits:
 263                  */
 264                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 265         }
 266 }
 267
 268 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 269                       struct tss_struct *tss)
 270 {
 271         struct thread_struct *prev, *next;
 272         unsigned long tifp, tifn;
 273
 274         prev = &prev_p->thread;
 275         next = &next_p->thread;
 276
 277         tifn = READ_ONCE(task_thread_info(next_p)->flags);
 278         tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 279         switch_to_bitmap(tss, prev, next, tifp, tifn);
 280
 281         propagate_user_return_notify(prev_p, next_p);
 282
 283         if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 284             arch_has_block_step()) {
 285                 unsigned long debugctl, msk;
 286
 287                 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 288                 debugctl &= ~DEBUGCTLMSR_BTF;
 289                 msk = tifn & _TIF_BLOCKSTEP;
 290                 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 291                 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 292         }
 293
 294         if ((tifp ^ tifn) & _TIF_NOTSC)
 295                 cr4_toggle_bits(X86_CR4_TSD);
 296
 297         if ((tifp ^ tifn) & _TIF_NOCPUID)
 298                 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 299 }
 300
 301 /*
 302  * Idle related variables and functions
 303  */
 304 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 305 EXPORT_SYMBOL(boot_option_idle_override);
 306
 307 static void (*x86_idle)(void);
 308
 309 #ifndef CONFIG_SMP
 310 static inline void play_dead(void)
 311 {
 312         BUG();
 313 }
 314 #endif
 315
 316 void arch_cpu_idle_enter(void)
 317 {
 318         tsc_verify_tsc_adjust(false);
 319         local_touch_nmi();
 320 }
 321
 322 void arch_cpu_idle_dead(void)
 323 {
 324         play_dead();
 325 }
 326
 327 /*
 328  * Called from the generic idle code.
 329  */
 330 void arch_cpu_idle(void)
 331 {
 332         x86_idle();
 333 }
 334
 335 /*
 336  * We use this if we don't have any better idle routine..
 337  */
 338 void __cpuidle default_idle(void)
 339 {
 340         trace_cpu_idle_rcuidle(1, smp_processor_id());
 341         safe_halt();
 342         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 343 }
 344 #ifdef CONFIG_APM_MODULE
 345 EXPORT_SYMBOL(default_idle);
 346 #endif
 347
 348 #ifdef CONFIG_XEN
 349 bool xen_set_default_idle(void)
 350 {
 351         bool ret = !!x86_idle;
 352
 353         x86_idle = default_idle;
 354
 355         return ret;
 356 }
 357 #endif
 358 void stop_this_cpu(void *dummy)
 359 {
 360         local_irq_disable();
 361         /*
 362          * Remove this CPU:
 363          */
 364         set_cpu_online(smp_processor_id(), false);
 365         disable_local_APIC();
 366         mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 367
 368         for (;;)
 369                 halt();
 370 }
 371
 372 /*
 373  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 374  * states (local apic timer and TSC stop).
 375  */
 376 static void amd_e400_idle(void)
 377 {
 378         /*
 379          * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 380          * gets set after static_cpu_has() places have been converted via
 381          * alternatives.
 382          */
 383         if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 384                 default_idle();
 385                 return;
 386         }
 387
 388         tick_broadcast_enter();
 389
 390         default_idle();
 391
 392         /*
 393          * The switch back from broadcast mode needs to be called with
 394          * interrupts disabled.
 395          */
 396         local_irq_disable();
 397         tick_broadcast_exit();
 398         local_irq_enable();
 399 }
 400
 401 /*
 402  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 403  * We can't rely on cpuidle installing MWAIT, because it will not load
 404  * on systems that support only C1 -- so the boot default must be MWAIT.
 405  *
 406  * Some AMD machines are the opposite, they depend on using HALT.
 407  *
 408  * So for default C1, which is used during boot until cpuidle loads,
 409  * use MWAIT-C1 on Intel HW that has it, else use HALT.
 410  */
 411 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 412 {
 413         if (c->x86_vendor != X86_VENDOR_INTEL)
 414                 return 0;
 415
 416         if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
 417                 return 0;
 418
 419         return 1;
 420 }
 421
 422 /*
 423  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 424  * with interrupts enabled and no flags, which is backwards compatible with the
 425  * original MWAIT implementation.
 426  */
 427 static __cpuidle void mwait_idle(void)
 428 {
 429         if (!current_set_polling_and_test()) {
 430                 trace_cpu_idle_rcuidle(1, smp_processor_id());
 431                 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 432                         mb(); /* quirk */
 433                         clflush((void *)&current_thread_info()->flags);
 434                         mb(); /* quirk */
 435                 }
 436
 437                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 438                 if (!need_resched())
 439                         __sti_mwait(0, 0);
 440                 else
 441                         local_irq_enable();
 442                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 443         } else {
 444                 local_irq_enable();
 445         }
 446         __current_clr_polling();
 447 }
 448
 449 void select_idle_routine(const struct cpuinfo_x86 *c)
 450 {
 451 #ifdef CONFIG_SMP
 452         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 453                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 454 #endif
 455         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 456                 return;
 457
 458         if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 459                 pr_info("using AMD E400 aware idle routine\n");
 460                 x86_idle = amd_e400_idle;
 461         } else if (prefer_mwait_c1_over_halt(c)) {
 462                 pr_info("using mwait in idle threads\n");
 463                 x86_idle = mwait_idle;
 464         } else
 465                 x86_idle = default_idle;
 466 }
 467
 468 void amd_e400_c1e_apic_setup(void)
 469 {
 470         if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 471                 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 472                 local_irq_disable();
 473                 tick_broadcast_force();
 474                 local_irq_enable();
 475         }
 476 }
 477
 478 void __init arch_post_acpi_subsys_init(void)
 479 {
 480         u32 lo, hi;
 481
 482         if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 483                 return;
 484
 485         /*
 486          * AMD E400 detection needs to happen after ACPI has been enabled. If
 487          * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 488          * MSR_K8_INT_PENDING_MSG.
 489          */
 490         rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 491         if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 492                 return;
 493
 494         boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 495
 496         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 497                 mark_tsc_unstable("TSC halt in AMD C1E");
 498         pr_info("System has AMD C1E enabled\n");
 499 }
 500
 501 static int __init idle_setup(char *str)
 502 {
 503         if (!str)
 504                 return -EINVAL;
 505
 506         if (!strcmp(str, "poll")) {
 507                 pr_info("using polling idle threads\n");
 508                 boot_option_idle_override = IDLE_POLL;
 509                 cpu_idle_poll_ctrl(true);
 510         } else if (!strcmp(str, "halt")) {
 511                 /*
 512                  * When the boot option of idle=halt is added, halt is
 513                  * forced to be used for CPU idle. In such case CPU C2/C3
 514                  * won't be used again.
 515                  * To continue to load the CPU idle driver, don't touch
 516                  * the boot_option_idle_override.
 517                  */
 518                 x86_idle = default_idle;
 519                 boot_option_idle_override = IDLE_HALT;
 520         } else if (!strcmp(str, "nomwait")) {
 521                 /*
 522                  * If the boot option of "idle=nomwait" is added,
 523                  * it means that mwait will be disabled for CPU C2/C3
 524                  * states. In such case it won't touch the variable
 525                  * of boot_option_idle_override.
 526                  */
 527                 boot_option_idle_override = IDLE_NOMWAIT;
 528         } else
 529                 return -1;
 530
 531         return 0;
 532 }
 533 early_param("idle", idle_setup);
 534
 535 unsigned long arch_align_stack(unsigned long sp)
 536 {
 537         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 538                 sp -= get_random_int() % 8192;
 539         return sp & ~0xf;
 540 }
 541
 542 unsigned long arch_randomize_brk(struct mm_struct *mm)
 543 {
 544         return randomize_page(mm->brk, 0x02000000);
 545 }
 546
 547 /*
 548  * Called from fs/proc with a reference on @p to find the function
 549  * which called into schedule(). This needs to be done carefully
 550  * because the task might wake up and we might look at a stack
 551  * changing under us.
 552  */
 553 unsigned long get_wchan(struct task_struct *p)
 554 {
 555         unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 556         int count = 0;
 557
 558         if (!p || p == current || p->state == TASK_RUNNING)
 559                 return 0;
 560
 561         if (!try_get_task_stack(p))
 562                 return 0;
 563
 564         start = (unsigned long)task_stack_page(p);
 565         if (!start)
 566                 goto out;
 567
 568         /*
 569          * Layout of the stack page:
 570          *
 571          * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 572          * PADDING
 573          * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 574          * stack
 575          * ----------- bottom = start
 576          *
 577          * The tasks stack pointer points at the location where the
 578          * framepointer is stored. The data on the stack is:
 579          * ... IP FP ... IP FP
 580          *
 581          * We need to read FP and IP, so we need to adjust the upper
 582          * bound by another unsigned long.
 583          */
 584         top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 585         top -= 2 * sizeof(unsigned long);
 586         bottom = start;
 587
 588         sp = READ_ONCE(p->thread.sp);
 589         if (sp < bottom || sp > top)
 590                 goto out;
 591
 592         fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 593         do {
 594                 if (fp < bottom || fp > top)
 595                         goto out;
 596                 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 597                 if (!in_sched_functions(ip)) {
 598                         ret = ip;
 599                         goto out;
 600                 }
 601                 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 602         } while (count++ < 16 && p->state != TASK_RUNNING);
 603
 604 out:
 605         put_task_stack(p);
 606         return ret;
 607 }
 608
 609 long do_arch_prctl_common(struct task_struct *task, int option,
 610                           unsigned long cpuid_enabled)
 611 {
 612         switch (option) {
 613         case ARCH_GET_CPUID:
 614                 return get_cpuid_mode();
 615         case ARCH_SET_CPUID:
 616                 return set_cpuid_mode(task, cpuid_enabled);
 617         }
 618
 619         return -EINVAL;
 620 }