2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/nospec-branch.h>
50 #include <asm/virtext.h>
53 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id svm_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
62 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
64 #define IOPM_ALLOC_ORDER 2
65 #define MSRPM_ALLOC_ORDER 1
67 #define SEG_TYPE_LDT 2
68 #define SEG_TYPE_BUSY_TSS16 3
70 #define SVM_FEATURE_NPT (1 << 0)
71 #define SVM_FEATURE_LBRV (1 << 1)
72 #define SVM_FEATURE_SVML (1 << 2)
73 #define SVM_FEATURE_NRIP (1 << 3)
74 #define SVM_FEATURE_TSC_RATE (1 << 4)
75 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
76 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
77 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
78 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80 #define SVM_AVIC_DOORBELL 0xc001011b
82 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
83 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
84 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
86 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
88 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
89 #define TSC_RATIO_MIN 0x0000000000000001ULL
90 #define TSC_RATIO_MAX 0x000000ffffffffffULL
92 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
95 * 0xff is broadcast, so the max index allowed for physical APIC ID
96 * table is 0xfe. APIC IDs above 0xff are reserved.
98 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
100 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
101 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
102 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
104 /* AVIC GATAG is encoded using VM and VCPU IDs */
105 #define AVIC_VCPU_ID_BITS 8
106 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
108 #define AVIC_VM_ID_BITS 24
109 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
110 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
112 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
113 (y & AVIC_VCPU_ID_MASK))
114 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
115 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
117 static bool erratum_383_found __read_mostly
;
119 static const u32 host_save_user_msrs
[] = {
121 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
124 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
128 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
132 struct nested_state
{
138 /* These are the merged vectors */
141 /* gpa pointers to the real vectors */
145 /* A VMEXIT is required but not yet emulated */
148 /* cache for intercepts of the guest */
151 u32 intercept_exceptions
;
154 /* Nested Paging related state */
158 #define MSRPM_OFFSETS 16
159 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
162 * Set osvw_len to higher value when updated Revision Guides
163 * are published and we know what the new status bits are
165 static uint64_t osvw_len
= 4, osvw_status
;
168 struct kvm_vcpu vcpu
;
170 unsigned long vmcb_pa
;
171 struct svm_cpu_data
*svm_data
;
172 uint64_t asid_generation
;
173 uint64_t sysenter_esp
;
174 uint64_t sysenter_eip
;
181 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
193 struct nested_state nested
;
196 u64 nmi_singlestep_guest_rflags
;
198 unsigned int3_injected
;
199 unsigned long int3_rip
;
201 /* cached guest cpuid flags for faster access */
202 bool nrips_enabled
: 1;
205 struct page
*avic_backing_page
;
206 u64
*avic_physical_id_cache
;
207 bool avic_is_running
;
210 * Per-vcpu list of struct amd_svm_iommu_ir:
211 * This is used mainly to store interrupt remapping information used
212 * when update the vcpu affinity. This avoids the need to scan for
213 * IRTE and try to match ga_tag in the IOMMU driver.
215 struct list_head ir_list
;
216 spinlock_t ir_list_lock
;
220 * This is a wrapper of struct amd_iommu_ir_data.
222 struct amd_svm_iommu_ir
{
223 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
224 void *data
; /* Storing pointer to struct amd_ir_data */
227 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
228 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
230 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
231 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
232 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
233 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
235 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
236 #define TSC_RATIO_DEFAULT 0x0100000000ULL
238 #define MSR_INVALID 0xffffffffU
240 static const struct svm_direct_access_msrs
{
241 u32 index
; /* Index of the MSR */
242 bool always
; /* True if intercept is always on */
243 } direct_access_msrs
[] = {
244 { .index
= MSR_STAR
, .always
= true },
245 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
247 { .index
= MSR_GS_BASE
, .always
= true },
248 { .index
= MSR_FS_BASE
, .always
= true },
249 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
250 { .index
= MSR_LSTAR
, .always
= true },
251 { .index
= MSR_CSTAR
, .always
= true },
252 { .index
= MSR_SYSCALL_MASK
, .always
= true },
254 { .index
= MSR_IA32_SPEC_CTRL
, .always
= true },
255 { .index
= MSR_IA32_PRED_CMD
, .always
= true },
256 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
257 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
258 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
259 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
260 { .index
= MSR_INVALID
, .always
= false },
263 /* enable NPT for AMD64 and X86 with PAE */
264 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
265 static bool npt_enabled
= true;
267 static bool npt_enabled
;
270 /* allow nested paging (virtualized MMU) for all guests */
271 static int npt
= true;
272 module_param(npt
, int, S_IRUGO
);
274 /* allow nested virtualization in KVM/SVM */
275 static int nested
= true;
276 module_param(nested
, int, S_IRUGO
);
278 /* enable / disable AVIC */
280 #ifdef CONFIG_X86_LOCAL_APIC
281 module_param(avic
, int, S_IRUGO
);
284 /* enable/disable Virtual VMLOAD VMSAVE */
285 static int vls
= true;
286 module_param(vls
, int, 0444);
288 /* AVIC VM ID bit masks and lock */
289 static DECLARE_BITMAP(avic_vm_id_bitmap
, AVIC_VM_ID_NR
);
290 static DEFINE_SPINLOCK(avic_vm_id_lock
);
292 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
293 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
294 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
296 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
297 static int nested_svm_intercept(struct vcpu_svm
*svm
);
298 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
299 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
300 bool has_error_code
, u32 error_code
);
303 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
304 pause filter count */
305 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
306 VMCB_ASID
, /* ASID */
307 VMCB_INTR
, /* int_ctl, int_vector */
308 VMCB_NPT
, /* npt_en, nCR3, gPAT */
309 VMCB_CR
, /* CR0, CR3, CR4, EFER */
310 VMCB_DR
, /* DR6, DR7 */
311 VMCB_DT
, /* GDT, IDT */
312 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
313 VMCB_CR2
, /* CR2 only */
314 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
315 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
316 * AVIC PHYSICAL_TABLE pointer,
317 * AVIC LOGICAL_TABLE pointer
322 /* TPR and CR2 are always written before VMRUN */
323 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
325 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
327 static inline void mark_all_dirty(struct vmcb
*vmcb
)
329 vmcb
->control
.clean
= 0;
332 static inline void mark_all_clean(struct vmcb
*vmcb
)
334 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
335 & ~VMCB_ALWAYS_DIRTY_MASK
;
338 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
340 vmcb
->control
.clean
&= ~(1 << bit
);
343 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
345 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
348 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
350 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
351 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
354 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
356 struct vcpu_svm
*svm
= to_svm(vcpu
);
357 u64
*entry
= svm
->avic_physical_id_cache
;
362 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
365 static void recalc_intercepts(struct vcpu_svm
*svm
)
367 struct vmcb_control_area
*c
, *h
;
368 struct nested_state
*g
;
370 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
372 if (!is_guest_mode(&svm
->vcpu
))
375 c
= &svm
->vmcb
->control
;
376 h
= &svm
->nested
.hsave
->control
;
379 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
380 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
381 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
382 c
->intercept
= h
->intercept
| g
->intercept
;
385 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
387 if (is_guest_mode(&svm
->vcpu
))
388 return svm
->nested
.hsave
;
393 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
395 struct vmcb
*vmcb
= get_host_vmcb(svm
);
397 vmcb
->control
.intercept_cr
|= (1U << bit
);
399 recalc_intercepts(svm
);
402 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
404 struct vmcb
*vmcb
= get_host_vmcb(svm
);
406 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
408 recalc_intercepts(svm
);
411 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
413 struct vmcb
*vmcb
= get_host_vmcb(svm
);
415 return vmcb
->control
.intercept_cr
& (1U << bit
);
418 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
420 struct vmcb
*vmcb
= get_host_vmcb(svm
);
422 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
423 | (1 << INTERCEPT_DR1_READ
)
424 | (1 << INTERCEPT_DR2_READ
)
425 | (1 << INTERCEPT_DR3_READ
)
426 | (1 << INTERCEPT_DR4_READ
)
427 | (1 << INTERCEPT_DR5_READ
)
428 | (1 << INTERCEPT_DR6_READ
)
429 | (1 << INTERCEPT_DR7_READ
)
430 | (1 << INTERCEPT_DR0_WRITE
)
431 | (1 << INTERCEPT_DR1_WRITE
)
432 | (1 << INTERCEPT_DR2_WRITE
)
433 | (1 << INTERCEPT_DR3_WRITE
)
434 | (1 << INTERCEPT_DR4_WRITE
)
435 | (1 << INTERCEPT_DR5_WRITE
)
436 | (1 << INTERCEPT_DR6_WRITE
)
437 | (1 << INTERCEPT_DR7_WRITE
);
439 recalc_intercepts(svm
);
442 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
444 struct vmcb
*vmcb
= get_host_vmcb(svm
);
446 vmcb
->control
.intercept_dr
= 0;
448 recalc_intercepts(svm
);
451 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
453 struct vmcb
*vmcb
= get_host_vmcb(svm
);
455 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
457 recalc_intercepts(svm
);
460 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
462 struct vmcb
*vmcb
= get_host_vmcb(svm
);
464 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
466 recalc_intercepts(svm
);
469 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
471 struct vmcb
*vmcb
= get_host_vmcb(svm
);
473 vmcb
->control
.intercept
|= (1ULL << bit
);
475 recalc_intercepts(svm
);
478 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
480 struct vmcb
*vmcb
= get_host_vmcb(svm
);
482 vmcb
->control
.intercept
&= ~(1ULL << bit
);
484 recalc_intercepts(svm
);
487 static inline void enable_gif(struct vcpu_svm
*svm
)
489 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
492 static inline void disable_gif(struct vcpu_svm
*svm
)
494 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
497 static inline bool gif_set(struct vcpu_svm
*svm
)
499 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
502 static unsigned long iopm_base
;
504 struct kvm_ldttss_desc
{
507 unsigned base1
:8, type
:5, dpl
:2, p
:1;
508 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
511 } __attribute__((packed
));
513 struct svm_cpu_data
{
519 struct kvm_ldttss_desc
*tss_desc
;
521 struct page
*save_area
;
523 struct vmcb
*current_vmcb
;
526 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
528 struct svm_init_data
{
533 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
535 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
536 #define MSRS_RANGE_SIZE 2048
537 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
539 static u32
svm_msrpm_offset(u32 msr
)
544 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
545 if (msr
< msrpm_ranges
[i
] ||
546 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
549 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
550 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
552 /* Now we have the u8 offset - but need the u32 offset */
556 /* MSR not in any range */
560 #define MAX_INST_SIZE 15
562 static inline void clgi(void)
564 asm volatile (__ex(SVM_CLGI
));
567 static inline void stgi(void)
569 asm volatile (__ex(SVM_STGI
));
572 static inline void invlpga(unsigned long addr
, u32 asid
)
574 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
577 static int get_npt_level(void)
580 return PT64_ROOT_LEVEL
;
582 return PT32E_ROOT_LEVEL
;
586 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
588 vcpu
->arch
.efer
= efer
;
589 if (!npt_enabled
&& !(efer
& EFER_LMA
))
592 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
593 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
596 static int is_external_interrupt(u32 info
)
598 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
599 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
602 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
604 struct vcpu_svm
*svm
= to_svm(vcpu
);
607 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
608 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
612 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
614 struct vcpu_svm
*svm
= to_svm(vcpu
);
617 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
619 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
623 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
625 struct vcpu_svm
*svm
= to_svm(vcpu
);
627 if (svm
->vmcb
->control
.next_rip
!= 0) {
628 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
629 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
632 if (!svm
->next_rip
) {
633 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
635 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
638 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
639 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
640 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
642 kvm_rip_write(vcpu
, svm
->next_rip
);
643 svm_set_interrupt_shadow(vcpu
, 0);
646 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
648 struct vcpu_svm
*svm
= to_svm(vcpu
);
649 unsigned nr
= vcpu
->arch
.exception
.nr
;
650 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
651 bool reinject
= vcpu
->arch
.exception
.reinject
;
652 u32 error_code
= vcpu
->arch
.exception
.error_code
;
655 * If we are within a nested VM we'd better #VMEXIT and let the guest
656 * handle the exception
659 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
662 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
663 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
666 * For guest debugging where we have to reinject #BP if some
667 * INT3 is guest-owned:
668 * Emulate nRIP by moving RIP forward. Will fail if injection
669 * raises a fault that is not intercepted. Still better than
670 * failing in all cases.
672 skip_emulated_instruction(&svm
->vcpu
);
673 rip
= kvm_rip_read(&svm
->vcpu
);
674 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
675 svm
->int3_injected
= rip
- old_rip
;
678 svm
->vmcb
->control
.event_inj
= nr
680 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
681 | SVM_EVTINJ_TYPE_EXEPT
;
682 svm
->vmcb
->control
.event_inj_err
= error_code
;
685 static void svm_init_erratum_383(void)
691 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
694 /* Use _safe variants to not break nested virtualization */
695 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
701 low
= lower_32_bits(val
);
702 high
= upper_32_bits(val
);
704 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
706 erratum_383_found
= true;
709 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
712 * Guests should see errata 400 and 415 as fixed (assuming that
713 * HLT and IO instructions are intercepted).
715 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
716 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
719 * By increasing VCPU's osvw.length to 3 we are telling the guest that
720 * all osvw.status bits inside that length, including bit 0 (which is
721 * reserved for erratum 298), are valid. However, if host processor's
722 * osvw_len is 0 then osvw_status[0] carries no information. We need to
723 * be conservative here and therefore we tell the guest that erratum 298
724 * is present (because we really don't know).
726 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
727 vcpu
->arch
.osvw
.status
|= 1;
730 static int has_svm(void)
734 if (!cpu_has_svm(&msg
)) {
735 printk(KERN_INFO
"has_svm: %s\n", msg
);
742 static void svm_hardware_disable(void)
744 /* Make sure we clean up behind us */
745 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
746 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
750 amd_pmu_disable_virt();
753 static int svm_hardware_enable(void)
756 struct svm_cpu_data
*sd
;
758 struct desc_struct
*gdt
;
759 int me
= raw_smp_processor_id();
761 rdmsrl(MSR_EFER
, efer
);
762 if (efer
& EFER_SVME
)
766 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
769 sd
= per_cpu(svm_data
, me
);
771 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
775 sd
->asid_generation
= 1;
776 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
777 sd
->next_asid
= sd
->max_asid
+ 1;
779 gdt
= get_current_gdt_rw();
780 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
782 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
784 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
786 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
787 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
788 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
795 * Note that it is possible to have a system with mixed processor
796 * revisions and therefore different OSVW bits. If bits are not the same
797 * on different processors then choose the worst case (i.e. if erratum
798 * is present on one processor and not on another then assume that the
799 * erratum is present everywhere).
801 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
802 uint64_t len
, status
= 0;
805 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
807 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
811 osvw_status
= osvw_len
= 0;
815 osvw_status
|= status
;
816 osvw_status
&= (1ULL << osvw_len
) - 1;
819 osvw_status
= osvw_len
= 0;
821 svm_init_erratum_383();
823 amd_pmu_enable_virt();
828 static void svm_cpu_uninit(int cpu
)
830 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
835 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
836 __free_page(sd
->save_area
);
840 static int svm_cpu_init(int cpu
)
842 struct svm_cpu_data
*sd
;
845 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
849 sd
->save_area
= alloc_page(GFP_KERNEL
);
854 per_cpu(svm_data
, cpu
) = sd
;
864 static bool valid_msr_intercept(u32 index
)
868 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
869 if (direct_access_msrs
[i
].index
== index
)
875 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
878 u8 bit_read
, bit_write
;
883 * If this warning triggers extend the direct_access_msrs list at the
884 * beginning of the file
886 WARN_ON(!valid_msr_intercept(msr
));
888 offset
= svm_msrpm_offset(msr
);
889 bit_read
= 2 * (msr
& 0x0f);
890 bit_write
= 2 * (msr
& 0x0f) + 1;
893 BUG_ON(offset
== MSR_INVALID
);
895 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
896 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
901 static void svm_vcpu_init_msrpm(u32
*msrpm
)
905 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
907 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
908 if (!direct_access_msrs
[i
].always
)
911 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
915 static void add_msr_offset(u32 offset
)
919 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
921 /* Offset already in list? */
922 if (msrpm_offsets
[i
] == offset
)
925 /* Slot used by another offset? */
926 if (msrpm_offsets
[i
] != MSR_INVALID
)
929 /* Add offset to list */
930 msrpm_offsets
[i
] = offset
;
936 * If this BUG triggers the msrpm_offsets table has an overflow. Just
937 * increase MSRPM_OFFSETS in this case.
942 static void init_msrpm_offsets(void)
946 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
948 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
951 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
952 BUG_ON(offset
== MSR_INVALID
);
954 add_msr_offset(offset
);
958 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
960 u32
*msrpm
= svm
->msrpm
;
962 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
963 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
964 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
965 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
966 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
969 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
971 u32
*msrpm
= svm
->msrpm
;
973 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
974 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
975 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
976 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
977 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
980 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
982 svm
->nmi_singlestep
= false;
983 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
984 /* Clear our flags if they were not set by the guest */
985 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
986 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
987 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
988 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
993 * This hash table is used to map VM_ID to a struct kvm_arch,
994 * when handling AMD IOMMU GALOG notification to schedule in
997 #define SVM_VM_DATA_HASH_BITS 8
998 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
999 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1002 * This function is called from IOMMU driver to notify
1003 * SVM to schedule in a particular vCPU of a particular VM.
1005 static int avic_ga_log_notifier(u32 ga_tag
)
1007 unsigned long flags
;
1008 struct kvm_arch
*ka
= NULL
;
1009 struct kvm_vcpu
*vcpu
= NULL
;
1010 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1011 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1013 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1015 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1016 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
1017 struct kvm
*kvm
= container_of(ka
, struct kvm
, arch
);
1018 struct kvm_arch
*vm_data
= &kvm
->arch
;
1020 if (vm_data
->avic_vm_id
!= vm_id
)
1022 vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
1025 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1031 * At this point, the IOMMU should have already set the pending
1032 * bit in the vAPIC backing page. So, we just need to schedule
1035 if (vcpu
->mode
== OUTSIDE_GUEST_MODE
)
1036 kvm_vcpu_wake_up(vcpu
);
1041 static __init
int svm_hardware_setup(void)
1044 struct page
*iopm_pages
;
1048 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1053 iopm_va
= page_address(iopm_pages
);
1054 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1055 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1057 init_msrpm_offsets();
1059 if (boot_cpu_has(X86_FEATURE_NX
))
1060 kvm_enable_efer_bits(EFER_NX
);
1062 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1063 kvm_enable_efer_bits(EFER_FFXSR
);
1065 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1066 kvm_has_tsc_control
= true;
1067 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1068 kvm_tsc_scaling_ratio_frac_bits
= 32;
1072 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1073 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1076 for_each_possible_cpu(cpu
) {
1077 r
= svm_cpu_init(cpu
);
1082 if (!boot_cpu_has(X86_FEATURE_NPT
))
1083 npt_enabled
= false;
1085 if (npt_enabled
&& !npt
) {
1086 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1087 npt_enabled
= false;
1091 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1098 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1099 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1102 pr_info("AVIC enabled\n");
1104 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1110 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1111 !IS_ENABLED(CONFIG_X86_64
)) {
1114 pr_info("Virtual VMLOAD VMSAVE supported\n");
1121 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1126 static __exit
void svm_hardware_unsetup(void)
1130 for_each_possible_cpu(cpu
)
1131 svm_cpu_uninit(cpu
);
1133 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1137 static void init_seg(struct vmcb_seg
*seg
)
1140 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1141 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1142 seg
->limit
= 0xffff;
1146 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1149 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1150 seg
->limit
= 0xffff;
1154 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1156 struct vcpu_svm
*svm
= to_svm(vcpu
);
1157 u64 g_tsc_offset
= 0;
1159 if (is_guest_mode(vcpu
)) {
1160 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1161 svm
->nested
.hsave
->control
.tsc_offset
;
1162 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1164 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1165 svm
->vmcb
->control
.tsc_offset
,
1168 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1170 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1173 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1175 struct vmcb
*vmcb
= svm
->vmcb
;
1176 struct kvm_arch
*vm_data
= &svm
->vcpu
.kvm
->arch
;
1177 phys_addr_t bpa
= page_to_phys(svm
->avic_backing_page
);
1178 phys_addr_t lpa
= page_to_phys(vm_data
->avic_logical_id_table_page
);
1179 phys_addr_t ppa
= page_to_phys(vm_data
->avic_physical_id_table_page
);
1181 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1182 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1183 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1184 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1185 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1186 svm
->vcpu
.arch
.apicv_active
= true;
1189 static void init_vmcb(struct vcpu_svm
*svm
)
1191 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1192 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1194 svm
->vcpu
.arch
.hflags
= 0;
1196 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1197 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1198 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1199 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1200 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1201 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1202 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1203 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1205 set_dr_intercepts(svm
);
1207 set_exception_intercept(svm
, PF_VECTOR
);
1208 set_exception_intercept(svm
, UD_VECTOR
);
1209 set_exception_intercept(svm
, MC_VECTOR
);
1210 set_exception_intercept(svm
, AC_VECTOR
);
1211 set_exception_intercept(svm
, DB_VECTOR
);
1213 set_intercept(svm
, INTERCEPT_INTR
);
1214 set_intercept(svm
, INTERCEPT_NMI
);
1215 set_intercept(svm
, INTERCEPT_SMI
);
1216 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1217 set_intercept(svm
, INTERCEPT_RDPMC
);
1218 set_intercept(svm
, INTERCEPT_CPUID
);
1219 set_intercept(svm
, INTERCEPT_INVD
);
1220 set_intercept(svm
, INTERCEPT_HLT
);
1221 set_intercept(svm
, INTERCEPT_INVLPG
);
1222 set_intercept(svm
, INTERCEPT_INVLPGA
);
1223 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1224 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1225 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1226 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1227 set_intercept(svm
, INTERCEPT_VMRUN
);
1228 set_intercept(svm
, INTERCEPT_VMMCALL
);
1229 set_intercept(svm
, INTERCEPT_VMLOAD
);
1230 set_intercept(svm
, INTERCEPT_VMSAVE
);
1231 set_intercept(svm
, INTERCEPT_STGI
);
1232 set_intercept(svm
, INTERCEPT_CLGI
);
1233 set_intercept(svm
, INTERCEPT_SKINIT
);
1234 set_intercept(svm
, INTERCEPT_WBINVD
);
1235 set_intercept(svm
, INTERCEPT_XSETBV
);
1237 if (!kvm_mwait_in_guest()) {
1238 set_intercept(svm
, INTERCEPT_MONITOR
);
1239 set_intercept(svm
, INTERCEPT_MWAIT
);
1242 control
->iopm_base_pa
= iopm_base
;
1243 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1244 control
->int_ctl
= V_INTR_MASKING_MASK
;
1246 init_seg(&save
->es
);
1247 init_seg(&save
->ss
);
1248 init_seg(&save
->ds
);
1249 init_seg(&save
->fs
);
1250 init_seg(&save
->gs
);
1252 save
->cs
.selector
= 0xf000;
1253 save
->cs
.base
= 0xffff0000;
1254 /* Executable/Readable Code Segment */
1255 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1256 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1257 save
->cs
.limit
= 0xffff;
1259 save
->gdtr
.limit
= 0xffff;
1260 save
->idtr
.limit
= 0xffff;
1262 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1263 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1265 svm_set_efer(&svm
->vcpu
, 0);
1266 save
->dr6
= 0xffff0ff0;
1267 kvm_set_rflags(&svm
->vcpu
, 2);
1268 save
->rip
= 0x0000fff0;
1269 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1272 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1273 * It also updates the guest-visible cr0 value.
1275 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1276 kvm_mmu_reset_context(&svm
->vcpu
);
1278 save
->cr4
= X86_CR4_PAE
;
1282 /* Setup VMCB for Nested Paging */
1283 control
->nested_ctl
= 1;
1284 clr_intercept(svm
, INTERCEPT_INVLPG
);
1285 clr_exception_intercept(svm
, PF_VECTOR
);
1286 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1287 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1288 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1292 svm
->asid_generation
= 0;
1294 svm
->nested
.vmcb
= 0;
1295 svm
->vcpu
.arch
.hflags
= 0;
1297 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1298 control
->pause_filter_count
= 3000;
1299 set_intercept(svm
, INTERCEPT_PAUSE
);
1303 avic_init_vmcb(svm
);
1306 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1307 * in VMCB and clear intercepts to avoid #VMEXIT.
1310 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1311 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1312 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1315 mark_all_dirty(svm
->vmcb
);
1321 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1324 u64
*avic_physical_id_table
;
1325 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
1327 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1330 avic_physical_id_table
= page_address(vm_data
->avic_physical_id_table_page
);
1332 return &avic_physical_id_table
[index
];
1337 * AVIC hardware walks the nested page table to check permissions,
1338 * but does not use the SPA address specified in the leaf page
1339 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1340 * field of the VMCB. Therefore, we set up the
1341 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1343 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1345 struct kvm
*kvm
= vcpu
->kvm
;
1348 if (kvm
->arch
.apic_access_page_done
)
1351 ret
= x86_set_memory_region(kvm
,
1352 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1353 APIC_DEFAULT_PHYS_BASE
,
1358 kvm
->arch
.apic_access_page_done
= true;
1362 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1365 u64
*entry
, new_entry
;
1366 int id
= vcpu
->vcpu_id
;
1367 struct vcpu_svm
*svm
= to_svm(vcpu
);
1369 ret
= avic_init_access_page(vcpu
);
1373 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1376 if (!svm
->vcpu
.arch
.apic
->regs
)
1379 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1381 /* Setting AVIC backing page address in the phy APIC ID table */
1382 entry
= avic_get_physical_id_entry(vcpu
, id
);
1386 new_entry
= READ_ONCE(*entry
);
1387 new_entry
= (page_to_phys(svm
->avic_backing_page
) &
1388 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1389 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
;
1390 WRITE_ONCE(*entry
, new_entry
);
1392 svm
->avic_physical_id_cache
= entry
;
1397 static inline int avic_get_next_vm_id(void)
1401 spin_lock(&avic_vm_id_lock
);
1403 /* AVIC VM ID is one-based. */
1404 id
= find_next_zero_bit(avic_vm_id_bitmap
, AVIC_VM_ID_NR
, 1);
1405 if (id
<= AVIC_VM_ID_MASK
)
1406 __set_bit(id
, avic_vm_id_bitmap
);
1410 spin_unlock(&avic_vm_id_lock
);
1414 static inline int avic_free_vm_id(int id
)
1416 if (id
<= 0 || id
> AVIC_VM_ID_MASK
)
1419 spin_lock(&avic_vm_id_lock
);
1420 __clear_bit(id
, avic_vm_id_bitmap
);
1421 spin_unlock(&avic_vm_id_lock
);
1425 static void avic_vm_destroy(struct kvm
*kvm
)
1427 unsigned long flags
;
1428 struct kvm_arch
*vm_data
= &kvm
->arch
;
1433 avic_free_vm_id(vm_data
->avic_vm_id
);
1435 if (vm_data
->avic_logical_id_table_page
)
1436 __free_page(vm_data
->avic_logical_id_table_page
);
1437 if (vm_data
->avic_physical_id_table_page
)
1438 __free_page(vm_data
->avic_physical_id_table_page
);
1440 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1441 hash_del(&vm_data
->hnode
);
1442 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1445 static int avic_vm_init(struct kvm
*kvm
)
1447 unsigned long flags
;
1448 int vm_id
, err
= -ENOMEM
;
1449 struct kvm_arch
*vm_data
= &kvm
->arch
;
1450 struct page
*p_page
;
1451 struct page
*l_page
;
1456 vm_id
= avic_get_next_vm_id();
1459 vm_data
->avic_vm_id
= (u32
)vm_id
;
1461 /* Allocating physical APIC ID table (4KB) */
1462 p_page
= alloc_page(GFP_KERNEL
);
1466 vm_data
->avic_physical_id_table_page
= p_page
;
1467 clear_page(page_address(p_page
));
1469 /* Allocating logical APIC ID table (4KB) */
1470 l_page
= alloc_page(GFP_KERNEL
);
1474 vm_data
->avic_logical_id_table_page
= l_page
;
1475 clear_page(page_address(l_page
));
1477 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1478 hash_add(svm_vm_data_hash
, &vm_data
->hnode
, vm_data
->avic_vm_id
);
1479 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1484 avic_vm_destroy(kvm
);
1489 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1492 unsigned long flags
;
1493 struct amd_svm_iommu_ir
*ir
;
1494 struct vcpu_svm
*svm
= to_svm(vcpu
);
1496 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1500 * Here, we go through the per-vcpu ir_list to update all existing
1501 * interrupt remapping table entry targeting this vcpu.
1503 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1505 if (list_empty(&svm
->ir_list
))
1508 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1509 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
1514 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
1518 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1521 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1522 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
1523 struct vcpu_svm
*svm
= to_svm(vcpu
);
1525 if (!kvm_vcpu_apicv_active(vcpu
))
1528 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
1531 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1532 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
1534 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
1535 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
1537 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1538 if (svm
->avic_is_running
)
1539 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1541 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1542 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
1543 svm
->avic_is_running
);
1546 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
1549 struct vcpu_svm
*svm
= to_svm(vcpu
);
1551 if (!kvm_vcpu_apicv_active(vcpu
))
1554 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1555 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
1556 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
1558 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1559 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1563 * This function is called during VCPU halt/unhalt.
1565 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
1567 struct vcpu_svm
*svm
= to_svm(vcpu
);
1569 svm
->avic_is_running
= is_run
;
1571 avic_vcpu_load(vcpu
, vcpu
->cpu
);
1573 avic_vcpu_put(vcpu
);
1576 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1578 struct vcpu_svm
*svm
= to_svm(vcpu
);
1583 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1584 MSR_IA32_APICBASE_ENABLE
;
1585 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1586 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1590 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
);
1591 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1593 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1594 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1597 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1599 struct vcpu_svm
*svm
;
1601 struct page
*msrpm_pages
;
1602 struct page
*hsave_page
;
1603 struct page
*nested_msrpm_pages
;
1606 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1612 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1617 page
= alloc_page(GFP_KERNEL
);
1621 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1625 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1626 if (!nested_msrpm_pages
)
1629 hsave_page
= alloc_page(GFP_KERNEL
);
1634 err
= avic_init_backing_page(&svm
->vcpu
);
1638 INIT_LIST_HEAD(&svm
->ir_list
);
1639 spin_lock_init(&svm
->ir_list_lock
);
1642 /* We initialize this flag to true to make sure that the is_running
1643 * bit would be set the first time the vcpu is loaded.
1645 svm
->avic_is_running
= true;
1647 svm
->nested
.hsave
= page_address(hsave_page
);
1649 svm
->msrpm
= page_address(msrpm_pages
);
1650 svm_vcpu_init_msrpm(svm
->msrpm
);
1652 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1653 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1655 svm
->vmcb
= page_address(page
);
1656 clear_page(svm
->vmcb
);
1657 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1658 svm
->asid_generation
= 0;
1661 svm_init_osvw(&svm
->vcpu
);
1666 __free_page(hsave_page
);
1668 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1670 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1674 kvm_vcpu_uninit(&svm
->vcpu
);
1676 kmem_cache_free(kvm_vcpu_cache
, svm
);
1678 return ERR_PTR(err
);
1681 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1683 struct vcpu_svm
*svm
= to_svm(vcpu
);
1685 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1686 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1687 __free_page(virt_to_page(svm
->nested
.hsave
));
1688 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1689 kvm_vcpu_uninit(vcpu
);
1690 kmem_cache_free(kvm_vcpu_cache
, svm
);
1693 * The VMCB could be recycled, causing a false negative in svm_vcpu_load;
1694 * block speculative execution.
1697 wrmsrl(MSR_IA32_PRED_CMD
, FEATURE_SET_IBPB
);
1700 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1702 struct vcpu_svm
*svm
= to_svm(vcpu
);
1703 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
1706 if (unlikely(cpu
!= vcpu
->cpu
)) {
1707 svm
->asid_generation
= 0;
1708 mark_all_dirty(svm
->vmcb
);
1711 #ifdef CONFIG_X86_64
1712 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1714 savesegment(fs
, svm
->host
.fs
);
1715 savesegment(gs
, svm
->host
.gs
);
1716 svm
->host
.ldt
= kvm_read_ldt();
1718 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1719 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1721 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1722 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1723 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1724 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1725 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1728 /* This assumes that the kernel never uses MSR_TSC_AUX */
1729 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1730 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
1732 if (sd
->current_vmcb
!= svm
->vmcb
) {
1733 sd
->current_vmcb
= svm
->vmcb
;
1735 wrmsrl(MSR_IA32_PRED_CMD
, FEATURE_SET_IBPB
);
1738 avic_vcpu_load(vcpu
, cpu
);
1741 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1743 struct vcpu_svm
*svm
= to_svm(vcpu
);
1746 avic_vcpu_put(vcpu
);
1748 ++vcpu
->stat
.host_state_reload
;
1749 kvm_load_ldt(svm
->host
.ldt
);
1750 #ifdef CONFIG_X86_64
1751 loadsegment(fs
, svm
->host
.fs
);
1752 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
1753 load_gs_index(svm
->host
.gs
);
1755 #ifdef CONFIG_X86_32_LAZY_GS
1756 loadsegment(gs
, svm
->host
.gs
);
1759 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1760 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1763 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
1765 avic_set_running(vcpu
, false);
1768 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
1770 avic_set_running(vcpu
, true);
1773 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1775 struct vcpu_svm
*svm
= to_svm(vcpu
);
1776 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
1778 if (svm
->nmi_singlestep
) {
1779 /* Hide our flags if they were not set by the guest */
1780 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1781 rflags
&= ~X86_EFLAGS_TF
;
1782 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1783 rflags
&= ~X86_EFLAGS_RF
;
1788 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1790 if (to_svm(vcpu
)->nmi_singlestep
)
1791 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1794 * Any change of EFLAGS.VM is accompanied by a reload of SS
1795 * (caused by either a task switch or an inter-privilege IRET),
1796 * so we do not need to update the CPL here.
1798 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1801 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1804 case VCPU_EXREG_PDPTR
:
1805 BUG_ON(!npt_enabled
);
1806 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1813 static void svm_set_vintr(struct vcpu_svm
*svm
)
1815 set_intercept(svm
, INTERCEPT_VINTR
);
1818 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1820 clr_intercept(svm
, INTERCEPT_VINTR
);
1823 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1825 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1828 case VCPU_SREG_CS
: return &save
->cs
;
1829 case VCPU_SREG_DS
: return &save
->ds
;
1830 case VCPU_SREG_ES
: return &save
->es
;
1831 case VCPU_SREG_FS
: return &save
->fs
;
1832 case VCPU_SREG_GS
: return &save
->gs
;
1833 case VCPU_SREG_SS
: return &save
->ss
;
1834 case VCPU_SREG_TR
: return &save
->tr
;
1835 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1841 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1843 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1848 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1849 struct kvm_segment
*var
, int seg
)
1851 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1853 var
->base
= s
->base
;
1854 var
->limit
= s
->limit
;
1855 var
->selector
= s
->selector
;
1856 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1857 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1858 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1859 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1860 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1861 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1862 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1865 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1866 * However, the SVM spec states that the G bit is not observed by the
1867 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1868 * So let's synthesize a legal G bit for all segments, this helps
1869 * running KVM nested. It also helps cross-vendor migration, because
1870 * Intel's vmentry has a check on the 'G' bit.
1872 var
->g
= s
->limit
> 0xfffff;
1875 * AMD's VMCB does not have an explicit unusable field, so emulate it
1876 * for cross vendor migration purposes by "not present"
1878 var
->unusable
= !var
->present
;
1883 * Work around a bug where the busy flag in the tr selector
1893 * The accessed bit must always be set in the segment
1894 * descriptor cache, although it can be cleared in the
1895 * descriptor, the cached bit always remains at 1. Since
1896 * Intel has a check on this, set it here to support
1897 * cross-vendor migration.
1904 * On AMD CPUs sometimes the DB bit in the segment
1905 * descriptor is left as 1, although the whole segment has
1906 * been made unusable. Clear it here to pass an Intel VMX
1907 * entry check when cross vendor migrating.
1911 /* This is symmetric with svm_set_segment() */
1912 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1917 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1919 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1924 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1926 struct vcpu_svm
*svm
= to_svm(vcpu
);
1928 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1929 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1932 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1934 struct vcpu_svm
*svm
= to_svm(vcpu
);
1936 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1937 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1938 mark_dirty(svm
->vmcb
, VMCB_DT
);
1941 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1943 struct vcpu_svm
*svm
= to_svm(vcpu
);
1945 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1946 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1949 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1951 struct vcpu_svm
*svm
= to_svm(vcpu
);
1953 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1954 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1955 mark_dirty(svm
->vmcb
, VMCB_DT
);
1958 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1962 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1966 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1970 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1972 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1973 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1975 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1976 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1978 mark_dirty(svm
->vmcb
, VMCB_CR
);
1980 if (gcr0
== *hcr0
) {
1981 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1982 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1984 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1985 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1989 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1991 struct vcpu_svm
*svm
= to_svm(vcpu
);
1993 #ifdef CONFIG_X86_64
1994 if (vcpu
->arch
.efer
& EFER_LME
) {
1995 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1996 vcpu
->arch
.efer
|= EFER_LMA
;
1997 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2000 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2001 vcpu
->arch
.efer
&= ~EFER_LMA
;
2002 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2006 vcpu
->arch
.cr0
= cr0
;
2009 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2012 * re-enable caching here because the QEMU bios
2013 * does not do it - this results in some delay at
2016 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2017 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2018 svm
->vmcb
->save
.cr0
= cr0
;
2019 mark_dirty(svm
->vmcb
, VMCB_CR
);
2020 update_cr0_intercept(svm
);
2023 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2025 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2026 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2028 if (cr4
& X86_CR4_VMXE
)
2031 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2032 svm_flush_tlb(vcpu
);
2034 vcpu
->arch
.cr4
= cr4
;
2037 cr4
|= host_cr4_mce
;
2038 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2039 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2043 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2044 struct kvm_segment
*var
, int seg
)
2046 struct vcpu_svm
*svm
= to_svm(vcpu
);
2047 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2049 s
->base
= var
->base
;
2050 s
->limit
= var
->limit
;
2051 s
->selector
= var
->selector
;
2052 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2053 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2054 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2055 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2056 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2057 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2058 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2059 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2062 * This is always accurate, except if SYSRET returned to a segment
2063 * with SS.DPL != 3. Intel does not have this quirk, and always
2064 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2065 * would entail passing the CPL to userspace and back.
2067 if (seg
== VCPU_SREG_SS
)
2068 /* This is symmetric with svm_get_segment() */
2069 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2071 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2074 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2076 struct vcpu_svm
*svm
= to_svm(vcpu
);
2078 clr_exception_intercept(svm
, BP_VECTOR
);
2080 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2081 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2082 set_exception_intercept(svm
, BP_VECTOR
);
2084 vcpu
->guest_debug
= 0;
2087 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2089 if (sd
->next_asid
> sd
->max_asid
) {
2090 ++sd
->asid_generation
;
2092 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2095 svm
->asid_generation
= sd
->asid_generation
;
2096 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2098 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2101 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2103 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2106 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2108 struct vcpu_svm
*svm
= to_svm(vcpu
);
2110 svm
->vmcb
->save
.dr6
= value
;
2111 mark_dirty(svm
->vmcb
, VMCB_DR
);
2114 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2116 struct vcpu_svm
*svm
= to_svm(vcpu
);
2118 get_debugreg(vcpu
->arch
.db
[0], 0);
2119 get_debugreg(vcpu
->arch
.db
[1], 1);
2120 get_debugreg(vcpu
->arch
.db
[2], 2);
2121 get_debugreg(vcpu
->arch
.db
[3], 3);
2122 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2123 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2125 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2126 set_dr_intercepts(svm
);
2129 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2131 struct vcpu_svm
*svm
= to_svm(vcpu
);
2133 svm
->vmcb
->save
.dr7
= value
;
2134 mark_dirty(svm
->vmcb
, VMCB_DR
);
2137 static int pf_interception(struct vcpu_svm
*svm
)
2139 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2140 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2142 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2143 svm
->vmcb
->control
.insn_bytes
,
2144 svm
->vmcb
->control
.insn_len
, !npt_enabled
);
2147 static int db_interception(struct vcpu_svm
*svm
)
2149 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2151 if (!(svm
->vcpu
.guest_debug
&
2152 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2153 !svm
->nmi_singlestep
) {
2154 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2158 if (svm
->nmi_singlestep
) {
2159 disable_nmi_singlestep(svm
);
2162 if (svm
->vcpu
.guest_debug
&
2163 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2164 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2165 kvm_run
->debug
.arch
.pc
=
2166 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2167 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2174 static int bp_interception(struct vcpu_svm
*svm
)
2176 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2178 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2179 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2180 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2184 static int ud_interception(struct vcpu_svm
*svm
)
2188 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
2189 if (er
!= EMULATE_DONE
)
2190 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2194 static int ac_interception(struct vcpu_svm
*svm
)
2196 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2200 static bool is_erratum_383(void)
2205 if (!erratum_383_found
)
2208 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2212 /* Bit 62 may or may not be set for this mce */
2213 value
&= ~(1ULL << 62);
2215 if (value
!= 0xb600000000010015ULL
)
2218 /* Clear MCi_STATUS registers */
2219 for (i
= 0; i
< 6; ++i
)
2220 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2222 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2226 value
&= ~(1ULL << 2);
2227 low
= lower_32_bits(value
);
2228 high
= upper_32_bits(value
);
2230 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2233 /* Flush tlb to evict multi-match entries */
2239 static void svm_handle_mce(struct vcpu_svm
*svm
)
2241 if (is_erratum_383()) {
2243 * Erratum 383 triggered. Guest state is corrupt so kill the
2246 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2248 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2254 * On an #MC intercept the MCE handler is not called automatically in
2255 * the host. So do it by hand here.
2259 /* not sure if we ever come back to this point */
2264 static int mc_interception(struct vcpu_svm
*svm
)
2269 static int shutdown_interception(struct vcpu_svm
*svm
)
2271 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2274 * VMCB is undefined after a SHUTDOWN intercept
2275 * so reinitialize it.
2277 clear_page(svm
->vmcb
);
2280 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2284 static int io_interception(struct vcpu_svm
*svm
)
2286 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2287 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2288 int size
, in
, string
, ret
;
2291 ++svm
->vcpu
.stat
.io_exits
;
2292 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2293 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2295 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2297 port
= io_info
>> 16;
2298 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2299 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2300 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2303 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2304 * KVM_EXIT_DEBUG here.
2307 return kvm_fast_pio_in(vcpu
, size
, port
) && ret
;
2309 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
2312 static int nmi_interception(struct vcpu_svm
*svm
)
2317 static int intr_interception(struct vcpu_svm
*svm
)
2319 ++svm
->vcpu
.stat
.irq_exits
;
2323 static int nop_on_interception(struct vcpu_svm
*svm
)
2328 static int halt_interception(struct vcpu_svm
*svm
)
2330 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2331 return kvm_emulate_halt(&svm
->vcpu
);
2334 static int vmmcall_interception(struct vcpu_svm
*svm
)
2336 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2337 return kvm_emulate_hypercall(&svm
->vcpu
);
2340 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2342 struct vcpu_svm
*svm
= to_svm(vcpu
);
2344 return svm
->nested
.nested_cr3
;
2347 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2349 struct vcpu_svm
*svm
= to_svm(vcpu
);
2350 u64 cr3
= svm
->nested
.nested_cr3
;
2354 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(cr3
), &pdpte
,
2355 offset_in_page(cr3
) + index
* 8, 8);
2361 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2364 struct vcpu_svm
*svm
= to_svm(vcpu
);
2366 svm
->vmcb
->control
.nested_cr3
= root
;
2367 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2368 svm_flush_tlb(vcpu
);
2371 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2372 struct x86_exception
*fault
)
2374 struct vcpu_svm
*svm
= to_svm(vcpu
);
2376 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2378 * TODO: track the cause of the nested page fault, and
2379 * correctly fill in the high bits of exit_info_1.
2381 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2382 svm
->vmcb
->control
.exit_code_hi
= 0;
2383 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2384 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2387 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2388 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2391 * The present bit is always zero for page structure faults on real
2394 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2395 svm
->vmcb
->control
.exit_info_1
&= ~1;
2397 nested_svm_vmexit(svm
);
2400 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2402 WARN_ON(mmu_is_nested(vcpu
));
2403 kvm_init_shadow_mmu(vcpu
);
2404 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2405 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2406 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2407 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2408 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
2409 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2410 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2413 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2415 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2418 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2420 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2421 !is_paging(&svm
->vcpu
)) {
2422 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2426 if (svm
->vmcb
->save
.cpl
) {
2427 kvm_inject_gp(&svm
->vcpu
, 0);
2434 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2435 bool has_error_code
, u32 error_code
)
2439 if (!is_guest_mode(&svm
->vcpu
))
2442 vmexit
= nested_svm_intercept(svm
);
2443 if (vmexit
!= NESTED_EXIT_DONE
)
2446 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2447 svm
->vmcb
->control
.exit_code_hi
= 0;
2448 svm
->vmcb
->control
.exit_info_1
= error_code
;
2451 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2452 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2453 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2454 * written only when inject_pending_event runs (DR6 would written here
2455 * too). This should be conditional on a new capability---if the
2456 * capability is disabled, kvm_multiple_exception would write the
2457 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2459 if (svm
->vcpu
.arch
.exception
.nested_apf
)
2460 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
2462 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2464 svm
->nested
.exit_required
= true;
2468 /* This function returns true if it is save to enable the irq window */
2469 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2471 if (!is_guest_mode(&svm
->vcpu
))
2474 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2477 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2481 * if vmexit was already requested (by intercepted exception
2482 * for instance) do not overwrite it with "external interrupt"
2485 if (svm
->nested
.exit_required
)
2488 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2489 svm
->vmcb
->control
.exit_info_1
= 0;
2490 svm
->vmcb
->control
.exit_info_2
= 0;
2492 if (svm
->nested
.intercept
& 1ULL) {
2494 * The #vmexit can't be emulated here directly because this
2495 * code path runs with irqs and preemption disabled. A
2496 * #vmexit emulation might sleep. Only signal request for
2499 svm
->nested
.exit_required
= true;
2500 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2507 /* This function returns true if it is save to enable the nmi window */
2508 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2510 if (!is_guest_mode(&svm
->vcpu
))
2513 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2516 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2517 svm
->nested
.exit_required
= true;
2522 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2528 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2529 if (is_error_page(page
))
2537 kvm_inject_gp(&svm
->vcpu
, 0);
2542 static void nested_svm_unmap(struct page
*page
)
2545 kvm_release_page_dirty(page
);
2548 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2550 unsigned port
, size
, iopm_len
;
2555 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2556 return NESTED_EXIT_HOST
;
2558 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2559 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2560 SVM_IOIO_SIZE_SHIFT
;
2561 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2562 start_bit
= port
% 8;
2563 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2564 mask
= (0xf >> (4 - size
)) << start_bit
;
2567 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2568 return NESTED_EXIT_DONE
;
2570 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2573 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2575 u32 offset
, msr
, value
;
2578 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2579 return NESTED_EXIT_HOST
;
2581 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2582 offset
= svm_msrpm_offset(msr
);
2583 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2584 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2586 if (offset
== MSR_INVALID
)
2587 return NESTED_EXIT_DONE
;
2589 /* Offset is in 32 bit units but need in 8 bit units */
2592 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2593 return NESTED_EXIT_DONE
;
2595 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2598 /* DB exceptions for our internal use must not cause vmexit */
2599 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
2603 /* if we're not singlestepping, it's not ours */
2604 if (!svm
->nmi_singlestep
)
2605 return NESTED_EXIT_DONE
;
2607 /* if it's not a singlestep exception, it's not ours */
2608 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
2609 return NESTED_EXIT_DONE
;
2610 if (!(dr6
& DR6_BS
))
2611 return NESTED_EXIT_DONE
;
2613 /* if the guest is singlestepping, it should get the vmexit */
2614 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
2615 disable_nmi_singlestep(svm
);
2616 return NESTED_EXIT_DONE
;
2619 /* it's ours, the nested hypervisor must not see this one */
2620 return NESTED_EXIT_HOST
;
2623 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2625 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2627 switch (exit_code
) {
2630 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2631 return NESTED_EXIT_HOST
;
2633 /* For now we are always handling NPFs when using them */
2635 return NESTED_EXIT_HOST
;
2637 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2638 /* When we're shadowing, trap PFs, but not async PF */
2639 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
2640 return NESTED_EXIT_HOST
;
2646 return NESTED_EXIT_CONTINUE
;
2650 * If this function returns true, this #vmexit was already handled
2652 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2654 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2655 int vmexit
= NESTED_EXIT_HOST
;
2657 switch (exit_code
) {
2659 vmexit
= nested_svm_exit_handled_msr(svm
);
2662 vmexit
= nested_svm_intercept_ioio(svm
);
2664 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2665 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2666 if (svm
->nested
.intercept_cr
& bit
)
2667 vmexit
= NESTED_EXIT_DONE
;
2670 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2671 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2672 if (svm
->nested
.intercept_dr
& bit
)
2673 vmexit
= NESTED_EXIT_DONE
;
2676 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2677 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2678 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
2679 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
2680 vmexit
= nested_svm_intercept_db(svm
);
2682 vmexit
= NESTED_EXIT_DONE
;
2684 /* async page fault always cause vmexit */
2685 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2686 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
2687 vmexit
= NESTED_EXIT_DONE
;
2690 case SVM_EXIT_ERR
: {
2691 vmexit
= NESTED_EXIT_DONE
;
2695 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2696 if (svm
->nested
.intercept
& exit_bits
)
2697 vmexit
= NESTED_EXIT_DONE
;
2704 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2708 vmexit
= nested_svm_intercept(svm
);
2710 if (vmexit
== NESTED_EXIT_DONE
)
2711 nested_svm_vmexit(svm
);
2716 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2718 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2719 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2721 dst
->intercept_cr
= from
->intercept_cr
;
2722 dst
->intercept_dr
= from
->intercept_dr
;
2723 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2724 dst
->intercept
= from
->intercept
;
2725 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2726 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2727 dst
->tsc_offset
= from
->tsc_offset
;
2728 dst
->asid
= from
->asid
;
2729 dst
->tlb_ctl
= from
->tlb_ctl
;
2730 dst
->int_ctl
= from
->int_ctl
;
2731 dst
->int_vector
= from
->int_vector
;
2732 dst
->int_state
= from
->int_state
;
2733 dst
->exit_code
= from
->exit_code
;
2734 dst
->exit_code_hi
= from
->exit_code_hi
;
2735 dst
->exit_info_1
= from
->exit_info_1
;
2736 dst
->exit_info_2
= from
->exit_info_2
;
2737 dst
->exit_int_info
= from
->exit_int_info
;
2738 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2739 dst
->nested_ctl
= from
->nested_ctl
;
2740 dst
->event_inj
= from
->event_inj
;
2741 dst
->event_inj_err
= from
->event_inj_err
;
2742 dst
->nested_cr3
= from
->nested_cr3
;
2743 dst
->virt_ext
= from
->virt_ext
;
2746 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2748 struct vmcb
*nested_vmcb
;
2749 struct vmcb
*hsave
= svm
->nested
.hsave
;
2750 struct vmcb
*vmcb
= svm
->vmcb
;
2753 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2754 vmcb
->control
.exit_info_1
,
2755 vmcb
->control
.exit_info_2
,
2756 vmcb
->control
.exit_int_info
,
2757 vmcb
->control
.exit_int_info_err
,
2760 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2764 /* Exit Guest-Mode */
2765 leave_guest_mode(&svm
->vcpu
);
2766 svm
->nested
.vmcb
= 0;
2768 /* Give the current vmcb to the guest */
2771 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2772 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2773 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2774 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2775 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2776 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2777 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2778 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2779 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2780 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2781 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2782 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2783 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2784 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2785 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2786 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2787 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2788 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2790 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2791 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2792 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2793 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2794 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2795 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2796 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2797 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2798 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2800 if (svm
->nrips_enabled
)
2801 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2804 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2805 * to make sure that we do not lose injected events. So check event_inj
2806 * here and copy it to exit_int_info if it is valid.
2807 * Exit_int_info and event_inj can't be both valid because the case
2808 * below only happens on a VMRUN instruction intercept which has
2809 * no valid exit_int_info set.
2811 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2812 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2814 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2815 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2818 nested_vmcb
->control
.tlb_ctl
= 0;
2819 nested_vmcb
->control
.event_inj
= 0;
2820 nested_vmcb
->control
.event_inj_err
= 0;
2822 /* We always set V_INTR_MASKING and remember the old value in hflags */
2823 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2824 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2826 /* Restore the original control entries */
2827 copy_vmcb_control_area(vmcb
, hsave
);
2829 kvm_clear_exception_queue(&svm
->vcpu
);
2830 kvm_clear_interrupt_queue(&svm
->vcpu
);
2832 svm
->nested
.nested_cr3
= 0;
2834 /* Restore selected save entries */
2835 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2836 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2837 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2838 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2839 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2840 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2841 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2842 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2843 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2844 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2846 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2847 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2849 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2851 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2852 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2853 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2854 svm
->vmcb
->save
.dr7
= 0;
2855 svm
->vmcb
->save
.cpl
= 0;
2856 svm
->vmcb
->control
.exit_int_info
= 0;
2858 mark_all_dirty(svm
->vmcb
);
2860 nested_svm_unmap(page
);
2862 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2863 kvm_mmu_reset_context(&svm
->vcpu
);
2864 kvm_mmu_load(&svm
->vcpu
);
2869 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2872 * This function merges the msr permission bitmaps of kvm and the
2873 * nested vmcb. It is optimized in that it only merges the parts where
2874 * the kvm msr permission bitmap may contain zero bits
2878 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2881 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2885 if (msrpm_offsets
[i
] == 0xffffffff)
2888 p
= msrpm_offsets
[i
];
2889 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2891 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2894 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2897 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2902 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2904 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2907 if (vmcb
->control
.asid
== 0)
2910 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2916 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2918 struct vmcb
*nested_vmcb
;
2919 struct vmcb
*hsave
= svm
->nested
.hsave
;
2920 struct vmcb
*vmcb
= svm
->vmcb
;
2924 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2926 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2930 if (!nested_vmcb_checks(nested_vmcb
)) {
2931 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2932 nested_vmcb
->control
.exit_code_hi
= 0;
2933 nested_vmcb
->control
.exit_info_1
= 0;
2934 nested_vmcb
->control
.exit_info_2
= 0;
2936 nested_svm_unmap(page
);
2941 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2942 nested_vmcb
->save
.rip
,
2943 nested_vmcb
->control
.int_ctl
,
2944 nested_vmcb
->control
.event_inj
,
2945 nested_vmcb
->control
.nested_ctl
);
2947 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2948 nested_vmcb
->control
.intercept_cr
>> 16,
2949 nested_vmcb
->control
.intercept_exceptions
,
2950 nested_vmcb
->control
.intercept
);
2952 /* Clear internal status */
2953 kvm_clear_exception_queue(&svm
->vcpu
);
2954 kvm_clear_interrupt_queue(&svm
->vcpu
);
2957 * Save the old vmcb, so we don't need to pick what we save, but can
2958 * restore everything when a VMEXIT occurs
2960 hsave
->save
.es
= vmcb
->save
.es
;
2961 hsave
->save
.cs
= vmcb
->save
.cs
;
2962 hsave
->save
.ss
= vmcb
->save
.ss
;
2963 hsave
->save
.ds
= vmcb
->save
.ds
;
2964 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2965 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2966 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2967 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2968 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2969 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2970 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2971 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2972 hsave
->save
.rax
= vmcb
->save
.rax
;
2974 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2976 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2978 copy_vmcb_control_area(hsave
, vmcb
);
2980 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2981 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2983 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2985 if (nested_vmcb
->control
.nested_ctl
) {
2986 kvm_mmu_unload(&svm
->vcpu
);
2987 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2988 nested_svm_init_mmu_context(&svm
->vcpu
);
2991 /* Load the nested guest state */
2992 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2993 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2994 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2995 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2996 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2997 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2998 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2999 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3000 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3001 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3003 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3004 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3006 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3008 /* Guest paging mode is active - reset mmu */
3009 kvm_mmu_reset_context(&svm
->vcpu
);
3011 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3012 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
3013 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
3014 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
3016 /* In case we don't even reach vcpu_run, the fields are not updated */
3017 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3018 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3019 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3020 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3021 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3022 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3024 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3025 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3027 /* cache intercepts */
3028 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3029 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3030 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3031 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3033 svm_flush_tlb(&svm
->vcpu
);
3034 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3035 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3036 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3038 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3040 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3041 /* We only want the cr8 intercept bits of the guest */
3042 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3043 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3046 /* We don't want to see VMMCALLs from a nested guest */
3047 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3049 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3050 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3051 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3052 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3053 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3054 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3056 nested_svm_unmap(page
);
3058 /* Enter Guest-Mode */
3059 enter_guest_mode(&svm
->vcpu
);
3062 * Merge guest and host intercepts - must be called with vcpu in
3063 * guest-mode to take affect here
3065 recalc_intercepts(svm
);
3067 svm
->nested
.vmcb
= vmcb_gpa
;
3071 mark_all_dirty(svm
->vmcb
);
3076 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3078 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3079 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3080 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3081 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3082 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3083 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3084 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3085 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3086 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3087 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3088 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3089 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3092 static int vmload_interception(struct vcpu_svm
*svm
)
3094 struct vmcb
*nested_vmcb
;
3098 if (nested_svm_check_permissions(svm
))
3101 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3105 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3106 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3108 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3109 nested_svm_unmap(page
);
3114 static int vmsave_interception(struct vcpu_svm
*svm
)
3116 struct vmcb
*nested_vmcb
;
3120 if (nested_svm_check_permissions(svm
))
3123 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3127 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3128 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3130 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3131 nested_svm_unmap(page
);
3136 static int vmrun_interception(struct vcpu_svm
*svm
)
3138 if (nested_svm_check_permissions(svm
))
3141 /* Save rip after vmrun instruction */
3142 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3144 if (!nested_svm_vmrun(svm
))
3147 if (!nested_svm_vmrun_msrpm(svm
))
3154 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3155 svm
->vmcb
->control
.exit_code_hi
= 0;
3156 svm
->vmcb
->control
.exit_info_1
= 0;
3157 svm
->vmcb
->control
.exit_info_2
= 0;
3159 nested_svm_vmexit(svm
);
3164 static int stgi_interception(struct vcpu_svm
*svm
)
3168 if (nested_svm_check_permissions(svm
))
3171 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3172 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3173 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3180 static int clgi_interception(struct vcpu_svm
*svm
)
3184 if (nested_svm_check_permissions(svm
))
3187 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3188 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3192 /* After a CLGI no interrupts should come */
3193 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3194 svm_clear_vintr(svm
);
3195 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3196 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3202 static int invlpga_interception(struct vcpu_svm
*svm
)
3204 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3206 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3207 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3209 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3210 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3212 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3213 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3216 static int skinit_interception(struct vcpu_svm
*svm
)
3218 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3220 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3224 static int wbinvd_interception(struct vcpu_svm
*svm
)
3226 return kvm_emulate_wbinvd(&svm
->vcpu
);
3229 static int xsetbv_interception(struct vcpu_svm
*svm
)
3231 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3232 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3234 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3235 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3236 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3242 static int task_switch_interception(struct vcpu_svm
*svm
)
3246 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3247 SVM_EXITINTINFO_TYPE_MASK
;
3248 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3250 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3252 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3253 bool has_error_code
= false;
3256 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3258 if (svm
->vmcb
->control
.exit_info_2
&
3259 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3260 reason
= TASK_SWITCH_IRET
;
3261 else if (svm
->vmcb
->control
.exit_info_2
&
3262 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3263 reason
= TASK_SWITCH_JMP
;
3265 reason
= TASK_SWITCH_GATE
;
3267 reason
= TASK_SWITCH_CALL
;
3269 if (reason
== TASK_SWITCH_GATE
) {
3271 case SVM_EXITINTINFO_TYPE_NMI
:
3272 svm
->vcpu
.arch
.nmi_injected
= false;
3274 case SVM_EXITINTINFO_TYPE_EXEPT
:
3275 if (svm
->vmcb
->control
.exit_info_2
&
3276 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3277 has_error_code
= true;
3279 (u32
)svm
->vmcb
->control
.exit_info_2
;
3281 kvm_clear_exception_queue(&svm
->vcpu
);
3283 case SVM_EXITINTINFO_TYPE_INTR
:
3284 kvm_clear_interrupt_queue(&svm
->vcpu
);
3291 if (reason
!= TASK_SWITCH_GATE
||
3292 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3293 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3294 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3295 skip_emulated_instruction(&svm
->vcpu
);
3297 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3300 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3301 has_error_code
, error_code
) == EMULATE_FAIL
) {
3302 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3303 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3304 svm
->vcpu
.run
->internal
.ndata
= 0;
3310 static int cpuid_interception(struct vcpu_svm
*svm
)
3312 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3313 return kvm_emulate_cpuid(&svm
->vcpu
);
3316 static int iret_interception(struct vcpu_svm
*svm
)
3318 ++svm
->vcpu
.stat
.nmi_window_exits
;
3319 clr_intercept(svm
, INTERCEPT_IRET
);
3320 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3321 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3322 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3326 static int invlpg_interception(struct vcpu_svm
*svm
)
3328 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3329 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3331 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3332 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3335 static int emulate_on_interception(struct vcpu_svm
*svm
)
3337 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3340 static int rdpmc_interception(struct vcpu_svm
*svm
)
3344 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3345 return emulate_on_interception(svm
);
3347 err
= kvm_rdpmc(&svm
->vcpu
);
3348 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3351 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3354 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3358 intercept
= svm
->nested
.intercept
;
3360 if (!is_guest_mode(&svm
->vcpu
) ||
3361 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3364 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3365 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3368 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3369 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3375 #define CR_VALID (1ULL << 63)
3377 static int cr_interception(struct vcpu_svm
*svm
)
3383 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3384 return emulate_on_interception(svm
);
3386 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3387 return emulate_on_interception(svm
);
3389 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3390 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3391 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3393 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3396 if (cr
>= 16) { /* mov to cr */
3398 val
= kvm_register_read(&svm
->vcpu
, reg
);
3401 if (!check_selective_cr0_intercepted(svm
, val
))
3402 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3408 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3411 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3414 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3417 WARN(1, "unhandled write to CR%d", cr
);
3418 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3421 } else { /* mov from cr */
3424 val
= kvm_read_cr0(&svm
->vcpu
);
3427 val
= svm
->vcpu
.arch
.cr2
;
3430 val
= kvm_read_cr3(&svm
->vcpu
);
3433 val
= kvm_read_cr4(&svm
->vcpu
);
3436 val
= kvm_get_cr8(&svm
->vcpu
);
3439 WARN(1, "unhandled read from CR%d", cr
);
3440 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3443 kvm_register_write(&svm
->vcpu
, reg
, val
);
3445 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3448 static int dr_interception(struct vcpu_svm
*svm
)
3453 if (svm
->vcpu
.guest_debug
== 0) {
3455 * No more DR vmexits; force a reload of the debug registers
3456 * and reenter on this instruction. The next vmexit will
3457 * retrieve the full state of the debug registers.
3459 clr_dr_intercepts(svm
);
3460 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3464 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3465 return emulate_on_interception(svm
);
3467 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3468 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3470 if (dr
>= 16) { /* mov to DRn */
3471 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3473 val
= kvm_register_read(&svm
->vcpu
, reg
);
3474 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3476 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3478 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3479 kvm_register_write(&svm
->vcpu
, reg
, val
);
3482 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3485 static int cr8_write_interception(struct vcpu_svm
*svm
)
3487 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3490 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3491 /* instruction emulation calls kvm_set_cr8() */
3492 r
= cr_interception(svm
);
3493 if (lapic_in_kernel(&svm
->vcpu
))
3495 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3497 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3501 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3503 struct vcpu_svm
*svm
= to_svm(vcpu
);
3505 switch (msr_info
->index
) {
3506 case MSR_IA32_TSC
: {
3507 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
3508 kvm_scale_tsc(vcpu
, rdtsc());
3513 msr_info
->data
= svm
->vmcb
->save
.star
;
3515 #ifdef CONFIG_X86_64
3517 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3520 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3522 case MSR_KERNEL_GS_BASE
:
3523 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3525 case MSR_SYSCALL_MASK
:
3526 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3529 case MSR_IA32_SYSENTER_CS
:
3530 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3532 case MSR_IA32_SYSENTER_EIP
:
3533 msr_info
->data
= svm
->sysenter_eip
;
3535 case MSR_IA32_SYSENTER_ESP
:
3536 msr_info
->data
= svm
->sysenter_esp
;
3539 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3541 msr_info
->data
= svm
->tsc_aux
;
3544 * Nobody will change the following 5 values in the VMCB so we can
3545 * safely return them on rdmsr. They will always be 0 until LBRV is
3548 case MSR_IA32_DEBUGCTLMSR
:
3549 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3551 case MSR_IA32_LASTBRANCHFROMIP
:
3552 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3554 case MSR_IA32_LASTBRANCHTOIP
:
3555 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3557 case MSR_IA32_LASTINTFROMIP
:
3558 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3560 case MSR_IA32_LASTINTTOIP
:
3561 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3563 case MSR_VM_HSAVE_PA
:
3564 msr_info
->data
= svm
->nested
.hsave_msr
;
3567 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3569 case MSR_IA32_SPEC_CTRL
:
3570 msr_info
->data
= svm
->spec_ctrl
;
3572 case MSR_IA32_UCODE_REV
:
3573 msr_info
->data
= 0x01000065;
3575 case MSR_F15H_IC_CFG
: {
3579 family
= guest_cpuid_family(vcpu
);
3580 model
= guest_cpuid_model(vcpu
);
3582 if (family
< 0 || model
< 0)
3583 return kvm_get_msr_common(vcpu
, msr_info
);
3587 if (family
== 0x15 &&
3588 (model
>= 0x2 && model
< 0x20))
3589 msr_info
->data
= 0x1E;
3593 return kvm_get_msr_common(vcpu
, msr_info
);
3598 static int rdmsr_interception(struct vcpu_svm
*svm
)
3600 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3601 struct msr_data msr_info
;
3603 msr_info
.index
= ecx
;
3604 msr_info
.host_initiated
= false;
3605 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3606 trace_kvm_msr_read_ex(ecx
);
3607 kvm_inject_gp(&svm
->vcpu
, 0);
3610 trace_kvm_msr_read(ecx
, msr_info
.data
);
3612 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3613 msr_info
.data
& 0xffffffff);
3614 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3615 msr_info
.data
>> 32);
3616 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3617 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3621 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3623 struct vcpu_svm
*svm
= to_svm(vcpu
);
3624 int svm_dis
, chg_mask
;
3626 if (data
& ~SVM_VM_CR_VALID_MASK
)
3629 chg_mask
= SVM_VM_CR_VALID_MASK
;
3631 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3632 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3634 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3635 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3637 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3639 /* check for svm_disable while efer.svme is set */
3640 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3646 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3648 struct vcpu_svm
*svm
= to_svm(vcpu
);
3650 u32 ecx
= msr
->index
;
3651 u64 data
= msr
->data
;
3654 kvm_write_tsc(vcpu
, msr
);
3657 svm
->vmcb
->save
.star
= data
;
3659 #ifdef CONFIG_X86_64
3661 svm
->vmcb
->save
.lstar
= data
;
3664 svm
->vmcb
->save
.cstar
= data
;
3666 case MSR_KERNEL_GS_BASE
:
3667 svm
->vmcb
->save
.kernel_gs_base
= data
;
3669 case MSR_SYSCALL_MASK
:
3670 svm
->vmcb
->save
.sfmask
= data
;
3673 case MSR_IA32_SYSENTER_CS
:
3674 svm
->vmcb
->save
.sysenter_cs
= data
;
3676 case MSR_IA32_SYSENTER_EIP
:
3677 svm
->sysenter_eip
= data
;
3678 svm
->vmcb
->save
.sysenter_eip
= data
;
3680 case MSR_IA32_SYSENTER_ESP
:
3681 svm
->sysenter_esp
= data
;
3682 svm
->vmcb
->save
.sysenter_esp
= data
;
3685 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3689 * This is rare, so we update the MSR here instead of using
3690 * direct_access_msrs. Doing that would require a rdmsr in
3693 svm
->tsc_aux
= data
;
3694 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
3696 case MSR_IA32_DEBUGCTLMSR
:
3697 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3698 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3702 if (data
& DEBUGCTL_RESERVED_BITS
)
3705 svm
->vmcb
->save
.dbgctl
= data
;
3706 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3707 if (data
& (1ULL<<0))
3708 svm_enable_lbrv(svm
);
3710 svm_disable_lbrv(svm
);
3712 case MSR_VM_HSAVE_PA
:
3713 svm
->nested
.hsave_msr
= data
;
3716 return svm_set_vm_cr(vcpu
, data
);
3718 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3720 case MSR_IA32_SPEC_CTRL
:
3721 svm
->spec_ctrl
= data
;
3723 case MSR_IA32_APICBASE
:
3724 if (kvm_vcpu_apicv_active(vcpu
))
3725 avic_update_vapic_bar(to_svm(vcpu
), data
);
3726 /* Follow through */
3728 return kvm_set_msr_common(vcpu
, msr
);
3733 static int wrmsr_interception(struct vcpu_svm
*svm
)
3735 struct msr_data msr
;
3736 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3737 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3741 msr
.host_initiated
= false;
3743 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3744 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3745 trace_kvm_msr_write_ex(ecx
, data
);
3746 kvm_inject_gp(&svm
->vcpu
, 0);
3749 trace_kvm_msr_write(ecx
, data
);
3750 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3754 static int msr_interception(struct vcpu_svm
*svm
)
3756 if (svm
->vmcb
->control
.exit_info_1
)
3757 return wrmsr_interception(svm
);
3759 return rdmsr_interception(svm
);
3762 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3764 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3765 svm_clear_vintr(svm
);
3766 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3767 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3768 ++svm
->vcpu
.stat
.irq_window_exits
;
3772 static int pause_interception(struct vcpu_svm
*svm
)
3774 kvm_vcpu_on_spin(&(svm
->vcpu
));
3778 static int nop_interception(struct vcpu_svm
*svm
)
3780 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
3783 static int monitor_interception(struct vcpu_svm
*svm
)
3785 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3786 return nop_interception(svm
);
3789 static int mwait_interception(struct vcpu_svm
*svm
)
3791 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3792 return nop_interception(svm
);
3795 enum avic_ipi_failure_cause
{
3796 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
3797 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
3798 AVIC_IPI_FAILURE_INVALID_TARGET
,
3799 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
3802 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
3804 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
3805 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
3806 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
3807 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
3808 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3810 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
3813 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
3815 * AVIC hardware handles the generation of
3816 * IPIs when the specified Message Type is Fixed
3817 * (also known as fixed delivery mode) and
3818 * the Trigger Mode is edge-triggered. The hardware
3819 * also supports self and broadcast delivery modes
3820 * specified via the Destination Shorthand(DSH)
3821 * field of the ICRL. Logical and physical APIC ID
3822 * formats are supported. All other IPI types cause
3823 * a #VMEXIT, which needs to emulated.
3825 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
3826 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
3828 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
3830 struct kvm_vcpu
*vcpu
;
3831 struct kvm
*kvm
= svm
->vcpu
.kvm
;
3832 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3835 * At this point, we expect that the AVIC HW has already
3836 * set the appropriate IRR bits on the valid target
3837 * vcpus. So, we just need to kick the appropriate vcpu.
3839 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
3840 bool m
= kvm_apic_match_dest(vcpu
, apic
,
3841 icrl
& KVM_APIC_SHORT_MASK
,
3842 GET_APIC_DEST_FIELD(icrh
),
3843 icrl
& KVM_APIC_DEST_MASK
);
3845 if (m
&& !avic_vcpu_is_running(vcpu
))
3846 kvm_vcpu_wake_up(vcpu
);
3850 case AVIC_IPI_FAILURE_INVALID_TARGET
:
3852 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
3853 WARN_ONCE(1, "Invalid backing page\n");
3856 pr_err("Unknown IPI interception\n");
3862 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
3864 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3866 u32
*logical_apic_id_table
;
3867 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
3872 if (flat
) { /* flat */
3873 index
= ffs(dlid
) - 1;
3876 } else { /* cluster */
3877 int cluster
= (dlid
& 0xf0) >> 4;
3878 int apic
= ffs(dlid
& 0x0f) - 1;
3880 if ((apic
< 0) || (apic
> 7) ||
3883 index
= (cluster
<< 2) + apic
;
3886 logical_apic_id_table
= (u32
*) page_address(vm_data
->avic_logical_id_table_page
);
3888 return &logical_apic_id_table
[index
];
3891 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
3895 u32
*entry
, new_entry
;
3897 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
3898 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
3902 new_entry
= READ_ONCE(*entry
);
3903 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
3904 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
3906 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3908 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
3909 WRITE_ONCE(*entry
, new_entry
);
3914 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
3917 struct vcpu_svm
*svm
= to_svm(vcpu
);
3918 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
3923 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
3924 if (ret
&& svm
->ldr_reg
) {
3925 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
3933 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
3936 struct vcpu_svm
*svm
= to_svm(vcpu
);
3937 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
3938 u32 id
= (apic_id_reg
>> 24) & 0xff;
3940 if (vcpu
->vcpu_id
== id
)
3943 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
3944 new = avic_get_physical_id_entry(vcpu
, id
);
3948 /* We need to move physical_id_entry to new offset */
3951 to_svm(vcpu
)->avic_physical_id_cache
= new;
3954 * Also update the guest physical APIC ID in the logical
3955 * APIC ID table entry if already setup the LDR.
3958 avic_handle_ldr_update(vcpu
);
3963 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
3965 struct vcpu_svm
*svm
= to_svm(vcpu
);
3966 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
3967 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
3968 u32 mod
= (dfr
>> 28) & 0xf;
3971 * We assume that all local APICs are using the same type.
3972 * If this changes, we need to flush the AVIC logical
3975 if (vm_data
->ldr_mode
== mod
)
3978 clear_page(page_address(vm_data
->avic_logical_id_table_page
));
3979 vm_data
->ldr_mode
= mod
;
3982 avic_handle_ldr_update(vcpu
);
3986 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
3988 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3989 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
3990 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
3994 if (avic_handle_apic_id_update(&svm
->vcpu
))
3998 if (avic_handle_ldr_update(&svm
->vcpu
))
4002 avic_handle_dfr_update(&svm
->vcpu
);
4008 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4013 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4042 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4045 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4046 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4047 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4048 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4049 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4050 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4051 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4053 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4054 trap
, write
, vector
);
4057 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4058 ret
= avic_unaccel_trap_write(svm
);
4060 /* Handling Fault */
4061 ret
= (emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4067 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4068 [SVM_EXIT_READ_CR0
] = cr_interception
,
4069 [SVM_EXIT_READ_CR3
] = cr_interception
,
4070 [SVM_EXIT_READ_CR4
] = cr_interception
,
4071 [SVM_EXIT_READ_CR8
] = cr_interception
,
4072 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4073 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4074 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4075 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4076 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4077 [SVM_EXIT_READ_DR0
] = dr_interception
,
4078 [SVM_EXIT_READ_DR1
] = dr_interception
,
4079 [SVM_EXIT_READ_DR2
] = dr_interception
,
4080 [SVM_EXIT_READ_DR3
] = dr_interception
,
4081 [SVM_EXIT_READ_DR4
] = dr_interception
,
4082 [SVM_EXIT_READ_DR5
] = dr_interception
,
4083 [SVM_EXIT_READ_DR6
] = dr_interception
,
4084 [SVM_EXIT_READ_DR7
] = dr_interception
,
4085 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4086 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4087 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4088 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4089 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4090 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4091 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4092 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4093 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4094 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4095 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4096 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4097 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4098 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4099 [SVM_EXIT_INTR
] = intr_interception
,
4100 [SVM_EXIT_NMI
] = nmi_interception
,
4101 [SVM_EXIT_SMI
] = nop_on_interception
,
4102 [SVM_EXIT_INIT
] = nop_on_interception
,
4103 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4104 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4105 [SVM_EXIT_CPUID
] = cpuid_interception
,
4106 [SVM_EXIT_IRET
] = iret_interception
,
4107 [SVM_EXIT_INVD
] = emulate_on_interception
,
4108 [SVM_EXIT_PAUSE
] = pause_interception
,
4109 [SVM_EXIT_HLT
] = halt_interception
,
4110 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4111 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4112 [SVM_EXIT_IOIO
] = io_interception
,
4113 [SVM_EXIT_MSR
] = msr_interception
,
4114 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4115 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4116 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4117 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4118 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4119 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4120 [SVM_EXIT_STGI
] = stgi_interception
,
4121 [SVM_EXIT_CLGI
] = clgi_interception
,
4122 [SVM_EXIT_SKINIT
] = skinit_interception
,
4123 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4124 [SVM_EXIT_MONITOR
] = monitor_interception
,
4125 [SVM_EXIT_MWAIT
] = mwait_interception
,
4126 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4127 [SVM_EXIT_NPF
] = pf_interception
,
4128 [SVM_EXIT_RSM
] = emulate_on_interception
,
4129 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4130 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4133 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4135 struct vcpu_svm
*svm
= to_svm(vcpu
);
4136 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4137 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4139 pr_err("VMCB Control Area:\n");
4140 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4141 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4142 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4143 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4144 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4145 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4146 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4147 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4148 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4149 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4150 pr_err("%-20s%d\n", "asid:", control
->asid
);
4151 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4152 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4153 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4154 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4155 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4156 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4157 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4158 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4159 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4160 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4161 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4162 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4163 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4164 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4165 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4166 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4167 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4168 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4169 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4170 pr_err("VMCB State Save Area:\n");
4171 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4173 save
->es
.selector
, save
->es
.attrib
,
4174 save
->es
.limit
, save
->es
.base
);
4175 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4177 save
->cs
.selector
, save
->cs
.attrib
,
4178 save
->cs
.limit
, save
->cs
.base
);
4179 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4181 save
->ss
.selector
, save
->ss
.attrib
,
4182 save
->ss
.limit
, save
->ss
.base
);
4183 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4185 save
->ds
.selector
, save
->ds
.attrib
,
4186 save
->ds
.limit
, save
->ds
.base
);
4187 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4189 save
->fs
.selector
, save
->fs
.attrib
,
4190 save
->fs
.limit
, save
->fs
.base
);
4191 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4193 save
->gs
.selector
, save
->gs
.attrib
,
4194 save
->gs
.limit
, save
->gs
.base
);
4195 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4197 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4198 save
->gdtr
.limit
, save
->gdtr
.base
);
4199 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4201 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4202 save
->ldtr
.limit
, save
->ldtr
.base
);
4203 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4205 save
->idtr
.selector
, save
->idtr
.attrib
,
4206 save
->idtr
.limit
, save
->idtr
.base
);
4207 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4209 save
->tr
.selector
, save
->tr
.attrib
,
4210 save
->tr
.limit
, save
->tr
.base
);
4211 pr_err("cpl: %d efer: %016llx\n",
4212 save
->cpl
, save
->efer
);
4213 pr_err("%-15s %016llx %-13s %016llx\n",
4214 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4215 pr_err("%-15s %016llx %-13s %016llx\n",
4216 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4217 pr_err("%-15s %016llx %-13s %016llx\n",
4218 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4219 pr_err("%-15s %016llx %-13s %016llx\n",
4220 "rip:", save
->rip
, "rflags:", save
->rflags
);
4221 pr_err("%-15s %016llx %-13s %016llx\n",
4222 "rsp:", save
->rsp
, "rax:", save
->rax
);
4223 pr_err("%-15s %016llx %-13s %016llx\n",
4224 "star:", save
->star
, "lstar:", save
->lstar
);
4225 pr_err("%-15s %016llx %-13s %016llx\n",
4226 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4227 pr_err("%-15s %016llx %-13s %016llx\n",
4228 "kernel_gs_base:", save
->kernel_gs_base
,
4229 "sysenter_cs:", save
->sysenter_cs
);
4230 pr_err("%-15s %016llx %-13s %016llx\n",
4231 "sysenter_esp:", save
->sysenter_esp
,
4232 "sysenter_eip:", save
->sysenter_eip
);
4233 pr_err("%-15s %016llx %-13s %016llx\n",
4234 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4235 pr_err("%-15s %016llx %-13s %016llx\n",
4236 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4237 pr_err("%-15s %016llx %-13s %016llx\n",
4238 "excp_from:", save
->last_excp_from
,
4239 "excp_to:", save
->last_excp_to
);
4242 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4244 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4246 *info1
= control
->exit_info_1
;
4247 *info2
= control
->exit_info_2
;
4250 static int handle_exit(struct kvm_vcpu
*vcpu
)
4252 struct vcpu_svm
*svm
= to_svm(vcpu
);
4253 struct kvm_run
*kvm_run
= vcpu
->run
;
4254 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4256 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4258 vcpu
->arch
.gpa_available
= (exit_code
== SVM_EXIT_NPF
);
4260 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4261 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4263 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4265 if (unlikely(svm
->nested
.exit_required
)) {
4266 nested_svm_vmexit(svm
);
4267 svm
->nested
.exit_required
= false;
4272 if (is_guest_mode(vcpu
)) {
4275 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4276 svm
->vmcb
->control
.exit_info_1
,
4277 svm
->vmcb
->control
.exit_info_2
,
4278 svm
->vmcb
->control
.exit_int_info
,
4279 svm
->vmcb
->control
.exit_int_info_err
,
4282 vmexit
= nested_svm_exit_special(svm
);
4284 if (vmexit
== NESTED_EXIT_CONTINUE
)
4285 vmexit
= nested_svm_exit_handled(svm
);
4287 if (vmexit
== NESTED_EXIT_DONE
)
4291 svm_complete_interrupts(svm
);
4293 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4294 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4295 kvm_run
->fail_entry
.hardware_entry_failure_reason
4296 = svm
->vmcb
->control
.exit_code
;
4297 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4302 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4303 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4304 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4305 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4306 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4308 __func__
, svm
->vmcb
->control
.exit_int_info
,
4311 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4312 || !svm_exit_handlers
[exit_code
]) {
4313 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4314 kvm_queue_exception(vcpu
, UD_VECTOR
);
4318 return svm_exit_handlers
[exit_code
](svm
);
4321 static void reload_tss(struct kvm_vcpu
*vcpu
)
4323 int cpu
= raw_smp_processor_id();
4325 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4326 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4330 static void pre_svm_run(struct vcpu_svm
*svm
)
4332 int cpu
= raw_smp_processor_id();
4334 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4336 /* FIXME: handle wraparound of asid_generation */
4337 if (svm
->asid_generation
!= sd
->asid_generation
)
4341 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
4343 struct vcpu_svm
*svm
= to_svm(vcpu
);
4345 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
4346 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
4347 set_intercept(svm
, INTERCEPT_IRET
);
4348 ++vcpu
->stat
.nmi_injections
;
4351 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
4353 struct vmcb_control_area
*control
;
4355 /* The following fields are ignored when AVIC is enabled */
4356 control
= &svm
->vmcb
->control
;
4357 control
->int_vector
= irq
;
4358 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
4359 control
->int_ctl
|= V_IRQ_MASK
|
4360 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
4361 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4364 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
4366 struct vcpu_svm
*svm
= to_svm(vcpu
);
4368 BUG_ON(!(gif_set(svm
)));
4370 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
4371 ++vcpu
->stat
.irq_injections
;
4373 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
4374 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
4377 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
4379 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
4382 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
4384 struct vcpu_svm
*svm
= to_svm(vcpu
);
4386 if (svm_nested_virtualize_tpr(vcpu
) ||
4387 kvm_vcpu_apicv_active(vcpu
))
4390 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4396 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4399 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
4404 static bool svm_get_enable_apicv(void)
4409 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
4413 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
4417 /* Note: Currently only used by Hyper-V. */
4418 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4420 struct vcpu_svm
*svm
= to_svm(vcpu
);
4421 struct vmcb
*vmcb
= svm
->vmcb
;
4426 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
4427 mark_dirty(vmcb
, VMCB_INTR
);
4430 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
4435 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
4437 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
4438 smp_mb__after_atomic();
4440 if (avic_vcpu_is_running(vcpu
))
4441 wrmsrl(SVM_AVIC_DOORBELL
,
4442 kvm_cpu_get_apicid(vcpu
->cpu
));
4444 kvm_vcpu_wake_up(vcpu
);
4447 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4449 unsigned long flags
;
4450 struct amd_svm_iommu_ir
*cur
;
4452 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4453 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
4454 if (cur
->data
!= pi
->ir_data
)
4456 list_del(&cur
->node
);
4460 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4463 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4466 unsigned long flags
;
4467 struct amd_svm_iommu_ir
*ir
;
4470 * In some cases, the existing irte is updaed and re-set,
4471 * so we need to check here if it's already been * added
4474 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
4475 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4476 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
4477 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
4478 struct vcpu_svm
*prev_svm
;
4485 prev_svm
= to_svm(prev_vcpu
);
4486 svm_ir_list_del(prev_svm
, pi
);
4490 * Allocating new amd_iommu_pi_data, which will get
4491 * add to the per-vcpu ir_list.
4493 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
4498 ir
->data
= pi
->ir_data
;
4500 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4501 list_add(&ir
->node
, &svm
->ir_list
);
4502 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4509 * The HW cannot support posting multicast/broadcast
4510 * interrupts to a vCPU. So, we still use legacy interrupt
4511 * remapping for these kind of interrupts.
4513 * For lowest-priority interrupts, we only support
4514 * those with single CPU as the destination, e.g. user
4515 * configures the interrupts via /proc/irq or uses
4516 * irqbalance to make the interrupts single-CPU.
4519 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
4520 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
4522 struct kvm_lapic_irq irq
;
4523 struct kvm_vcpu
*vcpu
= NULL
;
4525 kvm_set_msi_irq(kvm
, e
, &irq
);
4527 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
4528 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4529 __func__
, irq
.vector
);
4533 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
4535 *svm
= to_svm(vcpu
);
4536 vcpu_info
->pi_desc_addr
= page_to_phys((*svm
)->avic_backing_page
);
4537 vcpu_info
->vector
= irq
.vector
;
4543 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4546 * @host_irq: host irq of the interrupt
4547 * @guest_irq: gsi of the interrupt
4548 * @set: set or unset PI
4549 * returns 0 on success, < 0 on failure
4551 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
4552 uint32_t guest_irq
, bool set
)
4554 struct kvm_kernel_irq_routing_entry
*e
;
4555 struct kvm_irq_routing_table
*irq_rt
;
4556 int idx
, ret
= -EINVAL
;
4558 if (!kvm_arch_has_assigned_device(kvm
) ||
4559 !irq_remapping_cap(IRQ_POSTING_CAP
))
4562 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4563 __func__
, host_irq
, guest_irq
, set
);
4565 idx
= srcu_read_lock(&kvm
->irq_srcu
);
4566 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
4567 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
4569 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
4570 struct vcpu_data vcpu_info
;
4571 struct vcpu_svm
*svm
= NULL
;
4573 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
4577 * Here, we setup with legacy mode in the following cases:
4578 * 1. When cannot target interrupt to a specific vcpu.
4579 * 2. Unsetting posted interrupt.
4580 * 3. APIC virtialization is disabled for the vcpu.
4582 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
4583 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
4584 struct amd_iommu_pi_data pi
;
4586 /* Try to enable guest_mode in IRTE */
4587 pi
.base
= page_to_phys(svm
->avic_backing_page
) & AVIC_HPA_MASK
;
4588 pi
.ga_tag
= AVIC_GATAG(kvm
->arch
.avic_vm_id
,
4590 pi
.is_guest_mode
= true;
4591 pi
.vcpu_data
= &vcpu_info
;
4592 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4595 * Here, we successfully setting up vcpu affinity in
4596 * IOMMU guest mode. Now, we need to store the posted
4597 * interrupt information in a per-vcpu ir_list so that
4598 * we can reference to them directly when we update vcpu
4599 * scheduling information in IOMMU irte.
4601 if (!ret
&& pi
.is_guest_mode
)
4602 svm_ir_list_add(svm
, &pi
);
4604 /* Use legacy mode in IRTE */
4605 struct amd_iommu_pi_data pi
;
4608 * Here, pi is used to:
4609 * - Tell IOMMU to use legacy mode for this interrupt.
4610 * - Retrieve ga_tag of prior interrupt remapping data.
4612 pi
.is_guest_mode
= false;
4613 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4616 * Check if the posted interrupt was previously
4617 * setup with the guest_mode by checking if the ga_tag
4618 * was cached. If so, we need to clean up the per-vcpu
4621 if (!ret
&& pi
.prev_ga_tag
) {
4622 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
4623 struct kvm_vcpu
*vcpu
;
4625 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
4627 svm_ir_list_del(to_svm(vcpu
), &pi
);
4632 trace_kvm_pi_irte_update(svm
->vcpu
.vcpu_id
,
4635 vcpu_info
.pi_desc_addr
, set
);
4639 pr_err("%s: failed to update PI IRTE\n", __func__
);
4646 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
4650 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
4652 struct vcpu_svm
*svm
= to_svm(vcpu
);
4653 struct vmcb
*vmcb
= svm
->vmcb
;
4655 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
4656 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4657 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
4662 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4664 struct vcpu_svm
*svm
= to_svm(vcpu
);
4666 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4669 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4671 struct vcpu_svm
*svm
= to_svm(vcpu
);
4674 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
4675 set_intercept(svm
, INTERCEPT_IRET
);
4677 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
4678 clr_intercept(svm
, INTERCEPT_IRET
);
4682 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4684 struct vcpu_svm
*svm
= to_svm(vcpu
);
4685 struct vmcb
*vmcb
= svm
->vmcb
;
4688 if (!gif_set(svm
) ||
4689 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
4692 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
4694 if (is_guest_mode(vcpu
))
4695 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
4700 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4702 struct vcpu_svm
*svm
= to_svm(vcpu
);
4704 if (kvm_vcpu_apicv_active(vcpu
))
4708 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4709 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4710 * get that intercept, this function will be called again though and
4711 * we'll get the vintr intercept.
4713 if (gif_set(svm
) && nested_svm_intr(svm
)) {
4715 svm_inject_irq(svm
, 0x0);
4719 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4721 struct vcpu_svm
*svm
= to_svm(vcpu
);
4723 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
4725 return; /* IRET will cause a vm exit */
4727 if ((svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
) == 0)
4728 return; /* STGI will cause a vm exit */
4730 if (svm
->nested
.exit_required
)
4731 return; /* we're not going to run the guest yet */
4734 * Something prevents NMI from been injected. Single step over possible
4735 * problem (IRET or exception injection or interrupt shadow)
4737 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
4738 svm
->nmi_singlestep
= true;
4739 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
4742 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4747 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
4749 struct vcpu_svm
*svm
= to_svm(vcpu
);
4751 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
4752 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4754 svm
->asid_generation
--;
4757 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
4761 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
4763 struct vcpu_svm
*svm
= to_svm(vcpu
);
4765 if (svm_nested_virtualize_tpr(vcpu
))
4768 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
4769 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
4770 kvm_set_cr8(vcpu
, cr8
);
4774 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
4776 struct vcpu_svm
*svm
= to_svm(vcpu
);
4779 if (svm_nested_virtualize_tpr(vcpu
) ||
4780 kvm_vcpu_apicv_active(vcpu
))
4783 cr8
= kvm_get_cr8(vcpu
);
4784 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
4785 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
4788 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
4792 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
4793 unsigned int3_injected
= svm
->int3_injected
;
4795 svm
->int3_injected
= 0;
4798 * If we've made progress since setting HF_IRET_MASK, we've
4799 * executed an IRET and can allow NMI injection.
4801 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
4802 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
4803 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
4804 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4807 svm
->vcpu
.arch
.nmi_injected
= false;
4808 kvm_clear_exception_queue(&svm
->vcpu
);
4809 kvm_clear_interrupt_queue(&svm
->vcpu
);
4811 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
4814 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4816 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
4817 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
4820 case SVM_EXITINTINFO_TYPE_NMI
:
4821 svm
->vcpu
.arch
.nmi_injected
= true;
4823 case SVM_EXITINTINFO_TYPE_EXEPT
:
4825 * In case of software exceptions, do not reinject the vector,
4826 * but re-execute the instruction instead. Rewind RIP first
4827 * if we emulated INT3 before.
4829 if (kvm_exception_is_soft(vector
)) {
4830 if (vector
== BP_VECTOR
&& int3_injected
&&
4831 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
4832 kvm_rip_write(&svm
->vcpu
,
4833 kvm_rip_read(&svm
->vcpu
) -
4837 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
4838 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
4839 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
4842 kvm_requeue_exception(&svm
->vcpu
, vector
);
4844 case SVM_EXITINTINFO_TYPE_INTR
:
4845 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
4852 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
4854 struct vcpu_svm
*svm
= to_svm(vcpu
);
4855 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4857 control
->exit_int_info
= control
->event_inj
;
4858 control
->exit_int_info_err
= control
->event_inj_err
;
4859 control
->event_inj
= 0;
4860 svm_complete_interrupts(svm
);
4863 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
4865 struct vcpu_svm
*svm
= to_svm(vcpu
);
4867 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
4868 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
4869 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
4872 * A vmexit emulation is required before the vcpu can be executed
4875 if (unlikely(svm
->nested
.exit_required
))
4879 * Disable singlestep if we're injecting an interrupt/exception.
4880 * We don't want our modified rflags to be pushed on the stack where
4881 * we might not be able to easily reset them if we disabled NMI
4884 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
4886 * Event injection happens before external interrupts cause a
4887 * vmexit and interrupts are disabled here, so smp_send_reschedule
4888 * is enough to force an immediate vmexit.
4890 disable_nmi_singlestep(svm
);
4891 smp_send_reschedule(vcpu
->cpu
);
4896 sync_lapic_to_cr8(vcpu
);
4898 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
4904 /* SMB: Don't care about ibrs_inuse but rely on guest value */
4905 x86_spec_ctrl_set_guest(svm
->spec_ctrl
);
4908 "push %%" _ASM_BP
"; \n\t"
4909 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
4910 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
4911 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
4912 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
4913 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
4914 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
4915 #ifdef CONFIG_X86_64
4916 "mov %c[r8](%[svm]), %%r8 \n\t"
4917 "mov %c[r9](%[svm]), %%r9 \n\t"
4918 "mov %c[r10](%[svm]), %%r10 \n\t"
4919 "mov %c[r11](%[svm]), %%r11 \n\t"
4920 "mov %c[r12](%[svm]), %%r12 \n\t"
4921 "mov %c[r13](%[svm]), %%r13 \n\t"
4922 "mov %c[r14](%[svm]), %%r14 \n\t"
4923 "mov %c[r15](%[svm]), %%r15 \n\t"
4926 /* Enter guest mode */
4927 "push %%" _ASM_AX
" \n\t"
4928 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
4929 __ex(SVM_VMLOAD
) "\n\t"
4930 __ex(SVM_VMRUN
) "\n\t"
4931 __ex(SVM_VMSAVE
) "\n\t"
4932 "pop %%" _ASM_AX
" \n\t"
4934 /* Save guest registers, load host registers */
4935 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
4936 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
4937 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
4938 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
4939 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
4940 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
4941 #ifdef CONFIG_X86_64
4942 "mov %%r8, %c[r8](%[svm]) \n\t"
4943 "mov %%r9, %c[r9](%[svm]) \n\t"
4944 "mov %%r10, %c[r10](%[svm]) \n\t"
4945 "mov %%r11, %c[r11](%[svm]) \n\t"
4946 "mov %%r12, %c[r12](%[svm]) \n\t"
4947 "mov %%r13, %c[r13](%[svm]) \n\t"
4948 "mov %%r14, %c[r14](%[svm]) \n\t"
4949 "mov %%r15, %c[r15](%[svm]) \n\t"
4952 * Clear host registers marked as clobbered to prevent
4955 "xor %%" _ASM_BX
", %%" _ASM_BX
" \n\t"
4956 "xor %%" _ASM_CX
", %%" _ASM_CX
" \n\t"
4957 "xor %%" _ASM_DX
", %%" _ASM_DX
" \n\t"
4958 "xor %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
4959 "xor %%" _ASM_DI
", %%" _ASM_DI
" \n\t"
4960 #ifdef CONFIG_X86_64
4961 "xor %%r8, %%r8 \n\t"
4962 "xor %%r9, %%r9 \n\t"
4963 "xor %%r10, %%r10 \n\t"
4964 "xor %%r11, %%r11 \n\t"
4965 "xor %%r12, %%r12 \n\t"
4966 "xor %%r13, %%r13 \n\t"
4967 "xor %%r14, %%r14 \n\t"
4968 "xor %%r15, %%r15 \n\t"
4973 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
4974 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4975 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4976 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4977 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4978 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4979 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
4980 #ifdef CONFIG_X86_64
4981 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4982 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4983 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4984 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4985 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4986 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4987 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4988 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
4991 #ifdef CONFIG_X86_64
4992 , "rbx", "rcx", "rdx", "rsi", "rdi"
4993 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4995 , "ebx", "ecx", "edx", "esi", "edi"
4999 /* Eliminate branch target predictions from guest mode */
5002 x86_spec_ctrl_restore_host(svm
->spec_ctrl
);
5004 #ifdef CONFIG_X86_64
5005 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5007 loadsegment(fs
, svm
->host
.fs
);
5008 #ifndef CONFIG_X86_32_LAZY_GS
5009 loadsegment(gs
, svm
->host
.gs
);
5015 local_irq_disable();
5017 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5018 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5019 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5020 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5022 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5023 kvm_before_handle_nmi(&svm
->vcpu
);
5027 /* Any pending NMI will happen here */
5029 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5030 kvm_after_handle_nmi(&svm
->vcpu
);
5032 sync_cr8_to_lapic(vcpu
);
5036 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5038 /* if exit due to PF check for async PF */
5039 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5040 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5043 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5044 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5048 * We need to handle MC intercepts here before the vcpu has a chance to
5049 * change the physical cpu
5051 if (unlikely(svm
->vmcb
->control
.exit_code
==
5052 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5053 svm_handle_mce(svm
);
5055 mark_all_clean(svm
->vmcb
);
5057 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5059 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5061 struct vcpu_svm
*svm
= to_svm(vcpu
);
5063 svm
->vmcb
->save
.cr3
= root
;
5064 mark_dirty(svm
->vmcb
, VMCB_CR
);
5065 svm_flush_tlb(vcpu
);
5068 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5070 struct vcpu_svm
*svm
= to_svm(vcpu
);
5072 svm
->vmcb
->control
.nested_cr3
= root
;
5073 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5075 /* Also sync guest cr3 here in case we live migrate */
5076 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5077 mark_dirty(svm
->vmcb
, VMCB_CR
);
5079 svm_flush_tlb(vcpu
);
5082 static int is_disabled(void)
5086 rdmsrl(MSR_VM_CR
, vm_cr
);
5087 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5094 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5097 * Patch in the VMMCALL instruction:
5099 hypercall
[0] = 0x0f;
5100 hypercall
[1] = 0x01;
5101 hypercall
[2] = 0xd9;
5104 static void svm_check_processor_compat(void *rtn
)
5109 static bool svm_cpu_has_accelerated_tpr(void)
5114 static bool svm_has_high_real_mode_segbase(void)
5119 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5124 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5126 struct vcpu_svm
*svm
= to_svm(vcpu
);
5127 struct kvm_cpuid_entry2
*entry
;
5129 /* Update nrips enabled cache */
5130 svm
->nrips_enabled
= !!guest_cpuid_has_nrips(&svm
->vcpu
);
5132 if (!kvm_vcpu_apicv_active(vcpu
))
5135 entry
= kvm_find_cpuid_entry(vcpu
, 1, 0);
5137 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5140 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5145 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5149 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5152 entry
->eax
= 1; /* SVM revision 1 */
5153 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5154 ASID emulation to nested SVM */
5155 entry
->ecx
= 0; /* Reserved */
5156 entry
->edx
= 0; /* Per default do not support any
5157 additional features */
5159 /* Support next_rip if host supports it */
5160 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5161 entry
->edx
|= SVM_FEATURE_NRIP
;
5163 /* Support NPT for the guest if enabled */
5165 entry
->edx
|= SVM_FEATURE_NPT
;
5171 static int svm_get_lpage_level(void)
5173 return PT_PDPE_LEVEL
;
5176 static bool svm_rdtscp_supported(void)
5178 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5181 static bool svm_invpcid_supported(void)
5186 static bool svm_mpx_supported(void)
5191 static bool svm_xsaves_supported(void)
5196 static bool svm_has_wbinvd_exit(void)
5201 #define PRE_EX(exit) { .exit_code = (exit), \
5202 .stage = X86_ICPT_PRE_EXCEPT, }
5203 #define POST_EX(exit) { .exit_code = (exit), \
5204 .stage = X86_ICPT_POST_EXCEPT, }
5205 #define POST_MEM(exit) { .exit_code = (exit), \
5206 .stage = X86_ICPT_POST_MEMACCESS, }
5208 static const struct __x86_intercept
{
5210 enum x86_intercept_stage stage
;
5211 } x86_intercept_map
[] = {
5212 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5213 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5214 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5215 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5216 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5217 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5218 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5219 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5220 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5221 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5222 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5223 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5224 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5225 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5226 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5227 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5228 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5229 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5230 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5231 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5232 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5233 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5234 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5235 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5236 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5237 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5238 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5239 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5240 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5241 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5242 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5243 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5244 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5245 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5246 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5247 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5248 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5249 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5250 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5251 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5252 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5253 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5254 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5255 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5256 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5257 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5264 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5265 struct x86_instruction_info
*info
,
5266 enum x86_intercept_stage stage
)
5268 struct vcpu_svm
*svm
= to_svm(vcpu
);
5269 int vmexit
, ret
= X86EMUL_CONTINUE
;
5270 struct __x86_intercept icpt_info
;
5271 struct vmcb
*vmcb
= svm
->vmcb
;
5273 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5276 icpt_info
= x86_intercept_map
[info
->intercept
];
5278 if (stage
!= icpt_info
.stage
)
5281 switch (icpt_info
.exit_code
) {
5282 case SVM_EXIT_READ_CR0
:
5283 if (info
->intercept
== x86_intercept_cr_read
)
5284 icpt_info
.exit_code
+= info
->modrm_reg
;
5286 case SVM_EXIT_WRITE_CR0
: {
5287 unsigned long cr0
, val
;
5290 if (info
->intercept
== x86_intercept_cr_write
)
5291 icpt_info
.exit_code
+= info
->modrm_reg
;
5293 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
5294 info
->intercept
== x86_intercept_clts
)
5297 intercept
= svm
->nested
.intercept
;
5299 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
5302 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
5303 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
5305 if (info
->intercept
== x86_intercept_lmsw
) {
5308 /* lmsw can't clear PE - catch this here */
5309 if (cr0
& X86_CR0_PE
)
5314 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
5318 case SVM_EXIT_READ_DR0
:
5319 case SVM_EXIT_WRITE_DR0
:
5320 icpt_info
.exit_code
+= info
->modrm_reg
;
5323 if (info
->intercept
== x86_intercept_wrmsr
)
5324 vmcb
->control
.exit_info_1
= 1;
5326 vmcb
->control
.exit_info_1
= 0;
5328 case SVM_EXIT_PAUSE
:
5330 * We get this for NOP only, but pause
5331 * is rep not, check this here
5333 if (info
->rep_prefix
!= REPE_PREFIX
)
5335 case SVM_EXIT_IOIO
: {
5339 if (info
->intercept
== x86_intercept_in
||
5340 info
->intercept
== x86_intercept_ins
) {
5341 exit_info
= ((info
->src_val
& 0xffff) << 16) |
5343 bytes
= info
->dst_bytes
;
5345 exit_info
= (info
->dst_val
& 0xffff) << 16;
5346 bytes
= info
->src_bytes
;
5349 if (info
->intercept
== x86_intercept_outs
||
5350 info
->intercept
== x86_intercept_ins
)
5351 exit_info
|= SVM_IOIO_STR_MASK
;
5353 if (info
->rep_prefix
)
5354 exit_info
|= SVM_IOIO_REP_MASK
;
5356 bytes
= min(bytes
, 4u);
5358 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
5360 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
5362 vmcb
->control
.exit_info_1
= exit_info
;
5363 vmcb
->control
.exit_info_2
= info
->next_rip
;
5371 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5372 if (static_cpu_has(X86_FEATURE_NRIPS
))
5373 vmcb
->control
.next_rip
= info
->next_rip
;
5374 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
5375 vmexit
= nested_svm_exit_handled(svm
);
5377 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
5384 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
5388 * We must have an instruction with interrupts enabled, so
5389 * the timer interrupt isn't delayed by the interrupt shadow.
5392 local_irq_disable();
5395 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
5399 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
5401 if (avic_handle_apic_id_update(vcpu
) != 0)
5403 if (avic_handle_dfr_update(vcpu
) != 0)
5405 avic_handle_ldr_update(vcpu
);
5408 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
5410 /* [63:9] are reserved. */
5411 vcpu
->arch
.mcg_cap
&= 0x1ff;
5414 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
5415 .cpu_has_kvm_support
= has_svm
,
5416 .disabled_by_bios
= is_disabled
,
5417 .hardware_setup
= svm_hardware_setup
,
5418 .hardware_unsetup
= svm_hardware_unsetup
,
5419 .check_processor_compatibility
= svm_check_processor_compat
,
5420 .hardware_enable
= svm_hardware_enable
,
5421 .hardware_disable
= svm_hardware_disable
,
5422 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
5423 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
5425 .vcpu_create
= svm_create_vcpu
,
5426 .vcpu_free
= svm_free_vcpu
,
5427 .vcpu_reset
= svm_vcpu_reset
,
5429 .vm_init
= avic_vm_init
,
5430 .vm_destroy
= avic_vm_destroy
,
5432 .prepare_guest_switch
= svm_prepare_guest_switch
,
5433 .vcpu_load
= svm_vcpu_load
,
5434 .vcpu_put
= svm_vcpu_put
,
5435 .vcpu_blocking
= svm_vcpu_blocking
,
5436 .vcpu_unblocking
= svm_vcpu_unblocking
,
5438 .update_bp_intercept
= update_bp_intercept
,
5439 .get_msr
= svm_get_msr
,
5440 .set_msr
= svm_set_msr
,
5441 .get_segment_base
= svm_get_segment_base
,
5442 .get_segment
= svm_get_segment
,
5443 .set_segment
= svm_set_segment
,
5444 .get_cpl
= svm_get_cpl
,
5445 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
5446 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
5447 .decache_cr3
= svm_decache_cr3
,
5448 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
5449 .set_cr0
= svm_set_cr0
,
5450 .set_cr3
= svm_set_cr3
,
5451 .set_cr4
= svm_set_cr4
,
5452 .set_efer
= svm_set_efer
,
5453 .get_idt
= svm_get_idt
,
5454 .set_idt
= svm_set_idt
,
5455 .get_gdt
= svm_get_gdt
,
5456 .set_gdt
= svm_set_gdt
,
5457 .get_dr6
= svm_get_dr6
,
5458 .set_dr6
= svm_set_dr6
,
5459 .set_dr7
= svm_set_dr7
,
5460 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
5461 .cache_reg
= svm_cache_reg
,
5462 .get_rflags
= svm_get_rflags
,
5463 .set_rflags
= svm_set_rflags
,
5465 .tlb_flush
= svm_flush_tlb
,
5467 .run
= svm_vcpu_run
,
5468 .handle_exit
= handle_exit
,
5469 .skip_emulated_instruction
= skip_emulated_instruction
,
5470 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
5471 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
5472 .patch_hypercall
= svm_patch_hypercall
,
5473 .set_irq
= svm_set_irq
,
5474 .set_nmi
= svm_inject_nmi
,
5475 .queue_exception
= svm_queue_exception
,
5476 .cancel_injection
= svm_cancel_injection
,
5477 .interrupt_allowed
= svm_interrupt_allowed
,
5478 .nmi_allowed
= svm_nmi_allowed
,
5479 .get_nmi_mask
= svm_get_nmi_mask
,
5480 .set_nmi_mask
= svm_set_nmi_mask
,
5481 .enable_nmi_window
= enable_nmi_window
,
5482 .enable_irq_window
= enable_irq_window
,
5483 .update_cr8_intercept
= update_cr8_intercept
,
5484 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
5485 .get_enable_apicv
= svm_get_enable_apicv
,
5486 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
5487 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
5488 .hwapic_irr_update
= svm_hwapic_irr_update
,
5489 .hwapic_isr_update
= svm_hwapic_isr_update
,
5490 .apicv_post_state_restore
= avic_post_state_restore
,
5492 .set_tss_addr
= svm_set_tss_addr
,
5493 .get_tdp_level
= get_npt_level
,
5494 .get_mt_mask
= svm_get_mt_mask
,
5496 .get_exit_info
= svm_get_exit_info
,
5498 .get_lpage_level
= svm_get_lpage_level
,
5500 .cpuid_update
= svm_cpuid_update
,
5502 .rdtscp_supported
= svm_rdtscp_supported
,
5503 .invpcid_supported
= svm_invpcid_supported
,
5504 .mpx_supported
= svm_mpx_supported
,
5505 .xsaves_supported
= svm_xsaves_supported
,
5507 .set_supported_cpuid
= svm_set_supported_cpuid
,
5509 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
5511 .write_tsc_offset
= svm_write_tsc_offset
,
5513 .set_tdp_cr3
= set_tdp_cr3
,
5515 .check_intercept
= svm_check_intercept
,
5516 .handle_external_intr
= svm_handle_external_intr
,
5518 .sched_in
= svm_sched_in
,
5520 .pmu_ops
= &amd_pmu_ops
,
5521 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
5522 .update_pi_irte
= svm_update_pi_irte
,
5523 .setup_mce
= svm_setup_mce
,
5526 static int __init
svm_init(void)
5528 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
5529 __alignof__(struct vcpu_svm
), THIS_MODULE
);
5532 static void __exit
svm_exit(void)
5537 module_init(svm_init
)
5538 module_exit(svm_exit
)