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x86/svm: Set IBRS value on VM entry and exit
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48
49 #include <asm/virtext.h>
50 #include "trace.h"
51
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53
54 MODULE_AUTHOR("Qumranet");
55 MODULE_LICENSE("GPL");
56
57 static const struct x86_cpu_id svm_cpu_id[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_SVM),
59 {}
60 };
61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62
63 #define IOPM_ALLOC_ORDER 2
64 #define MSRPM_ALLOC_ORDER 1
65
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
68
69 #define SVM_FEATURE_NPT (1 << 0)
70 #define SVM_FEATURE_LBRV (1 << 1)
71 #define SVM_FEATURE_SVML (1 << 2)
72 #define SVM_FEATURE_NRIP (1 << 3)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78
79 #define SVM_AVIC_DOORBELL 0xc001011b
80
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
92
93 /*
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
96 */
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115
116 static bool erratum_383_found __read_mostly;
117
118 static const u32 host_save_user_msrs[] = {
119 #ifdef CONFIG_X86_64
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
121 MSR_FS_BASE,
122 #endif
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
124 MSR_TSC_AUX,
125 };
126
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
128
129 struct kvm_vcpu;
130
131 struct nested_state {
132 struct vmcb *hsave;
133 u64 hsave_msr;
134 u64 vm_cr_msr;
135 u64 vmcb;
136
137 /* These are the merged vectors */
138 u32 *msrpm;
139
140 /* gpa pointers to the real vectors */
141 u64 vmcb_msrpm;
142 u64 vmcb_iopm;
143
144 /* A VMEXIT is required but not yet emulated */
145 bool exit_required;
146
147 /* cache for intercepts of the guest */
148 u32 intercept_cr;
149 u32 intercept_dr;
150 u32 intercept_exceptions;
151 u64 intercept;
152
153 /* Nested Paging related state */
154 u64 nested_cr3;
155 };
156
157 #define MSRPM_OFFSETS 16
158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
159
160 /*
161 * Set osvw_len to higher value when updated Revision Guides
162 * are published and we know what the new status bits are
163 */
164 static uint64_t osvw_len = 4, osvw_status;
165
166 struct vcpu_svm {
167 struct kvm_vcpu vcpu;
168 struct vmcb *vmcb;
169 unsigned long vmcb_pa;
170 struct svm_cpu_data *svm_data;
171 uint64_t asid_generation;
172 uint64_t sysenter_esp;
173 uint64_t sysenter_eip;
174 uint64_t tsc_aux;
175
176 u64 next_rip;
177
178 u64 spec_ctrl;
179
180 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
181 struct {
182 u16 fs;
183 u16 gs;
184 u16 ldt;
185 u64 gs_base;
186 } host;
187
188 u32 *msrpm;
189
190 ulong nmi_iret_rip;
191
192 struct nested_state nested;
193
194 bool nmi_singlestep;
195 u64 nmi_singlestep_guest_rflags;
196
197 unsigned int3_injected;
198 unsigned long int3_rip;
199
200 /* cached guest cpuid flags for faster access */
201 bool nrips_enabled : 1;
202
203 u32 ldr_reg;
204 struct page *avic_backing_page;
205 u64 *avic_physical_id_cache;
206 bool avic_is_running;
207
208 /*
209 * Per-vcpu list of struct amd_svm_iommu_ir:
210 * This is used mainly to store interrupt remapping information used
211 * when update the vcpu affinity. This avoids the need to scan for
212 * IRTE and try to match ga_tag in the IOMMU driver.
213 */
214 struct list_head ir_list;
215 spinlock_t ir_list_lock;
216 };
217
218 /*
219 * This is a wrapper of struct amd_iommu_ir_data.
220 */
221 struct amd_svm_iommu_ir {
222 struct list_head node; /* Used by SVM for per-vcpu ir_list */
223 void *data; /* Storing pointer to struct amd_ir_data */
224 };
225
226 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
227 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
228
229 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
230 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
231 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
232 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
233
234 static DEFINE_PER_CPU(u64, current_tsc_ratio);
235 #define TSC_RATIO_DEFAULT 0x0100000000ULL
236
237 #define MSR_INVALID 0xffffffffU
238
239 static const struct svm_direct_access_msrs {
240 u32 index; /* Index of the MSR */
241 bool always; /* True if intercept is always on */
242 } direct_access_msrs[] = {
243 { .index = MSR_STAR, .always = true },
244 { .index = MSR_IA32_SYSENTER_CS, .always = true },
245 #ifdef CONFIG_X86_64
246 { .index = MSR_GS_BASE, .always = true },
247 { .index = MSR_FS_BASE, .always = true },
248 { .index = MSR_KERNEL_GS_BASE, .always = true },
249 { .index = MSR_LSTAR, .always = true },
250 { .index = MSR_CSTAR, .always = true },
251 { .index = MSR_SYSCALL_MASK, .always = true },
252 #endif
253 { .index = MSR_IA32_SPEC_CTRL, .always = true },
254 { .index = MSR_IA32_PRED_CMD, .always = true },
255 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
256 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
257 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
258 { .index = MSR_IA32_LASTINTTOIP, .always = false },
259 { .index = MSR_INVALID, .always = false },
260 };
261
262 /* enable NPT for AMD64 and X86 with PAE */
263 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
264 static bool npt_enabled = true;
265 #else
266 static bool npt_enabled;
267 #endif
268
269 /* allow nested paging (virtualized MMU) for all guests */
270 static int npt = true;
271 module_param(npt, int, S_IRUGO);
272
273 /* allow nested virtualization in KVM/SVM */
274 static int nested = true;
275 module_param(nested, int, S_IRUGO);
276
277 /* enable / disable AVIC */
278 static int avic;
279 #ifdef CONFIG_X86_LOCAL_APIC
280 module_param(avic, int, S_IRUGO);
281 #endif
282
283 /* enable/disable Virtual VMLOAD VMSAVE */
284 static int vls = true;
285 module_param(vls, int, 0444);
286
287 /* AVIC VM ID bit masks and lock */
288 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
289 static DEFINE_SPINLOCK(avic_vm_id_lock);
290
291 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
292 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
293 static void svm_complete_interrupts(struct vcpu_svm *svm);
294
295 static int nested_svm_exit_handled(struct vcpu_svm *svm);
296 static int nested_svm_intercept(struct vcpu_svm *svm);
297 static int nested_svm_vmexit(struct vcpu_svm *svm);
298 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
299 bool has_error_code, u32 error_code);
300
301 enum {
302 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
303 pause filter count */
304 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
305 VMCB_ASID, /* ASID */
306 VMCB_INTR, /* int_ctl, int_vector */
307 VMCB_NPT, /* npt_en, nCR3, gPAT */
308 VMCB_CR, /* CR0, CR3, CR4, EFER */
309 VMCB_DR, /* DR6, DR7 */
310 VMCB_DT, /* GDT, IDT */
311 VMCB_SEG, /* CS, DS, SS, ES, CPL */
312 VMCB_CR2, /* CR2 only */
313 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
314 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
315 * AVIC PHYSICAL_TABLE pointer,
316 * AVIC LOGICAL_TABLE pointer
317 */
318 VMCB_DIRTY_MAX,
319 };
320
321 /* TPR and CR2 are always written before VMRUN */
322 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
323
324 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
325
326 static inline void mark_all_dirty(struct vmcb *vmcb)
327 {
328 vmcb->control.clean = 0;
329 }
330
331 static inline void mark_all_clean(struct vmcb *vmcb)
332 {
333 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
334 & ~VMCB_ALWAYS_DIRTY_MASK;
335 }
336
337 static inline void mark_dirty(struct vmcb *vmcb, int bit)
338 {
339 vmcb->control.clean &= ~(1 << bit);
340 }
341
342 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
343 {
344 return container_of(vcpu, struct vcpu_svm, vcpu);
345 }
346
347 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
348 {
349 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
350 mark_dirty(svm->vmcb, VMCB_AVIC);
351 }
352
353 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
354 {
355 struct vcpu_svm *svm = to_svm(vcpu);
356 u64 *entry = svm->avic_physical_id_cache;
357
358 if (!entry)
359 return false;
360
361 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
362 }
363
364 static void recalc_intercepts(struct vcpu_svm *svm)
365 {
366 struct vmcb_control_area *c, *h;
367 struct nested_state *g;
368
369 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
370
371 if (!is_guest_mode(&svm->vcpu))
372 return;
373
374 c = &svm->vmcb->control;
375 h = &svm->nested.hsave->control;
376 g = &svm->nested;
377
378 c->intercept_cr = h->intercept_cr | g->intercept_cr;
379 c->intercept_dr = h->intercept_dr | g->intercept_dr;
380 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
381 c->intercept = h->intercept | g->intercept;
382 }
383
384 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
385 {
386 if (is_guest_mode(&svm->vcpu))
387 return svm->nested.hsave;
388 else
389 return svm->vmcb;
390 }
391
392 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
393 {
394 struct vmcb *vmcb = get_host_vmcb(svm);
395
396 vmcb->control.intercept_cr |= (1U << bit);
397
398 recalc_intercepts(svm);
399 }
400
401 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
402 {
403 struct vmcb *vmcb = get_host_vmcb(svm);
404
405 vmcb->control.intercept_cr &= ~(1U << bit);
406
407 recalc_intercepts(svm);
408 }
409
410 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
411 {
412 struct vmcb *vmcb = get_host_vmcb(svm);
413
414 return vmcb->control.intercept_cr & (1U << bit);
415 }
416
417 static inline void set_dr_intercepts(struct vcpu_svm *svm)
418 {
419 struct vmcb *vmcb = get_host_vmcb(svm);
420
421 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
422 | (1 << INTERCEPT_DR1_READ)
423 | (1 << INTERCEPT_DR2_READ)
424 | (1 << INTERCEPT_DR3_READ)
425 | (1 << INTERCEPT_DR4_READ)
426 | (1 << INTERCEPT_DR5_READ)
427 | (1 << INTERCEPT_DR6_READ)
428 | (1 << INTERCEPT_DR7_READ)
429 | (1 << INTERCEPT_DR0_WRITE)
430 | (1 << INTERCEPT_DR1_WRITE)
431 | (1 << INTERCEPT_DR2_WRITE)
432 | (1 << INTERCEPT_DR3_WRITE)
433 | (1 << INTERCEPT_DR4_WRITE)
434 | (1 << INTERCEPT_DR5_WRITE)
435 | (1 << INTERCEPT_DR6_WRITE)
436 | (1 << INTERCEPT_DR7_WRITE);
437
438 recalc_intercepts(svm);
439 }
440
441 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
442 {
443 struct vmcb *vmcb = get_host_vmcb(svm);
444
445 vmcb->control.intercept_dr = 0;
446
447 recalc_intercepts(svm);
448 }
449
450 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
451 {
452 struct vmcb *vmcb = get_host_vmcb(svm);
453
454 vmcb->control.intercept_exceptions |= (1U << bit);
455
456 recalc_intercepts(svm);
457 }
458
459 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
460 {
461 struct vmcb *vmcb = get_host_vmcb(svm);
462
463 vmcb->control.intercept_exceptions &= ~(1U << bit);
464
465 recalc_intercepts(svm);
466 }
467
468 static inline void set_intercept(struct vcpu_svm *svm, int bit)
469 {
470 struct vmcb *vmcb = get_host_vmcb(svm);
471
472 vmcb->control.intercept |= (1ULL << bit);
473
474 recalc_intercepts(svm);
475 }
476
477 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
478 {
479 struct vmcb *vmcb = get_host_vmcb(svm);
480
481 vmcb->control.intercept &= ~(1ULL << bit);
482
483 recalc_intercepts(svm);
484 }
485
486 static inline void enable_gif(struct vcpu_svm *svm)
487 {
488 svm->vcpu.arch.hflags |= HF_GIF_MASK;
489 }
490
491 static inline void disable_gif(struct vcpu_svm *svm)
492 {
493 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
494 }
495
496 static inline bool gif_set(struct vcpu_svm *svm)
497 {
498 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
499 }
500
501 static unsigned long iopm_base;
502
503 struct kvm_ldttss_desc {
504 u16 limit0;
505 u16 base0;
506 unsigned base1:8, type:5, dpl:2, p:1;
507 unsigned limit1:4, zero0:3, g:1, base2:8;
508 u32 base3;
509 u32 zero1;
510 } __attribute__((packed));
511
512 struct svm_cpu_data {
513 int cpu;
514
515 u64 asid_generation;
516 u32 max_asid;
517 u32 next_asid;
518 struct kvm_ldttss_desc *tss_desc;
519
520 struct page *save_area;
521 };
522
523 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
524
525 struct svm_init_data {
526 int cpu;
527 int r;
528 };
529
530 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
531
532 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
533 #define MSRS_RANGE_SIZE 2048
534 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
535
536 static u32 svm_msrpm_offset(u32 msr)
537 {
538 u32 offset;
539 int i;
540
541 for (i = 0; i < NUM_MSR_MAPS; i++) {
542 if (msr < msrpm_ranges[i] ||
543 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
544 continue;
545
546 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
547 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
548
549 /* Now we have the u8 offset - but need the u32 offset */
550 return offset / 4;
551 }
552
553 /* MSR not in any range */
554 return MSR_INVALID;
555 }
556
557 #define MAX_INST_SIZE 15
558
559 static inline void clgi(void)
560 {
561 asm volatile (__ex(SVM_CLGI));
562 }
563
564 static inline void stgi(void)
565 {
566 asm volatile (__ex(SVM_STGI));
567 }
568
569 static inline void invlpga(unsigned long addr, u32 asid)
570 {
571 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
572 }
573
574 static int get_npt_level(void)
575 {
576 #ifdef CONFIG_X86_64
577 return PT64_ROOT_LEVEL;
578 #else
579 return PT32E_ROOT_LEVEL;
580 #endif
581 }
582
583 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
584 {
585 vcpu->arch.efer = efer;
586 if (!npt_enabled && !(efer & EFER_LMA))
587 efer &= ~EFER_LME;
588
589 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
590 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
591 }
592
593 static int is_external_interrupt(u32 info)
594 {
595 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
596 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
597 }
598
599 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
600 {
601 struct vcpu_svm *svm = to_svm(vcpu);
602 u32 ret = 0;
603
604 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
605 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
606 return ret;
607 }
608
609 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
610 {
611 struct vcpu_svm *svm = to_svm(vcpu);
612
613 if (mask == 0)
614 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
615 else
616 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
617
618 }
619
620 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
621 {
622 struct vcpu_svm *svm = to_svm(vcpu);
623
624 if (svm->vmcb->control.next_rip != 0) {
625 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
626 svm->next_rip = svm->vmcb->control.next_rip;
627 }
628
629 if (!svm->next_rip) {
630 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
631 EMULATE_DONE)
632 printk(KERN_DEBUG "%s: NOP\n", __func__);
633 return;
634 }
635 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
636 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
637 __func__, kvm_rip_read(vcpu), svm->next_rip);
638
639 kvm_rip_write(vcpu, svm->next_rip);
640 svm_set_interrupt_shadow(vcpu, 0);
641 }
642
643 static void svm_queue_exception(struct kvm_vcpu *vcpu)
644 {
645 struct vcpu_svm *svm = to_svm(vcpu);
646 unsigned nr = vcpu->arch.exception.nr;
647 bool has_error_code = vcpu->arch.exception.has_error_code;
648 bool reinject = vcpu->arch.exception.reinject;
649 u32 error_code = vcpu->arch.exception.error_code;
650
651 /*
652 * If we are within a nested VM we'd better #VMEXIT and let the guest
653 * handle the exception
654 */
655 if (!reinject &&
656 nested_svm_check_exception(svm, nr, has_error_code, error_code))
657 return;
658
659 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
660 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
661
662 /*
663 * For guest debugging where we have to reinject #BP if some
664 * INT3 is guest-owned:
665 * Emulate nRIP by moving RIP forward. Will fail if injection
666 * raises a fault that is not intercepted. Still better than
667 * failing in all cases.
668 */
669 skip_emulated_instruction(&svm->vcpu);
670 rip = kvm_rip_read(&svm->vcpu);
671 svm->int3_rip = rip + svm->vmcb->save.cs.base;
672 svm->int3_injected = rip - old_rip;
673 }
674
675 svm->vmcb->control.event_inj = nr
676 | SVM_EVTINJ_VALID
677 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
678 | SVM_EVTINJ_TYPE_EXEPT;
679 svm->vmcb->control.event_inj_err = error_code;
680 }
681
682 static void svm_init_erratum_383(void)
683 {
684 u32 low, high;
685 int err;
686 u64 val;
687
688 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
689 return;
690
691 /* Use _safe variants to not break nested virtualization */
692 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
693 if (err)
694 return;
695
696 val |= (1ULL << 47);
697
698 low = lower_32_bits(val);
699 high = upper_32_bits(val);
700
701 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
702
703 erratum_383_found = true;
704 }
705
706 static void svm_init_osvw(struct kvm_vcpu *vcpu)
707 {
708 /*
709 * Guests should see errata 400 and 415 as fixed (assuming that
710 * HLT and IO instructions are intercepted).
711 */
712 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
713 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
714
715 /*
716 * By increasing VCPU's osvw.length to 3 we are telling the guest that
717 * all osvw.status bits inside that length, including bit 0 (which is
718 * reserved for erratum 298), are valid. However, if host processor's
719 * osvw_len is 0 then osvw_status[0] carries no information. We need to
720 * be conservative here and therefore we tell the guest that erratum 298
721 * is present (because we really don't know).
722 */
723 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
724 vcpu->arch.osvw.status |= 1;
725 }
726
727 static int has_svm(void)
728 {
729 const char *msg;
730
731 if (!cpu_has_svm(&msg)) {
732 printk(KERN_INFO "has_svm: %s\n", msg);
733 return 0;
734 }
735
736 return 1;
737 }
738
739 static void svm_hardware_disable(void)
740 {
741 /* Make sure we clean up behind us */
742 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
743 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
744
745 cpu_svm_disable();
746
747 amd_pmu_disable_virt();
748 }
749
750 static int svm_hardware_enable(void)
751 {
752
753 struct svm_cpu_data *sd;
754 uint64_t efer;
755 struct desc_struct *gdt;
756 int me = raw_smp_processor_id();
757
758 rdmsrl(MSR_EFER, efer);
759 if (efer & EFER_SVME)
760 return -EBUSY;
761
762 if (!has_svm()) {
763 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
764 return -EINVAL;
765 }
766 sd = per_cpu(svm_data, me);
767 if (!sd) {
768 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
769 return -EINVAL;
770 }
771
772 sd->asid_generation = 1;
773 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
774 sd->next_asid = sd->max_asid + 1;
775
776 gdt = get_current_gdt_rw();
777 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
778
779 wrmsrl(MSR_EFER, efer | EFER_SVME);
780
781 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
782
783 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
784 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
785 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
786 }
787
788
789 /*
790 * Get OSVW bits.
791 *
792 * Note that it is possible to have a system with mixed processor
793 * revisions and therefore different OSVW bits. If bits are not the same
794 * on different processors then choose the worst case (i.e. if erratum
795 * is present on one processor and not on another then assume that the
796 * erratum is present everywhere).
797 */
798 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
799 uint64_t len, status = 0;
800 int err;
801
802 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
803 if (!err)
804 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
805 &err);
806
807 if (err)
808 osvw_status = osvw_len = 0;
809 else {
810 if (len < osvw_len)
811 osvw_len = len;
812 osvw_status |= status;
813 osvw_status &= (1ULL << osvw_len) - 1;
814 }
815 } else
816 osvw_status = osvw_len = 0;
817
818 svm_init_erratum_383();
819
820 amd_pmu_enable_virt();
821
822 return 0;
823 }
824
825 static void svm_cpu_uninit(int cpu)
826 {
827 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
828
829 if (!sd)
830 return;
831
832 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
833 __free_page(sd->save_area);
834 kfree(sd);
835 }
836
837 static int svm_cpu_init(int cpu)
838 {
839 struct svm_cpu_data *sd;
840 int r;
841
842 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
843 if (!sd)
844 return -ENOMEM;
845 sd->cpu = cpu;
846 sd->save_area = alloc_page(GFP_KERNEL);
847 r = -ENOMEM;
848 if (!sd->save_area)
849 goto err_1;
850
851 per_cpu(svm_data, cpu) = sd;
852
853 return 0;
854
855 err_1:
856 kfree(sd);
857 return r;
858
859 }
860
861 static bool valid_msr_intercept(u32 index)
862 {
863 int i;
864
865 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
866 if (direct_access_msrs[i].index == index)
867 return true;
868
869 return false;
870 }
871
872 static void set_msr_interception(u32 *msrpm, unsigned msr,
873 int read, int write)
874 {
875 u8 bit_read, bit_write;
876 unsigned long tmp;
877 u32 offset;
878
879 /*
880 * If this warning triggers extend the direct_access_msrs list at the
881 * beginning of the file
882 */
883 WARN_ON(!valid_msr_intercept(msr));
884
885 offset = svm_msrpm_offset(msr);
886 bit_read = 2 * (msr & 0x0f);
887 bit_write = 2 * (msr & 0x0f) + 1;
888 tmp = msrpm[offset];
889
890 BUG_ON(offset == MSR_INVALID);
891
892 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
893 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
894
895 msrpm[offset] = tmp;
896 }
897
898 static void svm_vcpu_init_msrpm(u32 *msrpm)
899 {
900 int i;
901
902 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
903
904 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
905 if (!direct_access_msrs[i].always)
906 continue;
907
908 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
909 }
910 }
911
912 static void add_msr_offset(u32 offset)
913 {
914 int i;
915
916 for (i = 0; i < MSRPM_OFFSETS; ++i) {
917
918 /* Offset already in list? */
919 if (msrpm_offsets[i] == offset)
920 return;
921
922 /* Slot used by another offset? */
923 if (msrpm_offsets[i] != MSR_INVALID)
924 continue;
925
926 /* Add offset to list */
927 msrpm_offsets[i] = offset;
928
929 return;
930 }
931
932 /*
933 * If this BUG triggers the msrpm_offsets table has an overflow. Just
934 * increase MSRPM_OFFSETS in this case.
935 */
936 BUG();
937 }
938
939 static void init_msrpm_offsets(void)
940 {
941 int i;
942
943 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
944
945 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
946 u32 offset;
947
948 offset = svm_msrpm_offset(direct_access_msrs[i].index);
949 BUG_ON(offset == MSR_INVALID);
950
951 add_msr_offset(offset);
952 }
953 }
954
955 static void svm_enable_lbrv(struct vcpu_svm *svm)
956 {
957 u32 *msrpm = svm->msrpm;
958
959 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
960 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
961 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
962 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
963 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
964 }
965
966 static void svm_disable_lbrv(struct vcpu_svm *svm)
967 {
968 u32 *msrpm = svm->msrpm;
969
970 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
971 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
972 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
973 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
974 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
975 }
976
977 static void disable_nmi_singlestep(struct vcpu_svm *svm)
978 {
979 svm->nmi_singlestep = false;
980 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
981 /* Clear our flags if they were not set by the guest */
982 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
983 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
984 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
985 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
986 }
987 }
988
989 /* Note:
990 * This hash table is used to map VM_ID to a struct kvm_arch,
991 * when handling AMD IOMMU GALOG notification to schedule in
992 * a particular vCPU.
993 */
994 #define SVM_VM_DATA_HASH_BITS 8
995 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
996 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
997
998 /* Note:
999 * This function is called from IOMMU driver to notify
1000 * SVM to schedule in a particular vCPU of a particular VM.
1001 */
1002 static int avic_ga_log_notifier(u32 ga_tag)
1003 {
1004 unsigned long flags;
1005 struct kvm_arch *ka = NULL;
1006 struct kvm_vcpu *vcpu = NULL;
1007 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1008 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1009
1010 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1011
1012 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1013 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1014 struct kvm *kvm = container_of(ka, struct kvm, arch);
1015 struct kvm_arch *vm_data = &kvm->arch;
1016
1017 if (vm_data->avic_vm_id != vm_id)
1018 continue;
1019 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1020 break;
1021 }
1022 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1023
1024 if (!vcpu)
1025 return 0;
1026
1027 /* Note:
1028 * At this point, the IOMMU should have already set the pending
1029 * bit in the vAPIC backing page. So, we just need to schedule
1030 * in the vcpu.
1031 */
1032 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1033 kvm_vcpu_wake_up(vcpu);
1034
1035 return 0;
1036 }
1037
1038 static __init int svm_hardware_setup(void)
1039 {
1040 int cpu;
1041 struct page *iopm_pages;
1042 void *iopm_va;
1043 int r;
1044
1045 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1046
1047 if (!iopm_pages)
1048 return -ENOMEM;
1049
1050 iopm_va = page_address(iopm_pages);
1051 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1052 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1053
1054 init_msrpm_offsets();
1055
1056 if (boot_cpu_has(X86_FEATURE_NX))
1057 kvm_enable_efer_bits(EFER_NX);
1058
1059 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1060 kvm_enable_efer_bits(EFER_FFXSR);
1061
1062 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1063 kvm_has_tsc_control = true;
1064 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1065 kvm_tsc_scaling_ratio_frac_bits = 32;
1066 }
1067
1068 if (nested) {
1069 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1070 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1071 }
1072
1073 for_each_possible_cpu(cpu) {
1074 r = svm_cpu_init(cpu);
1075 if (r)
1076 goto err;
1077 }
1078
1079 if (!boot_cpu_has(X86_FEATURE_NPT))
1080 npt_enabled = false;
1081
1082 if (npt_enabled && !npt) {
1083 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1084 npt_enabled = false;
1085 }
1086
1087 if (npt_enabled) {
1088 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1089 kvm_enable_tdp();
1090 } else
1091 kvm_disable_tdp();
1092
1093 if (avic) {
1094 if (!npt_enabled ||
1095 !boot_cpu_has(X86_FEATURE_AVIC) ||
1096 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1097 avic = false;
1098 } else {
1099 pr_info("AVIC enabled\n");
1100
1101 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1102 }
1103 }
1104
1105 if (vls) {
1106 if (!npt_enabled ||
1107 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1108 !IS_ENABLED(CONFIG_X86_64)) {
1109 vls = false;
1110 } else {
1111 pr_info("Virtual VMLOAD VMSAVE supported\n");
1112 }
1113 }
1114
1115 return 0;
1116
1117 err:
1118 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1119 iopm_base = 0;
1120 return r;
1121 }
1122
1123 static __exit void svm_hardware_unsetup(void)
1124 {
1125 int cpu;
1126
1127 for_each_possible_cpu(cpu)
1128 svm_cpu_uninit(cpu);
1129
1130 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1131 iopm_base = 0;
1132 }
1133
1134 static void init_seg(struct vmcb_seg *seg)
1135 {
1136 seg->selector = 0;
1137 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1138 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1139 seg->limit = 0xffff;
1140 seg->base = 0;
1141 }
1142
1143 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1144 {
1145 seg->selector = 0;
1146 seg->attrib = SVM_SELECTOR_P_MASK | type;
1147 seg->limit = 0xffff;
1148 seg->base = 0;
1149 }
1150
1151 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1152 {
1153 struct vcpu_svm *svm = to_svm(vcpu);
1154 u64 g_tsc_offset = 0;
1155
1156 if (is_guest_mode(vcpu)) {
1157 g_tsc_offset = svm->vmcb->control.tsc_offset -
1158 svm->nested.hsave->control.tsc_offset;
1159 svm->nested.hsave->control.tsc_offset = offset;
1160 } else
1161 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1162 svm->vmcb->control.tsc_offset,
1163 offset);
1164
1165 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1166
1167 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1168 }
1169
1170 static void avic_init_vmcb(struct vcpu_svm *svm)
1171 {
1172 struct vmcb *vmcb = svm->vmcb;
1173 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1174 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1175 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1176 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1177
1178 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1179 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1180 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1181 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1182 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1183 svm->vcpu.arch.apicv_active = true;
1184 }
1185
1186 static void init_vmcb(struct vcpu_svm *svm)
1187 {
1188 struct vmcb_control_area *control = &svm->vmcb->control;
1189 struct vmcb_save_area *save = &svm->vmcb->save;
1190
1191 svm->vcpu.arch.hflags = 0;
1192
1193 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1194 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1195 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1196 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1197 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1198 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1199 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1200 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1201
1202 set_dr_intercepts(svm);
1203
1204 set_exception_intercept(svm, PF_VECTOR);
1205 set_exception_intercept(svm, UD_VECTOR);
1206 set_exception_intercept(svm, MC_VECTOR);
1207 set_exception_intercept(svm, AC_VECTOR);
1208 set_exception_intercept(svm, DB_VECTOR);
1209
1210 set_intercept(svm, INTERCEPT_INTR);
1211 set_intercept(svm, INTERCEPT_NMI);
1212 set_intercept(svm, INTERCEPT_SMI);
1213 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1214 set_intercept(svm, INTERCEPT_RDPMC);
1215 set_intercept(svm, INTERCEPT_CPUID);
1216 set_intercept(svm, INTERCEPT_INVD);
1217 set_intercept(svm, INTERCEPT_HLT);
1218 set_intercept(svm, INTERCEPT_INVLPG);
1219 set_intercept(svm, INTERCEPT_INVLPGA);
1220 set_intercept(svm, INTERCEPT_IOIO_PROT);
1221 set_intercept(svm, INTERCEPT_MSR_PROT);
1222 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1223 set_intercept(svm, INTERCEPT_SHUTDOWN);
1224 set_intercept(svm, INTERCEPT_VMRUN);
1225 set_intercept(svm, INTERCEPT_VMMCALL);
1226 set_intercept(svm, INTERCEPT_VMLOAD);
1227 set_intercept(svm, INTERCEPT_VMSAVE);
1228 set_intercept(svm, INTERCEPT_STGI);
1229 set_intercept(svm, INTERCEPT_CLGI);
1230 set_intercept(svm, INTERCEPT_SKINIT);
1231 set_intercept(svm, INTERCEPT_WBINVD);
1232 set_intercept(svm, INTERCEPT_XSETBV);
1233
1234 if (!kvm_mwait_in_guest()) {
1235 set_intercept(svm, INTERCEPT_MONITOR);
1236 set_intercept(svm, INTERCEPT_MWAIT);
1237 }
1238
1239 control->iopm_base_pa = iopm_base;
1240 control->msrpm_base_pa = __pa(svm->msrpm);
1241 control->int_ctl = V_INTR_MASKING_MASK;
1242
1243 init_seg(&save->es);
1244 init_seg(&save->ss);
1245 init_seg(&save->ds);
1246 init_seg(&save->fs);
1247 init_seg(&save->gs);
1248
1249 save->cs.selector = 0xf000;
1250 save->cs.base = 0xffff0000;
1251 /* Executable/Readable Code Segment */
1252 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1253 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1254 save->cs.limit = 0xffff;
1255
1256 save->gdtr.limit = 0xffff;
1257 save->idtr.limit = 0xffff;
1258
1259 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1260 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1261
1262 svm_set_efer(&svm->vcpu, 0);
1263 save->dr6 = 0xffff0ff0;
1264 kvm_set_rflags(&svm->vcpu, 2);
1265 save->rip = 0x0000fff0;
1266 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1267
1268 /*
1269 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1270 * It also updates the guest-visible cr0 value.
1271 */
1272 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1273 kvm_mmu_reset_context(&svm->vcpu);
1274
1275 save->cr4 = X86_CR4_PAE;
1276 /* rdx = ?? */
1277
1278 if (npt_enabled) {
1279 /* Setup VMCB for Nested Paging */
1280 control->nested_ctl = 1;
1281 clr_intercept(svm, INTERCEPT_INVLPG);
1282 clr_exception_intercept(svm, PF_VECTOR);
1283 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1284 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1285 save->g_pat = svm->vcpu.arch.pat;
1286 save->cr3 = 0;
1287 save->cr4 = 0;
1288 }
1289 svm->asid_generation = 0;
1290
1291 svm->nested.vmcb = 0;
1292 svm->vcpu.arch.hflags = 0;
1293
1294 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1295 control->pause_filter_count = 3000;
1296 set_intercept(svm, INTERCEPT_PAUSE);
1297 }
1298
1299 if (avic)
1300 avic_init_vmcb(svm);
1301
1302 /*
1303 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1304 * in VMCB and clear intercepts to avoid #VMEXIT.
1305 */
1306 if (vls) {
1307 clr_intercept(svm, INTERCEPT_VMLOAD);
1308 clr_intercept(svm, INTERCEPT_VMSAVE);
1309 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1310 }
1311
1312 mark_all_dirty(svm->vmcb);
1313
1314 enable_gif(svm);
1315
1316 }
1317
1318 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1319 unsigned int index)
1320 {
1321 u64 *avic_physical_id_table;
1322 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1323
1324 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1325 return NULL;
1326
1327 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1328
1329 return &avic_physical_id_table[index];
1330 }
1331
1332 /**
1333 * Note:
1334 * AVIC hardware walks the nested page table to check permissions,
1335 * but does not use the SPA address specified in the leaf page
1336 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1337 * field of the VMCB. Therefore, we set up the
1338 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1339 */
1340 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1341 {
1342 struct kvm *kvm = vcpu->kvm;
1343 int ret;
1344
1345 if (kvm->arch.apic_access_page_done)
1346 return 0;
1347
1348 ret = x86_set_memory_region(kvm,
1349 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1350 APIC_DEFAULT_PHYS_BASE,
1351 PAGE_SIZE);
1352 if (ret)
1353 return ret;
1354
1355 kvm->arch.apic_access_page_done = true;
1356 return 0;
1357 }
1358
1359 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1360 {
1361 int ret;
1362 u64 *entry, new_entry;
1363 int id = vcpu->vcpu_id;
1364 struct vcpu_svm *svm = to_svm(vcpu);
1365
1366 ret = avic_init_access_page(vcpu);
1367 if (ret)
1368 return ret;
1369
1370 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1371 return -EINVAL;
1372
1373 if (!svm->vcpu.arch.apic->regs)
1374 return -EINVAL;
1375
1376 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1377
1378 /* Setting AVIC backing page address in the phy APIC ID table */
1379 entry = avic_get_physical_id_entry(vcpu, id);
1380 if (!entry)
1381 return -EINVAL;
1382
1383 new_entry = READ_ONCE(*entry);
1384 new_entry = (page_to_phys(svm->avic_backing_page) &
1385 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1386 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1387 WRITE_ONCE(*entry, new_entry);
1388
1389 svm->avic_physical_id_cache = entry;
1390
1391 return 0;
1392 }
1393
1394 static inline int avic_get_next_vm_id(void)
1395 {
1396 int id;
1397
1398 spin_lock(&avic_vm_id_lock);
1399
1400 /* AVIC VM ID is one-based. */
1401 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1402 if (id <= AVIC_VM_ID_MASK)
1403 __set_bit(id, avic_vm_id_bitmap);
1404 else
1405 id = -EAGAIN;
1406
1407 spin_unlock(&avic_vm_id_lock);
1408 return id;
1409 }
1410
1411 static inline int avic_free_vm_id(int id)
1412 {
1413 if (id <= 0 || id > AVIC_VM_ID_MASK)
1414 return -EINVAL;
1415
1416 spin_lock(&avic_vm_id_lock);
1417 __clear_bit(id, avic_vm_id_bitmap);
1418 spin_unlock(&avic_vm_id_lock);
1419 return 0;
1420 }
1421
1422 static void avic_vm_destroy(struct kvm *kvm)
1423 {
1424 unsigned long flags;
1425 struct kvm_arch *vm_data = &kvm->arch;
1426
1427 if (!avic)
1428 return;
1429
1430 avic_free_vm_id(vm_data->avic_vm_id);
1431
1432 if (vm_data->avic_logical_id_table_page)
1433 __free_page(vm_data->avic_logical_id_table_page);
1434 if (vm_data->avic_physical_id_table_page)
1435 __free_page(vm_data->avic_physical_id_table_page);
1436
1437 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1438 hash_del(&vm_data->hnode);
1439 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1440 }
1441
1442 static int avic_vm_init(struct kvm *kvm)
1443 {
1444 unsigned long flags;
1445 int vm_id, err = -ENOMEM;
1446 struct kvm_arch *vm_data = &kvm->arch;
1447 struct page *p_page;
1448 struct page *l_page;
1449
1450 if (!avic)
1451 return 0;
1452
1453 vm_id = avic_get_next_vm_id();
1454 if (vm_id < 0)
1455 return vm_id;
1456 vm_data->avic_vm_id = (u32)vm_id;
1457
1458 /* Allocating physical APIC ID table (4KB) */
1459 p_page = alloc_page(GFP_KERNEL);
1460 if (!p_page)
1461 goto free_avic;
1462
1463 vm_data->avic_physical_id_table_page = p_page;
1464 clear_page(page_address(p_page));
1465
1466 /* Allocating logical APIC ID table (4KB) */
1467 l_page = alloc_page(GFP_KERNEL);
1468 if (!l_page)
1469 goto free_avic;
1470
1471 vm_data->avic_logical_id_table_page = l_page;
1472 clear_page(page_address(l_page));
1473
1474 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1475 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1476 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1477
1478 return 0;
1479
1480 free_avic:
1481 avic_vm_destroy(kvm);
1482 return err;
1483 }
1484
1485 static inline int
1486 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1487 {
1488 int ret = 0;
1489 unsigned long flags;
1490 struct amd_svm_iommu_ir *ir;
1491 struct vcpu_svm *svm = to_svm(vcpu);
1492
1493 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1494 return 0;
1495
1496 /*
1497 * Here, we go through the per-vcpu ir_list to update all existing
1498 * interrupt remapping table entry targeting this vcpu.
1499 */
1500 spin_lock_irqsave(&svm->ir_list_lock, flags);
1501
1502 if (list_empty(&svm->ir_list))
1503 goto out;
1504
1505 list_for_each_entry(ir, &svm->ir_list, node) {
1506 ret = amd_iommu_update_ga(cpu, r, ir->data);
1507 if (ret)
1508 break;
1509 }
1510 out:
1511 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1512 return ret;
1513 }
1514
1515 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1516 {
1517 u64 entry;
1518 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1519 int h_physical_id = kvm_cpu_get_apicid(cpu);
1520 struct vcpu_svm *svm = to_svm(vcpu);
1521
1522 if (!kvm_vcpu_apicv_active(vcpu))
1523 return;
1524
1525 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1526 return;
1527
1528 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1529 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1530
1531 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1532 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1533
1534 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1535 if (svm->avic_is_running)
1536 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1537
1538 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1539 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1540 svm->avic_is_running);
1541 }
1542
1543 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1544 {
1545 u64 entry;
1546 struct vcpu_svm *svm = to_svm(vcpu);
1547
1548 if (!kvm_vcpu_apicv_active(vcpu))
1549 return;
1550
1551 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1552 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1553 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1554
1555 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1556 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1557 }
1558
1559 /**
1560 * This function is called during VCPU halt/unhalt.
1561 */
1562 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1563 {
1564 struct vcpu_svm *svm = to_svm(vcpu);
1565
1566 svm->avic_is_running = is_run;
1567 if (is_run)
1568 avic_vcpu_load(vcpu, vcpu->cpu);
1569 else
1570 avic_vcpu_put(vcpu);
1571 }
1572
1573 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1574 {
1575 struct vcpu_svm *svm = to_svm(vcpu);
1576 u32 dummy;
1577 u32 eax = 1;
1578
1579 if (!init_event) {
1580 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1581 MSR_IA32_APICBASE_ENABLE;
1582 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1583 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1584 }
1585 init_vmcb(svm);
1586
1587 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1588 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1589
1590 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1591 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1592 }
1593
1594 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1595 {
1596 struct vcpu_svm *svm;
1597 struct page *page;
1598 struct page *msrpm_pages;
1599 struct page *hsave_page;
1600 struct page *nested_msrpm_pages;
1601 int err;
1602
1603 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1604 if (!svm) {
1605 err = -ENOMEM;
1606 goto out;
1607 }
1608
1609 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1610 if (err)
1611 goto free_svm;
1612
1613 err = -ENOMEM;
1614 page = alloc_page(GFP_KERNEL);
1615 if (!page)
1616 goto uninit;
1617
1618 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1619 if (!msrpm_pages)
1620 goto free_page1;
1621
1622 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1623 if (!nested_msrpm_pages)
1624 goto free_page2;
1625
1626 hsave_page = alloc_page(GFP_KERNEL);
1627 if (!hsave_page)
1628 goto free_page3;
1629
1630 if (avic) {
1631 err = avic_init_backing_page(&svm->vcpu);
1632 if (err)
1633 goto free_page4;
1634
1635 INIT_LIST_HEAD(&svm->ir_list);
1636 spin_lock_init(&svm->ir_list_lock);
1637 }
1638
1639 /* We initialize this flag to true to make sure that the is_running
1640 * bit would be set the first time the vcpu is loaded.
1641 */
1642 svm->avic_is_running = true;
1643
1644 svm->nested.hsave = page_address(hsave_page);
1645
1646 svm->msrpm = page_address(msrpm_pages);
1647 svm_vcpu_init_msrpm(svm->msrpm);
1648
1649 svm->nested.msrpm = page_address(nested_msrpm_pages);
1650 svm_vcpu_init_msrpm(svm->nested.msrpm);
1651
1652 svm->vmcb = page_address(page);
1653 clear_page(svm->vmcb);
1654 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1655 svm->asid_generation = 0;
1656 init_vmcb(svm);
1657
1658 svm_init_osvw(&svm->vcpu);
1659
1660 return &svm->vcpu;
1661
1662 free_page4:
1663 __free_page(hsave_page);
1664 free_page3:
1665 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1666 free_page2:
1667 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1668 free_page1:
1669 __free_page(page);
1670 uninit:
1671 kvm_vcpu_uninit(&svm->vcpu);
1672 free_svm:
1673 kmem_cache_free(kvm_vcpu_cache, svm);
1674 out:
1675 return ERR_PTR(err);
1676 }
1677
1678 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1679 {
1680 struct vcpu_svm *svm = to_svm(vcpu);
1681
1682 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1683 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1684 __free_page(virt_to_page(svm->nested.hsave));
1685 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1686 kvm_vcpu_uninit(vcpu);
1687 kmem_cache_free(kvm_vcpu_cache, svm);
1688 }
1689
1690 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1691 {
1692 struct vcpu_svm *svm = to_svm(vcpu);
1693 int i;
1694
1695 if (unlikely(cpu != vcpu->cpu)) {
1696 svm->asid_generation = 0;
1697 mark_all_dirty(svm->vmcb);
1698 }
1699
1700 #ifdef CONFIG_X86_64
1701 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1702 #endif
1703 savesegment(fs, svm->host.fs);
1704 savesegment(gs, svm->host.gs);
1705 svm->host.ldt = kvm_read_ldt();
1706
1707 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1708 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1709
1710 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1711 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1712 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1713 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1714 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1715 }
1716 }
1717 /* This assumes that the kernel never uses MSR_TSC_AUX */
1718 if (static_cpu_has(X86_FEATURE_RDTSCP))
1719 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1720
1721 avic_vcpu_load(vcpu, cpu);
1722 }
1723
1724 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1725 {
1726 struct vcpu_svm *svm = to_svm(vcpu);
1727 int i;
1728
1729 avic_vcpu_put(vcpu);
1730
1731 ++vcpu->stat.host_state_reload;
1732 kvm_load_ldt(svm->host.ldt);
1733 #ifdef CONFIG_X86_64
1734 loadsegment(fs, svm->host.fs);
1735 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1736 load_gs_index(svm->host.gs);
1737 #else
1738 #ifdef CONFIG_X86_32_LAZY_GS
1739 loadsegment(gs, svm->host.gs);
1740 #endif
1741 #endif
1742 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1743 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1744 }
1745
1746 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1747 {
1748 avic_set_running(vcpu, false);
1749 }
1750
1751 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1752 {
1753 avic_set_running(vcpu, true);
1754 }
1755
1756 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1757 {
1758 struct vcpu_svm *svm = to_svm(vcpu);
1759 unsigned long rflags = svm->vmcb->save.rflags;
1760
1761 if (svm->nmi_singlestep) {
1762 /* Hide our flags if they were not set by the guest */
1763 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1764 rflags &= ~X86_EFLAGS_TF;
1765 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1766 rflags &= ~X86_EFLAGS_RF;
1767 }
1768 return rflags;
1769 }
1770
1771 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1772 {
1773 if (to_svm(vcpu)->nmi_singlestep)
1774 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1775
1776 /*
1777 * Any change of EFLAGS.VM is accompanied by a reload of SS
1778 * (caused by either a task switch or an inter-privilege IRET),
1779 * so we do not need to update the CPL here.
1780 */
1781 to_svm(vcpu)->vmcb->save.rflags = rflags;
1782 }
1783
1784 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1785 {
1786 switch (reg) {
1787 case VCPU_EXREG_PDPTR:
1788 BUG_ON(!npt_enabled);
1789 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1790 break;
1791 default:
1792 BUG();
1793 }
1794 }
1795
1796 static void svm_set_vintr(struct vcpu_svm *svm)
1797 {
1798 set_intercept(svm, INTERCEPT_VINTR);
1799 }
1800
1801 static void svm_clear_vintr(struct vcpu_svm *svm)
1802 {
1803 clr_intercept(svm, INTERCEPT_VINTR);
1804 }
1805
1806 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1807 {
1808 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1809
1810 switch (seg) {
1811 case VCPU_SREG_CS: return &save->cs;
1812 case VCPU_SREG_DS: return &save->ds;
1813 case VCPU_SREG_ES: return &save->es;
1814 case VCPU_SREG_FS: return &save->fs;
1815 case VCPU_SREG_GS: return &save->gs;
1816 case VCPU_SREG_SS: return &save->ss;
1817 case VCPU_SREG_TR: return &save->tr;
1818 case VCPU_SREG_LDTR: return &save->ldtr;
1819 }
1820 BUG();
1821 return NULL;
1822 }
1823
1824 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1825 {
1826 struct vmcb_seg *s = svm_seg(vcpu, seg);
1827
1828 return s->base;
1829 }
1830
1831 static void svm_get_segment(struct kvm_vcpu *vcpu,
1832 struct kvm_segment *var, int seg)
1833 {
1834 struct vmcb_seg *s = svm_seg(vcpu, seg);
1835
1836 var->base = s->base;
1837 var->limit = s->limit;
1838 var->selector = s->selector;
1839 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1840 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1841 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1842 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1843 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1844 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1845 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1846
1847 /*
1848 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1849 * However, the SVM spec states that the G bit is not observed by the
1850 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1851 * So let's synthesize a legal G bit for all segments, this helps
1852 * running KVM nested. It also helps cross-vendor migration, because
1853 * Intel's vmentry has a check on the 'G' bit.
1854 */
1855 var->g = s->limit > 0xfffff;
1856
1857 /*
1858 * AMD's VMCB does not have an explicit unusable field, so emulate it
1859 * for cross vendor migration purposes by "not present"
1860 */
1861 var->unusable = !var->present;
1862
1863 switch (seg) {
1864 case VCPU_SREG_TR:
1865 /*
1866 * Work around a bug where the busy flag in the tr selector
1867 * isn't exposed
1868 */
1869 var->type |= 0x2;
1870 break;
1871 case VCPU_SREG_DS:
1872 case VCPU_SREG_ES:
1873 case VCPU_SREG_FS:
1874 case VCPU_SREG_GS:
1875 /*
1876 * The accessed bit must always be set in the segment
1877 * descriptor cache, although it can be cleared in the
1878 * descriptor, the cached bit always remains at 1. Since
1879 * Intel has a check on this, set it here to support
1880 * cross-vendor migration.
1881 */
1882 if (!var->unusable)
1883 var->type |= 0x1;
1884 break;
1885 case VCPU_SREG_SS:
1886 /*
1887 * On AMD CPUs sometimes the DB bit in the segment
1888 * descriptor is left as 1, although the whole segment has
1889 * been made unusable. Clear it here to pass an Intel VMX
1890 * entry check when cross vendor migrating.
1891 */
1892 if (var->unusable)
1893 var->db = 0;
1894 /* This is symmetric with svm_set_segment() */
1895 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1896 break;
1897 }
1898 }
1899
1900 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1901 {
1902 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1903
1904 return save->cpl;
1905 }
1906
1907 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1908 {
1909 struct vcpu_svm *svm = to_svm(vcpu);
1910
1911 dt->size = svm->vmcb->save.idtr.limit;
1912 dt->address = svm->vmcb->save.idtr.base;
1913 }
1914
1915 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1916 {
1917 struct vcpu_svm *svm = to_svm(vcpu);
1918
1919 svm->vmcb->save.idtr.limit = dt->size;
1920 svm->vmcb->save.idtr.base = dt->address ;
1921 mark_dirty(svm->vmcb, VMCB_DT);
1922 }
1923
1924 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1925 {
1926 struct vcpu_svm *svm = to_svm(vcpu);
1927
1928 dt->size = svm->vmcb->save.gdtr.limit;
1929 dt->address = svm->vmcb->save.gdtr.base;
1930 }
1931
1932 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1933 {
1934 struct vcpu_svm *svm = to_svm(vcpu);
1935
1936 svm->vmcb->save.gdtr.limit = dt->size;
1937 svm->vmcb->save.gdtr.base = dt->address ;
1938 mark_dirty(svm->vmcb, VMCB_DT);
1939 }
1940
1941 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1942 {
1943 }
1944
1945 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1946 {
1947 }
1948
1949 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1950 {
1951 }
1952
1953 static void update_cr0_intercept(struct vcpu_svm *svm)
1954 {
1955 ulong gcr0 = svm->vcpu.arch.cr0;
1956 u64 *hcr0 = &svm->vmcb->save.cr0;
1957
1958 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1959 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1960
1961 mark_dirty(svm->vmcb, VMCB_CR);
1962
1963 if (gcr0 == *hcr0) {
1964 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1965 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1966 } else {
1967 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1968 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1969 }
1970 }
1971
1972 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1973 {
1974 struct vcpu_svm *svm = to_svm(vcpu);
1975
1976 #ifdef CONFIG_X86_64
1977 if (vcpu->arch.efer & EFER_LME) {
1978 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1979 vcpu->arch.efer |= EFER_LMA;
1980 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1981 }
1982
1983 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1984 vcpu->arch.efer &= ~EFER_LMA;
1985 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1986 }
1987 }
1988 #endif
1989 vcpu->arch.cr0 = cr0;
1990
1991 if (!npt_enabled)
1992 cr0 |= X86_CR0_PG | X86_CR0_WP;
1993
1994 /*
1995 * re-enable caching here because the QEMU bios
1996 * does not do it - this results in some delay at
1997 * reboot
1998 */
1999 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2000 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2001 svm->vmcb->save.cr0 = cr0;
2002 mark_dirty(svm->vmcb, VMCB_CR);
2003 update_cr0_intercept(svm);
2004 }
2005
2006 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2007 {
2008 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2009 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2010
2011 if (cr4 & X86_CR4_VMXE)
2012 return 1;
2013
2014 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2015 svm_flush_tlb(vcpu);
2016
2017 vcpu->arch.cr4 = cr4;
2018 if (!npt_enabled)
2019 cr4 |= X86_CR4_PAE;
2020 cr4 |= host_cr4_mce;
2021 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2022 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2023 return 0;
2024 }
2025
2026 static void svm_set_segment(struct kvm_vcpu *vcpu,
2027 struct kvm_segment *var, int seg)
2028 {
2029 struct vcpu_svm *svm = to_svm(vcpu);
2030 struct vmcb_seg *s = svm_seg(vcpu, seg);
2031
2032 s->base = var->base;
2033 s->limit = var->limit;
2034 s->selector = var->selector;
2035 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2036 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2037 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2038 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2039 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2040 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2041 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2042 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2043
2044 /*
2045 * This is always accurate, except if SYSRET returned to a segment
2046 * with SS.DPL != 3. Intel does not have this quirk, and always
2047 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2048 * would entail passing the CPL to userspace and back.
2049 */
2050 if (seg == VCPU_SREG_SS)
2051 /* This is symmetric with svm_get_segment() */
2052 svm->vmcb->save.cpl = (var->dpl & 3);
2053
2054 mark_dirty(svm->vmcb, VMCB_SEG);
2055 }
2056
2057 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2058 {
2059 struct vcpu_svm *svm = to_svm(vcpu);
2060
2061 clr_exception_intercept(svm, BP_VECTOR);
2062
2063 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2065 set_exception_intercept(svm, BP_VECTOR);
2066 } else
2067 vcpu->guest_debug = 0;
2068 }
2069
2070 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2071 {
2072 if (sd->next_asid > sd->max_asid) {
2073 ++sd->asid_generation;
2074 sd->next_asid = 1;
2075 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2076 }
2077
2078 svm->asid_generation = sd->asid_generation;
2079 svm->vmcb->control.asid = sd->next_asid++;
2080
2081 mark_dirty(svm->vmcb, VMCB_ASID);
2082 }
2083
2084 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2085 {
2086 return to_svm(vcpu)->vmcb->save.dr6;
2087 }
2088
2089 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2090 {
2091 struct vcpu_svm *svm = to_svm(vcpu);
2092
2093 svm->vmcb->save.dr6 = value;
2094 mark_dirty(svm->vmcb, VMCB_DR);
2095 }
2096
2097 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2098 {
2099 struct vcpu_svm *svm = to_svm(vcpu);
2100
2101 get_debugreg(vcpu->arch.db[0], 0);
2102 get_debugreg(vcpu->arch.db[1], 1);
2103 get_debugreg(vcpu->arch.db[2], 2);
2104 get_debugreg(vcpu->arch.db[3], 3);
2105 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2106 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2107
2108 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2109 set_dr_intercepts(svm);
2110 }
2111
2112 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2113 {
2114 struct vcpu_svm *svm = to_svm(vcpu);
2115
2116 svm->vmcb->save.dr7 = value;
2117 mark_dirty(svm->vmcb, VMCB_DR);
2118 }
2119
2120 static int pf_interception(struct vcpu_svm *svm)
2121 {
2122 u64 fault_address = svm->vmcb->control.exit_info_2;
2123 u64 error_code = svm->vmcb->control.exit_info_1;
2124
2125 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2126 svm->vmcb->control.insn_bytes,
2127 svm->vmcb->control.insn_len, !npt_enabled);
2128 }
2129
2130 static int db_interception(struct vcpu_svm *svm)
2131 {
2132 struct kvm_run *kvm_run = svm->vcpu.run;
2133
2134 if (!(svm->vcpu.guest_debug &
2135 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2136 !svm->nmi_singlestep) {
2137 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2138 return 1;
2139 }
2140
2141 if (svm->nmi_singlestep) {
2142 disable_nmi_singlestep(svm);
2143 }
2144
2145 if (svm->vcpu.guest_debug &
2146 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2147 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2148 kvm_run->debug.arch.pc =
2149 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2150 kvm_run->debug.arch.exception = DB_VECTOR;
2151 return 0;
2152 }
2153
2154 return 1;
2155 }
2156
2157 static int bp_interception(struct vcpu_svm *svm)
2158 {
2159 struct kvm_run *kvm_run = svm->vcpu.run;
2160
2161 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2162 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2163 kvm_run->debug.arch.exception = BP_VECTOR;
2164 return 0;
2165 }
2166
2167 static int ud_interception(struct vcpu_svm *svm)
2168 {
2169 int er;
2170
2171 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2172 if (er != EMULATE_DONE)
2173 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2174 return 1;
2175 }
2176
2177 static int ac_interception(struct vcpu_svm *svm)
2178 {
2179 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2180 return 1;
2181 }
2182
2183 static bool is_erratum_383(void)
2184 {
2185 int err, i;
2186 u64 value;
2187
2188 if (!erratum_383_found)
2189 return false;
2190
2191 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2192 if (err)
2193 return false;
2194
2195 /* Bit 62 may or may not be set for this mce */
2196 value &= ~(1ULL << 62);
2197
2198 if (value != 0xb600000000010015ULL)
2199 return false;
2200
2201 /* Clear MCi_STATUS registers */
2202 for (i = 0; i < 6; ++i)
2203 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2204
2205 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2206 if (!err) {
2207 u32 low, high;
2208
2209 value &= ~(1ULL << 2);
2210 low = lower_32_bits(value);
2211 high = upper_32_bits(value);
2212
2213 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2214 }
2215
2216 /* Flush tlb to evict multi-match entries */
2217 __flush_tlb_all();
2218
2219 return true;
2220 }
2221
2222 static void svm_handle_mce(struct vcpu_svm *svm)
2223 {
2224 if (is_erratum_383()) {
2225 /*
2226 * Erratum 383 triggered. Guest state is corrupt so kill the
2227 * guest.
2228 */
2229 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2230
2231 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2232
2233 return;
2234 }
2235
2236 /*
2237 * On an #MC intercept the MCE handler is not called automatically in
2238 * the host. So do it by hand here.
2239 */
2240 asm volatile (
2241 "int $0x12\n");
2242 /* not sure if we ever come back to this point */
2243
2244 return;
2245 }
2246
2247 static int mc_interception(struct vcpu_svm *svm)
2248 {
2249 return 1;
2250 }
2251
2252 static int shutdown_interception(struct vcpu_svm *svm)
2253 {
2254 struct kvm_run *kvm_run = svm->vcpu.run;
2255
2256 /*
2257 * VMCB is undefined after a SHUTDOWN intercept
2258 * so reinitialize it.
2259 */
2260 clear_page(svm->vmcb);
2261 init_vmcb(svm);
2262
2263 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2264 return 0;
2265 }
2266
2267 static int io_interception(struct vcpu_svm *svm)
2268 {
2269 struct kvm_vcpu *vcpu = &svm->vcpu;
2270 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2271 int size, in, string, ret;
2272 unsigned port;
2273
2274 ++svm->vcpu.stat.io_exits;
2275 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2276 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2277 if (string)
2278 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2279
2280 port = io_info >> 16;
2281 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2282 svm->next_rip = svm->vmcb->control.exit_info_2;
2283 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2284
2285 /*
2286 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2287 * KVM_EXIT_DEBUG here.
2288 */
2289 if (in)
2290 return kvm_fast_pio_in(vcpu, size, port) && ret;
2291 else
2292 return kvm_fast_pio_out(vcpu, size, port) && ret;
2293 }
2294
2295 static int nmi_interception(struct vcpu_svm *svm)
2296 {
2297 return 1;
2298 }
2299
2300 static int intr_interception(struct vcpu_svm *svm)
2301 {
2302 ++svm->vcpu.stat.irq_exits;
2303 return 1;
2304 }
2305
2306 static int nop_on_interception(struct vcpu_svm *svm)
2307 {
2308 return 1;
2309 }
2310
2311 static int halt_interception(struct vcpu_svm *svm)
2312 {
2313 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2314 return kvm_emulate_halt(&svm->vcpu);
2315 }
2316
2317 static int vmmcall_interception(struct vcpu_svm *svm)
2318 {
2319 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2320 return kvm_emulate_hypercall(&svm->vcpu);
2321 }
2322
2323 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2324 {
2325 struct vcpu_svm *svm = to_svm(vcpu);
2326
2327 return svm->nested.nested_cr3;
2328 }
2329
2330 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2331 {
2332 struct vcpu_svm *svm = to_svm(vcpu);
2333 u64 cr3 = svm->nested.nested_cr3;
2334 u64 pdpte;
2335 int ret;
2336
2337 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2338 offset_in_page(cr3) + index * 8, 8);
2339 if (ret)
2340 return 0;
2341 return pdpte;
2342 }
2343
2344 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2345 unsigned long root)
2346 {
2347 struct vcpu_svm *svm = to_svm(vcpu);
2348
2349 svm->vmcb->control.nested_cr3 = root;
2350 mark_dirty(svm->vmcb, VMCB_NPT);
2351 svm_flush_tlb(vcpu);
2352 }
2353
2354 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2355 struct x86_exception *fault)
2356 {
2357 struct vcpu_svm *svm = to_svm(vcpu);
2358
2359 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2360 /*
2361 * TODO: track the cause of the nested page fault, and
2362 * correctly fill in the high bits of exit_info_1.
2363 */
2364 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2365 svm->vmcb->control.exit_code_hi = 0;
2366 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2367 svm->vmcb->control.exit_info_2 = fault->address;
2368 }
2369
2370 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2371 svm->vmcb->control.exit_info_1 |= fault->error_code;
2372
2373 /*
2374 * The present bit is always zero for page structure faults on real
2375 * hardware.
2376 */
2377 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2378 svm->vmcb->control.exit_info_1 &= ~1;
2379
2380 nested_svm_vmexit(svm);
2381 }
2382
2383 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2384 {
2385 WARN_ON(mmu_is_nested(vcpu));
2386 kvm_init_shadow_mmu(vcpu);
2387 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2388 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2389 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2390 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2391 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2392 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2393 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2394 }
2395
2396 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2397 {
2398 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2399 }
2400
2401 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2402 {
2403 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2404 !is_paging(&svm->vcpu)) {
2405 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2406 return 1;
2407 }
2408
2409 if (svm->vmcb->save.cpl) {
2410 kvm_inject_gp(&svm->vcpu, 0);
2411 return 1;
2412 }
2413
2414 return 0;
2415 }
2416
2417 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2418 bool has_error_code, u32 error_code)
2419 {
2420 int vmexit;
2421
2422 if (!is_guest_mode(&svm->vcpu))
2423 return 0;
2424
2425 vmexit = nested_svm_intercept(svm);
2426 if (vmexit != NESTED_EXIT_DONE)
2427 return 0;
2428
2429 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2430 svm->vmcb->control.exit_code_hi = 0;
2431 svm->vmcb->control.exit_info_1 = error_code;
2432
2433 /*
2434 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2435 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2436 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2437 * written only when inject_pending_event runs (DR6 would written here
2438 * too). This should be conditional on a new capability---if the
2439 * capability is disabled, kvm_multiple_exception would write the
2440 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2441 */
2442 if (svm->vcpu.arch.exception.nested_apf)
2443 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2444 else
2445 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2446
2447 svm->nested.exit_required = true;
2448 return vmexit;
2449 }
2450
2451 /* This function returns true if it is save to enable the irq window */
2452 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2453 {
2454 if (!is_guest_mode(&svm->vcpu))
2455 return true;
2456
2457 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2458 return true;
2459
2460 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2461 return false;
2462
2463 /*
2464 * if vmexit was already requested (by intercepted exception
2465 * for instance) do not overwrite it with "external interrupt"
2466 * vmexit.
2467 */
2468 if (svm->nested.exit_required)
2469 return false;
2470
2471 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2472 svm->vmcb->control.exit_info_1 = 0;
2473 svm->vmcb->control.exit_info_2 = 0;
2474
2475 if (svm->nested.intercept & 1ULL) {
2476 /*
2477 * The #vmexit can't be emulated here directly because this
2478 * code path runs with irqs and preemption disabled. A
2479 * #vmexit emulation might sleep. Only signal request for
2480 * the #vmexit here.
2481 */
2482 svm->nested.exit_required = true;
2483 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2484 return false;
2485 }
2486
2487 return true;
2488 }
2489
2490 /* This function returns true if it is save to enable the nmi window */
2491 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2492 {
2493 if (!is_guest_mode(&svm->vcpu))
2494 return true;
2495
2496 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2497 return true;
2498
2499 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2500 svm->nested.exit_required = true;
2501
2502 return false;
2503 }
2504
2505 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2506 {
2507 struct page *page;
2508
2509 might_sleep();
2510
2511 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2512 if (is_error_page(page))
2513 goto error;
2514
2515 *_page = page;
2516
2517 return kmap(page);
2518
2519 error:
2520 kvm_inject_gp(&svm->vcpu, 0);
2521
2522 return NULL;
2523 }
2524
2525 static void nested_svm_unmap(struct page *page)
2526 {
2527 kunmap(page);
2528 kvm_release_page_dirty(page);
2529 }
2530
2531 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2532 {
2533 unsigned port, size, iopm_len;
2534 u16 val, mask;
2535 u8 start_bit;
2536 u64 gpa;
2537
2538 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2539 return NESTED_EXIT_HOST;
2540
2541 port = svm->vmcb->control.exit_info_1 >> 16;
2542 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2543 SVM_IOIO_SIZE_SHIFT;
2544 gpa = svm->nested.vmcb_iopm + (port / 8);
2545 start_bit = port % 8;
2546 iopm_len = (start_bit + size > 8) ? 2 : 1;
2547 mask = (0xf >> (4 - size)) << start_bit;
2548 val = 0;
2549
2550 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2551 return NESTED_EXIT_DONE;
2552
2553 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2554 }
2555
2556 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2557 {
2558 u32 offset, msr, value;
2559 int write, mask;
2560
2561 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2562 return NESTED_EXIT_HOST;
2563
2564 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2565 offset = svm_msrpm_offset(msr);
2566 write = svm->vmcb->control.exit_info_1 & 1;
2567 mask = 1 << ((2 * (msr & 0xf)) + write);
2568
2569 if (offset == MSR_INVALID)
2570 return NESTED_EXIT_DONE;
2571
2572 /* Offset is in 32 bit units but need in 8 bit units */
2573 offset *= 4;
2574
2575 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2576 return NESTED_EXIT_DONE;
2577
2578 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2579 }
2580
2581 /* DB exceptions for our internal use must not cause vmexit */
2582 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2583 {
2584 unsigned long dr6;
2585
2586 /* if we're not singlestepping, it's not ours */
2587 if (!svm->nmi_singlestep)
2588 return NESTED_EXIT_DONE;
2589
2590 /* if it's not a singlestep exception, it's not ours */
2591 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2592 return NESTED_EXIT_DONE;
2593 if (!(dr6 & DR6_BS))
2594 return NESTED_EXIT_DONE;
2595
2596 /* if the guest is singlestepping, it should get the vmexit */
2597 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2598 disable_nmi_singlestep(svm);
2599 return NESTED_EXIT_DONE;
2600 }
2601
2602 /* it's ours, the nested hypervisor must not see this one */
2603 return NESTED_EXIT_HOST;
2604 }
2605
2606 static int nested_svm_exit_special(struct vcpu_svm *svm)
2607 {
2608 u32 exit_code = svm->vmcb->control.exit_code;
2609
2610 switch (exit_code) {
2611 case SVM_EXIT_INTR:
2612 case SVM_EXIT_NMI:
2613 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2614 return NESTED_EXIT_HOST;
2615 case SVM_EXIT_NPF:
2616 /* For now we are always handling NPFs when using them */
2617 if (npt_enabled)
2618 return NESTED_EXIT_HOST;
2619 break;
2620 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2621 /* When we're shadowing, trap PFs, but not async PF */
2622 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2623 return NESTED_EXIT_HOST;
2624 break;
2625 default:
2626 break;
2627 }
2628
2629 return NESTED_EXIT_CONTINUE;
2630 }
2631
2632 /*
2633 * If this function returns true, this #vmexit was already handled
2634 */
2635 static int nested_svm_intercept(struct vcpu_svm *svm)
2636 {
2637 u32 exit_code = svm->vmcb->control.exit_code;
2638 int vmexit = NESTED_EXIT_HOST;
2639
2640 switch (exit_code) {
2641 case SVM_EXIT_MSR:
2642 vmexit = nested_svm_exit_handled_msr(svm);
2643 break;
2644 case SVM_EXIT_IOIO:
2645 vmexit = nested_svm_intercept_ioio(svm);
2646 break;
2647 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2648 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2649 if (svm->nested.intercept_cr & bit)
2650 vmexit = NESTED_EXIT_DONE;
2651 break;
2652 }
2653 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2654 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2655 if (svm->nested.intercept_dr & bit)
2656 vmexit = NESTED_EXIT_DONE;
2657 break;
2658 }
2659 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2660 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2661 if (svm->nested.intercept_exceptions & excp_bits) {
2662 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2663 vmexit = nested_svm_intercept_db(svm);
2664 else
2665 vmexit = NESTED_EXIT_DONE;
2666 }
2667 /* async page fault always cause vmexit */
2668 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2669 svm->vcpu.arch.exception.nested_apf != 0)
2670 vmexit = NESTED_EXIT_DONE;
2671 break;
2672 }
2673 case SVM_EXIT_ERR: {
2674 vmexit = NESTED_EXIT_DONE;
2675 break;
2676 }
2677 default: {
2678 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2679 if (svm->nested.intercept & exit_bits)
2680 vmexit = NESTED_EXIT_DONE;
2681 }
2682 }
2683
2684 return vmexit;
2685 }
2686
2687 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2688 {
2689 int vmexit;
2690
2691 vmexit = nested_svm_intercept(svm);
2692
2693 if (vmexit == NESTED_EXIT_DONE)
2694 nested_svm_vmexit(svm);
2695
2696 return vmexit;
2697 }
2698
2699 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2700 {
2701 struct vmcb_control_area *dst = &dst_vmcb->control;
2702 struct vmcb_control_area *from = &from_vmcb->control;
2703
2704 dst->intercept_cr = from->intercept_cr;
2705 dst->intercept_dr = from->intercept_dr;
2706 dst->intercept_exceptions = from->intercept_exceptions;
2707 dst->intercept = from->intercept;
2708 dst->iopm_base_pa = from->iopm_base_pa;
2709 dst->msrpm_base_pa = from->msrpm_base_pa;
2710 dst->tsc_offset = from->tsc_offset;
2711 dst->asid = from->asid;
2712 dst->tlb_ctl = from->tlb_ctl;
2713 dst->int_ctl = from->int_ctl;
2714 dst->int_vector = from->int_vector;
2715 dst->int_state = from->int_state;
2716 dst->exit_code = from->exit_code;
2717 dst->exit_code_hi = from->exit_code_hi;
2718 dst->exit_info_1 = from->exit_info_1;
2719 dst->exit_info_2 = from->exit_info_2;
2720 dst->exit_int_info = from->exit_int_info;
2721 dst->exit_int_info_err = from->exit_int_info_err;
2722 dst->nested_ctl = from->nested_ctl;
2723 dst->event_inj = from->event_inj;
2724 dst->event_inj_err = from->event_inj_err;
2725 dst->nested_cr3 = from->nested_cr3;
2726 dst->virt_ext = from->virt_ext;
2727 }
2728
2729 static int nested_svm_vmexit(struct vcpu_svm *svm)
2730 {
2731 struct vmcb *nested_vmcb;
2732 struct vmcb *hsave = svm->nested.hsave;
2733 struct vmcb *vmcb = svm->vmcb;
2734 struct page *page;
2735
2736 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2737 vmcb->control.exit_info_1,
2738 vmcb->control.exit_info_2,
2739 vmcb->control.exit_int_info,
2740 vmcb->control.exit_int_info_err,
2741 KVM_ISA_SVM);
2742
2743 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2744 if (!nested_vmcb)
2745 return 1;
2746
2747 /* Exit Guest-Mode */
2748 leave_guest_mode(&svm->vcpu);
2749 svm->nested.vmcb = 0;
2750
2751 /* Give the current vmcb to the guest */
2752 disable_gif(svm);
2753
2754 nested_vmcb->save.es = vmcb->save.es;
2755 nested_vmcb->save.cs = vmcb->save.cs;
2756 nested_vmcb->save.ss = vmcb->save.ss;
2757 nested_vmcb->save.ds = vmcb->save.ds;
2758 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2759 nested_vmcb->save.idtr = vmcb->save.idtr;
2760 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2761 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2762 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2763 nested_vmcb->save.cr2 = vmcb->save.cr2;
2764 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2765 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2766 nested_vmcb->save.rip = vmcb->save.rip;
2767 nested_vmcb->save.rsp = vmcb->save.rsp;
2768 nested_vmcb->save.rax = vmcb->save.rax;
2769 nested_vmcb->save.dr7 = vmcb->save.dr7;
2770 nested_vmcb->save.dr6 = vmcb->save.dr6;
2771 nested_vmcb->save.cpl = vmcb->save.cpl;
2772
2773 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2774 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2775 nested_vmcb->control.int_state = vmcb->control.int_state;
2776 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2777 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2778 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2779 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2780 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2781 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2782
2783 if (svm->nrips_enabled)
2784 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2785
2786 /*
2787 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2788 * to make sure that we do not lose injected events. So check event_inj
2789 * here and copy it to exit_int_info if it is valid.
2790 * Exit_int_info and event_inj can't be both valid because the case
2791 * below only happens on a VMRUN instruction intercept which has
2792 * no valid exit_int_info set.
2793 */
2794 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2795 struct vmcb_control_area *nc = &nested_vmcb->control;
2796
2797 nc->exit_int_info = vmcb->control.event_inj;
2798 nc->exit_int_info_err = vmcb->control.event_inj_err;
2799 }
2800
2801 nested_vmcb->control.tlb_ctl = 0;
2802 nested_vmcb->control.event_inj = 0;
2803 nested_vmcb->control.event_inj_err = 0;
2804
2805 /* We always set V_INTR_MASKING and remember the old value in hflags */
2806 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2807 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2808
2809 /* Restore the original control entries */
2810 copy_vmcb_control_area(vmcb, hsave);
2811
2812 kvm_clear_exception_queue(&svm->vcpu);
2813 kvm_clear_interrupt_queue(&svm->vcpu);
2814
2815 svm->nested.nested_cr3 = 0;
2816
2817 /* Restore selected save entries */
2818 svm->vmcb->save.es = hsave->save.es;
2819 svm->vmcb->save.cs = hsave->save.cs;
2820 svm->vmcb->save.ss = hsave->save.ss;
2821 svm->vmcb->save.ds = hsave->save.ds;
2822 svm->vmcb->save.gdtr = hsave->save.gdtr;
2823 svm->vmcb->save.idtr = hsave->save.idtr;
2824 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2825 svm_set_efer(&svm->vcpu, hsave->save.efer);
2826 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2827 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2828 if (npt_enabled) {
2829 svm->vmcb->save.cr3 = hsave->save.cr3;
2830 svm->vcpu.arch.cr3 = hsave->save.cr3;
2831 } else {
2832 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2833 }
2834 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2835 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2836 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2837 svm->vmcb->save.dr7 = 0;
2838 svm->vmcb->save.cpl = 0;
2839 svm->vmcb->control.exit_int_info = 0;
2840
2841 mark_all_dirty(svm->vmcb);
2842
2843 nested_svm_unmap(page);
2844
2845 nested_svm_uninit_mmu_context(&svm->vcpu);
2846 kvm_mmu_reset_context(&svm->vcpu);
2847 kvm_mmu_load(&svm->vcpu);
2848
2849 return 0;
2850 }
2851
2852 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2853 {
2854 /*
2855 * This function merges the msr permission bitmaps of kvm and the
2856 * nested vmcb. It is optimized in that it only merges the parts where
2857 * the kvm msr permission bitmap may contain zero bits
2858 */
2859 int i;
2860
2861 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2862 return true;
2863
2864 for (i = 0; i < MSRPM_OFFSETS; i++) {
2865 u32 value, p;
2866 u64 offset;
2867
2868 if (msrpm_offsets[i] == 0xffffffff)
2869 break;
2870
2871 p = msrpm_offsets[i];
2872 offset = svm->nested.vmcb_msrpm + (p * 4);
2873
2874 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2875 return false;
2876
2877 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2878 }
2879
2880 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2881
2882 return true;
2883 }
2884
2885 static bool nested_vmcb_checks(struct vmcb *vmcb)
2886 {
2887 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2888 return false;
2889
2890 if (vmcb->control.asid == 0)
2891 return false;
2892
2893 if (vmcb->control.nested_ctl && !npt_enabled)
2894 return false;
2895
2896 return true;
2897 }
2898
2899 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2900 {
2901 struct vmcb *nested_vmcb;
2902 struct vmcb *hsave = svm->nested.hsave;
2903 struct vmcb *vmcb = svm->vmcb;
2904 struct page *page;
2905 u64 vmcb_gpa;
2906
2907 vmcb_gpa = svm->vmcb->save.rax;
2908
2909 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2910 if (!nested_vmcb)
2911 return false;
2912
2913 if (!nested_vmcb_checks(nested_vmcb)) {
2914 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2915 nested_vmcb->control.exit_code_hi = 0;
2916 nested_vmcb->control.exit_info_1 = 0;
2917 nested_vmcb->control.exit_info_2 = 0;
2918
2919 nested_svm_unmap(page);
2920
2921 return false;
2922 }
2923
2924 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2925 nested_vmcb->save.rip,
2926 nested_vmcb->control.int_ctl,
2927 nested_vmcb->control.event_inj,
2928 nested_vmcb->control.nested_ctl);
2929
2930 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2931 nested_vmcb->control.intercept_cr >> 16,
2932 nested_vmcb->control.intercept_exceptions,
2933 nested_vmcb->control.intercept);
2934
2935 /* Clear internal status */
2936 kvm_clear_exception_queue(&svm->vcpu);
2937 kvm_clear_interrupt_queue(&svm->vcpu);
2938
2939 /*
2940 * Save the old vmcb, so we don't need to pick what we save, but can
2941 * restore everything when a VMEXIT occurs
2942 */
2943 hsave->save.es = vmcb->save.es;
2944 hsave->save.cs = vmcb->save.cs;
2945 hsave->save.ss = vmcb->save.ss;
2946 hsave->save.ds = vmcb->save.ds;
2947 hsave->save.gdtr = vmcb->save.gdtr;
2948 hsave->save.idtr = vmcb->save.idtr;
2949 hsave->save.efer = svm->vcpu.arch.efer;
2950 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2951 hsave->save.cr4 = svm->vcpu.arch.cr4;
2952 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2953 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2954 hsave->save.rsp = vmcb->save.rsp;
2955 hsave->save.rax = vmcb->save.rax;
2956 if (npt_enabled)
2957 hsave->save.cr3 = vmcb->save.cr3;
2958 else
2959 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2960
2961 copy_vmcb_control_area(hsave, vmcb);
2962
2963 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2964 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2965 else
2966 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2967
2968 if (nested_vmcb->control.nested_ctl) {
2969 kvm_mmu_unload(&svm->vcpu);
2970 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2971 nested_svm_init_mmu_context(&svm->vcpu);
2972 }
2973
2974 /* Load the nested guest state */
2975 svm->vmcb->save.es = nested_vmcb->save.es;
2976 svm->vmcb->save.cs = nested_vmcb->save.cs;
2977 svm->vmcb->save.ss = nested_vmcb->save.ss;
2978 svm->vmcb->save.ds = nested_vmcb->save.ds;
2979 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2980 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2981 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2982 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2983 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2984 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2985 if (npt_enabled) {
2986 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2987 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2988 } else
2989 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2990
2991 /* Guest paging mode is active - reset mmu */
2992 kvm_mmu_reset_context(&svm->vcpu);
2993
2994 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2995 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2996 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2997 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2998
2999 /* In case we don't even reach vcpu_run, the fields are not updated */
3000 svm->vmcb->save.rax = nested_vmcb->save.rax;
3001 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3002 svm->vmcb->save.rip = nested_vmcb->save.rip;
3003 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3004 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3005 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3006
3007 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3008 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3009
3010 /* cache intercepts */
3011 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3012 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3013 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3014 svm->nested.intercept = nested_vmcb->control.intercept;
3015
3016 svm_flush_tlb(&svm->vcpu);
3017 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3018 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3019 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3020 else
3021 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3022
3023 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3024 /* We only want the cr8 intercept bits of the guest */
3025 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3026 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3027 }
3028
3029 /* We don't want to see VMMCALLs from a nested guest */
3030 clr_intercept(svm, INTERCEPT_VMMCALL);
3031
3032 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3033 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3034 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3035 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3036 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3037 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3038
3039 nested_svm_unmap(page);
3040
3041 /* Enter Guest-Mode */
3042 enter_guest_mode(&svm->vcpu);
3043
3044 /*
3045 * Merge guest and host intercepts - must be called with vcpu in
3046 * guest-mode to take affect here
3047 */
3048 recalc_intercepts(svm);
3049
3050 svm->nested.vmcb = vmcb_gpa;
3051
3052 enable_gif(svm);
3053
3054 mark_all_dirty(svm->vmcb);
3055
3056 return true;
3057 }
3058
3059 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3060 {
3061 to_vmcb->save.fs = from_vmcb->save.fs;
3062 to_vmcb->save.gs = from_vmcb->save.gs;
3063 to_vmcb->save.tr = from_vmcb->save.tr;
3064 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3065 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3066 to_vmcb->save.star = from_vmcb->save.star;
3067 to_vmcb->save.lstar = from_vmcb->save.lstar;
3068 to_vmcb->save.cstar = from_vmcb->save.cstar;
3069 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3070 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3071 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3072 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3073 }
3074
3075 static int vmload_interception(struct vcpu_svm *svm)
3076 {
3077 struct vmcb *nested_vmcb;
3078 struct page *page;
3079 int ret;
3080
3081 if (nested_svm_check_permissions(svm))
3082 return 1;
3083
3084 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3085 if (!nested_vmcb)
3086 return 1;
3087
3088 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3089 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3090
3091 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3092 nested_svm_unmap(page);
3093
3094 return ret;
3095 }
3096
3097 static int vmsave_interception(struct vcpu_svm *svm)
3098 {
3099 struct vmcb *nested_vmcb;
3100 struct page *page;
3101 int ret;
3102
3103 if (nested_svm_check_permissions(svm))
3104 return 1;
3105
3106 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3107 if (!nested_vmcb)
3108 return 1;
3109
3110 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3111 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3112
3113 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3114 nested_svm_unmap(page);
3115
3116 return ret;
3117 }
3118
3119 static int vmrun_interception(struct vcpu_svm *svm)
3120 {
3121 if (nested_svm_check_permissions(svm))
3122 return 1;
3123
3124 /* Save rip after vmrun instruction */
3125 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3126
3127 if (!nested_svm_vmrun(svm))
3128 return 1;
3129
3130 if (!nested_svm_vmrun_msrpm(svm))
3131 goto failed;
3132
3133 return 1;
3134
3135 failed:
3136
3137 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3138 svm->vmcb->control.exit_code_hi = 0;
3139 svm->vmcb->control.exit_info_1 = 0;
3140 svm->vmcb->control.exit_info_2 = 0;
3141
3142 nested_svm_vmexit(svm);
3143
3144 return 1;
3145 }
3146
3147 static int stgi_interception(struct vcpu_svm *svm)
3148 {
3149 int ret;
3150
3151 if (nested_svm_check_permissions(svm))
3152 return 1;
3153
3154 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3155 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3156 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3157
3158 enable_gif(svm);
3159
3160 return ret;
3161 }
3162
3163 static int clgi_interception(struct vcpu_svm *svm)
3164 {
3165 int ret;
3166
3167 if (nested_svm_check_permissions(svm))
3168 return 1;
3169
3170 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3171 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3172
3173 disable_gif(svm);
3174
3175 /* After a CLGI no interrupts should come */
3176 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3177 svm_clear_vintr(svm);
3178 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3179 mark_dirty(svm->vmcb, VMCB_INTR);
3180 }
3181
3182 return ret;
3183 }
3184
3185 static int invlpga_interception(struct vcpu_svm *svm)
3186 {
3187 struct kvm_vcpu *vcpu = &svm->vcpu;
3188
3189 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3190 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3191
3192 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3193 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3194
3195 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3196 return kvm_skip_emulated_instruction(&svm->vcpu);
3197 }
3198
3199 static int skinit_interception(struct vcpu_svm *svm)
3200 {
3201 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3202
3203 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3204 return 1;
3205 }
3206
3207 static int wbinvd_interception(struct vcpu_svm *svm)
3208 {
3209 return kvm_emulate_wbinvd(&svm->vcpu);
3210 }
3211
3212 static int xsetbv_interception(struct vcpu_svm *svm)
3213 {
3214 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3215 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3216
3217 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3218 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3219 return kvm_skip_emulated_instruction(&svm->vcpu);
3220 }
3221
3222 return 1;
3223 }
3224
3225 static int task_switch_interception(struct vcpu_svm *svm)
3226 {
3227 u16 tss_selector;
3228 int reason;
3229 int int_type = svm->vmcb->control.exit_int_info &
3230 SVM_EXITINTINFO_TYPE_MASK;
3231 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3232 uint32_t type =
3233 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3234 uint32_t idt_v =
3235 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3236 bool has_error_code = false;
3237 u32 error_code = 0;
3238
3239 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3240
3241 if (svm->vmcb->control.exit_info_2 &
3242 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3243 reason = TASK_SWITCH_IRET;
3244 else if (svm->vmcb->control.exit_info_2 &
3245 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3246 reason = TASK_SWITCH_JMP;
3247 else if (idt_v)
3248 reason = TASK_SWITCH_GATE;
3249 else
3250 reason = TASK_SWITCH_CALL;
3251
3252 if (reason == TASK_SWITCH_GATE) {
3253 switch (type) {
3254 case SVM_EXITINTINFO_TYPE_NMI:
3255 svm->vcpu.arch.nmi_injected = false;
3256 break;
3257 case SVM_EXITINTINFO_TYPE_EXEPT:
3258 if (svm->vmcb->control.exit_info_2 &
3259 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3260 has_error_code = true;
3261 error_code =
3262 (u32)svm->vmcb->control.exit_info_2;
3263 }
3264 kvm_clear_exception_queue(&svm->vcpu);
3265 break;
3266 case SVM_EXITINTINFO_TYPE_INTR:
3267 kvm_clear_interrupt_queue(&svm->vcpu);
3268 break;
3269 default:
3270 break;
3271 }
3272 }
3273
3274 if (reason != TASK_SWITCH_GATE ||
3275 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3276 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3277 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3278 skip_emulated_instruction(&svm->vcpu);
3279
3280 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3281 int_vec = -1;
3282
3283 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3284 has_error_code, error_code) == EMULATE_FAIL) {
3285 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3286 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3287 svm->vcpu.run->internal.ndata = 0;
3288 return 0;
3289 }
3290 return 1;
3291 }
3292
3293 static int cpuid_interception(struct vcpu_svm *svm)
3294 {
3295 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3296 return kvm_emulate_cpuid(&svm->vcpu);
3297 }
3298
3299 static int iret_interception(struct vcpu_svm *svm)
3300 {
3301 ++svm->vcpu.stat.nmi_window_exits;
3302 clr_intercept(svm, INTERCEPT_IRET);
3303 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3304 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3305 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3306 return 1;
3307 }
3308
3309 static int invlpg_interception(struct vcpu_svm *svm)
3310 {
3311 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3312 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3313
3314 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3315 return kvm_skip_emulated_instruction(&svm->vcpu);
3316 }
3317
3318 static int emulate_on_interception(struct vcpu_svm *svm)
3319 {
3320 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3321 }
3322
3323 static int rdpmc_interception(struct vcpu_svm *svm)
3324 {
3325 int err;
3326
3327 if (!static_cpu_has(X86_FEATURE_NRIPS))
3328 return emulate_on_interception(svm);
3329
3330 err = kvm_rdpmc(&svm->vcpu);
3331 return kvm_complete_insn_gp(&svm->vcpu, err);
3332 }
3333
3334 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3335 unsigned long val)
3336 {
3337 unsigned long cr0 = svm->vcpu.arch.cr0;
3338 bool ret = false;
3339 u64 intercept;
3340
3341 intercept = svm->nested.intercept;
3342
3343 if (!is_guest_mode(&svm->vcpu) ||
3344 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3345 return false;
3346
3347 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3348 val &= ~SVM_CR0_SELECTIVE_MASK;
3349
3350 if (cr0 ^ val) {
3351 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3352 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3353 }
3354
3355 return ret;
3356 }
3357
3358 #define CR_VALID (1ULL << 63)
3359
3360 static int cr_interception(struct vcpu_svm *svm)
3361 {
3362 int reg, cr;
3363 unsigned long val;
3364 int err;
3365
3366 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3367 return emulate_on_interception(svm);
3368
3369 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3370 return emulate_on_interception(svm);
3371
3372 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3373 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3374 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3375 else
3376 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3377
3378 err = 0;
3379 if (cr >= 16) { /* mov to cr */
3380 cr -= 16;
3381 val = kvm_register_read(&svm->vcpu, reg);
3382 switch (cr) {
3383 case 0:
3384 if (!check_selective_cr0_intercepted(svm, val))
3385 err = kvm_set_cr0(&svm->vcpu, val);
3386 else
3387 return 1;
3388
3389 break;
3390 case 3:
3391 err = kvm_set_cr3(&svm->vcpu, val);
3392 break;
3393 case 4:
3394 err = kvm_set_cr4(&svm->vcpu, val);
3395 break;
3396 case 8:
3397 err = kvm_set_cr8(&svm->vcpu, val);
3398 break;
3399 default:
3400 WARN(1, "unhandled write to CR%d", cr);
3401 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3402 return 1;
3403 }
3404 } else { /* mov from cr */
3405 switch (cr) {
3406 case 0:
3407 val = kvm_read_cr0(&svm->vcpu);
3408 break;
3409 case 2:
3410 val = svm->vcpu.arch.cr2;
3411 break;
3412 case 3:
3413 val = kvm_read_cr3(&svm->vcpu);
3414 break;
3415 case 4:
3416 val = kvm_read_cr4(&svm->vcpu);
3417 break;
3418 case 8:
3419 val = kvm_get_cr8(&svm->vcpu);
3420 break;
3421 default:
3422 WARN(1, "unhandled read from CR%d", cr);
3423 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3424 return 1;
3425 }
3426 kvm_register_write(&svm->vcpu, reg, val);
3427 }
3428 return kvm_complete_insn_gp(&svm->vcpu, err);
3429 }
3430
3431 static int dr_interception(struct vcpu_svm *svm)
3432 {
3433 int reg, dr;
3434 unsigned long val;
3435
3436 if (svm->vcpu.guest_debug == 0) {
3437 /*
3438 * No more DR vmexits; force a reload of the debug registers
3439 * and reenter on this instruction. The next vmexit will
3440 * retrieve the full state of the debug registers.
3441 */
3442 clr_dr_intercepts(svm);
3443 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3444 return 1;
3445 }
3446
3447 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3448 return emulate_on_interception(svm);
3449
3450 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3451 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3452
3453 if (dr >= 16) { /* mov to DRn */
3454 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3455 return 1;
3456 val = kvm_register_read(&svm->vcpu, reg);
3457 kvm_set_dr(&svm->vcpu, dr - 16, val);
3458 } else {
3459 if (!kvm_require_dr(&svm->vcpu, dr))
3460 return 1;
3461 kvm_get_dr(&svm->vcpu, dr, &val);
3462 kvm_register_write(&svm->vcpu, reg, val);
3463 }
3464
3465 return kvm_skip_emulated_instruction(&svm->vcpu);
3466 }
3467
3468 static int cr8_write_interception(struct vcpu_svm *svm)
3469 {
3470 struct kvm_run *kvm_run = svm->vcpu.run;
3471 int r;
3472
3473 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3474 /* instruction emulation calls kvm_set_cr8() */
3475 r = cr_interception(svm);
3476 if (lapic_in_kernel(&svm->vcpu))
3477 return r;
3478 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3479 return r;
3480 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3481 return 0;
3482 }
3483
3484 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3485 {
3486 struct vcpu_svm *svm = to_svm(vcpu);
3487
3488 switch (msr_info->index) {
3489 case MSR_IA32_TSC: {
3490 msr_info->data = svm->vmcb->control.tsc_offset +
3491 kvm_scale_tsc(vcpu, rdtsc());
3492
3493 break;
3494 }
3495 case MSR_STAR:
3496 msr_info->data = svm->vmcb->save.star;
3497 break;
3498 #ifdef CONFIG_X86_64
3499 case MSR_LSTAR:
3500 msr_info->data = svm->vmcb->save.lstar;
3501 break;
3502 case MSR_CSTAR:
3503 msr_info->data = svm->vmcb->save.cstar;
3504 break;
3505 case MSR_KERNEL_GS_BASE:
3506 msr_info->data = svm->vmcb->save.kernel_gs_base;
3507 break;
3508 case MSR_SYSCALL_MASK:
3509 msr_info->data = svm->vmcb->save.sfmask;
3510 break;
3511 #endif
3512 case MSR_IA32_SYSENTER_CS:
3513 msr_info->data = svm->vmcb->save.sysenter_cs;
3514 break;
3515 case MSR_IA32_SYSENTER_EIP:
3516 msr_info->data = svm->sysenter_eip;
3517 break;
3518 case MSR_IA32_SYSENTER_ESP:
3519 msr_info->data = svm->sysenter_esp;
3520 break;
3521 case MSR_TSC_AUX:
3522 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3523 return 1;
3524 msr_info->data = svm->tsc_aux;
3525 break;
3526 /*
3527 * Nobody will change the following 5 values in the VMCB so we can
3528 * safely return them on rdmsr. They will always be 0 until LBRV is
3529 * implemented.
3530 */
3531 case MSR_IA32_DEBUGCTLMSR:
3532 msr_info->data = svm->vmcb->save.dbgctl;
3533 break;
3534 case MSR_IA32_LASTBRANCHFROMIP:
3535 msr_info->data = svm->vmcb->save.br_from;
3536 break;
3537 case MSR_IA32_LASTBRANCHTOIP:
3538 msr_info->data = svm->vmcb->save.br_to;
3539 break;
3540 case MSR_IA32_LASTINTFROMIP:
3541 msr_info->data = svm->vmcb->save.last_excp_from;
3542 break;
3543 case MSR_IA32_LASTINTTOIP:
3544 msr_info->data = svm->vmcb->save.last_excp_to;
3545 break;
3546 case MSR_VM_HSAVE_PA:
3547 msr_info->data = svm->nested.hsave_msr;
3548 break;
3549 case MSR_VM_CR:
3550 msr_info->data = svm->nested.vm_cr_msr;
3551 break;
3552 case MSR_IA32_SPEC_CTRL:
3553 msr_info->data = svm->spec_ctrl;
3554 break;
3555 case MSR_IA32_UCODE_REV:
3556 msr_info->data = 0x01000065;
3557 break;
3558 case MSR_F15H_IC_CFG: {
3559
3560 int family, model;
3561
3562 family = guest_cpuid_family(vcpu);
3563 model = guest_cpuid_model(vcpu);
3564
3565 if (family < 0 || model < 0)
3566 return kvm_get_msr_common(vcpu, msr_info);
3567
3568 msr_info->data = 0;
3569
3570 if (family == 0x15 &&
3571 (model >= 0x2 && model < 0x20))
3572 msr_info->data = 0x1E;
3573 }
3574 break;
3575 default:
3576 return kvm_get_msr_common(vcpu, msr_info);
3577 }
3578 return 0;
3579 }
3580
3581 static int rdmsr_interception(struct vcpu_svm *svm)
3582 {
3583 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3584 struct msr_data msr_info;
3585
3586 msr_info.index = ecx;
3587 msr_info.host_initiated = false;
3588 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3589 trace_kvm_msr_read_ex(ecx);
3590 kvm_inject_gp(&svm->vcpu, 0);
3591 return 1;
3592 } else {
3593 trace_kvm_msr_read(ecx, msr_info.data);
3594
3595 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3596 msr_info.data & 0xffffffff);
3597 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3598 msr_info.data >> 32);
3599 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3600 return kvm_skip_emulated_instruction(&svm->vcpu);
3601 }
3602 }
3603
3604 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3605 {
3606 struct vcpu_svm *svm = to_svm(vcpu);
3607 int svm_dis, chg_mask;
3608
3609 if (data & ~SVM_VM_CR_VALID_MASK)
3610 return 1;
3611
3612 chg_mask = SVM_VM_CR_VALID_MASK;
3613
3614 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3615 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3616
3617 svm->nested.vm_cr_msr &= ~chg_mask;
3618 svm->nested.vm_cr_msr |= (data & chg_mask);
3619
3620 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3621
3622 /* check for svm_disable while efer.svme is set */
3623 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3624 return 1;
3625
3626 return 0;
3627 }
3628
3629 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3630 {
3631 struct vcpu_svm *svm = to_svm(vcpu);
3632
3633 u32 ecx = msr->index;
3634 u64 data = msr->data;
3635 switch (ecx) {
3636 case MSR_IA32_TSC:
3637 kvm_write_tsc(vcpu, msr);
3638 break;
3639 case MSR_STAR:
3640 svm->vmcb->save.star = data;
3641 break;
3642 #ifdef CONFIG_X86_64
3643 case MSR_LSTAR:
3644 svm->vmcb->save.lstar = data;
3645 break;
3646 case MSR_CSTAR:
3647 svm->vmcb->save.cstar = data;
3648 break;
3649 case MSR_KERNEL_GS_BASE:
3650 svm->vmcb->save.kernel_gs_base = data;
3651 break;
3652 case MSR_SYSCALL_MASK:
3653 svm->vmcb->save.sfmask = data;
3654 break;
3655 #endif
3656 case MSR_IA32_SYSENTER_CS:
3657 svm->vmcb->save.sysenter_cs = data;
3658 break;
3659 case MSR_IA32_SYSENTER_EIP:
3660 svm->sysenter_eip = data;
3661 svm->vmcb->save.sysenter_eip = data;
3662 break;
3663 case MSR_IA32_SYSENTER_ESP:
3664 svm->sysenter_esp = data;
3665 svm->vmcb->save.sysenter_esp = data;
3666 break;
3667 case MSR_TSC_AUX:
3668 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3669 return 1;
3670
3671 /*
3672 * This is rare, so we update the MSR here instead of using
3673 * direct_access_msrs. Doing that would require a rdmsr in
3674 * svm_vcpu_put.
3675 */
3676 svm->tsc_aux = data;
3677 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3678 break;
3679 case MSR_IA32_DEBUGCTLMSR:
3680 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3681 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3682 __func__, data);
3683 break;
3684 }
3685 if (data & DEBUGCTL_RESERVED_BITS)
3686 return 1;
3687
3688 svm->vmcb->save.dbgctl = data;
3689 mark_dirty(svm->vmcb, VMCB_LBR);
3690 if (data & (1ULL<<0))
3691 svm_enable_lbrv(svm);
3692 else
3693 svm_disable_lbrv(svm);
3694 break;
3695 case MSR_VM_HSAVE_PA:
3696 svm->nested.hsave_msr = data;
3697 break;
3698 case MSR_VM_CR:
3699 return svm_set_vm_cr(vcpu, data);
3700 case MSR_VM_IGNNE:
3701 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3702 break;
3703 case MSR_IA32_SPEC_CTRL:
3704 svm->spec_ctrl = data;
3705 break;
3706 case MSR_IA32_APICBASE:
3707 if (kvm_vcpu_apicv_active(vcpu))
3708 avic_update_vapic_bar(to_svm(vcpu), data);
3709 /* Follow through */
3710 default:
3711 return kvm_set_msr_common(vcpu, msr);
3712 }
3713 return 0;
3714 }
3715
3716 static int wrmsr_interception(struct vcpu_svm *svm)
3717 {
3718 struct msr_data msr;
3719 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3720 u64 data = kvm_read_edx_eax(&svm->vcpu);
3721
3722 msr.data = data;
3723 msr.index = ecx;
3724 msr.host_initiated = false;
3725
3726 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3727 if (kvm_set_msr(&svm->vcpu, &msr)) {
3728 trace_kvm_msr_write_ex(ecx, data);
3729 kvm_inject_gp(&svm->vcpu, 0);
3730 return 1;
3731 } else {
3732 trace_kvm_msr_write(ecx, data);
3733 return kvm_skip_emulated_instruction(&svm->vcpu);
3734 }
3735 }
3736
3737 static int msr_interception(struct vcpu_svm *svm)
3738 {
3739 if (svm->vmcb->control.exit_info_1)
3740 return wrmsr_interception(svm);
3741 else
3742 return rdmsr_interception(svm);
3743 }
3744
3745 static int interrupt_window_interception(struct vcpu_svm *svm)
3746 {
3747 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3748 svm_clear_vintr(svm);
3749 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3750 mark_dirty(svm->vmcb, VMCB_INTR);
3751 ++svm->vcpu.stat.irq_window_exits;
3752 return 1;
3753 }
3754
3755 static int pause_interception(struct vcpu_svm *svm)
3756 {
3757 kvm_vcpu_on_spin(&(svm->vcpu));
3758 return 1;
3759 }
3760
3761 static int nop_interception(struct vcpu_svm *svm)
3762 {
3763 return kvm_skip_emulated_instruction(&(svm->vcpu));
3764 }
3765
3766 static int monitor_interception(struct vcpu_svm *svm)
3767 {
3768 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3769 return nop_interception(svm);
3770 }
3771
3772 static int mwait_interception(struct vcpu_svm *svm)
3773 {
3774 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3775 return nop_interception(svm);
3776 }
3777
3778 enum avic_ipi_failure_cause {
3779 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3780 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3781 AVIC_IPI_FAILURE_INVALID_TARGET,
3782 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3783 };
3784
3785 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3786 {
3787 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3788 u32 icrl = svm->vmcb->control.exit_info_1;
3789 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3790 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3791 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3792
3793 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3794
3795 switch (id) {
3796 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3797 /*
3798 * AVIC hardware handles the generation of
3799 * IPIs when the specified Message Type is Fixed
3800 * (also known as fixed delivery mode) and
3801 * the Trigger Mode is edge-triggered. The hardware
3802 * also supports self and broadcast delivery modes
3803 * specified via the Destination Shorthand(DSH)
3804 * field of the ICRL. Logical and physical APIC ID
3805 * formats are supported. All other IPI types cause
3806 * a #VMEXIT, which needs to emulated.
3807 */
3808 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3809 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3810 break;
3811 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3812 int i;
3813 struct kvm_vcpu *vcpu;
3814 struct kvm *kvm = svm->vcpu.kvm;
3815 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3816
3817 /*
3818 * At this point, we expect that the AVIC HW has already
3819 * set the appropriate IRR bits on the valid target
3820 * vcpus. So, we just need to kick the appropriate vcpu.
3821 */
3822 kvm_for_each_vcpu(i, vcpu, kvm) {
3823 bool m = kvm_apic_match_dest(vcpu, apic,
3824 icrl & KVM_APIC_SHORT_MASK,
3825 GET_APIC_DEST_FIELD(icrh),
3826 icrl & KVM_APIC_DEST_MASK);
3827
3828 if (m && !avic_vcpu_is_running(vcpu))
3829 kvm_vcpu_wake_up(vcpu);
3830 }
3831 break;
3832 }
3833 case AVIC_IPI_FAILURE_INVALID_TARGET:
3834 break;
3835 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3836 WARN_ONCE(1, "Invalid backing page\n");
3837 break;
3838 default:
3839 pr_err("Unknown IPI interception\n");
3840 }
3841
3842 return 1;
3843 }
3844
3845 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3846 {
3847 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3848 int index;
3849 u32 *logical_apic_id_table;
3850 int dlid = GET_APIC_LOGICAL_ID(ldr);
3851
3852 if (!dlid)
3853 return NULL;
3854
3855 if (flat) { /* flat */
3856 index = ffs(dlid) - 1;
3857 if (index > 7)
3858 return NULL;
3859 } else { /* cluster */
3860 int cluster = (dlid & 0xf0) >> 4;
3861 int apic = ffs(dlid & 0x0f) - 1;
3862
3863 if ((apic < 0) || (apic > 7) ||
3864 (cluster >= 0xf))
3865 return NULL;
3866 index = (cluster << 2) + apic;
3867 }
3868
3869 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3870
3871 return &logical_apic_id_table[index];
3872 }
3873
3874 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3875 bool valid)
3876 {
3877 bool flat;
3878 u32 *entry, new_entry;
3879
3880 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3881 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3882 if (!entry)
3883 return -EINVAL;
3884
3885 new_entry = READ_ONCE(*entry);
3886 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3887 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3888 if (valid)
3889 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3890 else
3891 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3892 WRITE_ONCE(*entry, new_entry);
3893
3894 return 0;
3895 }
3896
3897 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3898 {
3899 int ret;
3900 struct vcpu_svm *svm = to_svm(vcpu);
3901 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3902
3903 if (!ldr)
3904 return 1;
3905
3906 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3907 if (ret && svm->ldr_reg) {
3908 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3909 svm->ldr_reg = 0;
3910 } else {
3911 svm->ldr_reg = ldr;
3912 }
3913 return ret;
3914 }
3915
3916 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3917 {
3918 u64 *old, *new;
3919 struct vcpu_svm *svm = to_svm(vcpu);
3920 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3921 u32 id = (apic_id_reg >> 24) & 0xff;
3922
3923 if (vcpu->vcpu_id == id)
3924 return 0;
3925
3926 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3927 new = avic_get_physical_id_entry(vcpu, id);
3928 if (!new || !old)
3929 return 1;
3930
3931 /* We need to move physical_id_entry to new offset */
3932 *new = *old;
3933 *old = 0ULL;
3934 to_svm(vcpu)->avic_physical_id_cache = new;
3935
3936 /*
3937 * Also update the guest physical APIC ID in the logical
3938 * APIC ID table entry if already setup the LDR.
3939 */
3940 if (svm->ldr_reg)
3941 avic_handle_ldr_update(vcpu);
3942
3943 return 0;
3944 }
3945
3946 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3947 {
3948 struct vcpu_svm *svm = to_svm(vcpu);
3949 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3950 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3951 u32 mod = (dfr >> 28) & 0xf;
3952
3953 /*
3954 * We assume that all local APICs are using the same type.
3955 * If this changes, we need to flush the AVIC logical
3956 * APID id table.
3957 */
3958 if (vm_data->ldr_mode == mod)
3959 return 0;
3960
3961 clear_page(page_address(vm_data->avic_logical_id_table_page));
3962 vm_data->ldr_mode = mod;
3963
3964 if (svm->ldr_reg)
3965 avic_handle_ldr_update(vcpu);
3966 return 0;
3967 }
3968
3969 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3970 {
3971 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3972 u32 offset = svm->vmcb->control.exit_info_1 &
3973 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3974
3975 switch (offset) {
3976 case APIC_ID:
3977 if (avic_handle_apic_id_update(&svm->vcpu))
3978 return 0;
3979 break;
3980 case APIC_LDR:
3981 if (avic_handle_ldr_update(&svm->vcpu))
3982 return 0;
3983 break;
3984 case APIC_DFR:
3985 avic_handle_dfr_update(&svm->vcpu);
3986 break;
3987 default:
3988 break;
3989 }
3990
3991 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3992
3993 return 1;
3994 }
3995
3996 static bool is_avic_unaccelerated_access_trap(u32 offset)
3997 {
3998 bool ret = false;
3999
4000 switch (offset) {
4001 case APIC_ID:
4002 case APIC_EOI:
4003 case APIC_RRR:
4004 case APIC_LDR:
4005 case APIC_DFR:
4006 case APIC_SPIV:
4007 case APIC_ESR:
4008 case APIC_ICR:
4009 case APIC_LVTT:
4010 case APIC_LVTTHMR:
4011 case APIC_LVTPC:
4012 case APIC_LVT0:
4013 case APIC_LVT1:
4014 case APIC_LVTERR:
4015 case APIC_TMICT:
4016 case APIC_TDCR:
4017 ret = true;
4018 break;
4019 default:
4020 break;
4021 }
4022 return ret;
4023 }
4024
4025 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4026 {
4027 int ret = 0;
4028 u32 offset = svm->vmcb->control.exit_info_1 &
4029 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4030 u32 vector = svm->vmcb->control.exit_info_2 &
4031 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4032 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4033 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4034 bool trap = is_avic_unaccelerated_access_trap(offset);
4035
4036 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4037 trap, write, vector);
4038 if (trap) {
4039 /* Handling Trap */
4040 WARN_ONCE(!write, "svm: Handling trap read.\n");
4041 ret = avic_unaccel_trap_write(svm);
4042 } else {
4043 /* Handling Fault */
4044 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4045 }
4046
4047 return ret;
4048 }
4049
4050 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4051 [SVM_EXIT_READ_CR0] = cr_interception,
4052 [SVM_EXIT_READ_CR3] = cr_interception,
4053 [SVM_EXIT_READ_CR4] = cr_interception,
4054 [SVM_EXIT_READ_CR8] = cr_interception,
4055 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4056 [SVM_EXIT_WRITE_CR0] = cr_interception,
4057 [SVM_EXIT_WRITE_CR3] = cr_interception,
4058 [SVM_EXIT_WRITE_CR4] = cr_interception,
4059 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4060 [SVM_EXIT_READ_DR0] = dr_interception,
4061 [SVM_EXIT_READ_DR1] = dr_interception,
4062 [SVM_EXIT_READ_DR2] = dr_interception,
4063 [SVM_EXIT_READ_DR3] = dr_interception,
4064 [SVM_EXIT_READ_DR4] = dr_interception,
4065 [SVM_EXIT_READ_DR5] = dr_interception,
4066 [SVM_EXIT_READ_DR6] = dr_interception,
4067 [SVM_EXIT_READ_DR7] = dr_interception,
4068 [SVM_EXIT_WRITE_DR0] = dr_interception,
4069 [SVM_EXIT_WRITE_DR1] = dr_interception,
4070 [SVM_EXIT_WRITE_DR2] = dr_interception,
4071 [SVM_EXIT_WRITE_DR3] = dr_interception,
4072 [SVM_EXIT_WRITE_DR4] = dr_interception,
4073 [SVM_EXIT_WRITE_DR5] = dr_interception,
4074 [SVM_EXIT_WRITE_DR6] = dr_interception,
4075 [SVM_EXIT_WRITE_DR7] = dr_interception,
4076 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4077 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4078 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4079 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4080 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4081 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4082 [SVM_EXIT_INTR] = intr_interception,
4083 [SVM_EXIT_NMI] = nmi_interception,
4084 [SVM_EXIT_SMI] = nop_on_interception,
4085 [SVM_EXIT_INIT] = nop_on_interception,
4086 [SVM_EXIT_VINTR] = interrupt_window_interception,
4087 [SVM_EXIT_RDPMC] = rdpmc_interception,
4088 [SVM_EXIT_CPUID] = cpuid_interception,
4089 [SVM_EXIT_IRET] = iret_interception,
4090 [SVM_EXIT_INVD] = emulate_on_interception,
4091 [SVM_EXIT_PAUSE] = pause_interception,
4092 [SVM_EXIT_HLT] = halt_interception,
4093 [SVM_EXIT_INVLPG] = invlpg_interception,
4094 [SVM_EXIT_INVLPGA] = invlpga_interception,
4095 [SVM_EXIT_IOIO] = io_interception,
4096 [SVM_EXIT_MSR] = msr_interception,
4097 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4098 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4099 [SVM_EXIT_VMRUN] = vmrun_interception,
4100 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4101 [SVM_EXIT_VMLOAD] = vmload_interception,
4102 [SVM_EXIT_VMSAVE] = vmsave_interception,
4103 [SVM_EXIT_STGI] = stgi_interception,
4104 [SVM_EXIT_CLGI] = clgi_interception,
4105 [SVM_EXIT_SKINIT] = skinit_interception,
4106 [SVM_EXIT_WBINVD] = wbinvd_interception,
4107 [SVM_EXIT_MONITOR] = monitor_interception,
4108 [SVM_EXIT_MWAIT] = mwait_interception,
4109 [SVM_EXIT_XSETBV] = xsetbv_interception,
4110 [SVM_EXIT_NPF] = pf_interception,
4111 [SVM_EXIT_RSM] = emulate_on_interception,
4112 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4113 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4114 };
4115
4116 static void dump_vmcb(struct kvm_vcpu *vcpu)
4117 {
4118 struct vcpu_svm *svm = to_svm(vcpu);
4119 struct vmcb_control_area *control = &svm->vmcb->control;
4120 struct vmcb_save_area *save = &svm->vmcb->save;
4121
4122 pr_err("VMCB Control Area:\n");
4123 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4124 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4125 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4126 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4127 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4128 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4129 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4130 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4131 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4132 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4133 pr_err("%-20s%d\n", "asid:", control->asid);
4134 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4135 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4136 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4137 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4138 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4139 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4140 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4141 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4142 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4143 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4144 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4145 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4146 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4147 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4148 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4149 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4150 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4151 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4152 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4153 pr_err("VMCB State Save Area:\n");
4154 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4155 "es:",
4156 save->es.selector, save->es.attrib,
4157 save->es.limit, save->es.base);
4158 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4159 "cs:",
4160 save->cs.selector, save->cs.attrib,
4161 save->cs.limit, save->cs.base);
4162 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4163 "ss:",
4164 save->ss.selector, save->ss.attrib,
4165 save->ss.limit, save->ss.base);
4166 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4167 "ds:",
4168 save->ds.selector, save->ds.attrib,
4169 save->ds.limit, save->ds.base);
4170 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4171 "fs:",
4172 save->fs.selector, save->fs.attrib,
4173 save->fs.limit, save->fs.base);
4174 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4175 "gs:",
4176 save->gs.selector, save->gs.attrib,
4177 save->gs.limit, save->gs.base);
4178 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4179 "gdtr:",
4180 save->gdtr.selector, save->gdtr.attrib,
4181 save->gdtr.limit, save->gdtr.base);
4182 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4183 "ldtr:",
4184 save->ldtr.selector, save->ldtr.attrib,
4185 save->ldtr.limit, save->ldtr.base);
4186 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4187 "idtr:",
4188 save->idtr.selector, save->idtr.attrib,
4189 save->idtr.limit, save->idtr.base);
4190 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4191 "tr:",
4192 save->tr.selector, save->tr.attrib,
4193 save->tr.limit, save->tr.base);
4194 pr_err("cpl: %d efer: %016llx\n",
4195 save->cpl, save->efer);
4196 pr_err("%-15s %016llx %-13s %016llx\n",
4197 "cr0:", save->cr0, "cr2:", save->cr2);
4198 pr_err("%-15s %016llx %-13s %016llx\n",
4199 "cr3:", save->cr3, "cr4:", save->cr4);
4200 pr_err("%-15s %016llx %-13s %016llx\n",
4201 "dr6:", save->dr6, "dr7:", save->dr7);
4202 pr_err("%-15s %016llx %-13s %016llx\n",
4203 "rip:", save->rip, "rflags:", save->rflags);
4204 pr_err("%-15s %016llx %-13s %016llx\n",
4205 "rsp:", save->rsp, "rax:", save->rax);
4206 pr_err("%-15s %016llx %-13s %016llx\n",
4207 "star:", save->star, "lstar:", save->lstar);
4208 pr_err("%-15s %016llx %-13s %016llx\n",
4209 "cstar:", save->cstar, "sfmask:", save->sfmask);
4210 pr_err("%-15s %016llx %-13s %016llx\n",
4211 "kernel_gs_base:", save->kernel_gs_base,
4212 "sysenter_cs:", save->sysenter_cs);
4213 pr_err("%-15s %016llx %-13s %016llx\n",
4214 "sysenter_esp:", save->sysenter_esp,
4215 "sysenter_eip:", save->sysenter_eip);
4216 pr_err("%-15s %016llx %-13s %016llx\n",
4217 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4218 pr_err("%-15s %016llx %-13s %016llx\n",
4219 "br_from:", save->br_from, "br_to:", save->br_to);
4220 pr_err("%-15s %016llx %-13s %016llx\n",
4221 "excp_from:", save->last_excp_from,
4222 "excp_to:", save->last_excp_to);
4223 }
4224
4225 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4226 {
4227 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4228
4229 *info1 = control->exit_info_1;
4230 *info2 = control->exit_info_2;
4231 }
4232
4233 static int handle_exit(struct kvm_vcpu *vcpu)
4234 {
4235 struct vcpu_svm *svm = to_svm(vcpu);
4236 struct kvm_run *kvm_run = vcpu->run;
4237 u32 exit_code = svm->vmcb->control.exit_code;
4238
4239 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4240
4241 vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4242
4243 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4244 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4245 if (npt_enabled)
4246 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4247
4248 if (unlikely(svm->nested.exit_required)) {
4249 nested_svm_vmexit(svm);
4250 svm->nested.exit_required = false;
4251
4252 return 1;
4253 }
4254
4255 if (is_guest_mode(vcpu)) {
4256 int vmexit;
4257
4258 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4259 svm->vmcb->control.exit_info_1,
4260 svm->vmcb->control.exit_info_2,
4261 svm->vmcb->control.exit_int_info,
4262 svm->vmcb->control.exit_int_info_err,
4263 KVM_ISA_SVM);
4264
4265 vmexit = nested_svm_exit_special(svm);
4266
4267 if (vmexit == NESTED_EXIT_CONTINUE)
4268 vmexit = nested_svm_exit_handled(svm);
4269
4270 if (vmexit == NESTED_EXIT_DONE)
4271 return 1;
4272 }
4273
4274 svm_complete_interrupts(svm);
4275
4276 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4277 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4278 kvm_run->fail_entry.hardware_entry_failure_reason
4279 = svm->vmcb->control.exit_code;
4280 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4281 dump_vmcb(vcpu);
4282 return 0;
4283 }
4284
4285 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4286 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4287 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4288 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4289 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4290 "exit_code 0x%x\n",
4291 __func__, svm->vmcb->control.exit_int_info,
4292 exit_code);
4293
4294 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4295 || !svm_exit_handlers[exit_code]) {
4296 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4297 kvm_queue_exception(vcpu, UD_VECTOR);
4298 return 1;
4299 }
4300
4301 return svm_exit_handlers[exit_code](svm);
4302 }
4303
4304 static void reload_tss(struct kvm_vcpu *vcpu)
4305 {
4306 int cpu = raw_smp_processor_id();
4307
4308 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4309 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4310 load_TR_desc();
4311 }
4312
4313 static void pre_svm_run(struct vcpu_svm *svm)
4314 {
4315 int cpu = raw_smp_processor_id();
4316
4317 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4318
4319 /* FIXME: handle wraparound of asid_generation */
4320 if (svm->asid_generation != sd->asid_generation)
4321 new_asid(svm, sd);
4322 }
4323
4324 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4325 {
4326 struct vcpu_svm *svm = to_svm(vcpu);
4327
4328 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4329 vcpu->arch.hflags |= HF_NMI_MASK;
4330 set_intercept(svm, INTERCEPT_IRET);
4331 ++vcpu->stat.nmi_injections;
4332 }
4333
4334 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4335 {
4336 struct vmcb_control_area *control;
4337
4338 /* The following fields are ignored when AVIC is enabled */
4339 control = &svm->vmcb->control;
4340 control->int_vector = irq;
4341 control->int_ctl &= ~V_INTR_PRIO_MASK;
4342 control->int_ctl |= V_IRQ_MASK |
4343 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4344 mark_dirty(svm->vmcb, VMCB_INTR);
4345 }
4346
4347 static void svm_set_irq(struct kvm_vcpu *vcpu)
4348 {
4349 struct vcpu_svm *svm = to_svm(vcpu);
4350
4351 BUG_ON(!(gif_set(svm)));
4352
4353 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4354 ++vcpu->stat.irq_injections;
4355
4356 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4357 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4358 }
4359
4360 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4361 {
4362 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4363 }
4364
4365 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4366 {
4367 struct vcpu_svm *svm = to_svm(vcpu);
4368
4369 if (svm_nested_virtualize_tpr(vcpu) ||
4370 kvm_vcpu_apicv_active(vcpu))
4371 return;
4372
4373 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4374
4375 if (irr == -1)
4376 return;
4377
4378 if (tpr >= irr)
4379 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4380 }
4381
4382 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4383 {
4384 return;
4385 }
4386
4387 static bool svm_get_enable_apicv(void)
4388 {
4389 return avic;
4390 }
4391
4392 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4393 {
4394 }
4395
4396 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4397 {
4398 }
4399
4400 /* Note: Currently only used by Hyper-V. */
4401 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4402 {
4403 struct vcpu_svm *svm = to_svm(vcpu);
4404 struct vmcb *vmcb = svm->vmcb;
4405
4406 if (!avic)
4407 return;
4408
4409 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4410 mark_dirty(vmcb, VMCB_INTR);
4411 }
4412
4413 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4414 {
4415 return;
4416 }
4417
4418 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4419 {
4420 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4421 smp_mb__after_atomic();
4422
4423 if (avic_vcpu_is_running(vcpu))
4424 wrmsrl(SVM_AVIC_DOORBELL,
4425 kvm_cpu_get_apicid(vcpu->cpu));
4426 else
4427 kvm_vcpu_wake_up(vcpu);
4428 }
4429
4430 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4431 {
4432 unsigned long flags;
4433 struct amd_svm_iommu_ir *cur;
4434
4435 spin_lock_irqsave(&svm->ir_list_lock, flags);
4436 list_for_each_entry(cur, &svm->ir_list, node) {
4437 if (cur->data != pi->ir_data)
4438 continue;
4439 list_del(&cur->node);
4440 kfree(cur);
4441 break;
4442 }
4443 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4444 }
4445
4446 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4447 {
4448 int ret = 0;
4449 unsigned long flags;
4450 struct amd_svm_iommu_ir *ir;
4451
4452 /**
4453 * In some cases, the existing irte is updaed and re-set,
4454 * so we need to check here if it's already been * added
4455 * to the ir_list.
4456 */
4457 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4458 struct kvm *kvm = svm->vcpu.kvm;
4459 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4460 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4461 struct vcpu_svm *prev_svm;
4462
4463 if (!prev_vcpu) {
4464 ret = -EINVAL;
4465 goto out;
4466 }
4467
4468 prev_svm = to_svm(prev_vcpu);
4469 svm_ir_list_del(prev_svm, pi);
4470 }
4471
4472 /**
4473 * Allocating new amd_iommu_pi_data, which will get
4474 * add to the per-vcpu ir_list.
4475 */
4476 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4477 if (!ir) {
4478 ret = -ENOMEM;
4479 goto out;
4480 }
4481 ir->data = pi->ir_data;
4482
4483 spin_lock_irqsave(&svm->ir_list_lock, flags);
4484 list_add(&ir->node, &svm->ir_list);
4485 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4486 out:
4487 return ret;
4488 }
4489
4490 /**
4491 * Note:
4492 * The HW cannot support posting multicast/broadcast
4493 * interrupts to a vCPU. So, we still use legacy interrupt
4494 * remapping for these kind of interrupts.
4495 *
4496 * For lowest-priority interrupts, we only support
4497 * those with single CPU as the destination, e.g. user
4498 * configures the interrupts via /proc/irq or uses
4499 * irqbalance to make the interrupts single-CPU.
4500 */
4501 static int
4502 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4503 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4504 {
4505 struct kvm_lapic_irq irq;
4506 struct kvm_vcpu *vcpu = NULL;
4507
4508 kvm_set_msi_irq(kvm, e, &irq);
4509
4510 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4511 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4512 __func__, irq.vector);
4513 return -1;
4514 }
4515
4516 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4517 irq.vector);
4518 *svm = to_svm(vcpu);
4519 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4520 vcpu_info->vector = irq.vector;
4521
4522 return 0;
4523 }
4524
4525 /*
4526 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4527 *
4528 * @kvm: kvm
4529 * @host_irq: host irq of the interrupt
4530 * @guest_irq: gsi of the interrupt
4531 * @set: set or unset PI
4532 * returns 0 on success, < 0 on failure
4533 */
4534 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4535 uint32_t guest_irq, bool set)
4536 {
4537 struct kvm_kernel_irq_routing_entry *e;
4538 struct kvm_irq_routing_table *irq_rt;
4539 int idx, ret = -EINVAL;
4540
4541 if (!kvm_arch_has_assigned_device(kvm) ||
4542 !irq_remapping_cap(IRQ_POSTING_CAP))
4543 return 0;
4544
4545 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4546 __func__, host_irq, guest_irq, set);
4547
4548 idx = srcu_read_lock(&kvm->irq_srcu);
4549 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4550 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4551
4552 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4553 struct vcpu_data vcpu_info;
4554 struct vcpu_svm *svm = NULL;
4555
4556 if (e->type != KVM_IRQ_ROUTING_MSI)
4557 continue;
4558
4559 /**
4560 * Here, we setup with legacy mode in the following cases:
4561 * 1. When cannot target interrupt to a specific vcpu.
4562 * 2. Unsetting posted interrupt.
4563 * 3. APIC virtialization is disabled for the vcpu.
4564 */
4565 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4566 kvm_vcpu_apicv_active(&svm->vcpu)) {
4567 struct amd_iommu_pi_data pi;
4568
4569 /* Try to enable guest_mode in IRTE */
4570 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4571 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4572 svm->vcpu.vcpu_id);
4573 pi.is_guest_mode = true;
4574 pi.vcpu_data = &vcpu_info;
4575 ret = irq_set_vcpu_affinity(host_irq, &pi);
4576
4577 /**
4578 * Here, we successfully setting up vcpu affinity in
4579 * IOMMU guest mode. Now, we need to store the posted
4580 * interrupt information in a per-vcpu ir_list so that
4581 * we can reference to them directly when we update vcpu
4582 * scheduling information in IOMMU irte.
4583 */
4584 if (!ret && pi.is_guest_mode)
4585 svm_ir_list_add(svm, &pi);
4586 } else {
4587 /* Use legacy mode in IRTE */
4588 struct amd_iommu_pi_data pi;
4589
4590 /**
4591 * Here, pi is used to:
4592 * - Tell IOMMU to use legacy mode for this interrupt.
4593 * - Retrieve ga_tag of prior interrupt remapping data.
4594 */
4595 pi.is_guest_mode = false;
4596 ret = irq_set_vcpu_affinity(host_irq, &pi);
4597
4598 /**
4599 * Check if the posted interrupt was previously
4600 * setup with the guest_mode by checking if the ga_tag
4601 * was cached. If so, we need to clean up the per-vcpu
4602 * ir_list.
4603 */
4604 if (!ret && pi.prev_ga_tag) {
4605 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4606 struct kvm_vcpu *vcpu;
4607
4608 vcpu = kvm_get_vcpu_by_id(kvm, id);
4609 if (vcpu)
4610 svm_ir_list_del(to_svm(vcpu), &pi);
4611 }
4612 }
4613
4614 if (!ret && svm) {
4615 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4616 host_irq, e->gsi,
4617 vcpu_info.vector,
4618 vcpu_info.pi_desc_addr, set);
4619 }
4620
4621 if (ret < 0) {
4622 pr_err("%s: failed to update PI IRTE\n", __func__);
4623 goto out;
4624 }
4625 }
4626
4627 ret = 0;
4628 out:
4629 srcu_read_unlock(&kvm->irq_srcu, idx);
4630 return ret;
4631 }
4632
4633 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4634 {
4635 struct vcpu_svm *svm = to_svm(vcpu);
4636 struct vmcb *vmcb = svm->vmcb;
4637 int ret;
4638 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4639 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4640 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4641
4642 return ret;
4643 }
4644
4645 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4646 {
4647 struct vcpu_svm *svm = to_svm(vcpu);
4648
4649 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4650 }
4651
4652 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4653 {
4654 struct vcpu_svm *svm = to_svm(vcpu);
4655
4656 if (masked) {
4657 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4658 set_intercept(svm, INTERCEPT_IRET);
4659 } else {
4660 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4661 clr_intercept(svm, INTERCEPT_IRET);
4662 }
4663 }
4664
4665 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4666 {
4667 struct vcpu_svm *svm = to_svm(vcpu);
4668 struct vmcb *vmcb = svm->vmcb;
4669 int ret;
4670
4671 if (!gif_set(svm) ||
4672 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4673 return 0;
4674
4675 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4676
4677 if (is_guest_mode(vcpu))
4678 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4679
4680 return ret;
4681 }
4682
4683 static void enable_irq_window(struct kvm_vcpu *vcpu)
4684 {
4685 struct vcpu_svm *svm = to_svm(vcpu);
4686
4687 if (kvm_vcpu_apicv_active(vcpu))
4688 return;
4689
4690 /*
4691 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4692 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4693 * get that intercept, this function will be called again though and
4694 * we'll get the vintr intercept.
4695 */
4696 if (gif_set(svm) && nested_svm_intr(svm)) {
4697 svm_set_vintr(svm);
4698 svm_inject_irq(svm, 0x0);
4699 }
4700 }
4701
4702 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4703 {
4704 struct vcpu_svm *svm = to_svm(vcpu);
4705
4706 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4707 == HF_NMI_MASK)
4708 return; /* IRET will cause a vm exit */
4709
4710 if ((svm->vcpu.arch.hflags & HF_GIF_MASK) == 0)
4711 return; /* STGI will cause a vm exit */
4712
4713 if (svm->nested.exit_required)
4714 return; /* we're not going to run the guest yet */
4715
4716 /*
4717 * Something prevents NMI from been injected. Single step over possible
4718 * problem (IRET or exception injection or interrupt shadow)
4719 */
4720 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4721 svm->nmi_singlestep = true;
4722 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4723 }
4724
4725 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4726 {
4727 return 0;
4728 }
4729
4730 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4731 {
4732 struct vcpu_svm *svm = to_svm(vcpu);
4733
4734 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4735 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4736 else
4737 svm->asid_generation--;
4738 }
4739
4740 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4741 {
4742 }
4743
4744 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4745 {
4746 struct vcpu_svm *svm = to_svm(vcpu);
4747
4748 if (svm_nested_virtualize_tpr(vcpu))
4749 return;
4750
4751 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4752 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4753 kvm_set_cr8(vcpu, cr8);
4754 }
4755 }
4756
4757 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4758 {
4759 struct vcpu_svm *svm = to_svm(vcpu);
4760 u64 cr8;
4761
4762 if (svm_nested_virtualize_tpr(vcpu) ||
4763 kvm_vcpu_apicv_active(vcpu))
4764 return;
4765
4766 cr8 = kvm_get_cr8(vcpu);
4767 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4768 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4769 }
4770
4771 static void svm_complete_interrupts(struct vcpu_svm *svm)
4772 {
4773 u8 vector;
4774 int type;
4775 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4776 unsigned int3_injected = svm->int3_injected;
4777
4778 svm->int3_injected = 0;
4779
4780 /*
4781 * If we've made progress since setting HF_IRET_MASK, we've
4782 * executed an IRET and can allow NMI injection.
4783 */
4784 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4785 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4786 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4787 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4788 }
4789
4790 svm->vcpu.arch.nmi_injected = false;
4791 kvm_clear_exception_queue(&svm->vcpu);
4792 kvm_clear_interrupt_queue(&svm->vcpu);
4793
4794 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4795 return;
4796
4797 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4798
4799 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4800 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4801
4802 switch (type) {
4803 case SVM_EXITINTINFO_TYPE_NMI:
4804 svm->vcpu.arch.nmi_injected = true;
4805 break;
4806 case SVM_EXITINTINFO_TYPE_EXEPT:
4807 /*
4808 * In case of software exceptions, do not reinject the vector,
4809 * but re-execute the instruction instead. Rewind RIP first
4810 * if we emulated INT3 before.
4811 */
4812 if (kvm_exception_is_soft(vector)) {
4813 if (vector == BP_VECTOR && int3_injected &&
4814 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4815 kvm_rip_write(&svm->vcpu,
4816 kvm_rip_read(&svm->vcpu) -
4817 int3_injected);
4818 break;
4819 }
4820 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4821 u32 err = svm->vmcb->control.exit_int_info_err;
4822 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4823
4824 } else
4825 kvm_requeue_exception(&svm->vcpu, vector);
4826 break;
4827 case SVM_EXITINTINFO_TYPE_INTR:
4828 kvm_queue_interrupt(&svm->vcpu, vector, false);
4829 break;
4830 default:
4831 break;
4832 }
4833 }
4834
4835 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4836 {
4837 struct vcpu_svm *svm = to_svm(vcpu);
4838 struct vmcb_control_area *control = &svm->vmcb->control;
4839
4840 control->exit_int_info = control->event_inj;
4841 control->exit_int_info_err = control->event_inj_err;
4842 control->event_inj = 0;
4843 svm_complete_interrupts(svm);
4844 }
4845
4846 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4847 {
4848 struct vcpu_svm *svm = to_svm(vcpu);
4849
4850 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4851 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4852 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4853
4854 /*
4855 * A vmexit emulation is required before the vcpu can be executed
4856 * again.
4857 */
4858 if (unlikely(svm->nested.exit_required))
4859 return;
4860
4861 /*
4862 * Disable singlestep if we're injecting an interrupt/exception.
4863 * We don't want our modified rflags to be pushed on the stack where
4864 * we might not be able to easily reset them if we disabled NMI
4865 * singlestep later.
4866 */
4867 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4868 /*
4869 * Event injection happens before external interrupts cause a
4870 * vmexit and interrupts are disabled here, so smp_send_reschedule
4871 * is enough to force an immediate vmexit.
4872 */
4873 disable_nmi_singlestep(svm);
4874 smp_send_reschedule(vcpu->cpu);
4875 }
4876
4877 pre_svm_run(svm);
4878
4879 sync_lapic_to_cr8(vcpu);
4880
4881 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4882
4883 clgi();
4884
4885 local_irq_enable();
4886
4887 if (ibrs_inuse && (svm->spec_ctrl != FEATURE_ENABLE_IBRS))
4888 wrmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
4889
4890 asm volatile (
4891 "push %%" _ASM_BP "; \n\t"
4892 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4893 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4894 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4895 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4896 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4897 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4898 #ifdef CONFIG_X86_64
4899 "mov %c[r8](%[svm]), %%r8 \n\t"
4900 "mov %c[r9](%[svm]), %%r9 \n\t"
4901 "mov %c[r10](%[svm]), %%r10 \n\t"
4902 "mov %c[r11](%[svm]), %%r11 \n\t"
4903 "mov %c[r12](%[svm]), %%r12 \n\t"
4904 "mov %c[r13](%[svm]), %%r13 \n\t"
4905 "mov %c[r14](%[svm]), %%r14 \n\t"
4906 "mov %c[r15](%[svm]), %%r15 \n\t"
4907 #endif
4908
4909 /* Enter guest mode */
4910 "push %%" _ASM_AX " \n\t"
4911 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4912 __ex(SVM_VMLOAD) "\n\t"
4913 __ex(SVM_VMRUN) "\n\t"
4914 __ex(SVM_VMSAVE) "\n\t"
4915 "pop %%" _ASM_AX " \n\t"
4916
4917 /* Save guest registers, load host registers */
4918 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4919 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4920 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4921 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4922 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4923 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4924 #ifdef CONFIG_X86_64
4925 "mov %%r8, %c[r8](%[svm]) \n\t"
4926 "mov %%r9, %c[r9](%[svm]) \n\t"
4927 "mov %%r10, %c[r10](%[svm]) \n\t"
4928 "mov %%r11, %c[r11](%[svm]) \n\t"
4929 "mov %%r12, %c[r12](%[svm]) \n\t"
4930 "mov %%r13, %c[r13](%[svm]) \n\t"
4931 "mov %%r14, %c[r14](%[svm]) \n\t"
4932 "mov %%r15, %c[r15](%[svm]) \n\t"
4933 #endif
4934 "pop %%" _ASM_BP
4935 :
4936 : [svm]"a"(svm),
4937 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4938 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4939 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4940 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4941 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4942 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4943 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4944 #ifdef CONFIG_X86_64
4945 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4946 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4947 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4948 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4949 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4950 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4951 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4952 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4953 #endif
4954 : "cc", "memory"
4955 #ifdef CONFIG_X86_64
4956 , "rbx", "rcx", "rdx", "rsi", "rdi"
4957 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4958 #else
4959 , "ebx", "ecx", "edx", "esi", "edi"
4960 #endif
4961 );
4962
4963 if (ibrs_inuse) {
4964 rdmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
4965 if (svm->spec_ctrl != FEATURE_ENABLE_IBRS)
4966 wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
4967 }
4968
4969 #ifdef CONFIG_X86_64
4970 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4971 #else
4972 loadsegment(fs, svm->host.fs);
4973 #ifndef CONFIG_X86_32_LAZY_GS
4974 loadsegment(gs, svm->host.gs);
4975 #endif
4976 #endif
4977
4978 reload_tss(vcpu);
4979
4980 local_irq_disable();
4981
4982 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4983 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4984 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4985 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4986
4987 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4988 kvm_before_handle_nmi(&svm->vcpu);
4989
4990 stgi();
4991
4992 /* Any pending NMI will happen here */
4993
4994 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4995 kvm_after_handle_nmi(&svm->vcpu);
4996
4997 sync_cr8_to_lapic(vcpu);
4998
4999 svm->next_rip = 0;
5000
5001 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5002
5003 /* if exit due to PF check for async PF */
5004 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5005 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5006
5007 if (npt_enabled) {
5008 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5009 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5010 }
5011
5012 /*
5013 * We need to handle MC intercepts here before the vcpu has a chance to
5014 * change the physical cpu
5015 */
5016 if (unlikely(svm->vmcb->control.exit_code ==
5017 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5018 svm_handle_mce(svm);
5019
5020 mark_all_clean(svm->vmcb);
5021 }
5022 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5023
5024 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5025 {
5026 struct vcpu_svm *svm = to_svm(vcpu);
5027
5028 svm->vmcb->save.cr3 = root;
5029 mark_dirty(svm->vmcb, VMCB_CR);
5030 svm_flush_tlb(vcpu);
5031 }
5032
5033 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5034 {
5035 struct vcpu_svm *svm = to_svm(vcpu);
5036
5037 svm->vmcb->control.nested_cr3 = root;
5038 mark_dirty(svm->vmcb, VMCB_NPT);
5039
5040 /* Also sync guest cr3 here in case we live migrate */
5041 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5042 mark_dirty(svm->vmcb, VMCB_CR);
5043
5044 svm_flush_tlb(vcpu);
5045 }
5046
5047 static int is_disabled(void)
5048 {
5049 u64 vm_cr;
5050
5051 rdmsrl(MSR_VM_CR, vm_cr);
5052 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5053 return 1;
5054
5055 return 0;
5056 }
5057
5058 static void
5059 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5060 {
5061 /*
5062 * Patch in the VMMCALL instruction:
5063 */
5064 hypercall[0] = 0x0f;
5065 hypercall[1] = 0x01;
5066 hypercall[2] = 0xd9;
5067 }
5068
5069 static void svm_check_processor_compat(void *rtn)
5070 {
5071 *(int *)rtn = 0;
5072 }
5073
5074 static bool svm_cpu_has_accelerated_tpr(void)
5075 {
5076 return false;
5077 }
5078
5079 static bool svm_has_high_real_mode_segbase(void)
5080 {
5081 return true;
5082 }
5083
5084 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5085 {
5086 return 0;
5087 }
5088
5089 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5090 {
5091 struct vcpu_svm *svm = to_svm(vcpu);
5092 struct kvm_cpuid_entry2 *entry;
5093
5094 /* Update nrips enabled cache */
5095 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5096
5097 if (!kvm_vcpu_apicv_active(vcpu))
5098 return;
5099
5100 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5101 if (entry)
5102 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5103 }
5104
5105 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5106 {
5107 switch (func) {
5108 case 0x1:
5109 if (avic)
5110 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5111 break;
5112 case 0x80000001:
5113 if (nested)
5114 entry->ecx |= (1 << 2); /* Set SVM bit */
5115 break;
5116 case 0x8000000A:
5117 entry->eax = 1; /* SVM revision 1 */
5118 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5119 ASID emulation to nested SVM */
5120 entry->ecx = 0; /* Reserved */
5121 entry->edx = 0; /* Per default do not support any
5122 additional features */
5123
5124 /* Support next_rip if host supports it */
5125 if (boot_cpu_has(X86_FEATURE_NRIPS))
5126 entry->edx |= SVM_FEATURE_NRIP;
5127
5128 /* Support NPT for the guest if enabled */
5129 if (npt_enabled)
5130 entry->edx |= SVM_FEATURE_NPT;
5131
5132 break;
5133 }
5134 }
5135
5136 static int svm_get_lpage_level(void)
5137 {
5138 return PT_PDPE_LEVEL;
5139 }
5140
5141 static bool svm_rdtscp_supported(void)
5142 {
5143 return boot_cpu_has(X86_FEATURE_RDTSCP);
5144 }
5145
5146 static bool svm_invpcid_supported(void)
5147 {
5148 return false;
5149 }
5150
5151 static bool svm_mpx_supported(void)
5152 {
5153 return false;
5154 }
5155
5156 static bool svm_xsaves_supported(void)
5157 {
5158 return false;
5159 }
5160
5161 static bool svm_has_wbinvd_exit(void)
5162 {
5163 return true;
5164 }
5165
5166 #define PRE_EX(exit) { .exit_code = (exit), \
5167 .stage = X86_ICPT_PRE_EXCEPT, }
5168 #define POST_EX(exit) { .exit_code = (exit), \
5169 .stage = X86_ICPT_POST_EXCEPT, }
5170 #define POST_MEM(exit) { .exit_code = (exit), \
5171 .stage = X86_ICPT_POST_MEMACCESS, }
5172
5173 static const struct __x86_intercept {
5174 u32 exit_code;
5175 enum x86_intercept_stage stage;
5176 } x86_intercept_map[] = {
5177 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5178 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5179 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5180 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5181 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5182 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5183 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5184 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5185 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5186 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5187 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5188 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5189 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5190 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5191 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5192 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5193 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5194 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5195 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5196 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5197 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5198 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5199 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5200 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5201 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5202 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5203 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5204 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5205 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5206 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5207 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5208 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5209 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5210 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5211 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5212 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5213 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5214 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5215 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5216 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5217 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5218 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5219 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5220 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5221 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5222 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5223 };
5224
5225 #undef PRE_EX
5226 #undef POST_EX
5227 #undef POST_MEM
5228
5229 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5230 struct x86_instruction_info *info,
5231 enum x86_intercept_stage stage)
5232 {
5233 struct vcpu_svm *svm = to_svm(vcpu);
5234 int vmexit, ret = X86EMUL_CONTINUE;
5235 struct __x86_intercept icpt_info;
5236 struct vmcb *vmcb = svm->vmcb;
5237
5238 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5239 goto out;
5240
5241 icpt_info = x86_intercept_map[info->intercept];
5242
5243 if (stage != icpt_info.stage)
5244 goto out;
5245
5246 switch (icpt_info.exit_code) {
5247 case SVM_EXIT_READ_CR0:
5248 if (info->intercept == x86_intercept_cr_read)
5249 icpt_info.exit_code += info->modrm_reg;
5250 break;
5251 case SVM_EXIT_WRITE_CR0: {
5252 unsigned long cr0, val;
5253 u64 intercept;
5254
5255 if (info->intercept == x86_intercept_cr_write)
5256 icpt_info.exit_code += info->modrm_reg;
5257
5258 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5259 info->intercept == x86_intercept_clts)
5260 break;
5261
5262 intercept = svm->nested.intercept;
5263
5264 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5265 break;
5266
5267 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5268 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5269
5270 if (info->intercept == x86_intercept_lmsw) {
5271 cr0 &= 0xfUL;
5272 val &= 0xfUL;
5273 /* lmsw can't clear PE - catch this here */
5274 if (cr0 & X86_CR0_PE)
5275 val |= X86_CR0_PE;
5276 }
5277
5278 if (cr0 ^ val)
5279 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5280
5281 break;
5282 }
5283 case SVM_EXIT_READ_DR0:
5284 case SVM_EXIT_WRITE_DR0:
5285 icpt_info.exit_code += info->modrm_reg;
5286 break;
5287 case SVM_EXIT_MSR:
5288 if (info->intercept == x86_intercept_wrmsr)
5289 vmcb->control.exit_info_1 = 1;
5290 else
5291 vmcb->control.exit_info_1 = 0;
5292 break;
5293 case SVM_EXIT_PAUSE:
5294 /*
5295 * We get this for NOP only, but pause
5296 * is rep not, check this here
5297 */
5298 if (info->rep_prefix != REPE_PREFIX)
5299 goto out;
5300 case SVM_EXIT_IOIO: {
5301 u64 exit_info;
5302 u32 bytes;
5303
5304 if (info->intercept == x86_intercept_in ||
5305 info->intercept == x86_intercept_ins) {
5306 exit_info = ((info->src_val & 0xffff) << 16) |
5307 SVM_IOIO_TYPE_MASK;
5308 bytes = info->dst_bytes;
5309 } else {
5310 exit_info = (info->dst_val & 0xffff) << 16;
5311 bytes = info->src_bytes;
5312 }
5313
5314 if (info->intercept == x86_intercept_outs ||
5315 info->intercept == x86_intercept_ins)
5316 exit_info |= SVM_IOIO_STR_MASK;
5317
5318 if (info->rep_prefix)
5319 exit_info |= SVM_IOIO_REP_MASK;
5320
5321 bytes = min(bytes, 4u);
5322
5323 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5324
5325 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5326
5327 vmcb->control.exit_info_1 = exit_info;
5328 vmcb->control.exit_info_2 = info->next_rip;
5329
5330 break;
5331 }
5332 default:
5333 break;
5334 }
5335
5336 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5337 if (static_cpu_has(X86_FEATURE_NRIPS))
5338 vmcb->control.next_rip = info->next_rip;
5339 vmcb->control.exit_code = icpt_info.exit_code;
5340 vmexit = nested_svm_exit_handled(svm);
5341
5342 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5343 : X86EMUL_CONTINUE;
5344
5345 out:
5346 return ret;
5347 }
5348
5349 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5350 {
5351 local_irq_enable();
5352 /*
5353 * We must have an instruction with interrupts enabled, so
5354 * the timer interrupt isn't delayed by the interrupt shadow.
5355 */
5356 asm("nop");
5357 local_irq_disable();
5358 }
5359
5360 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5361 {
5362 }
5363
5364 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5365 {
5366 if (avic_handle_apic_id_update(vcpu) != 0)
5367 return;
5368 if (avic_handle_dfr_update(vcpu) != 0)
5369 return;
5370 avic_handle_ldr_update(vcpu);
5371 }
5372
5373 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5374 {
5375 /* [63:9] are reserved. */
5376 vcpu->arch.mcg_cap &= 0x1ff;
5377 }
5378
5379 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5380 .cpu_has_kvm_support = has_svm,
5381 .disabled_by_bios = is_disabled,
5382 .hardware_setup = svm_hardware_setup,
5383 .hardware_unsetup = svm_hardware_unsetup,
5384 .check_processor_compatibility = svm_check_processor_compat,
5385 .hardware_enable = svm_hardware_enable,
5386 .hardware_disable = svm_hardware_disable,
5387 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5388 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5389
5390 .vcpu_create = svm_create_vcpu,
5391 .vcpu_free = svm_free_vcpu,
5392 .vcpu_reset = svm_vcpu_reset,
5393
5394 .vm_init = avic_vm_init,
5395 .vm_destroy = avic_vm_destroy,
5396
5397 .prepare_guest_switch = svm_prepare_guest_switch,
5398 .vcpu_load = svm_vcpu_load,
5399 .vcpu_put = svm_vcpu_put,
5400 .vcpu_blocking = svm_vcpu_blocking,
5401 .vcpu_unblocking = svm_vcpu_unblocking,
5402
5403 .update_bp_intercept = update_bp_intercept,
5404 .get_msr = svm_get_msr,
5405 .set_msr = svm_set_msr,
5406 .get_segment_base = svm_get_segment_base,
5407 .get_segment = svm_get_segment,
5408 .set_segment = svm_set_segment,
5409 .get_cpl = svm_get_cpl,
5410 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5411 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5412 .decache_cr3 = svm_decache_cr3,
5413 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5414 .set_cr0 = svm_set_cr0,
5415 .set_cr3 = svm_set_cr3,
5416 .set_cr4 = svm_set_cr4,
5417 .set_efer = svm_set_efer,
5418 .get_idt = svm_get_idt,
5419 .set_idt = svm_set_idt,
5420 .get_gdt = svm_get_gdt,
5421 .set_gdt = svm_set_gdt,
5422 .get_dr6 = svm_get_dr6,
5423 .set_dr6 = svm_set_dr6,
5424 .set_dr7 = svm_set_dr7,
5425 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5426 .cache_reg = svm_cache_reg,
5427 .get_rflags = svm_get_rflags,
5428 .set_rflags = svm_set_rflags,
5429
5430 .tlb_flush = svm_flush_tlb,
5431
5432 .run = svm_vcpu_run,
5433 .handle_exit = handle_exit,
5434 .skip_emulated_instruction = skip_emulated_instruction,
5435 .set_interrupt_shadow = svm_set_interrupt_shadow,
5436 .get_interrupt_shadow = svm_get_interrupt_shadow,
5437 .patch_hypercall = svm_patch_hypercall,
5438 .set_irq = svm_set_irq,
5439 .set_nmi = svm_inject_nmi,
5440 .queue_exception = svm_queue_exception,
5441 .cancel_injection = svm_cancel_injection,
5442 .interrupt_allowed = svm_interrupt_allowed,
5443 .nmi_allowed = svm_nmi_allowed,
5444 .get_nmi_mask = svm_get_nmi_mask,
5445 .set_nmi_mask = svm_set_nmi_mask,
5446 .enable_nmi_window = enable_nmi_window,
5447 .enable_irq_window = enable_irq_window,
5448 .update_cr8_intercept = update_cr8_intercept,
5449 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5450 .get_enable_apicv = svm_get_enable_apicv,
5451 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5452 .load_eoi_exitmap = svm_load_eoi_exitmap,
5453 .hwapic_irr_update = svm_hwapic_irr_update,
5454 .hwapic_isr_update = svm_hwapic_isr_update,
5455 .apicv_post_state_restore = avic_post_state_restore,
5456
5457 .set_tss_addr = svm_set_tss_addr,
5458 .get_tdp_level = get_npt_level,
5459 .get_mt_mask = svm_get_mt_mask,
5460
5461 .get_exit_info = svm_get_exit_info,
5462
5463 .get_lpage_level = svm_get_lpage_level,
5464
5465 .cpuid_update = svm_cpuid_update,
5466
5467 .rdtscp_supported = svm_rdtscp_supported,
5468 .invpcid_supported = svm_invpcid_supported,
5469 .mpx_supported = svm_mpx_supported,
5470 .xsaves_supported = svm_xsaves_supported,
5471
5472 .set_supported_cpuid = svm_set_supported_cpuid,
5473
5474 .has_wbinvd_exit = svm_has_wbinvd_exit,
5475
5476 .write_tsc_offset = svm_write_tsc_offset,
5477
5478 .set_tdp_cr3 = set_tdp_cr3,
5479
5480 .check_intercept = svm_check_intercept,
5481 .handle_external_intr = svm_handle_external_intr,
5482
5483 .sched_in = svm_sched_in,
5484
5485 .pmu_ops = &amd_pmu_ops,
5486 .deliver_posted_interrupt = svm_deliver_avic_intr,
5487 .update_pi_irte = svm_update_pi_irte,
5488 .setup_mce = svm_setup_mce,
5489 };
5490
5491 static int __init svm_init(void)
5492 {
5493 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5494 __alignof__(struct vcpu_svm), THIS_MODULE);
5495 }
5496
5497 static void __exit svm_exit(void)
5498 {
5499 kvm_exit();
5500 }
5501
5502 module_init(svm_init)
5503 module_exit(svm_exit)
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