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x86/retpoline: Fill return stack buffer on vmexit
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/nospec-branch.h>
49
50 #include <asm/virtext.h>
51 #include "trace.h"
52
53 #define __ex(x) __kvm_handle_fault_on_reboot(x)
54
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
57
58 static const struct x86_cpu_id svm_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_SVM),
60 {}
61 };
62 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
63
64 #define IOPM_ALLOC_ORDER 2
65 #define MSRPM_ALLOC_ORDER 1
66
67 #define SEG_TYPE_LDT 2
68 #define SEG_TYPE_BUSY_TSS16 3
69
70 #define SVM_FEATURE_NPT (1 << 0)
71 #define SVM_FEATURE_LBRV (1 << 1)
72 #define SVM_FEATURE_SVML (1 << 2)
73 #define SVM_FEATURE_NRIP (1 << 3)
74 #define SVM_FEATURE_TSC_RATE (1 << 4)
75 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
76 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
77 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
78 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
79
80 #define SVM_AVIC_DOORBELL 0xc001011b
81
82 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
83 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
84 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
85
86 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
87
88 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
89 #define TSC_RATIO_MIN 0x0000000000000001ULL
90 #define TSC_RATIO_MAX 0x000000ffffffffffULL
91
92 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
93
94 /*
95 * 0xff is broadcast, so the max index allowed for physical APIC ID
96 * table is 0xfe. APIC IDs above 0xff are reserved.
97 */
98 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
99
100 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
101 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
102 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
103
104 /* AVIC GATAG is encoded using VM and VCPU IDs */
105 #define AVIC_VCPU_ID_BITS 8
106 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
107
108 #define AVIC_VM_ID_BITS 24
109 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
110 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
111
112 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
113 (y & AVIC_VCPU_ID_MASK))
114 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
115 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
116
117 static bool erratum_383_found __read_mostly;
118
119 static const u32 host_save_user_msrs[] = {
120 #ifdef CONFIG_X86_64
121 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
122 MSR_FS_BASE,
123 #endif
124 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
125 MSR_TSC_AUX,
126 };
127
128 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
129
130 struct kvm_vcpu;
131
132 struct nested_state {
133 struct vmcb *hsave;
134 u64 hsave_msr;
135 u64 vm_cr_msr;
136 u64 vmcb;
137
138 /* These are the merged vectors */
139 u32 *msrpm;
140
141 /* gpa pointers to the real vectors */
142 u64 vmcb_msrpm;
143 u64 vmcb_iopm;
144
145 /* A VMEXIT is required but not yet emulated */
146 bool exit_required;
147
148 /* cache for intercepts of the guest */
149 u32 intercept_cr;
150 u32 intercept_dr;
151 u32 intercept_exceptions;
152 u64 intercept;
153
154 /* Nested Paging related state */
155 u64 nested_cr3;
156 };
157
158 #define MSRPM_OFFSETS 16
159 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
160
161 /*
162 * Set osvw_len to higher value when updated Revision Guides
163 * are published and we know what the new status bits are
164 */
165 static uint64_t osvw_len = 4, osvw_status;
166
167 struct vcpu_svm {
168 struct kvm_vcpu vcpu;
169 struct vmcb *vmcb;
170 unsigned long vmcb_pa;
171 struct svm_cpu_data *svm_data;
172 uint64_t asid_generation;
173 uint64_t sysenter_esp;
174 uint64_t sysenter_eip;
175 uint64_t tsc_aux;
176
177 u64 next_rip;
178
179 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
180 struct {
181 u16 fs;
182 u16 gs;
183 u16 ldt;
184 u64 gs_base;
185 } host;
186
187 u32 *msrpm;
188
189 ulong nmi_iret_rip;
190
191 struct nested_state nested;
192
193 bool nmi_singlestep;
194 u64 nmi_singlestep_guest_rflags;
195
196 unsigned int3_injected;
197 unsigned long int3_rip;
198
199 /* cached guest cpuid flags for faster access */
200 bool nrips_enabled : 1;
201
202 u32 ldr_reg;
203 struct page *avic_backing_page;
204 u64 *avic_physical_id_cache;
205 bool avic_is_running;
206
207 /*
208 * Per-vcpu list of struct amd_svm_iommu_ir:
209 * This is used mainly to store interrupt remapping information used
210 * when update the vcpu affinity. This avoids the need to scan for
211 * IRTE and try to match ga_tag in the IOMMU driver.
212 */
213 struct list_head ir_list;
214 spinlock_t ir_list_lock;
215 };
216
217 /*
218 * This is a wrapper of struct amd_iommu_ir_data.
219 */
220 struct amd_svm_iommu_ir {
221 struct list_head node; /* Used by SVM for per-vcpu ir_list */
222 void *data; /* Storing pointer to struct amd_ir_data */
223 };
224
225 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
226 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
227
228 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
229 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
230 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
231 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
232
233 static DEFINE_PER_CPU(u64, current_tsc_ratio);
234 #define TSC_RATIO_DEFAULT 0x0100000000ULL
235
236 #define MSR_INVALID 0xffffffffU
237
238 static const struct svm_direct_access_msrs {
239 u32 index; /* Index of the MSR */
240 bool always; /* True if intercept is always on */
241 } direct_access_msrs[] = {
242 { .index = MSR_STAR, .always = true },
243 { .index = MSR_IA32_SYSENTER_CS, .always = true },
244 #ifdef CONFIG_X86_64
245 { .index = MSR_GS_BASE, .always = true },
246 { .index = MSR_FS_BASE, .always = true },
247 { .index = MSR_KERNEL_GS_BASE, .always = true },
248 { .index = MSR_LSTAR, .always = true },
249 { .index = MSR_CSTAR, .always = true },
250 { .index = MSR_SYSCALL_MASK, .always = true },
251 #endif
252 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
253 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
254 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
255 { .index = MSR_IA32_LASTINTTOIP, .always = false },
256 { .index = MSR_INVALID, .always = false },
257 };
258
259 /* enable NPT for AMD64 and X86 with PAE */
260 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
261 static bool npt_enabled = true;
262 #else
263 static bool npt_enabled;
264 #endif
265
266 /* allow nested paging (virtualized MMU) for all guests */
267 static int npt = true;
268 module_param(npt, int, S_IRUGO);
269
270 /* allow nested virtualization in KVM/SVM */
271 static int nested = true;
272 module_param(nested, int, S_IRUGO);
273
274 /* enable / disable AVIC */
275 static int avic;
276 #ifdef CONFIG_X86_LOCAL_APIC
277 module_param(avic, int, S_IRUGO);
278 #endif
279
280 /* enable/disable Virtual VMLOAD VMSAVE */
281 static int vls = true;
282 module_param(vls, int, 0444);
283
284 /* AVIC VM ID bit masks and lock */
285 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
286 static DEFINE_SPINLOCK(avic_vm_id_lock);
287
288 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
289 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
290 static void svm_complete_interrupts(struct vcpu_svm *svm);
291
292 static int nested_svm_exit_handled(struct vcpu_svm *svm);
293 static int nested_svm_intercept(struct vcpu_svm *svm);
294 static int nested_svm_vmexit(struct vcpu_svm *svm);
295 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
296 bool has_error_code, u32 error_code);
297
298 enum {
299 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
300 pause filter count */
301 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
302 VMCB_ASID, /* ASID */
303 VMCB_INTR, /* int_ctl, int_vector */
304 VMCB_NPT, /* npt_en, nCR3, gPAT */
305 VMCB_CR, /* CR0, CR3, CR4, EFER */
306 VMCB_DR, /* DR6, DR7 */
307 VMCB_DT, /* GDT, IDT */
308 VMCB_SEG, /* CS, DS, SS, ES, CPL */
309 VMCB_CR2, /* CR2 only */
310 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
311 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
312 * AVIC PHYSICAL_TABLE pointer,
313 * AVIC LOGICAL_TABLE pointer
314 */
315 VMCB_DIRTY_MAX,
316 };
317
318 /* TPR and CR2 are always written before VMRUN */
319 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
320
321 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
322
323 static inline void mark_all_dirty(struct vmcb *vmcb)
324 {
325 vmcb->control.clean = 0;
326 }
327
328 static inline void mark_all_clean(struct vmcb *vmcb)
329 {
330 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
331 & ~VMCB_ALWAYS_DIRTY_MASK;
332 }
333
334 static inline void mark_dirty(struct vmcb *vmcb, int bit)
335 {
336 vmcb->control.clean &= ~(1 << bit);
337 }
338
339 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
340 {
341 return container_of(vcpu, struct vcpu_svm, vcpu);
342 }
343
344 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
345 {
346 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
347 mark_dirty(svm->vmcb, VMCB_AVIC);
348 }
349
350 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
351 {
352 struct vcpu_svm *svm = to_svm(vcpu);
353 u64 *entry = svm->avic_physical_id_cache;
354
355 if (!entry)
356 return false;
357
358 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
359 }
360
361 static void recalc_intercepts(struct vcpu_svm *svm)
362 {
363 struct vmcb_control_area *c, *h;
364 struct nested_state *g;
365
366 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
367
368 if (!is_guest_mode(&svm->vcpu))
369 return;
370
371 c = &svm->vmcb->control;
372 h = &svm->nested.hsave->control;
373 g = &svm->nested;
374
375 c->intercept_cr = h->intercept_cr | g->intercept_cr;
376 c->intercept_dr = h->intercept_dr | g->intercept_dr;
377 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
378 c->intercept = h->intercept | g->intercept;
379 }
380
381 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
382 {
383 if (is_guest_mode(&svm->vcpu))
384 return svm->nested.hsave;
385 else
386 return svm->vmcb;
387 }
388
389 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
390 {
391 struct vmcb *vmcb = get_host_vmcb(svm);
392
393 vmcb->control.intercept_cr |= (1U << bit);
394
395 recalc_intercepts(svm);
396 }
397
398 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
399 {
400 struct vmcb *vmcb = get_host_vmcb(svm);
401
402 vmcb->control.intercept_cr &= ~(1U << bit);
403
404 recalc_intercepts(svm);
405 }
406
407 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
408 {
409 struct vmcb *vmcb = get_host_vmcb(svm);
410
411 return vmcb->control.intercept_cr & (1U << bit);
412 }
413
414 static inline void set_dr_intercepts(struct vcpu_svm *svm)
415 {
416 struct vmcb *vmcb = get_host_vmcb(svm);
417
418 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
419 | (1 << INTERCEPT_DR1_READ)
420 | (1 << INTERCEPT_DR2_READ)
421 | (1 << INTERCEPT_DR3_READ)
422 | (1 << INTERCEPT_DR4_READ)
423 | (1 << INTERCEPT_DR5_READ)
424 | (1 << INTERCEPT_DR6_READ)
425 | (1 << INTERCEPT_DR7_READ)
426 | (1 << INTERCEPT_DR0_WRITE)
427 | (1 << INTERCEPT_DR1_WRITE)
428 | (1 << INTERCEPT_DR2_WRITE)
429 | (1 << INTERCEPT_DR3_WRITE)
430 | (1 << INTERCEPT_DR4_WRITE)
431 | (1 << INTERCEPT_DR5_WRITE)
432 | (1 << INTERCEPT_DR6_WRITE)
433 | (1 << INTERCEPT_DR7_WRITE);
434
435 recalc_intercepts(svm);
436 }
437
438 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
439 {
440 struct vmcb *vmcb = get_host_vmcb(svm);
441
442 vmcb->control.intercept_dr = 0;
443
444 recalc_intercepts(svm);
445 }
446
447 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
448 {
449 struct vmcb *vmcb = get_host_vmcb(svm);
450
451 vmcb->control.intercept_exceptions |= (1U << bit);
452
453 recalc_intercepts(svm);
454 }
455
456 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
457 {
458 struct vmcb *vmcb = get_host_vmcb(svm);
459
460 vmcb->control.intercept_exceptions &= ~(1U << bit);
461
462 recalc_intercepts(svm);
463 }
464
465 static inline void set_intercept(struct vcpu_svm *svm, int bit)
466 {
467 struct vmcb *vmcb = get_host_vmcb(svm);
468
469 vmcb->control.intercept |= (1ULL << bit);
470
471 recalc_intercepts(svm);
472 }
473
474 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
475 {
476 struct vmcb *vmcb = get_host_vmcb(svm);
477
478 vmcb->control.intercept &= ~(1ULL << bit);
479
480 recalc_intercepts(svm);
481 }
482
483 static inline void enable_gif(struct vcpu_svm *svm)
484 {
485 svm->vcpu.arch.hflags |= HF_GIF_MASK;
486 }
487
488 static inline void disable_gif(struct vcpu_svm *svm)
489 {
490 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
491 }
492
493 static inline bool gif_set(struct vcpu_svm *svm)
494 {
495 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
496 }
497
498 static unsigned long iopm_base;
499
500 struct kvm_ldttss_desc {
501 u16 limit0;
502 u16 base0;
503 unsigned base1:8, type:5, dpl:2, p:1;
504 unsigned limit1:4, zero0:3, g:1, base2:8;
505 u32 base3;
506 u32 zero1;
507 } __attribute__((packed));
508
509 struct svm_cpu_data {
510 int cpu;
511
512 u64 asid_generation;
513 u32 max_asid;
514 u32 next_asid;
515 struct kvm_ldttss_desc *tss_desc;
516
517 struct page *save_area;
518 };
519
520 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
521
522 struct svm_init_data {
523 int cpu;
524 int r;
525 };
526
527 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
528
529 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
530 #define MSRS_RANGE_SIZE 2048
531 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
532
533 static u32 svm_msrpm_offset(u32 msr)
534 {
535 u32 offset;
536 int i;
537
538 for (i = 0; i < NUM_MSR_MAPS; i++) {
539 if (msr < msrpm_ranges[i] ||
540 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
541 continue;
542
543 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
544 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
545
546 /* Now we have the u8 offset - but need the u32 offset */
547 return offset / 4;
548 }
549
550 /* MSR not in any range */
551 return MSR_INVALID;
552 }
553
554 #define MAX_INST_SIZE 15
555
556 static inline void clgi(void)
557 {
558 asm volatile (__ex(SVM_CLGI));
559 }
560
561 static inline void stgi(void)
562 {
563 asm volatile (__ex(SVM_STGI));
564 }
565
566 static inline void invlpga(unsigned long addr, u32 asid)
567 {
568 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
569 }
570
571 static int get_npt_level(void)
572 {
573 #ifdef CONFIG_X86_64
574 return PT64_ROOT_LEVEL;
575 #else
576 return PT32E_ROOT_LEVEL;
577 #endif
578 }
579
580 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
581 {
582 vcpu->arch.efer = efer;
583 if (!npt_enabled && !(efer & EFER_LMA))
584 efer &= ~EFER_LME;
585
586 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
587 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
588 }
589
590 static int is_external_interrupt(u32 info)
591 {
592 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
593 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
594 }
595
596 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
597 {
598 struct vcpu_svm *svm = to_svm(vcpu);
599 u32 ret = 0;
600
601 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
602 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
603 return ret;
604 }
605
606 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
607 {
608 struct vcpu_svm *svm = to_svm(vcpu);
609
610 if (mask == 0)
611 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
612 else
613 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
614
615 }
616
617 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
618 {
619 struct vcpu_svm *svm = to_svm(vcpu);
620
621 if (svm->vmcb->control.next_rip != 0) {
622 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
623 svm->next_rip = svm->vmcb->control.next_rip;
624 }
625
626 if (!svm->next_rip) {
627 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
628 EMULATE_DONE)
629 printk(KERN_DEBUG "%s: NOP\n", __func__);
630 return;
631 }
632 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
633 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
634 __func__, kvm_rip_read(vcpu), svm->next_rip);
635
636 kvm_rip_write(vcpu, svm->next_rip);
637 svm_set_interrupt_shadow(vcpu, 0);
638 }
639
640 static void svm_queue_exception(struct kvm_vcpu *vcpu)
641 {
642 struct vcpu_svm *svm = to_svm(vcpu);
643 unsigned nr = vcpu->arch.exception.nr;
644 bool has_error_code = vcpu->arch.exception.has_error_code;
645 bool reinject = vcpu->arch.exception.reinject;
646 u32 error_code = vcpu->arch.exception.error_code;
647
648 /*
649 * If we are within a nested VM we'd better #VMEXIT and let the guest
650 * handle the exception
651 */
652 if (!reinject &&
653 nested_svm_check_exception(svm, nr, has_error_code, error_code))
654 return;
655
656 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
657 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
658
659 /*
660 * For guest debugging where we have to reinject #BP if some
661 * INT3 is guest-owned:
662 * Emulate nRIP by moving RIP forward. Will fail if injection
663 * raises a fault that is not intercepted. Still better than
664 * failing in all cases.
665 */
666 skip_emulated_instruction(&svm->vcpu);
667 rip = kvm_rip_read(&svm->vcpu);
668 svm->int3_rip = rip + svm->vmcb->save.cs.base;
669 svm->int3_injected = rip - old_rip;
670 }
671
672 svm->vmcb->control.event_inj = nr
673 | SVM_EVTINJ_VALID
674 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
675 | SVM_EVTINJ_TYPE_EXEPT;
676 svm->vmcb->control.event_inj_err = error_code;
677 }
678
679 static void svm_init_erratum_383(void)
680 {
681 u32 low, high;
682 int err;
683 u64 val;
684
685 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
686 return;
687
688 /* Use _safe variants to not break nested virtualization */
689 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
690 if (err)
691 return;
692
693 val |= (1ULL << 47);
694
695 low = lower_32_bits(val);
696 high = upper_32_bits(val);
697
698 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
699
700 erratum_383_found = true;
701 }
702
703 static void svm_init_osvw(struct kvm_vcpu *vcpu)
704 {
705 /*
706 * Guests should see errata 400 and 415 as fixed (assuming that
707 * HLT and IO instructions are intercepted).
708 */
709 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
710 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
711
712 /*
713 * By increasing VCPU's osvw.length to 3 we are telling the guest that
714 * all osvw.status bits inside that length, including bit 0 (which is
715 * reserved for erratum 298), are valid. However, if host processor's
716 * osvw_len is 0 then osvw_status[0] carries no information. We need to
717 * be conservative here and therefore we tell the guest that erratum 298
718 * is present (because we really don't know).
719 */
720 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
721 vcpu->arch.osvw.status |= 1;
722 }
723
724 static int has_svm(void)
725 {
726 const char *msg;
727
728 if (!cpu_has_svm(&msg)) {
729 printk(KERN_INFO "has_svm: %s\n", msg);
730 return 0;
731 }
732
733 return 1;
734 }
735
736 static void svm_hardware_disable(void)
737 {
738 /* Make sure we clean up behind us */
739 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
740 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
741
742 cpu_svm_disable();
743
744 amd_pmu_disable_virt();
745 }
746
747 static int svm_hardware_enable(void)
748 {
749
750 struct svm_cpu_data *sd;
751 uint64_t efer;
752 struct desc_struct *gdt;
753 int me = raw_smp_processor_id();
754
755 rdmsrl(MSR_EFER, efer);
756 if (efer & EFER_SVME)
757 return -EBUSY;
758
759 if (!has_svm()) {
760 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
761 return -EINVAL;
762 }
763 sd = per_cpu(svm_data, me);
764 if (!sd) {
765 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
766 return -EINVAL;
767 }
768
769 sd->asid_generation = 1;
770 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
771 sd->next_asid = sd->max_asid + 1;
772
773 gdt = get_current_gdt_rw();
774 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
775
776 wrmsrl(MSR_EFER, efer | EFER_SVME);
777
778 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
779
780 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
781 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
782 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
783 }
784
785
786 /*
787 * Get OSVW bits.
788 *
789 * Note that it is possible to have a system with mixed processor
790 * revisions and therefore different OSVW bits. If bits are not the same
791 * on different processors then choose the worst case (i.e. if erratum
792 * is present on one processor and not on another then assume that the
793 * erratum is present everywhere).
794 */
795 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
796 uint64_t len, status = 0;
797 int err;
798
799 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
800 if (!err)
801 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
802 &err);
803
804 if (err)
805 osvw_status = osvw_len = 0;
806 else {
807 if (len < osvw_len)
808 osvw_len = len;
809 osvw_status |= status;
810 osvw_status &= (1ULL << osvw_len) - 1;
811 }
812 } else
813 osvw_status = osvw_len = 0;
814
815 svm_init_erratum_383();
816
817 amd_pmu_enable_virt();
818
819 return 0;
820 }
821
822 static void svm_cpu_uninit(int cpu)
823 {
824 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
825
826 if (!sd)
827 return;
828
829 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
830 __free_page(sd->save_area);
831 kfree(sd);
832 }
833
834 static int svm_cpu_init(int cpu)
835 {
836 struct svm_cpu_data *sd;
837 int r;
838
839 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
840 if (!sd)
841 return -ENOMEM;
842 sd->cpu = cpu;
843 sd->save_area = alloc_page(GFP_KERNEL);
844 r = -ENOMEM;
845 if (!sd->save_area)
846 goto err_1;
847
848 per_cpu(svm_data, cpu) = sd;
849
850 return 0;
851
852 err_1:
853 kfree(sd);
854 return r;
855
856 }
857
858 static bool valid_msr_intercept(u32 index)
859 {
860 int i;
861
862 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
863 if (direct_access_msrs[i].index == index)
864 return true;
865
866 return false;
867 }
868
869 static void set_msr_interception(u32 *msrpm, unsigned msr,
870 int read, int write)
871 {
872 u8 bit_read, bit_write;
873 unsigned long tmp;
874 u32 offset;
875
876 /*
877 * If this warning triggers extend the direct_access_msrs list at the
878 * beginning of the file
879 */
880 WARN_ON(!valid_msr_intercept(msr));
881
882 offset = svm_msrpm_offset(msr);
883 bit_read = 2 * (msr & 0x0f);
884 bit_write = 2 * (msr & 0x0f) + 1;
885 tmp = msrpm[offset];
886
887 BUG_ON(offset == MSR_INVALID);
888
889 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
890 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
891
892 msrpm[offset] = tmp;
893 }
894
895 static void svm_vcpu_init_msrpm(u32 *msrpm)
896 {
897 int i;
898
899 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
900
901 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
902 if (!direct_access_msrs[i].always)
903 continue;
904
905 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
906 }
907 }
908
909 static void add_msr_offset(u32 offset)
910 {
911 int i;
912
913 for (i = 0; i < MSRPM_OFFSETS; ++i) {
914
915 /* Offset already in list? */
916 if (msrpm_offsets[i] == offset)
917 return;
918
919 /* Slot used by another offset? */
920 if (msrpm_offsets[i] != MSR_INVALID)
921 continue;
922
923 /* Add offset to list */
924 msrpm_offsets[i] = offset;
925
926 return;
927 }
928
929 /*
930 * If this BUG triggers the msrpm_offsets table has an overflow. Just
931 * increase MSRPM_OFFSETS in this case.
932 */
933 BUG();
934 }
935
936 static void init_msrpm_offsets(void)
937 {
938 int i;
939
940 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
941
942 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
943 u32 offset;
944
945 offset = svm_msrpm_offset(direct_access_msrs[i].index);
946 BUG_ON(offset == MSR_INVALID);
947
948 add_msr_offset(offset);
949 }
950 }
951
952 static void svm_enable_lbrv(struct vcpu_svm *svm)
953 {
954 u32 *msrpm = svm->msrpm;
955
956 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
957 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
958 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
959 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
960 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
961 }
962
963 static void svm_disable_lbrv(struct vcpu_svm *svm)
964 {
965 u32 *msrpm = svm->msrpm;
966
967 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
968 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
969 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
970 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
971 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
972 }
973
974 static void disable_nmi_singlestep(struct vcpu_svm *svm)
975 {
976 svm->nmi_singlestep = false;
977 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
978 /* Clear our flags if they were not set by the guest */
979 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
980 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
981 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
982 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
983 }
984 }
985
986 /* Note:
987 * This hash table is used to map VM_ID to a struct kvm_arch,
988 * when handling AMD IOMMU GALOG notification to schedule in
989 * a particular vCPU.
990 */
991 #define SVM_VM_DATA_HASH_BITS 8
992 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
993 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
994
995 /* Note:
996 * This function is called from IOMMU driver to notify
997 * SVM to schedule in a particular vCPU of a particular VM.
998 */
999 static int avic_ga_log_notifier(u32 ga_tag)
1000 {
1001 unsigned long flags;
1002 struct kvm_arch *ka = NULL;
1003 struct kvm_vcpu *vcpu = NULL;
1004 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1005 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1006
1007 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1008
1009 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1010 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1011 struct kvm *kvm = container_of(ka, struct kvm, arch);
1012 struct kvm_arch *vm_data = &kvm->arch;
1013
1014 if (vm_data->avic_vm_id != vm_id)
1015 continue;
1016 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1017 break;
1018 }
1019 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1020
1021 if (!vcpu)
1022 return 0;
1023
1024 /* Note:
1025 * At this point, the IOMMU should have already set the pending
1026 * bit in the vAPIC backing page. So, we just need to schedule
1027 * in the vcpu.
1028 */
1029 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1030 kvm_vcpu_wake_up(vcpu);
1031
1032 return 0;
1033 }
1034
1035 static __init int svm_hardware_setup(void)
1036 {
1037 int cpu;
1038 struct page *iopm_pages;
1039 void *iopm_va;
1040 int r;
1041
1042 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1043
1044 if (!iopm_pages)
1045 return -ENOMEM;
1046
1047 iopm_va = page_address(iopm_pages);
1048 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1049 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1050
1051 init_msrpm_offsets();
1052
1053 if (boot_cpu_has(X86_FEATURE_NX))
1054 kvm_enable_efer_bits(EFER_NX);
1055
1056 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1057 kvm_enable_efer_bits(EFER_FFXSR);
1058
1059 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1060 kvm_has_tsc_control = true;
1061 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1062 kvm_tsc_scaling_ratio_frac_bits = 32;
1063 }
1064
1065 if (nested) {
1066 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1067 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1068 }
1069
1070 for_each_possible_cpu(cpu) {
1071 r = svm_cpu_init(cpu);
1072 if (r)
1073 goto err;
1074 }
1075
1076 if (!boot_cpu_has(X86_FEATURE_NPT))
1077 npt_enabled = false;
1078
1079 if (npt_enabled && !npt) {
1080 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1081 npt_enabled = false;
1082 }
1083
1084 if (npt_enabled) {
1085 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1086 kvm_enable_tdp();
1087 } else
1088 kvm_disable_tdp();
1089
1090 if (avic) {
1091 if (!npt_enabled ||
1092 !boot_cpu_has(X86_FEATURE_AVIC) ||
1093 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1094 avic = false;
1095 } else {
1096 pr_info("AVIC enabled\n");
1097
1098 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1099 }
1100 }
1101
1102 if (vls) {
1103 if (!npt_enabled ||
1104 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1105 !IS_ENABLED(CONFIG_X86_64)) {
1106 vls = false;
1107 } else {
1108 pr_info("Virtual VMLOAD VMSAVE supported\n");
1109 }
1110 }
1111
1112 return 0;
1113
1114 err:
1115 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1116 iopm_base = 0;
1117 return r;
1118 }
1119
1120 static __exit void svm_hardware_unsetup(void)
1121 {
1122 int cpu;
1123
1124 for_each_possible_cpu(cpu)
1125 svm_cpu_uninit(cpu);
1126
1127 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1128 iopm_base = 0;
1129 }
1130
1131 static void init_seg(struct vmcb_seg *seg)
1132 {
1133 seg->selector = 0;
1134 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1135 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1136 seg->limit = 0xffff;
1137 seg->base = 0;
1138 }
1139
1140 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1141 {
1142 seg->selector = 0;
1143 seg->attrib = SVM_SELECTOR_P_MASK | type;
1144 seg->limit = 0xffff;
1145 seg->base = 0;
1146 }
1147
1148 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1149 {
1150 struct vcpu_svm *svm = to_svm(vcpu);
1151 u64 g_tsc_offset = 0;
1152
1153 if (is_guest_mode(vcpu)) {
1154 g_tsc_offset = svm->vmcb->control.tsc_offset -
1155 svm->nested.hsave->control.tsc_offset;
1156 svm->nested.hsave->control.tsc_offset = offset;
1157 } else
1158 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1159 svm->vmcb->control.tsc_offset,
1160 offset);
1161
1162 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1163
1164 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1165 }
1166
1167 static void avic_init_vmcb(struct vcpu_svm *svm)
1168 {
1169 struct vmcb *vmcb = svm->vmcb;
1170 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1171 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1172 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1173 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1174
1175 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1176 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1177 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1178 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1179 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1180 svm->vcpu.arch.apicv_active = true;
1181 }
1182
1183 static void init_vmcb(struct vcpu_svm *svm)
1184 {
1185 struct vmcb_control_area *control = &svm->vmcb->control;
1186 struct vmcb_save_area *save = &svm->vmcb->save;
1187
1188 svm->vcpu.arch.hflags = 0;
1189
1190 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1191 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1192 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1193 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1194 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1195 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1196 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1197 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1198
1199 set_dr_intercepts(svm);
1200
1201 set_exception_intercept(svm, PF_VECTOR);
1202 set_exception_intercept(svm, UD_VECTOR);
1203 set_exception_intercept(svm, MC_VECTOR);
1204 set_exception_intercept(svm, AC_VECTOR);
1205 set_exception_intercept(svm, DB_VECTOR);
1206
1207 set_intercept(svm, INTERCEPT_INTR);
1208 set_intercept(svm, INTERCEPT_NMI);
1209 set_intercept(svm, INTERCEPT_SMI);
1210 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1211 set_intercept(svm, INTERCEPT_RDPMC);
1212 set_intercept(svm, INTERCEPT_CPUID);
1213 set_intercept(svm, INTERCEPT_INVD);
1214 set_intercept(svm, INTERCEPT_HLT);
1215 set_intercept(svm, INTERCEPT_INVLPG);
1216 set_intercept(svm, INTERCEPT_INVLPGA);
1217 set_intercept(svm, INTERCEPT_IOIO_PROT);
1218 set_intercept(svm, INTERCEPT_MSR_PROT);
1219 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1220 set_intercept(svm, INTERCEPT_SHUTDOWN);
1221 set_intercept(svm, INTERCEPT_VMRUN);
1222 set_intercept(svm, INTERCEPT_VMMCALL);
1223 set_intercept(svm, INTERCEPT_VMLOAD);
1224 set_intercept(svm, INTERCEPT_VMSAVE);
1225 set_intercept(svm, INTERCEPT_STGI);
1226 set_intercept(svm, INTERCEPT_CLGI);
1227 set_intercept(svm, INTERCEPT_SKINIT);
1228 set_intercept(svm, INTERCEPT_WBINVD);
1229 set_intercept(svm, INTERCEPT_XSETBV);
1230
1231 if (!kvm_mwait_in_guest()) {
1232 set_intercept(svm, INTERCEPT_MONITOR);
1233 set_intercept(svm, INTERCEPT_MWAIT);
1234 }
1235
1236 control->iopm_base_pa = iopm_base;
1237 control->msrpm_base_pa = __pa(svm->msrpm);
1238 control->int_ctl = V_INTR_MASKING_MASK;
1239
1240 init_seg(&save->es);
1241 init_seg(&save->ss);
1242 init_seg(&save->ds);
1243 init_seg(&save->fs);
1244 init_seg(&save->gs);
1245
1246 save->cs.selector = 0xf000;
1247 save->cs.base = 0xffff0000;
1248 /* Executable/Readable Code Segment */
1249 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1250 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1251 save->cs.limit = 0xffff;
1252
1253 save->gdtr.limit = 0xffff;
1254 save->idtr.limit = 0xffff;
1255
1256 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1257 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1258
1259 svm_set_efer(&svm->vcpu, 0);
1260 save->dr6 = 0xffff0ff0;
1261 kvm_set_rflags(&svm->vcpu, 2);
1262 save->rip = 0x0000fff0;
1263 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1264
1265 /*
1266 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1267 * It also updates the guest-visible cr0 value.
1268 */
1269 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1270 kvm_mmu_reset_context(&svm->vcpu);
1271
1272 save->cr4 = X86_CR4_PAE;
1273 /* rdx = ?? */
1274
1275 if (npt_enabled) {
1276 /* Setup VMCB for Nested Paging */
1277 control->nested_ctl = 1;
1278 clr_intercept(svm, INTERCEPT_INVLPG);
1279 clr_exception_intercept(svm, PF_VECTOR);
1280 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1281 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1282 save->g_pat = svm->vcpu.arch.pat;
1283 save->cr3 = 0;
1284 save->cr4 = 0;
1285 }
1286 svm->asid_generation = 0;
1287
1288 svm->nested.vmcb = 0;
1289 svm->vcpu.arch.hflags = 0;
1290
1291 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1292 control->pause_filter_count = 3000;
1293 set_intercept(svm, INTERCEPT_PAUSE);
1294 }
1295
1296 if (avic)
1297 avic_init_vmcb(svm);
1298
1299 /*
1300 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1301 * in VMCB and clear intercepts to avoid #VMEXIT.
1302 */
1303 if (vls) {
1304 clr_intercept(svm, INTERCEPT_VMLOAD);
1305 clr_intercept(svm, INTERCEPT_VMSAVE);
1306 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1307 }
1308
1309 mark_all_dirty(svm->vmcb);
1310
1311 enable_gif(svm);
1312
1313 }
1314
1315 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1316 unsigned int index)
1317 {
1318 u64 *avic_physical_id_table;
1319 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1320
1321 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1322 return NULL;
1323
1324 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1325
1326 return &avic_physical_id_table[index];
1327 }
1328
1329 /**
1330 * Note:
1331 * AVIC hardware walks the nested page table to check permissions,
1332 * but does not use the SPA address specified in the leaf page
1333 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1334 * field of the VMCB. Therefore, we set up the
1335 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1336 */
1337 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1338 {
1339 struct kvm *kvm = vcpu->kvm;
1340 int ret;
1341
1342 if (kvm->arch.apic_access_page_done)
1343 return 0;
1344
1345 ret = x86_set_memory_region(kvm,
1346 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1347 APIC_DEFAULT_PHYS_BASE,
1348 PAGE_SIZE);
1349 if (ret)
1350 return ret;
1351
1352 kvm->arch.apic_access_page_done = true;
1353 return 0;
1354 }
1355
1356 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1357 {
1358 int ret;
1359 u64 *entry, new_entry;
1360 int id = vcpu->vcpu_id;
1361 struct vcpu_svm *svm = to_svm(vcpu);
1362
1363 ret = avic_init_access_page(vcpu);
1364 if (ret)
1365 return ret;
1366
1367 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1368 return -EINVAL;
1369
1370 if (!svm->vcpu.arch.apic->regs)
1371 return -EINVAL;
1372
1373 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1374
1375 /* Setting AVIC backing page address in the phy APIC ID table */
1376 entry = avic_get_physical_id_entry(vcpu, id);
1377 if (!entry)
1378 return -EINVAL;
1379
1380 new_entry = READ_ONCE(*entry);
1381 new_entry = (page_to_phys(svm->avic_backing_page) &
1382 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1383 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1384 WRITE_ONCE(*entry, new_entry);
1385
1386 svm->avic_physical_id_cache = entry;
1387
1388 return 0;
1389 }
1390
1391 static inline int avic_get_next_vm_id(void)
1392 {
1393 int id;
1394
1395 spin_lock(&avic_vm_id_lock);
1396
1397 /* AVIC VM ID is one-based. */
1398 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1399 if (id <= AVIC_VM_ID_MASK)
1400 __set_bit(id, avic_vm_id_bitmap);
1401 else
1402 id = -EAGAIN;
1403
1404 spin_unlock(&avic_vm_id_lock);
1405 return id;
1406 }
1407
1408 static inline int avic_free_vm_id(int id)
1409 {
1410 if (id <= 0 || id > AVIC_VM_ID_MASK)
1411 return -EINVAL;
1412
1413 spin_lock(&avic_vm_id_lock);
1414 __clear_bit(id, avic_vm_id_bitmap);
1415 spin_unlock(&avic_vm_id_lock);
1416 return 0;
1417 }
1418
1419 static void avic_vm_destroy(struct kvm *kvm)
1420 {
1421 unsigned long flags;
1422 struct kvm_arch *vm_data = &kvm->arch;
1423
1424 if (!avic)
1425 return;
1426
1427 avic_free_vm_id(vm_data->avic_vm_id);
1428
1429 if (vm_data->avic_logical_id_table_page)
1430 __free_page(vm_data->avic_logical_id_table_page);
1431 if (vm_data->avic_physical_id_table_page)
1432 __free_page(vm_data->avic_physical_id_table_page);
1433
1434 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1435 hash_del(&vm_data->hnode);
1436 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1437 }
1438
1439 static int avic_vm_init(struct kvm *kvm)
1440 {
1441 unsigned long flags;
1442 int vm_id, err = -ENOMEM;
1443 struct kvm_arch *vm_data = &kvm->arch;
1444 struct page *p_page;
1445 struct page *l_page;
1446
1447 if (!avic)
1448 return 0;
1449
1450 vm_id = avic_get_next_vm_id();
1451 if (vm_id < 0)
1452 return vm_id;
1453 vm_data->avic_vm_id = (u32)vm_id;
1454
1455 /* Allocating physical APIC ID table (4KB) */
1456 p_page = alloc_page(GFP_KERNEL);
1457 if (!p_page)
1458 goto free_avic;
1459
1460 vm_data->avic_physical_id_table_page = p_page;
1461 clear_page(page_address(p_page));
1462
1463 /* Allocating logical APIC ID table (4KB) */
1464 l_page = alloc_page(GFP_KERNEL);
1465 if (!l_page)
1466 goto free_avic;
1467
1468 vm_data->avic_logical_id_table_page = l_page;
1469 clear_page(page_address(l_page));
1470
1471 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1472 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1473 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1474
1475 return 0;
1476
1477 free_avic:
1478 avic_vm_destroy(kvm);
1479 return err;
1480 }
1481
1482 static inline int
1483 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1484 {
1485 int ret = 0;
1486 unsigned long flags;
1487 struct amd_svm_iommu_ir *ir;
1488 struct vcpu_svm *svm = to_svm(vcpu);
1489
1490 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1491 return 0;
1492
1493 /*
1494 * Here, we go through the per-vcpu ir_list to update all existing
1495 * interrupt remapping table entry targeting this vcpu.
1496 */
1497 spin_lock_irqsave(&svm->ir_list_lock, flags);
1498
1499 if (list_empty(&svm->ir_list))
1500 goto out;
1501
1502 list_for_each_entry(ir, &svm->ir_list, node) {
1503 ret = amd_iommu_update_ga(cpu, r, ir->data);
1504 if (ret)
1505 break;
1506 }
1507 out:
1508 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1509 return ret;
1510 }
1511
1512 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1513 {
1514 u64 entry;
1515 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1516 int h_physical_id = kvm_cpu_get_apicid(cpu);
1517 struct vcpu_svm *svm = to_svm(vcpu);
1518
1519 if (!kvm_vcpu_apicv_active(vcpu))
1520 return;
1521
1522 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1523 return;
1524
1525 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1526 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1527
1528 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1529 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1530
1531 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1532 if (svm->avic_is_running)
1533 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1534
1535 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1536 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1537 svm->avic_is_running);
1538 }
1539
1540 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1541 {
1542 u64 entry;
1543 struct vcpu_svm *svm = to_svm(vcpu);
1544
1545 if (!kvm_vcpu_apicv_active(vcpu))
1546 return;
1547
1548 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1549 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1550 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1551
1552 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1553 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1554 }
1555
1556 /**
1557 * This function is called during VCPU halt/unhalt.
1558 */
1559 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1560 {
1561 struct vcpu_svm *svm = to_svm(vcpu);
1562
1563 svm->avic_is_running = is_run;
1564 if (is_run)
1565 avic_vcpu_load(vcpu, vcpu->cpu);
1566 else
1567 avic_vcpu_put(vcpu);
1568 }
1569
1570 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1571 {
1572 struct vcpu_svm *svm = to_svm(vcpu);
1573 u32 dummy;
1574 u32 eax = 1;
1575
1576 if (!init_event) {
1577 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1578 MSR_IA32_APICBASE_ENABLE;
1579 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1580 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1581 }
1582 init_vmcb(svm);
1583
1584 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1585 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1586
1587 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1588 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1589 }
1590
1591 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1592 {
1593 struct vcpu_svm *svm;
1594 struct page *page;
1595 struct page *msrpm_pages;
1596 struct page *hsave_page;
1597 struct page *nested_msrpm_pages;
1598 int err;
1599
1600 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1601 if (!svm) {
1602 err = -ENOMEM;
1603 goto out;
1604 }
1605
1606 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1607 if (err)
1608 goto free_svm;
1609
1610 err = -ENOMEM;
1611 page = alloc_page(GFP_KERNEL);
1612 if (!page)
1613 goto uninit;
1614
1615 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1616 if (!msrpm_pages)
1617 goto free_page1;
1618
1619 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1620 if (!nested_msrpm_pages)
1621 goto free_page2;
1622
1623 hsave_page = alloc_page(GFP_KERNEL);
1624 if (!hsave_page)
1625 goto free_page3;
1626
1627 if (avic) {
1628 err = avic_init_backing_page(&svm->vcpu);
1629 if (err)
1630 goto free_page4;
1631
1632 INIT_LIST_HEAD(&svm->ir_list);
1633 spin_lock_init(&svm->ir_list_lock);
1634 }
1635
1636 /* We initialize this flag to true to make sure that the is_running
1637 * bit would be set the first time the vcpu is loaded.
1638 */
1639 svm->avic_is_running = true;
1640
1641 svm->nested.hsave = page_address(hsave_page);
1642
1643 svm->msrpm = page_address(msrpm_pages);
1644 svm_vcpu_init_msrpm(svm->msrpm);
1645
1646 svm->nested.msrpm = page_address(nested_msrpm_pages);
1647 svm_vcpu_init_msrpm(svm->nested.msrpm);
1648
1649 svm->vmcb = page_address(page);
1650 clear_page(svm->vmcb);
1651 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1652 svm->asid_generation = 0;
1653 init_vmcb(svm);
1654
1655 svm_init_osvw(&svm->vcpu);
1656
1657 return &svm->vcpu;
1658
1659 free_page4:
1660 __free_page(hsave_page);
1661 free_page3:
1662 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1663 free_page2:
1664 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1665 free_page1:
1666 __free_page(page);
1667 uninit:
1668 kvm_vcpu_uninit(&svm->vcpu);
1669 free_svm:
1670 kmem_cache_free(kvm_vcpu_cache, svm);
1671 out:
1672 return ERR_PTR(err);
1673 }
1674
1675 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1676 {
1677 struct vcpu_svm *svm = to_svm(vcpu);
1678
1679 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1680 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1681 __free_page(virt_to_page(svm->nested.hsave));
1682 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1683 kvm_vcpu_uninit(vcpu);
1684 kmem_cache_free(kvm_vcpu_cache, svm);
1685 }
1686
1687 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1688 {
1689 struct vcpu_svm *svm = to_svm(vcpu);
1690 int i;
1691
1692 if (unlikely(cpu != vcpu->cpu)) {
1693 svm->asid_generation = 0;
1694 mark_all_dirty(svm->vmcb);
1695 }
1696
1697 #ifdef CONFIG_X86_64
1698 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1699 #endif
1700 savesegment(fs, svm->host.fs);
1701 savesegment(gs, svm->host.gs);
1702 svm->host.ldt = kvm_read_ldt();
1703
1704 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1705 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1706
1707 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1708 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1709 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1710 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1711 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1712 }
1713 }
1714 /* This assumes that the kernel never uses MSR_TSC_AUX */
1715 if (static_cpu_has(X86_FEATURE_RDTSCP))
1716 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1717
1718 avic_vcpu_load(vcpu, cpu);
1719 }
1720
1721 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1722 {
1723 struct vcpu_svm *svm = to_svm(vcpu);
1724 int i;
1725
1726 avic_vcpu_put(vcpu);
1727
1728 ++vcpu->stat.host_state_reload;
1729 kvm_load_ldt(svm->host.ldt);
1730 #ifdef CONFIG_X86_64
1731 loadsegment(fs, svm->host.fs);
1732 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1733 load_gs_index(svm->host.gs);
1734 #else
1735 #ifdef CONFIG_X86_32_LAZY_GS
1736 loadsegment(gs, svm->host.gs);
1737 #endif
1738 #endif
1739 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1740 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1741 }
1742
1743 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1744 {
1745 avic_set_running(vcpu, false);
1746 }
1747
1748 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1749 {
1750 avic_set_running(vcpu, true);
1751 }
1752
1753 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1754 {
1755 struct vcpu_svm *svm = to_svm(vcpu);
1756 unsigned long rflags = svm->vmcb->save.rflags;
1757
1758 if (svm->nmi_singlestep) {
1759 /* Hide our flags if they were not set by the guest */
1760 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1761 rflags &= ~X86_EFLAGS_TF;
1762 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1763 rflags &= ~X86_EFLAGS_RF;
1764 }
1765 return rflags;
1766 }
1767
1768 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1769 {
1770 if (to_svm(vcpu)->nmi_singlestep)
1771 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1772
1773 /*
1774 * Any change of EFLAGS.VM is accompanied by a reload of SS
1775 * (caused by either a task switch or an inter-privilege IRET),
1776 * so we do not need to update the CPL here.
1777 */
1778 to_svm(vcpu)->vmcb->save.rflags = rflags;
1779 }
1780
1781 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1782 {
1783 switch (reg) {
1784 case VCPU_EXREG_PDPTR:
1785 BUG_ON(!npt_enabled);
1786 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1787 break;
1788 default:
1789 BUG();
1790 }
1791 }
1792
1793 static void svm_set_vintr(struct vcpu_svm *svm)
1794 {
1795 set_intercept(svm, INTERCEPT_VINTR);
1796 }
1797
1798 static void svm_clear_vintr(struct vcpu_svm *svm)
1799 {
1800 clr_intercept(svm, INTERCEPT_VINTR);
1801 }
1802
1803 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1804 {
1805 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1806
1807 switch (seg) {
1808 case VCPU_SREG_CS: return &save->cs;
1809 case VCPU_SREG_DS: return &save->ds;
1810 case VCPU_SREG_ES: return &save->es;
1811 case VCPU_SREG_FS: return &save->fs;
1812 case VCPU_SREG_GS: return &save->gs;
1813 case VCPU_SREG_SS: return &save->ss;
1814 case VCPU_SREG_TR: return &save->tr;
1815 case VCPU_SREG_LDTR: return &save->ldtr;
1816 }
1817 BUG();
1818 return NULL;
1819 }
1820
1821 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1822 {
1823 struct vmcb_seg *s = svm_seg(vcpu, seg);
1824
1825 return s->base;
1826 }
1827
1828 static void svm_get_segment(struct kvm_vcpu *vcpu,
1829 struct kvm_segment *var, int seg)
1830 {
1831 struct vmcb_seg *s = svm_seg(vcpu, seg);
1832
1833 var->base = s->base;
1834 var->limit = s->limit;
1835 var->selector = s->selector;
1836 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1837 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1838 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1839 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1840 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1841 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1842 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1843
1844 /*
1845 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1846 * However, the SVM spec states that the G bit is not observed by the
1847 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1848 * So let's synthesize a legal G bit for all segments, this helps
1849 * running KVM nested. It also helps cross-vendor migration, because
1850 * Intel's vmentry has a check on the 'G' bit.
1851 */
1852 var->g = s->limit > 0xfffff;
1853
1854 /*
1855 * AMD's VMCB does not have an explicit unusable field, so emulate it
1856 * for cross vendor migration purposes by "not present"
1857 */
1858 var->unusable = !var->present;
1859
1860 switch (seg) {
1861 case VCPU_SREG_TR:
1862 /*
1863 * Work around a bug where the busy flag in the tr selector
1864 * isn't exposed
1865 */
1866 var->type |= 0x2;
1867 break;
1868 case VCPU_SREG_DS:
1869 case VCPU_SREG_ES:
1870 case VCPU_SREG_FS:
1871 case VCPU_SREG_GS:
1872 /*
1873 * The accessed bit must always be set in the segment
1874 * descriptor cache, although it can be cleared in the
1875 * descriptor, the cached bit always remains at 1. Since
1876 * Intel has a check on this, set it here to support
1877 * cross-vendor migration.
1878 */
1879 if (!var->unusable)
1880 var->type |= 0x1;
1881 break;
1882 case VCPU_SREG_SS:
1883 /*
1884 * On AMD CPUs sometimes the DB bit in the segment
1885 * descriptor is left as 1, although the whole segment has
1886 * been made unusable. Clear it here to pass an Intel VMX
1887 * entry check when cross vendor migrating.
1888 */
1889 if (var->unusable)
1890 var->db = 0;
1891 /* This is symmetric with svm_set_segment() */
1892 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1893 break;
1894 }
1895 }
1896
1897 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1898 {
1899 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1900
1901 return save->cpl;
1902 }
1903
1904 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1905 {
1906 struct vcpu_svm *svm = to_svm(vcpu);
1907
1908 dt->size = svm->vmcb->save.idtr.limit;
1909 dt->address = svm->vmcb->save.idtr.base;
1910 }
1911
1912 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1913 {
1914 struct vcpu_svm *svm = to_svm(vcpu);
1915
1916 svm->vmcb->save.idtr.limit = dt->size;
1917 svm->vmcb->save.idtr.base = dt->address ;
1918 mark_dirty(svm->vmcb, VMCB_DT);
1919 }
1920
1921 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1922 {
1923 struct vcpu_svm *svm = to_svm(vcpu);
1924
1925 dt->size = svm->vmcb->save.gdtr.limit;
1926 dt->address = svm->vmcb->save.gdtr.base;
1927 }
1928
1929 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1930 {
1931 struct vcpu_svm *svm = to_svm(vcpu);
1932
1933 svm->vmcb->save.gdtr.limit = dt->size;
1934 svm->vmcb->save.gdtr.base = dt->address ;
1935 mark_dirty(svm->vmcb, VMCB_DT);
1936 }
1937
1938 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1939 {
1940 }
1941
1942 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1943 {
1944 }
1945
1946 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1947 {
1948 }
1949
1950 static void update_cr0_intercept(struct vcpu_svm *svm)
1951 {
1952 ulong gcr0 = svm->vcpu.arch.cr0;
1953 u64 *hcr0 = &svm->vmcb->save.cr0;
1954
1955 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1956 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1957
1958 mark_dirty(svm->vmcb, VMCB_CR);
1959
1960 if (gcr0 == *hcr0) {
1961 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1962 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1963 } else {
1964 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1965 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1966 }
1967 }
1968
1969 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1970 {
1971 struct vcpu_svm *svm = to_svm(vcpu);
1972
1973 #ifdef CONFIG_X86_64
1974 if (vcpu->arch.efer & EFER_LME) {
1975 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1976 vcpu->arch.efer |= EFER_LMA;
1977 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1978 }
1979
1980 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1981 vcpu->arch.efer &= ~EFER_LMA;
1982 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1983 }
1984 }
1985 #endif
1986 vcpu->arch.cr0 = cr0;
1987
1988 if (!npt_enabled)
1989 cr0 |= X86_CR0_PG | X86_CR0_WP;
1990
1991 /*
1992 * re-enable caching here because the QEMU bios
1993 * does not do it - this results in some delay at
1994 * reboot
1995 */
1996 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1997 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1998 svm->vmcb->save.cr0 = cr0;
1999 mark_dirty(svm->vmcb, VMCB_CR);
2000 update_cr0_intercept(svm);
2001 }
2002
2003 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2004 {
2005 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2006 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2007
2008 if (cr4 & X86_CR4_VMXE)
2009 return 1;
2010
2011 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2012 svm_flush_tlb(vcpu);
2013
2014 vcpu->arch.cr4 = cr4;
2015 if (!npt_enabled)
2016 cr4 |= X86_CR4_PAE;
2017 cr4 |= host_cr4_mce;
2018 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2019 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2020 return 0;
2021 }
2022
2023 static void svm_set_segment(struct kvm_vcpu *vcpu,
2024 struct kvm_segment *var, int seg)
2025 {
2026 struct vcpu_svm *svm = to_svm(vcpu);
2027 struct vmcb_seg *s = svm_seg(vcpu, seg);
2028
2029 s->base = var->base;
2030 s->limit = var->limit;
2031 s->selector = var->selector;
2032 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2033 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2034 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2035 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2036 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2037 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2038 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2039 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2040
2041 /*
2042 * This is always accurate, except if SYSRET returned to a segment
2043 * with SS.DPL != 3. Intel does not have this quirk, and always
2044 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2045 * would entail passing the CPL to userspace and back.
2046 */
2047 if (seg == VCPU_SREG_SS)
2048 /* This is symmetric with svm_get_segment() */
2049 svm->vmcb->save.cpl = (var->dpl & 3);
2050
2051 mark_dirty(svm->vmcb, VMCB_SEG);
2052 }
2053
2054 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2055 {
2056 struct vcpu_svm *svm = to_svm(vcpu);
2057
2058 clr_exception_intercept(svm, BP_VECTOR);
2059
2060 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2061 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2062 set_exception_intercept(svm, BP_VECTOR);
2063 } else
2064 vcpu->guest_debug = 0;
2065 }
2066
2067 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2068 {
2069 if (sd->next_asid > sd->max_asid) {
2070 ++sd->asid_generation;
2071 sd->next_asid = 1;
2072 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2073 }
2074
2075 svm->asid_generation = sd->asid_generation;
2076 svm->vmcb->control.asid = sd->next_asid++;
2077
2078 mark_dirty(svm->vmcb, VMCB_ASID);
2079 }
2080
2081 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2082 {
2083 return to_svm(vcpu)->vmcb->save.dr6;
2084 }
2085
2086 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2087 {
2088 struct vcpu_svm *svm = to_svm(vcpu);
2089
2090 svm->vmcb->save.dr6 = value;
2091 mark_dirty(svm->vmcb, VMCB_DR);
2092 }
2093
2094 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2095 {
2096 struct vcpu_svm *svm = to_svm(vcpu);
2097
2098 get_debugreg(vcpu->arch.db[0], 0);
2099 get_debugreg(vcpu->arch.db[1], 1);
2100 get_debugreg(vcpu->arch.db[2], 2);
2101 get_debugreg(vcpu->arch.db[3], 3);
2102 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2103 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2104
2105 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2106 set_dr_intercepts(svm);
2107 }
2108
2109 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2110 {
2111 struct vcpu_svm *svm = to_svm(vcpu);
2112
2113 svm->vmcb->save.dr7 = value;
2114 mark_dirty(svm->vmcb, VMCB_DR);
2115 }
2116
2117 static int pf_interception(struct vcpu_svm *svm)
2118 {
2119 u64 fault_address = svm->vmcb->control.exit_info_2;
2120 u64 error_code = svm->vmcb->control.exit_info_1;
2121
2122 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2123 svm->vmcb->control.insn_bytes,
2124 svm->vmcb->control.insn_len, !npt_enabled);
2125 }
2126
2127 static int db_interception(struct vcpu_svm *svm)
2128 {
2129 struct kvm_run *kvm_run = svm->vcpu.run;
2130
2131 if (!(svm->vcpu.guest_debug &
2132 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2133 !svm->nmi_singlestep) {
2134 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2135 return 1;
2136 }
2137
2138 if (svm->nmi_singlestep) {
2139 disable_nmi_singlestep(svm);
2140 }
2141
2142 if (svm->vcpu.guest_debug &
2143 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2144 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2145 kvm_run->debug.arch.pc =
2146 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2147 kvm_run->debug.arch.exception = DB_VECTOR;
2148 return 0;
2149 }
2150
2151 return 1;
2152 }
2153
2154 static int bp_interception(struct vcpu_svm *svm)
2155 {
2156 struct kvm_run *kvm_run = svm->vcpu.run;
2157
2158 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2159 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2160 kvm_run->debug.arch.exception = BP_VECTOR;
2161 return 0;
2162 }
2163
2164 static int ud_interception(struct vcpu_svm *svm)
2165 {
2166 int er;
2167
2168 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2169 if (er != EMULATE_DONE)
2170 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2171 return 1;
2172 }
2173
2174 static int ac_interception(struct vcpu_svm *svm)
2175 {
2176 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2177 return 1;
2178 }
2179
2180 static bool is_erratum_383(void)
2181 {
2182 int err, i;
2183 u64 value;
2184
2185 if (!erratum_383_found)
2186 return false;
2187
2188 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2189 if (err)
2190 return false;
2191
2192 /* Bit 62 may or may not be set for this mce */
2193 value &= ~(1ULL << 62);
2194
2195 if (value != 0xb600000000010015ULL)
2196 return false;
2197
2198 /* Clear MCi_STATUS registers */
2199 for (i = 0; i < 6; ++i)
2200 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2201
2202 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2203 if (!err) {
2204 u32 low, high;
2205
2206 value &= ~(1ULL << 2);
2207 low = lower_32_bits(value);
2208 high = upper_32_bits(value);
2209
2210 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2211 }
2212
2213 /* Flush tlb to evict multi-match entries */
2214 __flush_tlb_all();
2215
2216 return true;
2217 }
2218
2219 static void svm_handle_mce(struct vcpu_svm *svm)
2220 {
2221 if (is_erratum_383()) {
2222 /*
2223 * Erratum 383 triggered. Guest state is corrupt so kill the
2224 * guest.
2225 */
2226 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2227
2228 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2229
2230 return;
2231 }
2232
2233 /*
2234 * On an #MC intercept the MCE handler is not called automatically in
2235 * the host. So do it by hand here.
2236 */
2237 asm volatile (
2238 "int $0x12\n");
2239 /* not sure if we ever come back to this point */
2240
2241 return;
2242 }
2243
2244 static int mc_interception(struct vcpu_svm *svm)
2245 {
2246 return 1;
2247 }
2248
2249 static int shutdown_interception(struct vcpu_svm *svm)
2250 {
2251 struct kvm_run *kvm_run = svm->vcpu.run;
2252
2253 /*
2254 * VMCB is undefined after a SHUTDOWN intercept
2255 * so reinitialize it.
2256 */
2257 clear_page(svm->vmcb);
2258 init_vmcb(svm);
2259
2260 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2261 return 0;
2262 }
2263
2264 static int io_interception(struct vcpu_svm *svm)
2265 {
2266 struct kvm_vcpu *vcpu = &svm->vcpu;
2267 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2268 int size, in, string, ret;
2269 unsigned port;
2270
2271 ++svm->vcpu.stat.io_exits;
2272 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2273 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2274 if (string)
2275 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2276
2277 port = io_info >> 16;
2278 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2279 svm->next_rip = svm->vmcb->control.exit_info_2;
2280 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2281
2282 /*
2283 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2284 * KVM_EXIT_DEBUG here.
2285 */
2286 if (in)
2287 return kvm_fast_pio_in(vcpu, size, port) && ret;
2288 else
2289 return kvm_fast_pio_out(vcpu, size, port) && ret;
2290 }
2291
2292 static int nmi_interception(struct vcpu_svm *svm)
2293 {
2294 return 1;
2295 }
2296
2297 static int intr_interception(struct vcpu_svm *svm)
2298 {
2299 ++svm->vcpu.stat.irq_exits;
2300 return 1;
2301 }
2302
2303 static int nop_on_interception(struct vcpu_svm *svm)
2304 {
2305 return 1;
2306 }
2307
2308 static int halt_interception(struct vcpu_svm *svm)
2309 {
2310 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2311 return kvm_emulate_halt(&svm->vcpu);
2312 }
2313
2314 static int vmmcall_interception(struct vcpu_svm *svm)
2315 {
2316 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2317 return kvm_emulate_hypercall(&svm->vcpu);
2318 }
2319
2320 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2321 {
2322 struct vcpu_svm *svm = to_svm(vcpu);
2323
2324 return svm->nested.nested_cr3;
2325 }
2326
2327 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2328 {
2329 struct vcpu_svm *svm = to_svm(vcpu);
2330 u64 cr3 = svm->nested.nested_cr3;
2331 u64 pdpte;
2332 int ret;
2333
2334 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2335 offset_in_page(cr3) + index * 8, 8);
2336 if (ret)
2337 return 0;
2338 return pdpte;
2339 }
2340
2341 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2342 unsigned long root)
2343 {
2344 struct vcpu_svm *svm = to_svm(vcpu);
2345
2346 svm->vmcb->control.nested_cr3 = root;
2347 mark_dirty(svm->vmcb, VMCB_NPT);
2348 svm_flush_tlb(vcpu);
2349 }
2350
2351 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2352 struct x86_exception *fault)
2353 {
2354 struct vcpu_svm *svm = to_svm(vcpu);
2355
2356 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2357 /*
2358 * TODO: track the cause of the nested page fault, and
2359 * correctly fill in the high bits of exit_info_1.
2360 */
2361 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2362 svm->vmcb->control.exit_code_hi = 0;
2363 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2364 svm->vmcb->control.exit_info_2 = fault->address;
2365 }
2366
2367 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2368 svm->vmcb->control.exit_info_1 |= fault->error_code;
2369
2370 /*
2371 * The present bit is always zero for page structure faults on real
2372 * hardware.
2373 */
2374 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2375 svm->vmcb->control.exit_info_1 &= ~1;
2376
2377 nested_svm_vmexit(svm);
2378 }
2379
2380 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2381 {
2382 WARN_ON(mmu_is_nested(vcpu));
2383 kvm_init_shadow_mmu(vcpu);
2384 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2385 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2386 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2387 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2388 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2389 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2390 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2391 }
2392
2393 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2394 {
2395 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2396 }
2397
2398 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2399 {
2400 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2401 !is_paging(&svm->vcpu)) {
2402 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2403 return 1;
2404 }
2405
2406 if (svm->vmcb->save.cpl) {
2407 kvm_inject_gp(&svm->vcpu, 0);
2408 return 1;
2409 }
2410
2411 return 0;
2412 }
2413
2414 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2415 bool has_error_code, u32 error_code)
2416 {
2417 int vmexit;
2418
2419 if (!is_guest_mode(&svm->vcpu))
2420 return 0;
2421
2422 vmexit = nested_svm_intercept(svm);
2423 if (vmexit != NESTED_EXIT_DONE)
2424 return 0;
2425
2426 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2427 svm->vmcb->control.exit_code_hi = 0;
2428 svm->vmcb->control.exit_info_1 = error_code;
2429
2430 /*
2431 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2432 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2433 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2434 * written only when inject_pending_event runs (DR6 would written here
2435 * too). This should be conditional on a new capability---if the
2436 * capability is disabled, kvm_multiple_exception would write the
2437 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2438 */
2439 if (svm->vcpu.arch.exception.nested_apf)
2440 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2441 else
2442 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2443
2444 svm->nested.exit_required = true;
2445 return vmexit;
2446 }
2447
2448 /* This function returns true if it is save to enable the irq window */
2449 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2450 {
2451 if (!is_guest_mode(&svm->vcpu))
2452 return true;
2453
2454 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2455 return true;
2456
2457 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2458 return false;
2459
2460 /*
2461 * if vmexit was already requested (by intercepted exception
2462 * for instance) do not overwrite it with "external interrupt"
2463 * vmexit.
2464 */
2465 if (svm->nested.exit_required)
2466 return false;
2467
2468 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2469 svm->vmcb->control.exit_info_1 = 0;
2470 svm->vmcb->control.exit_info_2 = 0;
2471
2472 if (svm->nested.intercept & 1ULL) {
2473 /*
2474 * The #vmexit can't be emulated here directly because this
2475 * code path runs with irqs and preemption disabled. A
2476 * #vmexit emulation might sleep. Only signal request for
2477 * the #vmexit here.
2478 */
2479 svm->nested.exit_required = true;
2480 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2481 return false;
2482 }
2483
2484 return true;
2485 }
2486
2487 /* This function returns true if it is save to enable the nmi window */
2488 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2489 {
2490 if (!is_guest_mode(&svm->vcpu))
2491 return true;
2492
2493 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2494 return true;
2495
2496 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2497 svm->nested.exit_required = true;
2498
2499 return false;
2500 }
2501
2502 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2503 {
2504 struct page *page;
2505
2506 might_sleep();
2507
2508 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2509 if (is_error_page(page))
2510 goto error;
2511
2512 *_page = page;
2513
2514 return kmap(page);
2515
2516 error:
2517 kvm_inject_gp(&svm->vcpu, 0);
2518
2519 return NULL;
2520 }
2521
2522 static void nested_svm_unmap(struct page *page)
2523 {
2524 kunmap(page);
2525 kvm_release_page_dirty(page);
2526 }
2527
2528 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2529 {
2530 unsigned port, size, iopm_len;
2531 u16 val, mask;
2532 u8 start_bit;
2533 u64 gpa;
2534
2535 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2536 return NESTED_EXIT_HOST;
2537
2538 port = svm->vmcb->control.exit_info_1 >> 16;
2539 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2540 SVM_IOIO_SIZE_SHIFT;
2541 gpa = svm->nested.vmcb_iopm + (port / 8);
2542 start_bit = port % 8;
2543 iopm_len = (start_bit + size > 8) ? 2 : 1;
2544 mask = (0xf >> (4 - size)) << start_bit;
2545 val = 0;
2546
2547 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2548 return NESTED_EXIT_DONE;
2549
2550 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2551 }
2552
2553 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2554 {
2555 u32 offset, msr, value;
2556 int write, mask;
2557
2558 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2559 return NESTED_EXIT_HOST;
2560
2561 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2562 offset = svm_msrpm_offset(msr);
2563 write = svm->vmcb->control.exit_info_1 & 1;
2564 mask = 1 << ((2 * (msr & 0xf)) + write);
2565
2566 if (offset == MSR_INVALID)
2567 return NESTED_EXIT_DONE;
2568
2569 /* Offset is in 32 bit units but need in 8 bit units */
2570 offset *= 4;
2571
2572 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2573 return NESTED_EXIT_DONE;
2574
2575 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2576 }
2577
2578 /* DB exceptions for our internal use must not cause vmexit */
2579 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2580 {
2581 unsigned long dr6;
2582
2583 /* if we're not singlestepping, it's not ours */
2584 if (!svm->nmi_singlestep)
2585 return NESTED_EXIT_DONE;
2586
2587 /* if it's not a singlestep exception, it's not ours */
2588 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2589 return NESTED_EXIT_DONE;
2590 if (!(dr6 & DR6_BS))
2591 return NESTED_EXIT_DONE;
2592
2593 /* if the guest is singlestepping, it should get the vmexit */
2594 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2595 disable_nmi_singlestep(svm);
2596 return NESTED_EXIT_DONE;
2597 }
2598
2599 /* it's ours, the nested hypervisor must not see this one */
2600 return NESTED_EXIT_HOST;
2601 }
2602
2603 static int nested_svm_exit_special(struct vcpu_svm *svm)
2604 {
2605 u32 exit_code = svm->vmcb->control.exit_code;
2606
2607 switch (exit_code) {
2608 case SVM_EXIT_INTR:
2609 case SVM_EXIT_NMI:
2610 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2611 return NESTED_EXIT_HOST;
2612 case SVM_EXIT_NPF:
2613 /* For now we are always handling NPFs when using them */
2614 if (npt_enabled)
2615 return NESTED_EXIT_HOST;
2616 break;
2617 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2618 /* When we're shadowing, trap PFs, but not async PF */
2619 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2620 return NESTED_EXIT_HOST;
2621 break;
2622 default:
2623 break;
2624 }
2625
2626 return NESTED_EXIT_CONTINUE;
2627 }
2628
2629 /*
2630 * If this function returns true, this #vmexit was already handled
2631 */
2632 static int nested_svm_intercept(struct vcpu_svm *svm)
2633 {
2634 u32 exit_code = svm->vmcb->control.exit_code;
2635 int vmexit = NESTED_EXIT_HOST;
2636
2637 switch (exit_code) {
2638 case SVM_EXIT_MSR:
2639 vmexit = nested_svm_exit_handled_msr(svm);
2640 break;
2641 case SVM_EXIT_IOIO:
2642 vmexit = nested_svm_intercept_ioio(svm);
2643 break;
2644 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2645 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2646 if (svm->nested.intercept_cr & bit)
2647 vmexit = NESTED_EXIT_DONE;
2648 break;
2649 }
2650 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2651 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2652 if (svm->nested.intercept_dr & bit)
2653 vmexit = NESTED_EXIT_DONE;
2654 break;
2655 }
2656 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2657 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2658 if (svm->nested.intercept_exceptions & excp_bits) {
2659 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2660 vmexit = nested_svm_intercept_db(svm);
2661 else
2662 vmexit = NESTED_EXIT_DONE;
2663 }
2664 /* async page fault always cause vmexit */
2665 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2666 svm->vcpu.arch.exception.nested_apf != 0)
2667 vmexit = NESTED_EXIT_DONE;
2668 break;
2669 }
2670 case SVM_EXIT_ERR: {
2671 vmexit = NESTED_EXIT_DONE;
2672 break;
2673 }
2674 default: {
2675 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2676 if (svm->nested.intercept & exit_bits)
2677 vmexit = NESTED_EXIT_DONE;
2678 }
2679 }
2680
2681 return vmexit;
2682 }
2683
2684 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2685 {
2686 int vmexit;
2687
2688 vmexit = nested_svm_intercept(svm);
2689
2690 if (vmexit == NESTED_EXIT_DONE)
2691 nested_svm_vmexit(svm);
2692
2693 return vmexit;
2694 }
2695
2696 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2697 {
2698 struct vmcb_control_area *dst = &dst_vmcb->control;
2699 struct vmcb_control_area *from = &from_vmcb->control;
2700
2701 dst->intercept_cr = from->intercept_cr;
2702 dst->intercept_dr = from->intercept_dr;
2703 dst->intercept_exceptions = from->intercept_exceptions;
2704 dst->intercept = from->intercept;
2705 dst->iopm_base_pa = from->iopm_base_pa;
2706 dst->msrpm_base_pa = from->msrpm_base_pa;
2707 dst->tsc_offset = from->tsc_offset;
2708 dst->asid = from->asid;
2709 dst->tlb_ctl = from->tlb_ctl;
2710 dst->int_ctl = from->int_ctl;
2711 dst->int_vector = from->int_vector;
2712 dst->int_state = from->int_state;
2713 dst->exit_code = from->exit_code;
2714 dst->exit_code_hi = from->exit_code_hi;
2715 dst->exit_info_1 = from->exit_info_1;
2716 dst->exit_info_2 = from->exit_info_2;
2717 dst->exit_int_info = from->exit_int_info;
2718 dst->exit_int_info_err = from->exit_int_info_err;
2719 dst->nested_ctl = from->nested_ctl;
2720 dst->event_inj = from->event_inj;
2721 dst->event_inj_err = from->event_inj_err;
2722 dst->nested_cr3 = from->nested_cr3;
2723 dst->virt_ext = from->virt_ext;
2724 }
2725
2726 static int nested_svm_vmexit(struct vcpu_svm *svm)
2727 {
2728 struct vmcb *nested_vmcb;
2729 struct vmcb *hsave = svm->nested.hsave;
2730 struct vmcb *vmcb = svm->vmcb;
2731 struct page *page;
2732
2733 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2734 vmcb->control.exit_info_1,
2735 vmcb->control.exit_info_2,
2736 vmcb->control.exit_int_info,
2737 vmcb->control.exit_int_info_err,
2738 KVM_ISA_SVM);
2739
2740 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2741 if (!nested_vmcb)
2742 return 1;
2743
2744 /* Exit Guest-Mode */
2745 leave_guest_mode(&svm->vcpu);
2746 svm->nested.vmcb = 0;
2747
2748 /* Give the current vmcb to the guest */
2749 disable_gif(svm);
2750
2751 nested_vmcb->save.es = vmcb->save.es;
2752 nested_vmcb->save.cs = vmcb->save.cs;
2753 nested_vmcb->save.ss = vmcb->save.ss;
2754 nested_vmcb->save.ds = vmcb->save.ds;
2755 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2756 nested_vmcb->save.idtr = vmcb->save.idtr;
2757 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2758 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2759 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2760 nested_vmcb->save.cr2 = vmcb->save.cr2;
2761 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2762 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2763 nested_vmcb->save.rip = vmcb->save.rip;
2764 nested_vmcb->save.rsp = vmcb->save.rsp;
2765 nested_vmcb->save.rax = vmcb->save.rax;
2766 nested_vmcb->save.dr7 = vmcb->save.dr7;
2767 nested_vmcb->save.dr6 = vmcb->save.dr6;
2768 nested_vmcb->save.cpl = vmcb->save.cpl;
2769
2770 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2771 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2772 nested_vmcb->control.int_state = vmcb->control.int_state;
2773 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2774 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2775 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2776 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2777 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2778 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2779
2780 if (svm->nrips_enabled)
2781 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2782
2783 /*
2784 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2785 * to make sure that we do not lose injected events. So check event_inj
2786 * here and copy it to exit_int_info if it is valid.
2787 * Exit_int_info and event_inj can't be both valid because the case
2788 * below only happens on a VMRUN instruction intercept which has
2789 * no valid exit_int_info set.
2790 */
2791 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2792 struct vmcb_control_area *nc = &nested_vmcb->control;
2793
2794 nc->exit_int_info = vmcb->control.event_inj;
2795 nc->exit_int_info_err = vmcb->control.event_inj_err;
2796 }
2797
2798 nested_vmcb->control.tlb_ctl = 0;
2799 nested_vmcb->control.event_inj = 0;
2800 nested_vmcb->control.event_inj_err = 0;
2801
2802 /* We always set V_INTR_MASKING and remember the old value in hflags */
2803 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2804 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2805
2806 /* Restore the original control entries */
2807 copy_vmcb_control_area(vmcb, hsave);
2808
2809 kvm_clear_exception_queue(&svm->vcpu);
2810 kvm_clear_interrupt_queue(&svm->vcpu);
2811
2812 svm->nested.nested_cr3 = 0;
2813
2814 /* Restore selected save entries */
2815 svm->vmcb->save.es = hsave->save.es;
2816 svm->vmcb->save.cs = hsave->save.cs;
2817 svm->vmcb->save.ss = hsave->save.ss;
2818 svm->vmcb->save.ds = hsave->save.ds;
2819 svm->vmcb->save.gdtr = hsave->save.gdtr;
2820 svm->vmcb->save.idtr = hsave->save.idtr;
2821 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2822 svm_set_efer(&svm->vcpu, hsave->save.efer);
2823 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2824 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2825 if (npt_enabled) {
2826 svm->vmcb->save.cr3 = hsave->save.cr3;
2827 svm->vcpu.arch.cr3 = hsave->save.cr3;
2828 } else {
2829 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2830 }
2831 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2832 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2833 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2834 svm->vmcb->save.dr7 = 0;
2835 svm->vmcb->save.cpl = 0;
2836 svm->vmcb->control.exit_int_info = 0;
2837
2838 mark_all_dirty(svm->vmcb);
2839
2840 nested_svm_unmap(page);
2841
2842 nested_svm_uninit_mmu_context(&svm->vcpu);
2843 kvm_mmu_reset_context(&svm->vcpu);
2844 kvm_mmu_load(&svm->vcpu);
2845
2846 return 0;
2847 }
2848
2849 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2850 {
2851 /*
2852 * This function merges the msr permission bitmaps of kvm and the
2853 * nested vmcb. It is optimized in that it only merges the parts where
2854 * the kvm msr permission bitmap may contain zero bits
2855 */
2856 int i;
2857
2858 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2859 return true;
2860
2861 for (i = 0; i < MSRPM_OFFSETS; i++) {
2862 u32 value, p;
2863 u64 offset;
2864
2865 if (msrpm_offsets[i] == 0xffffffff)
2866 break;
2867
2868 p = msrpm_offsets[i];
2869 offset = svm->nested.vmcb_msrpm + (p * 4);
2870
2871 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2872 return false;
2873
2874 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2875 }
2876
2877 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2878
2879 return true;
2880 }
2881
2882 static bool nested_vmcb_checks(struct vmcb *vmcb)
2883 {
2884 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2885 return false;
2886
2887 if (vmcb->control.asid == 0)
2888 return false;
2889
2890 if (vmcb->control.nested_ctl && !npt_enabled)
2891 return false;
2892
2893 return true;
2894 }
2895
2896 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2897 {
2898 struct vmcb *nested_vmcb;
2899 struct vmcb *hsave = svm->nested.hsave;
2900 struct vmcb *vmcb = svm->vmcb;
2901 struct page *page;
2902 u64 vmcb_gpa;
2903
2904 vmcb_gpa = svm->vmcb->save.rax;
2905
2906 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2907 if (!nested_vmcb)
2908 return false;
2909
2910 if (!nested_vmcb_checks(nested_vmcb)) {
2911 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2912 nested_vmcb->control.exit_code_hi = 0;
2913 nested_vmcb->control.exit_info_1 = 0;
2914 nested_vmcb->control.exit_info_2 = 0;
2915
2916 nested_svm_unmap(page);
2917
2918 return false;
2919 }
2920
2921 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2922 nested_vmcb->save.rip,
2923 nested_vmcb->control.int_ctl,
2924 nested_vmcb->control.event_inj,
2925 nested_vmcb->control.nested_ctl);
2926
2927 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2928 nested_vmcb->control.intercept_cr >> 16,
2929 nested_vmcb->control.intercept_exceptions,
2930 nested_vmcb->control.intercept);
2931
2932 /* Clear internal status */
2933 kvm_clear_exception_queue(&svm->vcpu);
2934 kvm_clear_interrupt_queue(&svm->vcpu);
2935
2936 /*
2937 * Save the old vmcb, so we don't need to pick what we save, but can
2938 * restore everything when a VMEXIT occurs
2939 */
2940 hsave->save.es = vmcb->save.es;
2941 hsave->save.cs = vmcb->save.cs;
2942 hsave->save.ss = vmcb->save.ss;
2943 hsave->save.ds = vmcb->save.ds;
2944 hsave->save.gdtr = vmcb->save.gdtr;
2945 hsave->save.idtr = vmcb->save.idtr;
2946 hsave->save.efer = svm->vcpu.arch.efer;
2947 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2948 hsave->save.cr4 = svm->vcpu.arch.cr4;
2949 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2950 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2951 hsave->save.rsp = vmcb->save.rsp;
2952 hsave->save.rax = vmcb->save.rax;
2953 if (npt_enabled)
2954 hsave->save.cr3 = vmcb->save.cr3;
2955 else
2956 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2957
2958 copy_vmcb_control_area(hsave, vmcb);
2959
2960 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2961 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2962 else
2963 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2964
2965 if (nested_vmcb->control.nested_ctl) {
2966 kvm_mmu_unload(&svm->vcpu);
2967 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2968 nested_svm_init_mmu_context(&svm->vcpu);
2969 }
2970
2971 /* Load the nested guest state */
2972 svm->vmcb->save.es = nested_vmcb->save.es;
2973 svm->vmcb->save.cs = nested_vmcb->save.cs;
2974 svm->vmcb->save.ss = nested_vmcb->save.ss;
2975 svm->vmcb->save.ds = nested_vmcb->save.ds;
2976 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2977 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2978 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2979 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2980 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2981 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2982 if (npt_enabled) {
2983 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2984 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2985 } else
2986 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2987
2988 /* Guest paging mode is active - reset mmu */
2989 kvm_mmu_reset_context(&svm->vcpu);
2990
2991 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2992 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2993 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2994 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2995
2996 /* In case we don't even reach vcpu_run, the fields are not updated */
2997 svm->vmcb->save.rax = nested_vmcb->save.rax;
2998 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2999 svm->vmcb->save.rip = nested_vmcb->save.rip;
3000 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3001 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3002 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3003
3004 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3005 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3006
3007 /* cache intercepts */
3008 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3009 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3010 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3011 svm->nested.intercept = nested_vmcb->control.intercept;
3012
3013 svm_flush_tlb(&svm->vcpu);
3014 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3015 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3016 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3017 else
3018 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3019
3020 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3021 /* We only want the cr8 intercept bits of the guest */
3022 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3023 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3024 }
3025
3026 /* We don't want to see VMMCALLs from a nested guest */
3027 clr_intercept(svm, INTERCEPT_VMMCALL);
3028
3029 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3030 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3031 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3032 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3033 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3034 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3035
3036 nested_svm_unmap(page);
3037
3038 /* Enter Guest-Mode */
3039 enter_guest_mode(&svm->vcpu);
3040
3041 /*
3042 * Merge guest and host intercepts - must be called with vcpu in
3043 * guest-mode to take affect here
3044 */
3045 recalc_intercepts(svm);
3046
3047 svm->nested.vmcb = vmcb_gpa;
3048
3049 enable_gif(svm);
3050
3051 mark_all_dirty(svm->vmcb);
3052
3053 return true;
3054 }
3055
3056 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3057 {
3058 to_vmcb->save.fs = from_vmcb->save.fs;
3059 to_vmcb->save.gs = from_vmcb->save.gs;
3060 to_vmcb->save.tr = from_vmcb->save.tr;
3061 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3062 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3063 to_vmcb->save.star = from_vmcb->save.star;
3064 to_vmcb->save.lstar = from_vmcb->save.lstar;
3065 to_vmcb->save.cstar = from_vmcb->save.cstar;
3066 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3067 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3068 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3069 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3070 }
3071
3072 static int vmload_interception(struct vcpu_svm *svm)
3073 {
3074 struct vmcb *nested_vmcb;
3075 struct page *page;
3076 int ret;
3077
3078 if (nested_svm_check_permissions(svm))
3079 return 1;
3080
3081 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3082 if (!nested_vmcb)
3083 return 1;
3084
3085 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3086 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3087
3088 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3089 nested_svm_unmap(page);
3090
3091 return ret;
3092 }
3093
3094 static int vmsave_interception(struct vcpu_svm *svm)
3095 {
3096 struct vmcb *nested_vmcb;
3097 struct page *page;
3098 int ret;
3099
3100 if (nested_svm_check_permissions(svm))
3101 return 1;
3102
3103 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3104 if (!nested_vmcb)
3105 return 1;
3106
3107 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3108 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3109
3110 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3111 nested_svm_unmap(page);
3112
3113 return ret;
3114 }
3115
3116 static int vmrun_interception(struct vcpu_svm *svm)
3117 {
3118 if (nested_svm_check_permissions(svm))
3119 return 1;
3120
3121 /* Save rip after vmrun instruction */
3122 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3123
3124 if (!nested_svm_vmrun(svm))
3125 return 1;
3126
3127 if (!nested_svm_vmrun_msrpm(svm))
3128 goto failed;
3129
3130 return 1;
3131
3132 failed:
3133
3134 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3135 svm->vmcb->control.exit_code_hi = 0;
3136 svm->vmcb->control.exit_info_1 = 0;
3137 svm->vmcb->control.exit_info_2 = 0;
3138
3139 nested_svm_vmexit(svm);
3140
3141 return 1;
3142 }
3143
3144 static int stgi_interception(struct vcpu_svm *svm)
3145 {
3146 int ret;
3147
3148 if (nested_svm_check_permissions(svm))
3149 return 1;
3150
3151 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3152 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3153 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3154
3155 enable_gif(svm);
3156
3157 return ret;
3158 }
3159
3160 static int clgi_interception(struct vcpu_svm *svm)
3161 {
3162 int ret;
3163
3164 if (nested_svm_check_permissions(svm))
3165 return 1;
3166
3167 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3168 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3169
3170 disable_gif(svm);
3171
3172 /* After a CLGI no interrupts should come */
3173 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3174 svm_clear_vintr(svm);
3175 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3176 mark_dirty(svm->vmcb, VMCB_INTR);
3177 }
3178
3179 return ret;
3180 }
3181
3182 static int invlpga_interception(struct vcpu_svm *svm)
3183 {
3184 struct kvm_vcpu *vcpu = &svm->vcpu;
3185
3186 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3187 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3188
3189 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3190 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3191
3192 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3193 return kvm_skip_emulated_instruction(&svm->vcpu);
3194 }
3195
3196 static int skinit_interception(struct vcpu_svm *svm)
3197 {
3198 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3199
3200 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3201 return 1;
3202 }
3203
3204 static int wbinvd_interception(struct vcpu_svm *svm)
3205 {
3206 return kvm_emulate_wbinvd(&svm->vcpu);
3207 }
3208
3209 static int xsetbv_interception(struct vcpu_svm *svm)
3210 {
3211 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3212 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3213
3214 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3215 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3216 return kvm_skip_emulated_instruction(&svm->vcpu);
3217 }
3218
3219 return 1;
3220 }
3221
3222 static int task_switch_interception(struct vcpu_svm *svm)
3223 {
3224 u16 tss_selector;
3225 int reason;
3226 int int_type = svm->vmcb->control.exit_int_info &
3227 SVM_EXITINTINFO_TYPE_MASK;
3228 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3229 uint32_t type =
3230 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3231 uint32_t idt_v =
3232 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3233 bool has_error_code = false;
3234 u32 error_code = 0;
3235
3236 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3237
3238 if (svm->vmcb->control.exit_info_2 &
3239 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3240 reason = TASK_SWITCH_IRET;
3241 else if (svm->vmcb->control.exit_info_2 &
3242 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3243 reason = TASK_SWITCH_JMP;
3244 else if (idt_v)
3245 reason = TASK_SWITCH_GATE;
3246 else
3247 reason = TASK_SWITCH_CALL;
3248
3249 if (reason == TASK_SWITCH_GATE) {
3250 switch (type) {
3251 case SVM_EXITINTINFO_TYPE_NMI:
3252 svm->vcpu.arch.nmi_injected = false;
3253 break;
3254 case SVM_EXITINTINFO_TYPE_EXEPT:
3255 if (svm->vmcb->control.exit_info_2 &
3256 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3257 has_error_code = true;
3258 error_code =
3259 (u32)svm->vmcb->control.exit_info_2;
3260 }
3261 kvm_clear_exception_queue(&svm->vcpu);
3262 break;
3263 case SVM_EXITINTINFO_TYPE_INTR:
3264 kvm_clear_interrupt_queue(&svm->vcpu);
3265 break;
3266 default:
3267 break;
3268 }
3269 }
3270
3271 if (reason != TASK_SWITCH_GATE ||
3272 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3273 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3274 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3275 skip_emulated_instruction(&svm->vcpu);
3276
3277 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3278 int_vec = -1;
3279
3280 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3281 has_error_code, error_code) == EMULATE_FAIL) {
3282 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3283 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3284 svm->vcpu.run->internal.ndata = 0;
3285 return 0;
3286 }
3287 return 1;
3288 }
3289
3290 static int cpuid_interception(struct vcpu_svm *svm)
3291 {
3292 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3293 return kvm_emulate_cpuid(&svm->vcpu);
3294 }
3295
3296 static int iret_interception(struct vcpu_svm *svm)
3297 {
3298 ++svm->vcpu.stat.nmi_window_exits;
3299 clr_intercept(svm, INTERCEPT_IRET);
3300 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3301 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3302 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3303 return 1;
3304 }
3305
3306 static int invlpg_interception(struct vcpu_svm *svm)
3307 {
3308 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3309 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3310
3311 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3312 return kvm_skip_emulated_instruction(&svm->vcpu);
3313 }
3314
3315 static int emulate_on_interception(struct vcpu_svm *svm)
3316 {
3317 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3318 }
3319
3320 static int rdpmc_interception(struct vcpu_svm *svm)
3321 {
3322 int err;
3323
3324 if (!static_cpu_has(X86_FEATURE_NRIPS))
3325 return emulate_on_interception(svm);
3326
3327 err = kvm_rdpmc(&svm->vcpu);
3328 return kvm_complete_insn_gp(&svm->vcpu, err);
3329 }
3330
3331 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3332 unsigned long val)
3333 {
3334 unsigned long cr0 = svm->vcpu.arch.cr0;
3335 bool ret = false;
3336 u64 intercept;
3337
3338 intercept = svm->nested.intercept;
3339
3340 if (!is_guest_mode(&svm->vcpu) ||
3341 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3342 return false;
3343
3344 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3345 val &= ~SVM_CR0_SELECTIVE_MASK;
3346
3347 if (cr0 ^ val) {
3348 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3349 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3350 }
3351
3352 return ret;
3353 }
3354
3355 #define CR_VALID (1ULL << 63)
3356
3357 static int cr_interception(struct vcpu_svm *svm)
3358 {
3359 int reg, cr;
3360 unsigned long val;
3361 int err;
3362
3363 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3364 return emulate_on_interception(svm);
3365
3366 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3367 return emulate_on_interception(svm);
3368
3369 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3370 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3371 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3372 else
3373 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3374
3375 err = 0;
3376 if (cr >= 16) { /* mov to cr */
3377 cr -= 16;
3378 val = kvm_register_read(&svm->vcpu, reg);
3379 switch (cr) {
3380 case 0:
3381 if (!check_selective_cr0_intercepted(svm, val))
3382 err = kvm_set_cr0(&svm->vcpu, val);
3383 else
3384 return 1;
3385
3386 break;
3387 case 3:
3388 err = kvm_set_cr3(&svm->vcpu, val);
3389 break;
3390 case 4:
3391 err = kvm_set_cr4(&svm->vcpu, val);
3392 break;
3393 case 8:
3394 err = kvm_set_cr8(&svm->vcpu, val);
3395 break;
3396 default:
3397 WARN(1, "unhandled write to CR%d", cr);
3398 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3399 return 1;
3400 }
3401 } else { /* mov from cr */
3402 switch (cr) {
3403 case 0:
3404 val = kvm_read_cr0(&svm->vcpu);
3405 break;
3406 case 2:
3407 val = svm->vcpu.arch.cr2;
3408 break;
3409 case 3:
3410 val = kvm_read_cr3(&svm->vcpu);
3411 break;
3412 case 4:
3413 val = kvm_read_cr4(&svm->vcpu);
3414 break;
3415 case 8:
3416 val = kvm_get_cr8(&svm->vcpu);
3417 break;
3418 default:
3419 WARN(1, "unhandled read from CR%d", cr);
3420 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3421 return 1;
3422 }
3423 kvm_register_write(&svm->vcpu, reg, val);
3424 }
3425 return kvm_complete_insn_gp(&svm->vcpu, err);
3426 }
3427
3428 static int dr_interception(struct vcpu_svm *svm)
3429 {
3430 int reg, dr;
3431 unsigned long val;
3432
3433 if (svm->vcpu.guest_debug == 0) {
3434 /*
3435 * No more DR vmexits; force a reload of the debug registers
3436 * and reenter on this instruction. The next vmexit will
3437 * retrieve the full state of the debug registers.
3438 */
3439 clr_dr_intercepts(svm);
3440 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3441 return 1;
3442 }
3443
3444 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3445 return emulate_on_interception(svm);
3446
3447 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3448 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3449
3450 if (dr >= 16) { /* mov to DRn */
3451 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3452 return 1;
3453 val = kvm_register_read(&svm->vcpu, reg);
3454 kvm_set_dr(&svm->vcpu, dr - 16, val);
3455 } else {
3456 if (!kvm_require_dr(&svm->vcpu, dr))
3457 return 1;
3458 kvm_get_dr(&svm->vcpu, dr, &val);
3459 kvm_register_write(&svm->vcpu, reg, val);
3460 }
3461
3462 return kvm_skip_emulated_instruction(&svm->vcpu);
3463 }
3464
3465 static int cr8_write_interception(struct vcpu_svm *svm)
3466 {
3467 struct kvm_run *kvm_run = svm->vcpu.run;
3468 int r;
3469
3470 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3471 /* instruction emulation calls kvm_set_cr8() */
3472 r = cr_interception(svm);
3473 if (lapic_in_kernel(&svm->vcpu))
3474 return r;
3475 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3476 return r;
3477 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3478 return 0;
3479 }
3480
3481 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3482 {
3483 struct vcpu_svm *svm = to_svm(vcpu);
3484
3485 switch (msr_info->index) {
3486 case MSR_IA32_TSC: {
3487 msr_info->data = svm->vmcb->control.tsc_offset +
3488 kvm_scale_tsc(vcpu, rdtsc());
3489
3490 break;
3491 }
3492 case MSR_STAR:
3493 msr_info->data = svm->vmcb->save.star;
3494 break;
3495 #ifdef CONFIG_X86_64
3496 case MSR_LSTAR:
3497 msr_info->data = svm->vmcb->save.lstar;
3498 break;
3499 case MSR_CSTAR:
3500 msr_info->data = svm->vmcb->save.cstar;
3501 break;
3502 case MSR_KERNEL_GS_BASE:
3503 msr_info->data = svm->vmcb->save.kernel_gs_base;
3504 break;
3505 case MSR_SYSCALL_MASK:
3506 msr_info->data = svm->vmcb->save.sfmask;
3507 break;
3508 #endif
3509 case MSR_IA32_SYSENTER_CS:
3510 msr_info->data = svm->vmcb->save.sysenter_cs;
3511 break;
3512 case MSR_IA32_SYSENTER_EIP:
3513 msr_info->data = svm->sysenter_eip;
3514 break;
3515 case MSR_IA32_SYSENTER_ESP:
3516 msr_info->data = svm->sysenter_esp;
3517 break;
3518 case MSR_TSC_AUX:
3519 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3520 return 1;
3521 msr_info->data = svm->tsc_aux;
3522 break;
3523 /*
3524 * Nobody will change the following 5 values in the VMCB so we can
3525 * safely return them on rdmsr. They will always be 0 until LBRV is
3526 * implemented.
3527 */
3528 case MSR_IA32_DEBUGCTLMSR:
3529 msr_info->data = svm->vmcb->save.dbgctl;
3530 break;
3531 case MSR_IA32_LASTBRANCHFROMIP:
3532 msr_info->data = svm->vmcb->save.br_from;
3533 break;
3534 case MSR_IA32_LASTBRANCHTOIP:
3535 msr_info->data = svm->vmcb->save.br_to;
3536 break;
3537 case MSR_IA32_LASTINTFROMIP:
3538 msr_info->data = svm->vmcb->save.last_excp_from;
3539 break;
3540 case MSR_IA32_LASTINTTOIP:
3541 msr_info->data = svm->vmcb->save.last_excp_to;
3542 break;
3543 case MSR_VM_HSAVE_PA:
3544 msr_info->data = svm->nested.hsave_msr;
3545 break;
3546 case MSR_VM_CR:
3547 msr_info->data = svm->nested.vm_cr_msr;
3548 break;
3549 case MSR_IA32_UCODE_REV:
3550 msr_info->data = 0x01000065;
3551 break;
3552 case MSR_F15H_IC_CFG: {
3553
3554 int family, model;
3555
3556 family = guest_cpuid_family(vcpu);
3557 model = guest_cpuid_model(vcpu);
3558
3559 if (family < 0 || model < 0)
3560 return kvm_get_msr_common(vcpu, msr_info);
3561
3562 msr_info->data = 0;
3563
3564 if (family == 0x15 &&
3565 (model >= 0x2 && model < 0x20))
3566 msr_info->data = 0x1E;
3567 }
3568 break;
3569 default:
3570 return kvm_get_msr_common(vcpu, msr_info);
3571 }
3572 return 0;
3573 }
3574
3575 static int rdmsr_interception(struct vcpu_svm *svm)
3576 {
3577 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3578 struct msr_data msr_info;
3579
3580 msr_info.index = ecx;
3581 msr_info.host_initiated = false;
3582 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3583 trace_kvm_msr_read_ex(ecx);
3584 kvm_inject_gp(&svm->vcpu, 0);
3585 return 1;
3586 } else {
3587 trace_kvm_msr_read(ecx, msr_info.data);
3588
3589 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3590 msr_info.data & 0xffffffff);
3591 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3592 msr_info.data >> 32);
3593 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3594 return kvm_skip_emulated_instruction(&svm->vcpu);
3595 }
3596 }
3597
3598 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3599 {
3600 struct vcpu_svm *svm = to_svm(vcpu);
3601 int svm_dis, chg_mask;
3602
3603 if (data & ~SVM_VM_CR_VALID_MASK)
3604 return 1;
3605
3606 chg_mask = SVM_VM_CR_VALID_MASK;
3607
3608 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3609 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3610
3611 svm->nested.vm_cr_msr &= ~chg_mask;
3612 svm->nested.vm_cr_msr |= (data & chg_mask);
3613
3614 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3615
3616 /* check for svm_disable while efer.svme is set */
3617 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3618 return 1;
3619
3620 return 0;
3621 }
3622
3623 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3624 {
3625 struct vcpu_svm *svm = to_svm(vcpu);
3626
3627 u32 ecx = msr->index;
3628 u64 data = msr->data;
3629 switch (ecx) {
3630 case MSR_IA32_TSC:
3631 kvm_write_tsc(vcpu, msr);
3632 break;
3633 case MSR_STAR:
3634 svm->vmcb->save.star = data;
3635 break;
3636 #ifdef CONFIG_X86_64
3637 case MSR_LSTAR:
3638 svm->vmcb->save.lstar = data;
3639 break;
3640 case MSR_CSTAR:
3641 svm->vmcb->save.cstar = data;
3642 break;
3643 case MSR_KERNEL_GS_BASE:
3644 svm->vmcb->save.kernel_gs_base = data;
3645 break;
3646 case MSR_SYSCALL_MASK:
3647 svm->vmcb->save.sfmask = data;
3648 break;
3649 #endif
3650 case MSR_IA32_SYSENTER_CS:
3651 svm->vmcb->save.sysenter_cs = data;
3652 break;
3653 case MSR_IA32_SYSENTER_EIP:
3654 svm->sysenter_eip = data;
3655 svm->vmcb->save.sysenter_eip = data;
3656 break;
3657 case MSR_IA32_SYSENTER_ESP:
3658 svm->sysenter_esp = data;
3659 svm->vmcb->save.sysenter_esp = data;
3660 break;
3661 case MSR_TSC_AUX:
3662 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3663 return 1;
3664
3665 /*
3666 * This is rare, so we update the MSR here instead of using
3667 * direct_access_msrs. Doing that would require a rdmsr in
3668 * svm_vcpu_put.
3669 */
3670 svm->tsc_aux = data;
3671 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3672 break;
3673 case MSR_IA32_DEBUGCTLMSR:
3674 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3675 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3676 __func__, data);
3677 break;
3678 }
3679 if (data & DEBUGCTL_RESERVED_BITS)
3680 return 1;
3681
3682 svm->vmcb->save.dbgctl = data;
3683 mark_dirty(svm->vmcb, VMCB_LBR);
3684 if (data & (1ULL<<0))
3685 svm_enable_lbrv(svm);
3686 else
3687 svm_disable_lbrv(svm);
3688 break;
3689 case MSR_VM_HSAVE_PA:
3690 svm->nested.hsave_msr = data;
3691 break;
3692 case MSR_VM_CR:
3693 return svm_set_vm_cr(vcpu, data);
3694 case MSR_VM_IGNNE:
3695 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3696 break;
3697 case MSR_IA32_APICBASE:
3698 if (kvm_vcpu_apicv_active(vcpu))
3699 avic_update_vapic_bar(to_svm(vcpu), data);
3700 /* Follow through */
3701 default:
3702 return kvm_set_msr_common(vcpu, msr);
3703 }
3704 return 0;
3705 }
3706
3707 static int wrmsr_interception(struct vcpu_svm *svm)
3708 {
3709 struct msr_data msr;
3710 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3711 u64 data = kvm_read_edx_eax(&svm->vcpu);
3712
3713 msr.data = data;
3714 msr.index = ecx;
3715 msr.host_initiated = false;
3716
3717 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3718 if (kvm_set_msr(&svm->vcpu, &msr)) {
3719 trace_kvm_msr_write_ex(ecx, data);
3720 kvm_inject_gp(&svm->vcpu, 0);
3721 return 1;
3722 } else {
3723 trace_kvm_msr_write(ecx, data);
3724 return kvm_skip_emulated_instruction(&svm->vcpu);
3725 }
3726 }
3727
3728 static int msr_interception(struct vcpu_svm *svm)
3729 {
3730 if (svm->vmcb->control.exit_info_1)
3731 return wrmsr_interception(svm);
3732 else
3733 return rdmsr_interception(svm);
3734 }
3735
3736 static int interrupt_window_interception(struct vcpu_svm *svm)
3737 {
3738 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3739 svm_clear_vintr(svm);
3740 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3741 mark_dirty(svm->vmcb, VMCB_INTR);
3742 ++svm->vcpu.stat.irq_window_exits;
3743 return 1;
3744 }
3745
3746 static int pause_interception(struct vcpu_svm *svm)
3747 {
3748 kvm_vcpu_on_spin(&(svm->vcpu));
3749 return 1;
3750 }
3751
3752 static int nop_interception(struct vcpu_svm *svm)
3753 {
3754 return kvm_skip_emulated_instruction(&(svm->vcpu));
3755 }
3756
3757 static int monitor_interception(struct vcpu_svm *svm)
3758 {
3759 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3760 return nop_interception(svm);
3761 }
3762
3763 static int mwait_interception(struct vcpu_svm *svm)
3764 {
3765 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3766 return nop_interception(svm);
3767 }
3768
3769 enum avic_ipi_failure_cause {
3770 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3771 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3772 AVIC_IPI_FAILURE_INVALID_TARGET,
3773 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3774 };
3775
3776 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3777 {
3778 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3779 u32 icrl = svm->vmcb->control.exit_info_1;
3780 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3781 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3782 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3783
3784 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3785
3786 switch (id) {
3787 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3788 /*
3789 * AVIC hardware handles the generation of
3790 * IPIs when the specified Message Type is Fixed
3791 * (also known as fixed delivery mode) and
3792 * the Trigger Mode is edge-triggered. The hardware
3793 * also supports self and broadcast delivery modes
3794 * specified via the Destination Shorthand(DSH)
3795 * field of the ICRL. Logical and physical APIC ID
3796 * formats are supported. All other IPI types cause
3797 * a #VMEXIT, which needs to emulated.
3798 */
3799 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3800 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3801 break;
3802 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3803 int i;
3804 struct kvm_vcpu *vcpu;
3805 struct kvm *kvm = svm->vcpu.kvm;
3806 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3807
3808 /*
3809 * At this point, we expect that the AVIC HW has already
3810 * set the appropriate IRR bits on the valid target
3811 * vcpus. So, we just need to kick the appropriate vcpu.
3812 */
3813 kvm_for_each_vcpu(i, vcpu, kvm) {
3814 bool m = kvm_apic_match_dest(vcpu, apic,
3815 icrl & KVM_APIC_SHORT_MASK,
3816 GET_APIC_DEST_FIELD(icrh),
3817 icrl & KVM_APIC_DEST_MASK);
3818
3819 if (m && !avic_vcpu_is_running(vcpu))
3820 kvm_vcpu_wake_up(vcpu);
3821 }
3822 break;
3823 }
3824 case AVIC_IPI_FAILURE_INVALID_TARGET:
3825 break;
3826 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3827 WARN_ONCE(1, "Invalid backing page\n");
3828 break;
3829 default:
3830 pr_err("Unknown IPI interception\n");
3831 }
3832
3833 return 1;
3834 }
3835
3836 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3837 {
3838 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3839 int index;
3840 u32 *logical_apic_id_table;
3841 int dlid = GET_APIC_LOGICAL_ID(ldr);
3842
3843 if (!dlid)
3844 return NULL;
3845
3846 if (flat) { /* flat */
3847 index = ffs(dlid) - 1;
3848 if (index > 7)
3849 return NULL;
3850 } else { /* cluster */
3851 int cluster = (dlid & 0xf0) >> 4;
3852 int apic = ffs(dlid & 0x0f) - 1;
3853
3854 if ((apic < 0) || (apic > 7) ||
3855 (cluster >= 0xf))
3856 return NULL;
3857 index = (cluster << 2) + apic;
3858 }
3859
3860 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3861
3862 return &logical_apic_id_table[index];
3863 }
3864
3865 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3866 bool valid)
3867 {
3868 bool flat;
3869 u32 *entry, new_entry;
3870
3871 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3872 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3873 if (!entry)
3874 return -EINVAL;
3875
3876 new_entry = READ_ONCE(*entry);
3877 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3878 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3879 if (valid)
3880 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3881 else
3882 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3883 WRITE_ONCE(*entry, new_entry);
3884
3885 return 0;
3886 }
3887
3888 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3889 {
3890 int ret;
3891 struct vcpu_svm *svm = to_svm(vcpu);
3892 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3893
3894 if (!ldr)
3895 return 1;
3896
3897 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3898 if (ret && svm->ldr_reg) {
3899 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3900 svm->ldr_reg = 0;
3901 } else {
3902 svm->ldr_reg = ldr;
3903 }
3904 return ret;
3905 }
3906
3907 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3908 {
3909 u64 *old, *new;
3910 struct vcpu_svm *svm = to_svm(vcpu);
3911 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3912 u32 id = (apic_id_reg >> 24) & 0xff;
3913
3914 if (vcpu->vcpu_id == id)
3915 return 0;
3916
3917 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3918 new = avic_get_physical_id_entry(vcpu, id);
3919 if (!new || !old)
3920 return 1;
3921
3922 /* We need to move physical_id_entry to new offset */
3923 *new = *old;
3924 *old = 0ULL;
3925 to_svm(vcpu)->avic_physical_id_cache = new;
3926
3927 /*
3928 * Also update the guest physical APIC ID in the logical
3929 * APIC ID table entry if already setup the LDR.
3930 */
3931 if (svm->ldr_reg)
3932 avic_handle_ldr_update(vcpu);
3933
3934 return 0;
3935 }
3936
3937 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3938 {
3939 struct vcpu_svm *svm = to_svm(vcpu);
3940 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3941 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3942 u32 mod = (dfr >> 28) & 0xf;
3943
3944 /*
3945 * We assume that all local APICs are using the same type.
3946 * If this changes, we need to flush the AVIC logical
3947 * APID id table.
3948 */
3949 if (vm_data->ldr_mode == mod)
3950 return 0;
3951
3952 clear_page(page_address(vm_data->avic_logical_id_table_page));
3953 vm_data->ldr_mode = mod;
3954
3955 if (svm->ldr_reg)
3956 avic_handle_ldr_update(vcpu);
3957 return 0;
3958 }
3959
3960 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3961 {
3962 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3963 u32 offset = svm->vmcb->control.exit_info_1 &
3964 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3965
3966 switch (offset) {
3967 case APIC_ID:
3968 if (avic_handle_apic_id_update(&svm->vcpu))
3969 return 0;
3970 break;
3971 case APIC_LDR:
3972 if (avic_handle_ldr_update(&svm->vcpu))
3973 return 0;
3974 break;
3975 case APIC_DFR:
3976 avic_handle_dfr_update(&svm->vcpu);
3977 break;
3978 default:
3979 break;
3980 }
3981
3982 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3983
3984 return 1;
3985 }
3986
3987 static bool is_avic_unaccelerated_access_trap(u32 offset)
3988 {
3989 bool ret = false;
3990
3991 switch (offset) {
3992 case APIC_ID:
3993 case APIC_EOI:
3994 case APIC_RRR:
3995 case APIC_LDR:
3996 case APIC_DFR:
3997 case APIC_SPIV:
3998 case APIC_ESR:
3999 case APIC_ICR:
4000 case APIC_LVTT:
4001 case APIC_LVTTHMR:
4002 case APIC_LVTPC:
4003 case APIC_LVT0:
4004 case APIC_LVT1:
4005 case APIC_LVTERR:
4006 case APIC_TMICT:
4007 case APIC_TDCR:
4008 ret = true;
4009 break;
4010 default:
4011 break;
4012 }
4013 return ret;
4014 }
4015
4016 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4017 {
4018 int ret = 0;
4019 u32 offset = svm->vmcb->control.exit_info_1 &
4020 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4021 u32 vector = svm->vmcb->control.exit_info_2 &
4022 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4023 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4024 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4025 bool trap = is_avic_unaccelerated_access_trap(offset);
4026
4027 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4028 trap, write, vector);
4029 if (trap) {
4030 /* Handling Trap */
4031 WARN_ONCE(!write, "svm: Handling trap read.\n");
4032 ret = avic_unaccel_trap_write(svm);
4033 } else {
4034 /* Handling Fault */
4035 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4036 }
4037
4038 return ret;
4039 }
4040
4041 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4042 [SVM_EXIT_READ_CR0] = cr_interception,
4043 [SVM_EXIT_READ_CR3] = cr_interception,
4044 [SVM_EXIT_READ_CR4] = cr_interception,
4045 [SVM_EXIT_READ_CR8] = cr_interception,
4046 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4047 [SVM_EXIT_WRITE_CR0] = cr_interception,
4048 [SVM_EXIT_WRITE_CR3] = cr_interception,
4049 [SVM_EXIT_WRITE_CR4] = cr_interception,
4050 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4051 [SVM_EXIT_READ_DR0] = dr_interception,
4052 [SVM_EXIT_READ_DR1] = dr_interception,
4053 [SVM_EXIT_READ_DR2] = dr_interception,
4054 [SVM_EXIT_READ_DR3] = dr_interception,
4055 [SVM_EXIT_READ_DR4] = dr_interception,
4056 [SVM_EXIT_READ_DR5] = dr_interception,
4057 [SVM_EXIT_READ_DR6] = dr_interception,
4058 [SVM_EXIT_READ_DR7] = dr_interception,
4059 [SVM_EXIT_WRITE_DR0] = dr_interception,
4060 [SVM_EXIT_WRITE_DR1] = dr_interception,
4061 [SVM_EXIT_WRITE_DR2] = dr_interception,
4062 [SVM_EXIT_WRITE_DR3] = dr_interception,
4063 [SVM_EXIT_WRITE_DR4] = dr_interception,
4064 [SVM_EXIT_WRITE_DR5] = dr_interception,
4065 [SVM_EXIT_WRITE_DR6] = dr_interception,
4066 [SVM_EXIT_WRITE_DR7] = dr_interception,
4067 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4068 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4069 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4070 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4071 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4072 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4073 [SVM_EXIT_INTR] = intr_interception,
4074 [SVM_EXIT_NMI] = nmi_interception,
4075 [SVM_EXIT_SMI] = nop_on_interception,
4076 [SVM_EXIT_INIT] = nop_on_interception,
4077 [SVM_EXIT_VINTR] = interrupt_window_interception,
4078 [SVM_EXIT_RDPMC] = rdpmc_interception,
4079 [SVM_EXIT_CPUID] = cpuid_interception,
4080 [SVM_EXIT_IRET] = iret_interception,
4081 [SVM_EXIT_INVD] = emulate_on_interception,
4082 [SVM_EXIT_PAUSE] = pause_interception,
4083 [SVM_EXIT_HLT] = halt_interception,
4084 [SVM_EXIT_INVLPG] = invlpg_interception,
4085 [SVM_EXIT_INVLPGA] = invlpga_interception,
4086 [SVM_EXIT_IOIO] = io_interception,
4087 [SVM_EXIT_MSR] = msr_interception,
4088 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4089 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4090 [SVM_EXIT_VMRUN] = vmrun_interception,
4091 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4092 [SVM_EXIT_VMLOAD] = vmload_interception,
4093 [SVM_EXIT_VMSAVE] = vmsave_interception,
4094 [SVM_EXIT_STGI] = stgi_interception,
4095 [SVM_EXIT_CLGI] = clgi_interception,
4096 [SVM_EXIT_SKINIT] = skinit_interception,
4097 [SVM_EXIT_WBINVD] = wbinvd_interception,
4098 [SVM_EXIT_MONITOR] = monitor_interception,
4099 [SVM_EXIT_MWAIT] = mwait_interception,
4100 [SVM_EXIT_XSETBV] = xsetbv_interception,
4101 [SVM_EXIT_NPF] = pf_interception,
4102 [SVM_EXIT_RSM] = emulate_on_interception,
4103 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4104 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4105 };
4106
4107 static void dump_vmcb(struct kvm_vcpu *vcpu)
4108 {
4109 struct vcpu_svm *svm = to_svm(vcpu);
4110 struct vmcb_control_area *control = &svm->vmcb->control;
4111 struct vmcb_save_area *save = &svm->vmcb->save;
4112
4113 pr_err("VMCB Control Area:\n");
4114 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4115 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4116 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4117 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4118 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4119 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4120 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4121 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4122 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4123 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4124 pr_err("%-20s%d\n", "asid:", control->asid);
4125 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4126 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4127 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4128 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4129 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4130 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4131 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4132 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4133 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4134 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4135 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4136 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4137 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4138 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4139 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4140 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4141 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4142 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4143 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4144 pr_err("VMCB State Save Area:\n");
4145 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4146 "es:",
4147 save->es.selector, save->es.attrib,
4148 save->es.limit, save->es.base);
4149 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4150 "cs:",
4151 save->cs.selector, save->cs.attrib,
4152 save->cs.limit, save->cs.base);
4153 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4154 "ss:",
4155 save->ss.selector, save->ss.attrib,
4156 save->ss.limit, save->ss.base);
4157 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4158 "ds:",
4159 save->ds.selector, save->ds.attrib,
4160 save->ds.limit, save->ds.base);
4161 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4162 "fs:",
4163 save->fs.selector, save->fs.attrib,
4164 save->fs.limit, save->fs.base);
4165 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4166 "gs:",
4167 save->gs.selector, save->gs.attrib,
4168 save->gs.limit, save->gs.base);
4169 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4170 "gdtr:",
4171 save->gdtr.selector, save->gdtr.attrib,
4172 save->gdtr.limit, save->gdtr.base);
4173 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4174 "ldtr:",
4175 save->ldtr.selector, save->ldtr.attrib,
4176 save->ldtr.limit, save->ldtr.base);
4177 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4178 "idtr:",
4179 save->idtr.selector, save->idtr.attrib,
4180 save->idtr.limit, save->idtr.base);
4181 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4182 "tr:",
4183 save->tr.selector, save->tr.attrib,
4184 save->tr.limit, save->tr.base);
4185 pr_err("cpl: %d efer: %016llx\n",
4186 save->cpl, save->efer);
4187 pr_err("%-15s %016llx %-13s %016llx\n",
4188 "cr0:", save->cr0, "cr2:", save->cr2);
4189 pr_err("%-15s %016llx %-13s %016llx\n",
4190 "cr3:", save->cr3, "cr4:", save->cr4);
4191 pr_err("%-15s %016llx %-13s %016llx\n",
4192 "dr6:", save->dr6, "dr7:", save->dr7);
4193 pr_err("%-15s %016llx %-13s %016llx\n",
4194 "rip:", save->rip, "rflags:", save->rflags);
4195 pr_err("%-15s %016llx %-13s %016llx\n",
4196 "rsp:", save->rsp, "rax:", save->rax);
4197 pr_err("%-15s %016llx %-13s %016llx\n",
4198 "star:", save->star, "lstar:", save->lstar);
4199 pr_err("%-15s %016llx %-13s %016llx\n",
4200 "cstar:", save->cstar, "sfmask:", save->sfmask);
4201 pr_err("%-15s %016llx %-13s %016llx\n",
4202 "kernel_gs_base:", save->kernel_gs_base,
4203 "sysenter_cs:", save->sysenter_cs);
4204 pr_err("%-15s %016llx %-13s %016llx\n",
4205 "sysenter_esp:", save->sysenter_esp,
4206 "sysenter_eip:", save->sysenter_eip);
4207 pr_err("%-15s %016llx %-13s %016llx\n",
4208 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4209 pr_err("%-15s %016llx %-13s %016llx\n",
4210 "br_from:", save->br_from, "br_to:", save->br_to);
4211 pr_err("%-15s %016llx %-13s %016llx\n",
4212 "excp_from:", save->last_excp_from,
4213 "excp_to:", save->last_excp_to);
4214 }
4215
4216 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4217 {
4218 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4219
4220 *info1 = control->exit_info_1;
4221 *info2 = control->exit_info_2;
4222 }
4223
4224 static int handle_exit(struct kvm_vcpu *vcpu)
4225 {
4226 struct vcpu_svm *svm = to_svm(vcpu);
4227 struct kvm_run *kvm_run = vcpu->run;
4228 u32 exit_code = svm->vmcb->control.exit_code;
4229
4230 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4231
4232 vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4233
4234 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4235 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4236 if (npt_enabled)
4237 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4238
4239 if (unlikely(svm->nested.exit_required)) {
4240 nested_svm_vmexit(svm);
4241 svm->nested.exit_required = false;
4242
4243 return 1;
4244 }
4245
4246 if (is_guest_mode(vcpu)) {
4247 int vmexit;
4248
4249 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4250 svm->vmcb->control.exit_info_1,
4251 svm->vmcb->control.exit_info_2,
4252 svm->vmcb->control.exit_int_info,
4253 svm->vmcb->control.exit_int_info_err,
4254 KVM_ISA_SVM);
4255
4256 vmexit = nested_svm_exit_special(svm);
4257
4258 if (vmexit == NESTED_EXIT_CONTINUE)
4259 vmexit = nested_svm_exit_handled(svm);
4260
4261 if (vmexit == NESTED_EXIT_DONE)
4262 return 1;
4263 }
4264
4265 svm_complete_interrupts(svm);
4266
4267 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4268 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4269 kvm_run->fail_entry.hardware_entry_failure_reason
4270 = svm->vmcb->control.exit_code;
4271 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4272 dump_vmcb(vcpu);
4273 return 0;
4274 }
4275
4276 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4277 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4278 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4279 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4280 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4281 "exit_code 0x%x\n",
4282 __func__, svm->vmcb->control.exit_int_info,
4283 exit_code);
4284
4285 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4286 || !svm_exit_handlers[exit_code]) {
4287 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4288 kvm_queue_exception(vcpu, UD_VECTOR);
4289 return 1;
4290 }
4291
4292 return svm_exit_handlers[exit_code](svm);
4293 }
4294
4295 static void reload_tss(struct kvm_vcpu *vcpu)
4296 {
4297 int cpu = raw_smp_processor_id();
4298
4299 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4300 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4301 load_TR_desc();
4302 }
4303
4304 static void pre_svm_run(struct vcpu_svm *svm)
4305 {
4306 int cpu = raw_smp_processor_id();
4307
4308 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4309
4310 /* FIXME: handle wraparound of asid_generation */
4311 if (svm->asid_generation != sd->asid_generation)
4312 new_asid(svm, sd);
4313 }
4314
4315 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4316 {
4317 struct vcpu_svm *svm = to_svm(vcpu);
4318
4319 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4320 vcpu->arch.hflags |= HF_NMI_MASK;
4321 set_intercept(svm, INTERCEPT_IRET);
4322 ++vcpu->stat.nmi_injections;
4323 }
4324
4325 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4326 {
4327 struct vmcb_control_area *control;
4328
4329 /* The following fields are ignored when AVIC is enabled */
4330 control = &svm->vmcb->control;
4331 control->int_vector = irq;
4332 control->int_ctl &= ~V_INTR_PRIO_MASK;
4333 control->int_ctl |= V_IRQ_MASK |
4334 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4335 mark_dirty(svm->vmcb, VMCB_INTR);
4336 }
4337
4338 static void svm_set_irq(struct kvm_vcpu *vcpu)
4339 {
4340 struct vcpu_svm *svm = to_svm(vcpu);
4341
4342 BUG_ON(!(gif_set(svm)));
4343
4344 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4345 ++vcpu->stat.irq_injections;
4346
4347 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4348 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4349 }
4350
4351 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4352 {
4353 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4354 }
4355
4356 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4357 {
4358 struct vcpu_svm *svm = to_svm(vcpu);
4359
4360 if (svm_nested_virtualize_tpr(vcpu) ||
4361 kvm_vcpu_apicv_active(vcpu))
4362 return;
4363
4364 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4365
4366 if (irr == -1)
4367 return;
4368
4369 if (tpr >= irr)
4370 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4371 }
4372
4373 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4374 {
4375 return;
4376 }
4377
4378 static bool svm_get_enable_apicv(void)
4379 {
4380 return avic;
4381 }
4382
4383 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4384 {
4385 }
4386
4387 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4388 {
4389 }
4390
4391 /* Note: Currently only used by Hyper-V. */
4392 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4393 {
4394 struct vcpu_svm *svm = to_svm(vcpu);
4395 struct vmcb *vmcb = svm->vmcb;
4396
4397 if (!avic)
4398 return;
4399
4400 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4401 mark_dirty(vmcb, VMCB_INTR);
4402 }
4403
4404 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4405 {
4406 return;
4407 }
4408
4409 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4410 {
4411 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4412 smp_mb__after_atomic();
4413
4414 if (avic_vcpu_is_running(vcpu))
4415 wrmsrl(SVM_AVIC_DOORBELL,
4416 kvm_cpu_get_apicid(vcpu->cpu));
4417 else
4418 kvm_vcpu_wake_up(vcpu);
4419 }
4420
4421 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4422 {
4423 unsigned long flags;
4424 struct amd_svm_iommu_ir *cur;
4425
4426 spin_lock_irqsave(&svm->ir_list_lock, flags);
4427 list_for_each_entry(cur, &svm->ir_list, node) {
4428 if (cur->data != pi->ir_data)
4429 continue;
4430 list_del(&cur->node);
4431 kfree(cur);
4432 break;
4433 }
4434 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4435 }
4436
4437 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4438 {
4439 int ret = 0;
4440 unsigned long flags;
4441 struct amd_svm_iommu_ir *ir;
4442
4443 /**
4444 * In some cases, the existing irte is updaed and re-set,
4445 * so we need to check here if it's already been * added
4446 * to the ir_list.
4447 */
4448 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4449 struct kvm *kvm = svm->vcpu.kvm;
4450 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4451 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4452 struct vcpu_svm *prev_svm;
4453
4454 if (!prev_vcpu) {
4455 ret = -EINVAL;
4456 goto out;
4457 }
4458
4459 prev_svm = to_svm(prev_vcpu);
4460 svm_ir_list_del(prev_svm, pi);
4461 }
4462
4463 /**
4464 * Allocating new amd_iommu_pi_data, which will get
4465 * add to the per-vcpu ir_list.
4466 */
4467 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4468 if (!ir) {
4469 ret = -ENOMEM;
4470 goto out;
4471 }
4472 ir->data = pi->ir_data;
4473
4474 spin_lock_irqsave(&svm->ir_list_lock, flags);
4475 list_add(&ir->node, &svm->ir_list);
4476 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4477 out:
4478 return ret;
4479 }
4480
4481 /**
4482 * Note:
4483 * The HW cannot support posting multicast/broadcast
4484 * interrupts to a vCPU. So, we still use legacy interrupt
4485 * remapping for these kind of interrupts.
4486 *
4487 * For lowest-priority interrupts, we only support
4488 * those with single CPU as the destination, e.g. user
4489 * configures the interrupts via /proc/irq or uses
4490 * irqbalance to make the interrupts single-CPU.
4491 */
4492 static int
4493 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4494 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4495 {
4496 struct kvm_lapic_irq irq;
4497 struct kvm_vcpu *vcpu = NULL;
4498
4499 kvm_set_msi_irq(kvm, e, &irq);
4500
4501 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4502 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4503 __func__, irq.vector);
4504 return -1;
4505 }
4506
4507 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4508 irq.vector);
4509 *svm = to_svm(vcpu);
4510 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4511 vcpu_info->vector = irq.vector;
4512
4513 return 0;
4514 }
4515
4516 /*
4517 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4518 *
4519 * @kvm: kvm
4520 * @host_irq: host irq of the interrupt
4521 * @guest_irq: gsi of the interrupt
4522 * @set: set or unset PI
4523 * returns 0 on success, < 0 on failure
4524 */
4525 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4526 uint32_t guest_irq, bool set)
4527 {
4528 struct kvm_kernel_irq_routing_entry *e;
4529 struct kvm_irq_routing_table *irq_rt;
4530 int idx, ret = -EINVAL;
4531
4532 if (!kvm_arch_has_assigned_device(kvm) ||
4533 !irq_remapping_cap(IRQ_POSTING_CAP))
4534 return 0;
4535
4536 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4537 __func__, host_irq, guest_irq, set);
4538
4539 idx = srcu_read_lock(&kvm->irq_srcu);
4540 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4541 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4542
4543 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4544 struct vcpu_data vcpu_info;
4545 struct vcpu_svm *svm = NULL;
4546
4547 if (e->type != KVM_IRQ_ROUTING_MSI)
4548 continue;
4549
4550 /**
4551 * Here, we setup with legacy mode in the following cases:
4552 * 1. When cannot target interrupt to a specific vcpu.
4553 * 2. Unsetting posted interrupt.
4554 * 3. APIC virtialization is disabled for the vcpu.
4555 */
4556 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4557 kvm_vcpu_apicv_active(&svm->vcpu)) {
4558 struct amd_iommu_pi_data pi;
4559
4560 /* Try to enable guest_mode in IRTE */
4561 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4562 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4563 svm->vcpu.vcpu_id);
4564 pi.is_guest_mode = true;
4565 pi.vcpu_data = &vcpu_info;
4566 ret = irq_set_vcpu_affinity(host_irq, &pi);
4567
4568 /**
4569 * Here, we successfully setting up vcpu affinity in
4570 * IOMMU guest mode. Now, we need to store the posted
4571 * interrupt information in a per-vcpu ir_list so that
4572 * we can reference to them directly when we update vcpu
4573 * scheduling information in IOMMU irte.
4574 */
4575 if (!ret && pi.is_guest_mode)
4576 svm_ir_list_add(svm, &pi);
4577 } else {
4578 /* Use legacy mode in IRTE */
4579 struct amd_iommu_pi_data pi;
4580
4581 /**
4582 * Here, pi is used to:
4583 * - Tell IOMMU to use legacy mode for this interrupt.
4584 * - Retrieve ga_tag of prior interrupt remapping data.
4585 */
4586 pi.is_guest_mode = false;
4587 ret = irq_set_vcpu_affinity(host_irq, &pi);
4588
4589 /**
4590 * Check if the posted interrupt was previously
4591 * setup with the guest_mode by checking if the ga_tag
4592 * was cached. If so, we need to clean up the per-vcpu
4593 * ir_list.
4594 */
4595 if (!ret && pi.prev_ga_tag) {
4596 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4597 struct kvm_vcpu *vcpu;
4598
4599 vcpu = kvm_get_vcpu_by_id(kvm, id);
4600 if (vcpu)
4601 svm_ir_list_del(to_svm(vcpu), &pi);
4602 }
4603 }
4604
4605 if (!ret && svm) {
4606 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4607 host_irq, e->gsi,
4608 vcpu_info.vector,
4609 vcpu_info.pi_desc_addr, set);
4610 }
4611
4612 if (ret < 0) {
4613 pr_err("%s: failed to update PI IRTE\n", __func__);
4614 goto out;
4615 }
4616 }
4617
4618 ret = 0;
4619 out:
4620 srcu_read_unlock(&kvm->irq_srcu, idx);
4621 return ret;
4622 }
4623
4624 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4625 {
4626 struct vcpu_svm *svm = to_svm(vcpu);
4627 struct vmcb *vmcb = svm->vmcb;
4628 int ret;
4629 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4630 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4631 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4632
4633 return ret;
4634 }
4635
4636 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4637 {
4638 struct vcpu_svm *svm = to_svm(vcpu);
4639
4640 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4641 }
4642
4643 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4644 {
4645 struct vcpu_svm *svm = to_svm(vcpu);
4646
4647 if (masked) {
4648 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4649 set_intercept(svm, INTERCEPT_IRET);
4650 } else {
4651 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4652 clr_intercept(svm, INTERCEPT_IRET);
4653 }
4654 }
4655
4656 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4657 {
4658 struct vcpu_svm *svm = to_svm(vcpu);
4659 struct vmcb *vmcb = svm->vmcb;
4660 int ret;
4661
4662 if (!gif_set(svm) ||
4663 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4664 return 0;
4665
4666 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4667
4668 if (is_guest_mode(vcpu))
4669 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4670
4671 return ret;
4672 }
4673
4674 static void enable_irq_window(struct kvm_vcpu *vcpu)
4675 {
4676 struct vcpu_svm *svm = to_svm(vcpu);
4677
4678 if (kvm_vcpu_apicv_active(vcpu))
4679 return;
4680
4681 /*
4682 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4683 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4684 * get that intercept, this function will be called again though and
4685 * we'll get the vintr intercept.
4686 */
4687 if (gif_set(svm) && nested_svm_intr(svm)) {
4688 svm_set_vintr(svm);
4689 svm_inject_irq(svm, 0x0);
4690 }
4691 }
4692
4693 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4694 {
4695 struct vcpu_svm *svm = to_svm(vcpu);
4696
4697 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4698 == HF_NMI_MASK)
4699 return; /* IRET will cause a vm exit */
4700
4701 if ((svm->vcpu.arch.hflags & HF_GIF_MASK) == 0)
4702 return; /* STGI will cause a vm exit */
4703
4704 if (svm->nested.exit_required)
4705 return; /* we're not going to run the guest yet */
4706
4707 /*
4708 * Something prevents NMI from been injected. Single step over possible
4709 * problem (IRET or exception injection or interrupt shadow)
4710 */
4711 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4712 svm->nmi_singlestep = true;
4713 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4714 }
4715
4716 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4717 {
4718 return 0;
4719 }
4720
4721 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4722 {
4723 struct vcpu_svm *svm = to_svm(vcpu);
4724
4725 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4726 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4727 else
4728 svm->asid_generation--;
4729 }
4730
4731 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4732 {
4733 }
4734
4735 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4736 {
4737 struct vcpu_svm *svm = to_svm(vcpu);
4738
4739 if (svm_nested_virtualize_tpr(vcpu))
4740 return;
4741
4742 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4743 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4744 kvm_set_cr8(vcpu, cr8);
4745 }
4746 }
4747
4748 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4749 {
4750 struct vcpu_svm *svm = to_svm(vcpu);
4751 u64 cr8;
4752
4753 if (svm_nested_virtualize_tpr(vcpu) ||
4754 kvm_vcpu_apicv_active(vcpu))
4755 return;
4756
4757 cr8 = kvm_get_cr8(vcpu);
4758 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4759 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4760 }
4761
4762 static void svm_complete_interrupts(struct vcpu_svm *svm)
4763 {
4764 u8 vector;
4765 int type;
4766 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4767 unsigned int3_injected = svm->int3_injected;
4768
4769 svm->int3_injected = 0;
4770
4771 /*
4772 * If we've made progress since setting HF_IRET_MASK, we've
4773 * executed an IRET and can allow NMI injection.
4774 */
4775 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4776 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4777 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4778 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4779 }
4780
4781 svm->vcpu.arch.nmi_injected = false;
4782 kvm_clear_exception_queue(&svm->vcpu);
4783 kvm_clear_interrupt_queue(&svm->vcpu);
4784
4785 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4786 return;
4787
4788 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4789
4790 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4791 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4792
4793 switch (type) {
4794 case SVM_EXITINTINFO_TYPE_NMI:
4795 svm->vcpu.arch.nmi_injected = true;
4796 break;
4797 case SVM_EXITINTINFO_TYPE_EXEPT:
4798 /*
4799 * In case of software exceptions, do not reinject the vector,
4800 * but re-execute the instruction instead. Rewind RIP first
4801 * if we emulated INT3 before.
4802 */
4803 if (kvm_exception_is_soft(vector)) {
4804 if (vector == BP_VECTOR && int3_injected &&
4805 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4806 kvm_rip_write(&svm->vcpu,
4807 kvm_rip_read(&svm->vcpu) -
4808 int3_injected);
4809 break;
4810 }
4811 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4812 u32 err = svm->vmcb->control.exit_int_info_err;
4813 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4814
4815 } else
4816 kvm_requeue_exception(&svm->vcpu, vector);
4817 break;
4818 case SVM_EXITINTINFO_TYPE_INTR:
4819 kvm_queue_interrupt(&svm->vcpu, vector, false);
4820 break;
4821 default:
4822 break;
4823 }
4824 }
4825
4826 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4827 {
4828 struct vcpu_svm *svm = to_svm(vcpu);
4829 struct vmcb_control_area *control = &svm->vmcb->control;
4830
4831 control->exit_int_info = control->event_inj;
4832 control->exit_int_info_err = control->event_inj_err;
4833 control->event_inj = 0;
4834 svm_complete_interrupts(svm);
4835 }
4836
4837 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4838 {
4839 struct vcpu_svm *svm = to_svm(vcpu);
4840
4841 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4842 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4843 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4844
4845 /*
4846 * A vmexit emulation is required before the vcpu can be executed
4847 * again.
4848 */
4849 if (unlikely(svm->nested.exit_required))
4850 return;
4851
4852 /*
4853 * Disable singlestep if we're injecting an interrupt/exception.
4854 * We don't want our modified rflags to be pushed on the stack where
4855 * we might not be able to easily reset them if we disabled NMI
4856 * singlestep later.
4857 */
4858 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4859 /*
4860 * Event injection happens before external interrupts cause a
4861 * vmexit and interrupts are disabled here, so smp_send_reschedule
4862 * is enough to force an immediate vmexit.
4863 */
4864 disable_nmi_singlestep(svm);
4865 smp_send_reschedule(vcpu->cpu);
4866 }
4867
4868 pre_svm_run(svm);
4869
4870 sync_lapic_to_cr8(vcpu);
4871
4872 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4873
4874 clgi();
4875
4876 local_irq_enable();
4877
4878 asm volatile (
4879 "push %%" _ASM_BP "; \n\t"
4880 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4881 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4882 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4883 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4884 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4885 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4886 #ifdef CONFIG_X86_64
4887 "mov %c[r8](%[svm]), %%r8 \n\t"
4888 "mov %c[r9](%[svm]), %%r9 \n\t"
4889 "mov %c[r10](%[svm]), %%r10 \n\t"
4890 "mov %c[r11](%[svm]), %%r11 \n\t"
4891 "mov %c[r12](%[svm]), %%r12 \n\t"
4892 "mov %c[r13](%[svm]), %%r13 \n\t"
4893 "mov %c[r14](%[svm]), %%r14 \n\t"
4894 "mov %c[r15](%[svm]), %%r15 \n\t"
4895 #endif
4896
4897 /* Enter guest mode */
4898 "push %%" _ASM_AX " \n\t"
4899 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4900 __ex(SVM_VMLOAD) "\n\t"
4901 __ex(SVM_VMRUN) "\n\t"
4902 __ex(SVM_VMSAVE) "\n\t"
4903 "pop %%" _ASM_AX " \n\t"
4904
4905 /* Save guest registers, load host registers */
4906 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4907 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4908 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4909 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4910 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4911 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4912 #ifdef CONFIG_X86_64
4913 "mov %%r8, %c[r8](%[svm]) \n\t"
4914 "mov %%r9, %c[r9](%[svm]) \n\t"
4915 "mov %%r10, %c[r10](%[svm]) \n\t"
4916 "mov %%r11, %c[r11](%[svm]) \n\t"
4917 "mov %%r12, %c[r12](%[svm]) \n\t"
4918 "mov %%r13, %c[r13](%[svm]) \n\t"
4919 "mov %%r14, %c[r14](%[svm]) \n\t"
4920 "mov %%r15, %c[r15](%[svm]) \n\t"
4921 #endif
4922 /*
4923 * Clear host registers marked as clobbered to prevent
4924 * speculative use.
4925 */
4926 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
4927 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
4928 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
4929 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
4930 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
4931 #ifdef CONFIG_X86_64
4932 "xor %%r8, %%r8 \n\t"
4933 "xor %%r9, %%r9 \n\t"
4934 "xor %%r10, %%r10 \n\t"
4935 "xor %%r11, %%r11 \n\t"
4936 "xor %%r12, %%r12 \n\t"
4937 "xor %%r13, %%r13 \n\t"
4938 "xor %%r14, %%r14 \n\t"
4939 "xor %%r15, %%r15 \n\t"
4940 #endif
4941 "pop %%" _ASM_BP
4942 :
4943 : [svm]"a"(svm),
4944 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4945 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4946 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4947 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4948 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4949 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4950 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4951 #ifdef CONFIG_X86_64
4952 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4953 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4954 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4955 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4956 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4957 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4958 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4959 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4960 #endif
4961 : "cc", "memory"
4962 #ifdef CONFIG_X86_64
4963 , "rbx", "rcx", "rdx", "rsi", "rdi"
4964 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4965 #else
4966 , "ebx", "ecx", "edx", "esi", "edi"
4967 #endif
4968 );
4969
4970 /* Eliminate branch target predictions from guest mode */
4971 vmexit_fill_RSB();
4972
4973 #ifdef CONFIG_X86_64
4974 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4975 #else
4976 loadsegment(fs, svm->host.fs);
4977 #ifndef CONFIG_X86_32_LAZY_GS
4978 loadsegment(gs, svm->host.gs);
4979 #endif
4980 #endif
4981
4982 reload_tss(vcpu);
4983
4984 local_irq_disable();
4985
4986 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4987 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4988 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4989 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4990
4991 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4992 kvm_before_handle_nmi(&svm->vcpu);
4993
4994 stgi();
4995
4996 /* Any pending NMI will happen here */
4997
4998 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4999 kvm_after_handle_nmi(&svm->vcpu);
5000
5001 sync_cr8_to_lapic(vcpu);
5002
5003 svm->next_rip = 0;
5004
5005 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5006
5007 /* if exit due to PF check for async PF */
5008 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5009 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5010
5011 if (npt_enabled) {
5012 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5013 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5014 }
5015
5016 /*
5017 * We need to handle MC intercepts here before the vcpu has a chance to
5018 * change the physical cpu
5019 */
5020 if (unlikely(svm->vmcb->control.exit_code ==
5021 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5022 svm_handle_mce(svm);
5023
5024 mark_all_clean(svm->vmcb);
5025 }
5026 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5027
5028 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5029 {
5030 struct vcpu_svm *svm = to_svm(vcpu);
5031
5032 svm->vmcb->save.cr3 = root;
5033 mark_dirty(svm->vmcb, VMCB_CR);
5034 svm_flush_tlb(vcpu);
5035 }
5036
5037 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5038 {
5039 struct vcpu_svm *svm = to_svm(vcpu);
5040
5041 svm->vmcb->control.nested_cr3 = root;
5042 mark_dirty(svm->vmcb, VMCB_NPT);
5043
5044 /* Also sync guest cr3 here in case we live migrate */
5045 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5046 mark_dirty(svm->vmcb, VMCB_CR);
5047
5048 svm_flush_tlb(vcpu);
5049 }
5050
5051 static int is_disabled(void)
5052 {
5053 u64 vm_cr;
5054
5055 rdmsrl(MSR_VM_CR, vm_cr);
5056 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5057 return 1;
5058
5059 return 0;
5060 }
5061
5062 static void
5063 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5064 {
5065 /*
5066 * Patch in the VMMCALL instruction:
5067 */
5068 hypercall[0] = 0x0f;
5069 hypercall[1] = 0x01;
5070 hypercall[2] = 0xd9;
5071 }
5072
5073 static void svm_check_processor_compat(void *rtn)
5074 {
5075 *(int *)rtn = 0;
5076 }
5077
5078 static bool svm_cpu_has_accelerated_tpr(void)
5079 {
5080 return false;
5081 }
5082
5083 static bool svm_has_high_real_mode_segbase(void)
5084 {
5085 return true;
5086 }
5087
5088 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5089 {
5090 return 0;
5091 }
5092
5093 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5094 {
5095 struct vcpu_svm *svm = to_svm(vcpu);
5096 struct kvm_cpuid_entry2 *entry;
5097
5098 /* Update nrips enabled cache */
5099 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5100
5101 if (!kvm_vcpu_apicv_active(vcpu))
5102 return;
5103
5104 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5105 if (entry)
5106 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5107 }
5108
5109 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5110 {
5111 switch (func) {
5112 case 0x1:
5113 if (avic)
5114 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5115 break;
5116 case 0x80000001:
5117 if (nested)
5118 entry->ecx |= (1 << 2); /* Set SVM bit */
5119 break;
5120 case 0x8000000A:
5121 entry->eax = 1; /* SVM revision 1 */
5122 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5123 ASID emulation to nested SVM */
5124 entry->ecx = 0; /* Reserved */
5125 entry->edx = 0; /* Per default do not support any
5126 additional features */
5127
5128 /* Support next_rip if host supports it */
5129 if (boot_cpu_has(X86_FEATURE_NRIPS))
5130 entry->edx |= SVM_FEATURE_NRIP;
5131
5132 /* Support NPT for the guest if enabled */
5133 if (npt_enabled)
5134 entry->edx |= SVM_FEATURE_NPT;
5135
5136 break;
5137 }
5138 }
5139
5140 static int svm_get_lpage_level(void)
5141 {
5142 return PT_PDPE_LEVEL;
5143 }
5144
5145 static bool svm_rdtscp_supported(void)
5146 {
5147 return boot_cpu_has(X86_FEATURE_RDTSCP);
5148 }
5149
5150 static bool svm_invpcid_supported(void)
5151 {
5152 return false;
5153 }
5154
5155 static bool svm_mpx_supported(void)
5156 {
5157 return false;
5158 }
5159
5160 static bool svm_xsaves_supported(void)
5161 {
5162 return false;
5163 }
5164
5165 static bool svm_has_wbinvd_exit(void)
5166 {
5167 return true;
5168 }
5169
5170 #define PRE_EX(exit) { .exit_code = (exit), \
5171 .stage = X86_ICPT_PRE_EXCEPT, }
5172 #define POST_EX(exit) { .exit_code = (exit), \
5173 .stage = X86_ICPT_POST_EXCEPT, }
5174 #define POST_MEM(exit) { .exit_code = (exit), \
5175 .stage = X86_ICPT_POST_MEMACCESS, }
5176
5177 static const struct __x86_intercept {
5178 u32 exit_code;
5179 enum x86_intercept_stage stage;
5180 } x86_intercept_map[] = {
5181 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5182 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5183 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5184 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5185 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5186 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5187 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5188 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5189 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5190 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5191 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5192 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5193 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5194 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5195 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5196 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5197 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5198 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5199 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5200 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5201 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5202 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5203 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5204 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5205 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5206 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5207 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5208 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5209 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5210 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5211 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5212 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5213 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5214 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5215 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5216 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5217 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5218 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5219 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5220 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5221 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5222 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5223 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5224 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5225 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5226 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5227 };
5228
5229 #undef PRE_EX
5230 #undef POST_EX
5231 #undef POST_MEM
5232
5233 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5234 struct x86_instruction_info *info,
5235 enum x86_intercept_stage stage)
5236 {
5237 struct vcpu_svm *svm = to_svm(vcpu);
5238 int vmexit, ret = X86EMUL_CONTINUE;
5239 struct __x86_intercept icpt_info;
5240 struct vmcb *vmcb = svm->vmcb;
5241
5242 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5243 goto out;
5244
5245 icpt_info = x86_intercept_map[info->intercept];
5246
5247 if (stage != icpt_info.stage)
5248 goto out;
5249
5250 switch (icpt_info.exit_code) {
5251 case SVM_EXIT_READ_CR0:
5252 if (info->intercept == x86_intercept_cr_read)
5253 icpt_info.exit_code += info->modrm_reg;
5254 break;
5255 case SVM_EXIT_WRITE_CR0: {
5256 unsigned long cr0, val;
5257 u64 intercept;
5258
5259 if (info->intercept == x86_intercept_cr_write)
5260 icpt_info.exit_code += info->modrm_reg;
5261
5262 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5263 info->intercept == x86_intercept_clts)
5264 break;
5265
5266 intercept = svm->nested.intercept;
5267
5268 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5269 break;
5270
5271 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5272 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5273
5274 if (info->intercept == x86_intercept_lmsw) {
5275 cr0 &= 0xfUL;
5276 val &= 0xfUL;
5277 /* lmsw can't clear PE - catch this here */
5278 if (cr0 & X86_CR0_PE)
5279 val |= X86_CR0_PE;
5280 }
5281
5282 if (cr0 ^ val)
5283 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5284
5285 break;
5286 }
5287 case SVM_EXIT_READ_DR0:
5288 case SVM_EXIT_WRITE_DR0:
5289 icpt_info.exit_code += info->modrm_reg;
5290 break;
5291 case SVM_EXIT_MSR:
5292 if (info->intercept == x86_intercept_wrmsr)
5293 vmcb->control.exit_info_1 = 1;
5294 else
5295 vmcb->control.exit_info_1 = 0;
5296 break;
5297 case SVM_EXIT_PAUSE:
5298 /*
5299 * We get this for NOP only, but pause
5300 * is rep not, check this here
5301 */
5302 if (info->rep_prefix != REPE_PREFIX)
5303 goto out;
5304 case SVM_EXIT_IOIO: {
5305 u64 exit_info;
5306 u32 bytes;
5307
5308 if (info->intercept == x86_intercept_in ||
5309 info->intercept == x86_intercept_ins) {
5310 exit_info = ((info->src_val & 0xffff) << 16) |
5311 SVM_IOIO_TYPE_MASK;
5312 bytes = info->dst_bytes;
5313 } else {
5314 exit_info = (info->dst_val & 0xffff) << 16;
5315 bytes = info->src_bytes;
5316 }
5317
5318 if (info->intercept == x86_intercept_outs ||
5319 info->intercept == x86_intercept_ins)
5320 exit_info |= SVM_IOIO_STR_MASK;
5321
5322 if (info->rep_prefix)
5323 exit_info |= SVM_IOIO_REP_MASK;
5324
5325 bytes = min(bytes, 4u);
5326
5327 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5328
5329 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5330
5331 vmcb->control.exit_info_1 = exit_info;
5332 vmcb->control.exit_info_2 = info->next_rip;
5333
5334 break;
5335 }
5336 default:
5337 break;
5338 }
5339
5340 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5341 if (static_cpu_has(X86_FEATURE_NRIPS))
5342 vmcb->control.next_rip = info->next_rip;
5343 vmcb->control.exit_code = icpt_info.exit_code;
5344 vmexit = nested_svm_exit_handled(svm);
5345
5346 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5347 : X86EMUL_CONTINUE;
5348
5349 out:
5350 return ret;
5351 }
5352
5353 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5354 {
5355 local_irq_enable();
5356 /*
5357 * We must have an instruction with interrupts enabled, so
5358 * the timer interrupt isn't delayed by the interrupt shadow.
5359 */
5360 asm("nop");
5361 local_irq_disable();
5362 }
5363
5364 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5365 {
5366 }
5367
5368 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5369 {
5370 if (avic_handle_apic_id_update(vcpu) != 0)
5371 return;
5372 if (avic_handle_dfr_update(vcpu) != 0)
5373 return;
5374 avic_handle_ldr_update(vcpu);
5375 }
5376
5377 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5378 {
5379 /* [63:9] are reserved. */
5380 vcpu->arch.mcg_cap &= 0x1ff;
5381 }
5382
5383 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5384 .cpu_has_kvm_support = has_svm,
5385 .disabled_by_bios = is_disabled,
5386 .hardware_setup = svm_hardware_setup,
5387 .hardware_unsetup = svm_hardware_unsetup,
5388 .check_processor_compatibility = svm_check_processor_compat,
5389 .hardware_enable = svm_hardware_enable,
5390 .hardware_disable = svm_hardware_disable,
5391 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5392 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5393
5394 .vcpu_create = svm_create_vcpu,
5395 .vcpu_free = svm_free_vcpu,
5396 .vcpu_reset = svm_vcpu_reset,
5397
5398 .vm_init = avic_vm_init,
5399 .vm_destroy = avic_vm_destroy,
5400
5401 .prepare_guest_switch = svm_prepare_guest_switch,
5402 .vcpu_load = svm_vcpu_load,
5403 .vcpu_put = svm_vcpu_put,
5404 .vcpu_blocking = svm_vcpu_blocking,
5405 .vcpu_unblocking = svm_vcpu_unblocking,
5406
5407 .update_bp_intercept = update_bp_intercept,
5408 .get_msr = svm_get_msr,
5409 .set_msr = svm_set_msr,
5410 .get_segment_base = svm_get_segment_base,
5411 .get_segment = svm_get_segment,
5412 .set_segment = svm_set_segment,
5413 .get_cpl = svm_get_cpl,
5414 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5415 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5416 .decache_cr3 = svm_decache_cr3,
5417 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5418 .set_cr0 = svm_set_cr0,
5419 .set_cr3 = svm_set_cr3,
5420 .set_cr4 = svm_set_cr4,
5421 .set_efer = svm_set_efer,
5422 .get_idt = svm_get_idt,
5423 .set_idt = svm_set_idt,
5424 .get_gdt = svm_get_gdt,
5425 .set_gdt = svm_set_gdt,
5426 .get_dr6 = svm_get_dr6,
5427 .set_dr6 = svm_set_dr6,
5428 .set_dr7 = svm_set_dr7,
5429 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5430 .cache_reg = svm_cache_reg,
5431 .get_rflags = svm_get_rflags,
5432 .set_rflags = svm_set_rflags,
5433
5434 .tlb_flush = svm_flush_tlb,
5435
5436 .run = svm_vcpu_run,
5437 .handle_exit = handle_exit,
5438 .skip_emulated_instruction = skip_emulated_instruction,
5439 .set_interrupt_shadow = svm_set_interrupt_shadow,
5440 .get_interrupt_shadow = svm_get_interrupt_shadow,
5441 .patch_hypercall = svm_patch_hypercall,
5442 .set_irq = svm_set_irq,
5443 .set_nmi = svm_inject_nmi,
5444 .queue_exception = svm_queue_exception,
5445 .cancel_injection = svm_cancel_injection,
5446 .interrupt_allowed = svm_interrupt_allowed,
5447 .nmi_allowed = svm_nmi_allowed,
5448 .get_nmi_mask = svm_get_nmi_mask,
5449 .set_nmi_mask = svm_set_nmi_mask,
5450 .enable_nmi_window = enable_nmi_window,
5451 .enable_irq_window = enable_irq_window,
5452 .update_cr8_intercept = update_cr8_intercept,
5453 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5454 .get_enable_apicv = svm_get_enable_apicv,
5455 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5456 .load_eoi_exitmap = svm_load_eoi_exitmap,
5457 .hwapic_irr_update = svm_hwapic_irr_update,
5458 .hwapic_isr_update = svm_hwapic_isr_update,
5459 .apicv_post_state_restore = avic_post_state_restore,
5460
5461 .set_tss_addr = svm_set_tss_addr,
5462 .get_tdp_level = get_npt_level,
5463 .get_mt_mask = svm_get_mt_mask,
5464
5465 .get_exit_info = svm_get_exit_info,
5466
5467 .get_lpage_level = svm_get_lpage_level,
5468
5469 .cpuid_update = svm_cpuid_update,
5470
5471 .rdtscp_supported = svm_rdtscp_supported,
5472 .invpcid_supported = svm_invpcid_supported,
5473 .mpx_supported = svm_mpx_supported,
5474 .xsaves_supported = svm_xsaves_supported,
5475
5476 .set_supported_cpuid = svm_set_supported_cpuid,
5477
5478 .has_wbinvd_exit = svm_has_wbinvd_exit,
5479
5480 .write_tsc_offset = svm_write_tsc_offset,
5481
5482 .set_tdp_cr3 = set_tdp_cr3,
5483
5484 .check_intercept = svm_check_intercept,
5485 .handle_external_intr = svm_handle_external_intr,
5486
5487 .sched_in = svm_sched_in,
5488
5489 .pmu_ops = &amd_pmu_ops,
5490 .deliver_posted_interrupt = svm_deliver_avic_intr,
5491 .update_pi_irte = svm_update_pi_irte,
5492 .setup_mce = svm_setup_mce,
5493 };
5494
5495 static int __init svm_init(void)
5496 {
5497 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5498 __alignof__(struct vcpu_svm), THIS_MODULE);
5499 }
5500
5501 static void __exit svm_exit(void)
5502 {
5503 kvm_exit();
5504 }
5505
5506 module_init(svm_init)
5507 module_exit(svm_exit)
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