2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
139 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
149 * According to test, this time is usually smaller than 128 cycles.
150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
156 #define KVM_VMX_DEFAULT_PLE_GAP 128
157 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
163 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
164 module_param(ple_gap
, int, S_IRUGO
);
166 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
167 module_param(ple_window
, int, S_IRUGO
);
169 /* Default doubles per-vcpu window every exit. */
170 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
171 module_param(ple_window_grow
, int, S_IRUGO
);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
175 module_param(ple_window_shrink
, int, S_IRUGO
);
177 /* Default is to compute the maximum so we can never overflow. */
178 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
180 module_param(ple_window_max
, int, S_IRUGO
);
182 extern const ulong vmx_return
;
184 #define NR_AUTOLOAD_MSRS 8
185 #define VMCS02_POOL_SIZE 1
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
200 struct vmcs
*shadow_vmcs
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
247 u64 eoi_exit_bitmap0
;
248 u64 eoi_exit_bitmap1
;
249 u64 eoi_exit_bitmap2
;
250 u64 eoi_exit_bitmap3
;
252 u64 guest_physical_address
;
253 u64 vmcs_link_pointer
;
254 u64 guest_ia32_debugctl
;
257 u64 guest_ia32_perf_global_ctrl
;
265 u64 host_ia32_perf_global_ctrl
;
266 u64 padding64
[8]; /* room for future expansion */
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
273 natural_width cr0_guest_host_mask
;
274 natural_width cr4_guest_host_mask
;
275 natural_width cr0_read_shadow
;
276 natural_width cr4_read_shadow
;
277 natural_width cr3_target_value0
;
278 natural_width cr3_target_value1
;
279 natural_width cr3_target_value2
;
280 natural_width cr3_target_value3
;
281 natural_width exit_qualification
;
282 natural_width guest_linear_address
;
283 natural_width guest_cr0
;
284 natural_width guest_cr3
;
285 natural_width guest_cr4
;
286 natural_width guest_es_base
;
287 natural_width guest_cs_base
;
288 natural_width guest_ss_base
;
289 natural_width guest_ds_base
;
290 natural_width guest_fs_base
;
291 natural_width guest_gs_base
;
292 natural_width guest_ldtr_base
;
293 natural_width guest_tr_base
;
294 natural_width guest_gdtr_base
;
295 natural_width guest_idtr_base
;
296 natural_width guest_dr7
;
297 natural_width guest_rsp
;
298 natural_width guest_rip
;
299 natural_width guest_rflags
;
300 natural_width guest_pending_dbg_exceptions
;
301 natural_width guest_sysenter_esp
;
302 natural_width guest_sysenter_eip
;
303 natural_width host_cr0
;
304 natural_width host_cr3
;
305 natural_width host_cr4
;
306 natural_width host_fs_base
;
307 natural_width host_gs_base
;
308 natural_width host_tr_base
;
309 natural_width host_gdtr_base
;
310 natural_width host_idtr_base
;
311 natural_width host_ia32_sysenter_esp
;
312 natural_width host_ia32_sysenter_eip
;
313 natural_width host_rsp
;
314 natural_width host_rip
;
315 natural_width paddingl
[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control
;
317 u32 cpu_based_vm_exec_control
;
318 u32 exception_bitmap
;
319 u32 page_fault_error_code_mask
;
320 u32 page_fault_error_code_match
;
321 u32 cr3_target_count
;
322 u32 vm_exit_controls
;
323 u32 vm_exit_msr_store_count
;
324 u32 vm_exit_msr_load_count
;
325 u32 vm_entry_controls
;
326 u32 vm_entry_msr_load_count
;
327 u32 vm_entry_intr_info_field
;
328 u32 vm_entry_exception_error_code
;
329 u32 vm_entry_instruction_len
;
331 u32 secondary_vm_exec_control
;
332 u32 vm_instruction_error
;
334 u32 vm_exit_intr_info
;
335 u32 vm_exit_intr_error_code
;
336 u32 idt_vectoring_info_field
;
337 u32 idt_vectoring_error_code
;
338 u32 vm_exit_instruction_len
;
339 u32 vmx_instruction_info
;
346 u32 guest_ldtr_limit
;
348 u32 guest_gdtr_limit
;
349 u32 guest_idtr_limit
;
350 u32 guest_es_ar_bytes
;
351 u32 guest_cs_ar_bytes
;
352 u32 guest_ss_ar_bytes
;
353 u32 guest_ds_ar_bytes
;
354 u32 guest_fs_ar_bytes
;
355 u32 guest_gs_ar_bytes
;
356 u32 guest_ldtr_ar_bytes
;
357 u32 guest_tr_ar_bytes
;
358 u32 guest_interruptibility_info
;
359 u32 guest_activity_state
;
360 u32 guest_sysenter_cs
;
361 u32 host_ia32_sysenter_cs
;
362 u32 vmx_preemption_timer_value
;
363 u32 padding32
[7]; /* room for future expansion */
364 u16 virtual_processor_id
;
366 u16 guest_es_selector
;
367 u16 guest_cs_selector
;
368 u16 guest_ss_selector
;
369 u16 guest_ds_selector
;
370 u16 guest_fs_selector
;
371 u16 guest_gs_selector
;
372 u16 guest_ldtr_selector
;
373 u16 guest_tr_selector
;
374 u16 guest_intr_status
;
375 u16 host_es_selector
;
376 u16 host_cs_selector
;
377 u16 host_ss_selector
;
378 u16 host_ds_selector
;
379 u16 host_fs_selector
;
380 u16 host_gs_selector
;
381 u16 host_tr_selector
;
385 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
386 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
387 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
389 #define VMCS12_REVISION 0x11e57ed0
392 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
393 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
394 * current implementation, 4K are reserved to avoid future complications.
396 #define VMCS12_SIZE 0x1000
398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
400 struct list_head list
;
402 struct loaded_vmcs vmcs02
;
406 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
407 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 /* Has the level1 guest done vmxon? */
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
416 /* The host-usable pointer to the above */
417 struct page
*current_vmcs12_page
;
418 struct vmcs12
*current_vmcs12
;
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 struct vmcs12
*cached_vmcs12
;
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
429 bool sync_shadow_vmcs
;
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool
;
434 bool change_vmcs01_virtual_x2apic_mode
;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending
;
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
441 struct page
*apic_access_page
;
442 struct page
*virtual_apic_page
;
443 struct page
*pi_desc_page
;
444 struct pi_desc
*pi_desc
;
448 unsigned long *msr_bitmap
;
450 struct hrtimer preemption_timer
;
451 bool preemption_timer_expired
;
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
464 u32 nested_vmx_procbased_ctls_low
;
465 u32 nested_vmx_procbased_ctls_high
;
466 u32 nested_vmx_secondary_ctls_low
;
467 u32 nested_vmx_secondary_ctls_high
;
468 u32 nested_vmx_pinbased_ctls_low
;
469 u32 nested_vmx_pinbased_ctls_high
;
470 u32 nested_vmx_exit_ctls_low
;
471 u32 nested_vmx_exit_ctls_high
;
472 u32 nested_vmx_entry_ctls_low
;
473 u32 nested_vmx_entry_ctls_high
;
474 u32 nested_vmx_misc_low
;
475 u32 nested_vmx_misc_high
;
476 u32 nested_vmx_ept_caps
;
477 u32 nested_vmx_vpid_caps
;
478 u64 nested_vmx_basic
;
479 u64 nested_vmx_cr0_fixed0
;
480 u64 nested_vmx_cr0_fixed1
;
481 u64 nested_vmx_cr4_fixed0
;
482 u64 nested_vmx_cr4_fixed1
;
483 u64 nested_vmx_vmcs_enum
;
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
489 /* Posted-Interrupt Descriptor */
491 u32 pir
[8]; /* Posted interrupt requested */
494 /* bit 256 - Outstanding Notification */
496 /* bit 257 - Suppress Notification */
498 /* bit 271:258 - Reserved */
500 /* bit 279:272 - Notification Vector */
502 /* bit 287:280 - Reserved */
504 /* bit 319:288 - Notification Destination */
512 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
514 return test_and_set_bit(POSTED_INTR_ON
,
515 (unsigned long *)&pi_desc
->control
);
518 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
520 return test_and_clear_bit(POSTED_INTR_ON
,
521 (unsigned long *)&pi_desc
->control
);
524 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
526 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
529 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
531 return clear_bit(POSTED_INTR_SN
,
532 (unsigned long *)&pi_desc
->control
);
535 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
537 return set_bit(POSTED_INTR_SN
,
538 (unsigned long *)&pi_desc
->control
);
541 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
543 clear_bit(POSTED_INTR_ON
,
544 (unsigned long *)&pi_desc
->control
);
547 static inline int pi_test_on(struct pi_desc
*pi_desc
)
549 return test_bit(POSTED_INTR_ON
,
550 (unsigned long *)&pi_desc
->control
);
553 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
555 return test_bit(POSTED_INTR_SN
,
556 (unsigned long *)&pi_desc
->control
);
560 struct kvm_vcpu vcpu
;
561 unsigned long host_rsp
;
563 bool nmi_known_unmasked
;
565 u32 idt_vectoring_info
;
567 struct shared_msr_entry
*guest_msrs
;
570 unsigned long host_idt_base
;
572 u64 msr_host_kernel_gs_base
;
573 u64 msr_guest_kernel_gs_base
;
575 u32 vm_entry_controls_shadow
;
576 u32 vm_exit_controls_shadow
;
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
582 struct loaded_vmcs vmcs01
;
583 struct loaded_vmcs
*loaded_vmcs
;
584 bool __launched
; /* temporary, used in vmx_vcpu_run */
585 struct msr_autoload
{
587 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
588 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
592 u16 fs_sel
, gs_sel
, ldt_sel
;
596 int gs_ldt_reload_needed
;
597 int fs_reload_needed
;
598 u64 msr_host_bndcfgs
;
599 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
604 struct kvm_segment segs
[8];
607 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment
{
616 bool emulation_required
;
618 /* Support for vnmi-less CPUs */
619 int soft_vnmi_blocked
;
621 s64 vnmi_blocked_time
;
624 /* Posted interrupt descriptor */
625 struct pi_desc pi_desc
;
627 /* Support for a guest hypervisor (nested VMX) */
628 struct nested_vmx nested
;
630 /* Dynamic PLE window. */
632 bool ple_window_dirty
;
634 /* Support for PML */
635 #define PML_ENTITY_NUM 512
638 /* apic deadline value in host tsc */
641 u64 current_tsc_ratio
;
643 bool guest_pkru_valid
;
648 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
649 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
650 * in msr_ia32_feature_control_valid_bits.
652 u64 msr_ia32_feature_control
;
653 u64 msr_ia32_feature_control_valid_bits
;
656 enum segment_cache_field
{
665 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
667 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
670 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
672 return &(to_vmx(vcpu
)->pi_desc
);
675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
676 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
677 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
678 [number##_HIGH] = VMCS12_OFFSET(name)+4
681 static unsigned long shadow_read_only_fields
[] = {
683 * We do NOT shadow fields that are modified when L0
684 * traps and emulates any vmx instruction (e.g. VMPTRLD,
685 * VMXON...) executed by L1.
686 * For example, VM_INSTRUCTION_ERROR is read
687 * by L1 if a vmx instruction fails (part of the error path).
688 * Note the code assumes this logic. If for some reason
689 * we start shadowing these fields then we need to
690 * force a shadow sync when L0 emulates vmx instructions
691 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
692 * by nested_vmx_failValid)
696 VM_EXIT_INSTRUCTION_LEN
,
697 IDT_VECTORING_INFO_FIELD
,
698 IDT_VECTORING_ERROR_CODE
,
699 VM_EXIT_INTR_ERROR_CODE
,
701 GUEST_LINEAR_ADDRESS
,
702 GUEST_PHYSICAL_ADDRESS
704 static int max_shadow_read_only_fields
=
705 ARRAY_SIZE(shadow_read_only_fields
);
707 static unsigned long shadow_read_write_fields
[] = {
714 GUEST_INTERRUPTIBILITY_INFO
,
727 CPU_BASED_VM_EXEC_CONTROL
,
728 VM_ENTRY_EXCEPTION_ERROR_CODE
,
729 VM_ENTRY_INTR_INFO_FIELD
,
730 VM_ENTRY_INSTRUCTION_LEN
,
731 VM_ENTRY_EXCEPTION_ERROR_CODE
,
737 static int max_shadow_read_write_fields
=
738 ARRAY_SIZE(shadow_read_write_fields
);
740 static const unsigned short vmcs_field_to_offset_table
[] = {
741 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
742 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
743 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
744 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
745 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
746 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
747 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
748 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
749 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
750 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
751 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(EPT_POINTER
, ept_pointer
),
770 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
771 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
772 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
773 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
774 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
775 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
776 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
777 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
778 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
779 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
780 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
781 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
782 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
783 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
784 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
785 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
786 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
787 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
788 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
789 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
790 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
791 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
792 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
793 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
794 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
795 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
796 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
797 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
798 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
799 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
800 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
801 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
802 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
803 FIELD(TPR_THRESHOLD
, tpr_threshold
),
804 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
805 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
806 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
807 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
808 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
809 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
810 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
811 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
812 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
813 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
814 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
815 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
816 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
817 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
818 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
819 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
820 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
821 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
822 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
823 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
824 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
825 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
826 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
827 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
828 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
829 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
830 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
831 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
832 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
833 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
834 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
835 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
836 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
837 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
838 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
839 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
840 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
841 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
842 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
843 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
844 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
845 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
846 FIELD(GUEST_CR0
, guest_cr0
),
847 FIELD(GUEST_CR3
, guest_cr3
),
848 FIELD(GUEST_CR4
, guest_cr4
),
849 FIELD(GUEST_ES_BASE
, guest_es_base
),
850 FIELD(GUEST_CS_BASE
, guest_cs_base
),
851 FIELD(GUEST_SS_BASE
, guest_ss_base
),
852 FIELD(GUEST_DS_BASE
, guest_ds_base
),
853 FIELD(GUEST_FS_BASE
, guest_fs_base
),
854 FIELD(GUEST_GS_BASE
, guest_gs_base
),
855 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
856 FIELD(GUEST_TR_BASE
, guest_tr_base
),
857 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
858 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
859 FIELD(GUEST_DR7
, guest_dr7
),
860 FIELD(GUEST_RSP
, guest_rsp
),
861 FIELD(GUEST_RIP
, guest_rip
),
862 FIELD(GUEST_RFLAGS
, guest_rflags
),
863 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
864 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
865 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
866 FIELD(HOST_CR0
, host_cr0
),
867 FIELD(HOST_CR3
, host_cr3
),
868 FIELD(HOST_CR4
, host_cr4
),
869 FIELD(HOST_FS_BASE
, host_fs_base
),
870 FIELD(HOST_GS_BASE
, host_gs_base
),
871 FIELD(HOST_TR_BASE
, host_tr_base
),
872 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
873 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
874 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
875 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
876 FIELD(HOST_RSP
, host_rsp
),
877 FIELD(HOST_RIP
, host_rip
),
880 static inline short vmcs_field_to_offset(unsigned long field
)
882 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
884 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
885 vmcs_field_to_offset_table
[field
] == 0)
888 return vmcs_field_to_offset_table
[field
];
891 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
893 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
896 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
898 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
899 if (is_error_page(page
))
905 static void nested_release_page(struct page
*page
)
907 kvm_release_page_dirty(page
);
910 static void nested_release_page_clean(struct page
*page
)
912 kvm_release_page_clean(page
);
915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
916 static u64
construct_eptp(unsigned long root_hpa
);
917 static void kvm_cpu_vmxon(u64 addr
);
918 static void kvm_cpu_vmxoff(void);
919 static bool vmx_xsaves_supported(void);
920 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
921 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
922 struct kvm_segment
*var
, int seg
);
923 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
924 struct kvm_segment
*var
, int seg
);
925 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
926 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
927 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
928 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
929 static int alloc_identity_pagetable(struct kvm
*kvm
);
931 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
932 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
938 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
944 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
945 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
950 VMX_MSR_BITMAP_LEGACY
,
951 VMX_MSR_BITMAP_LONGMODE
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
954 VMX_MSR_BITMAP_LEGACY_X2APIC
,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
961 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
963 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
974 static bool cpu_has_load_ia32_efer
;
975 static bool cpu_has_load_perf_global_ctrl
;
977 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
978 static DEFINE_SPINLOCK(vmx_vpid_lock
);
980 static struct vmcs_config
{
985 u32 pin_based_exec_ctrl
;
986 u32 cpu_based_exec_ctrl
;
987 u32 cpu_based_2nd_exec_ctrl
;
992 static struct vmx_capability
{
997 #define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1005 static const struct kvm_vmx_segment_field
{
1010 } kvm_vmx_segment_fields
[] = {
1011 VMX_SEGMENT_FIELD(CS
),
1012 VMX_SEGMENT_FIELD(DS
),
1013 VMX_SEGMENT_FIELD(ES
),
1014 VMX_SEGMENT_FIELD(FS
),
1015 VMX_SEGMENT_FIELD(GS
),
1016 VMX_SEGMENT_FIELD(SS
),
1017 VMX_SEGMENT_FIELD(TR
),
1018 VMX_SEGMENT_FIELD(LDTR
),
1021 static u64 host_efer
;
1023 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027 * away by decrementing the array size.
1029 static const u32 vmx_msr_index
[] = {
1030 #ifdef CONFIG_X86_64
1031 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1033 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1036 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1038 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1039 INTR_INFO_VALID_MASK
)) ==
1040 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1043 static inline bool is_debug(u32 intr_info
)
1045 return is_exception_n(intr_info
, DB_VECTOR
);
1048 static inline bool is_breakpoint(u32 intr_info
)
1050 return is_exception_n(intr_info
, BP_VECTOR
);
1053 static inline bool is_page_fault(u32 intr_info
)
1055 return is_exception_n(intr_info
, PF_VECTOR
);
1058 static inline bool is_no_device(u32 intr_info
)
1060 return is_exception_n(intr_info
, NM_VECTOR
);
1063 static inline bool is_invalid_opcode(u32 intr_info
)
1065 return is_exception_n(intr_info
, UD_VECTOR
);
1068 static inline bool is_external_interrupt(u32 intr_info
)
1070 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1071 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1074 static inline bool is_machine_check(u32 intr_info
)
1076 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1077 INTR_INFO_VALID_MASK
)) ==
1078 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config
.cpu_based_exec_ctrl
&
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms
[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax
= cpuid_eax(0x00000001), i
;
1163 /* Clear the reserved bits */
1164 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1165 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1166 if (eax
== vmx_preemption_cpu_tfms
[i
])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config
.pin_based_exec_ctrl
&
1175 PIN_BASED_VMX_PREEMPTION_TIMER
;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1181 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1219 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1222 static inline bool cpu_has_vmx_invept_context(void)
1224 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1227 static inline bool cpu_has_vmx_invept_global(void)
1229 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1234 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1239 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1242 static inline bool cpu_has_vmx_ept(void)
1244 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1245 SECONDARY_EXEC_ENABLE_EPT
;
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1251 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1254 static inline bool cpu_has_vmx_ple(void)
1256 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1257 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1260 static inline bool cpu_has_vmx_basic_inout(void)
1262 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1267 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1270 static inline bool cpu_has_vmx_vpid(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1273 SECONDARY_EXEC_ENABLE_VPID
;
1276 static inline bool cpu_has_vmx_rdtscp(void)
1278 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1279 SECONDARY_EXEC_RDTSCP
;
1282 static inline bool cpu_has_vmx_invpcid(void)
1284 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1285 SECONDARY_EXEC_ENABLE_INVPCID
;
1288 static inline bool cpu_has_virtual_nmis(void)
1290 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_WBINVD_EXITING
;
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1302 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1303 /* check if the cpu supports writing r/o exit information fields */
1304 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1307 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1308 SECONDARY_EXEC_SHADOW_VMCS
;
1311 static inline bool cpu_has_vmx_pml(void)
1313 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1318 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1319 SECONDARY_EXEC_TSC_SCALING
;
1322 static inline bool report_flexpriority(void)
1324 return flexpriority_enabled
;
1327 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1329 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1332 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1334 return (vmcs12
->cpu_based_vm_exec_control
&
1335 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1336 (vmcs12
->secondary_vm_exec_control
& bit
);
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1341 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1346 return vmcs12
->pin_based_vm_exec_control
&
1347 PIN_BASED_VMX_PREEMPTION_TIMER
;
1350 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1352 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1357 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1358 vmx_xsaves_supported();
1361 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1363 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1366 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1371 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1376 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1378 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1381 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1383 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1386 static inline bool is_nmi(u32 intr_info
)
1388 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1389 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1392 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1394 unsigned long exit_qualification
);
1395 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1396 struct vmcs12
*vmcs12
,
1397 u32 reason
, unsigned long qualification
);
1399 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1403 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1404 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1409 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1415 } operand
= { vpid
, 0, gva
};
1417 asm volatile (__ex(ASM_VMX_INVVPID
)
1418 /* CF==1 or ZF==1 --> rc = -1 */
1419 "; ja 1f ; ud2 ; 1:"
1420 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1423 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1427 } operand
= {eptp
, gpa
};
1429 asm volatile (__ex(ASM_VMX_INVEPT
)
1430 /* CF==1 or ZF==1 --> rc = -1 */
1431 "; ja 1f ; ud2 ; 1:\n"
1432 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1435 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1439 i
= __find_msr_index(vmx
, msr
);
1441 return &vmx
->guest_msrs
[i
];
1445 static void vmcs_clear(struct vmcs
*vmcs
)
1447 u64 phys_addr
= __pa(vmcs
);
1450 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1451 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1454 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1458 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1460 vmcs_clear(loaded_vmcs
->vmcs
);
1461 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1462 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1463 loaded_vmcs
->cpu
= -1;
1464 loaded_vmcs
->launched
= 0;
1467 static void vmcs_load(struct vmcs
*vmcs
)
1469 u64 phys_addr
= __pa(vmcs
);
1472 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1473 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1476 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1480 #ifdef CONFIG_KEXEC_CORE
1482 * This bitmap is used to indicate whether the vmclear
1483 * operation is enabled on all cpus. All disabled by
1486 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1488 static inline void crash_enable_local_vmclear(int cpu
)
1490 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1493 static inline void crash_disable_local_vmclear(int cpu
)
1495 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1498 static inline int crash_local_vmclear_enabled(int cpu
)
1500 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static void crash_vmclear_local_loaded_vmcss(void)
1505 int cpu
= raw_smp_processor_id();
1506 struct loaded_vmcs
*v
;
1508 if (!crash_local_vmclear_enabled(cpu
))
1511 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1512 loaded_vmcss_on_cpu_link
)
1513 vmcs_clear(v
->vmcs
);
1516 static inline void crash_enable_local_vmclear(int cpu
) { }
1517 static inline void crash_disable_local_vmclear(int cpu
) { }
1518 #endif /* CONFIG_KEXEC_CORE */
1520 static void __loaded_vmcs_clear(void *arg
)
1522 struct loaded_vmcs
*loaded_vmcs
= arg
;
1523 int cpu
= raw_smp_processor_id();
1525 if (loaded_vmcs
->cpu
!= cpu
)
1526 return; /* vcpu migration can race with cpu offline */
1527 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1528 per_cpu(current_vmcs
, cpu
) = NULL
;
1529 crash_disable_local_vmclear(cpu
);
1530 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1533 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1534 * is before setting loaded_vmcs->vcpu to -1 which is done in
1535 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1536 * then adds the vmcs into percpu list before it is deleted.
1540 loaded_vmcs_init(loaded_vmcs
);
1541 crash_enable_local_vmclear(cpu
);
1544 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1546 int cpu
= loaded_vmcs
->cpu
;
1549 smp_call_function_single(cpu
,
1550 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1553 static inline void vpid_sync_vcpu_single(int vpid
)
1558 if (cpu_has_vmx_invvpid_single())
1559 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1562 static inline void vpid_sync_vcpu_global(void)
1564 if (cpu_has_vmx_invvpid_global())
1565 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1568 static inline void vpid_sync_context(int vpid
)
1570 if (cpu_has_vmx_invvpid_single())
1571 vpid_sync_vcpu_single(vpid
);
1573 vpid_sync_vcpu_global();
1576 static inline void ept_sync_global(void)
1578 if (cpu_has_vmx_invept_global())
1579 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1582 static inline void ept_sync_context(u64 eptp
)
1585 if (cpu_has_vmx_invept_context())
1586 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1592 static __always_inline
void vmcs_check16(unsigned long field
)
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1595 "16-bit accessor invalid for 64-bit field");
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1597 "16-bit accessor invalid for 64-bit high field");
1598 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1599 "16-bit accessor invalid for 32-bit high field");
1600 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1601 "16-bit accessor invalid for natural width field");
1604 static __always_inline
void vmcs_check32(unsigned long field
)
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1607 "32-bit accessor invalid for 16-bit field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1609 "32-bit accessor invalid for natural width field");
1612 static __always_inline
void vmcs_check64(unsigned long field
)
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1615 "64-bit accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1617 "64-bit accessor invalid for 64-bit high field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1619 "64-bit accessor invalid for 32-bit field");
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1621 "64-bit accessor invalid for natural width field");
1624 static __always_inline
void vmcs_checkl(unsigned long field
)
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1627 "Natural width accessor invalid for 16-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1629 "Natural width accessor invalid for 64-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1631 "Natural width accessor invalid for 64-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1633 "Natural width accessor invalid for 32-bit field");
1636 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1638 unsigned long value
;
1640 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1641 : "=a"(value
) : "d"(field
) : "cc");
1645 static __always_inline u16
vmcs_read16(unsigned long field
)
1647 vmcs_check16(field
);
1648 return __vmcs_readl(field
);
1651 static __always_inline u32
vmcs_read32(unsigned long field
)
1653 vmcs_check32(field
);
1654 return __vmcs_readl(field
);
1657 static __always_inline u64
vmcs_read64(unsigned long field
)
1659 vmcs_check64(field
);
1660 #ifdef CONFIG_X86_64
1661 return __vmcs_readl(field
);
1663 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1667 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1670 return __vmcs_readl(field
);
1673 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1675 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1676 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1680 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1684 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1685 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1686 if (unlikely(error
))
1687 vmwrite_error(field
, value
);
1690 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1692 vmcs_check16(field
);
1693 __vmcs_writel(field
, value
);
1696 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1698 vmcs_check32(field
);
1699 __vmcs_writel(field
, value
);
1702 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1704 vmcs_check64(field
);
1705 __vmcs_writel(field
, value
);
1706 #ifndef CONFIG_X86_64
1708 __vmcs_writel(field
+1, value
>> 32);
1712 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1715 __vmcs_writel(field
, value
);
1718 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1720 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1721 "vmcs_clear_bits does not support 64-bit fields");
1722 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1725 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1727 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1728 "vmcs_set_bits does not support 64-bit fields");
1729 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1732 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1734 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1737 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1739 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1740 vmx
->vm_entry_controls_shadow
= val
;
1743 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1745 if (vmx
->vm_entry_controls_shadow
!= val
)
1746 vm_entry_controls_init(vmx
, val
);
1749 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1751 return vmx
->vm_entry_controls_shadow
;
1755 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1757 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1760 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1762 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1765 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1767 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1770 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1772 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1773 vmx
->vm_exit_controls_shadow
= val
;
1776 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1778 if (vmx
->vm_exit_controls_shadow
!= val
)
1779 vm_exit_controls_init(vmx
, val
);
1782 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1784 return vmx
->vm_exit_controls_shadow
;
1788 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1790 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1793 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1795 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1798 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1800 vmx
->segment_cache
.bitmask
= 0;
1803 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1807 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1809 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1810 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1811 vmx
->segment_cache
.bitmask
= 0;
1813 ret
= vmx
->segment_cache
.bitmask
& mask
;
1814 vmx
->segment_cache
.bitmask
|= mask
;
1818 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1820 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1822 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1823 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1827 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1829 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1831 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1832 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1836 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1838 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1840 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1841 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1845 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1847 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1849 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1850 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1854 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1858 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1859 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1860 if ((vcpu
->guest_debug
&
1861 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1862 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1863 eb
|= 1u << BP_VECTOR
;
1864 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1867 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1869 /* When we are running a nested L2 guest and L1 specified for it a
1870 * certain exception bitmap, we must trap the same exceptions and pass
1871 * them to L1. When running L2, we will only handle the exceptions
1872 * specified above if L1 did not want them.
1874 if (is_guest_mode(vcpu
))
1875 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1877 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1880 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1881 unsigned long entry
, unsigned long exit
)
1883 vm_entry_controls_clearbit(vmx
, entry
);
1884 vm_exit_controls_clearbit(vmx
, exit
);
1887 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1890 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1894 if (cpu_has_load_ia32_efer
) {
1895 clear_atomic_switch_msr_special(vmx
,
1896 VM_ENTRY_LOAD_IA32_EFER
,
1897 VM_EXIT_LOAD_IA32_EFER
);
1901 case MSR_CORE_PERF_GLOBAL_CTRL
:
1902 if (cpu_has_load_perf_global_ctrl
) {
1903 clear_atomic_switch_msr_special(vmx
,
1904 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1905 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1911 for (i
= 0; i
< m
->nr
; ++i
)
1912 if (m
->guest
[i
].index
== msr
)
1918 m
->guest
[i
] = m
->guest
[m
->nr
];
1919 m
->host
[i
] = m
->host
[m
->nr
];
1920 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1921 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1924 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1925 unsigned long entry
, unsigned long exit
,
1926 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1927 u64 guest_val
, u64 host_val
)
1929 vmcs_write64(guest_val_vmcs
, guest_val
);
1930 vmcs_write64(host_val_vmcs
, host_val
);
1931 vm_entry_controls_setbit(vmx
, entry
);
1932 vm_exit_controls_setbit(vmx
, exit
);
1935 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1936 u64 guest_val
, u64 host_val
)
1939 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1943 if (cpu_has_load_ia32_efer
) {
1944 add_atomic_switch_msr_special(vmx
,
1945 VM_ENTRY_LOAD_IA32_EFER
,
1946 VM_EXIT_LOAD_IA32_EFER
,
1949 guest_val
, host_val
);
1953 case MSR_CORE_PERF_GLOBAL_CTRL
:
1954 if (cpu_has_load_perf_global_ctrl
) {
1955 add_atomic_switch_msr_special(vmx
,
1956 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1957 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1958 GUEST_IA32_PERF_GLOBAL_CTRL
,
1959 HOST_IA32_PERF_GLOBAL_CTRL
,
1960 guest_val
, host_val
);
1964 case MSR_IA32_PEBS_ENABLE
:
1965 /* PEBS needs a quiescent period after being disabled (to write
1966 * a record). Disabling PEBS through VMX MSR swapping doesn't
1967 * provide that period, so a CPU could write host's record into
1970 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1973 for (i
= 0; i
< m
->nr
; ++i
)
1974 if (m
->guest
[i
].index
== msr
)
1977 if (i
== NR_AUTOLOAD_MSRS
) {
1978 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1979 "Can't add msr %x\n", msr
);
1981 } else if (i
== m
->nr
) {
1983 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1984 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1987 m
->guest
[i
].index
= msr
;
1988 m
->guest
[i
].value
= guest_val
;
1989 m
->host
[i
].index
= msr
;
1990 m
->host
[i
].value
= host_val
;
1993 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1995 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1996 u64 ignore_bits
= 0;
2000 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2001 * host CPUID is more efficient than testing guest CPUID
2002 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2004 if (boot_cpu_has(X86_FEATURE_SMEP
))
2005 guest_efer
|= EFER_NX
;
2006 else if (!(guest_efer
& EFER_NX
))
2007 ignore_bits
|= EFER_NX
;
2011 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2013 ignore_bits
|= EFER_SCE
;
2014 #ifdef CONFIG_X86_64
2015 ignore_bits
|= EFER_LMA
| EFER_LME
;
2016 /* SCE is meaningful only in long mode on Intel */
2017 if (guest_efer
& EFER_LMA
)
2018 ignore_bits
&= ~(u64
)EFER_SCE
;
2021 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2024 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2025 * On CPUs that support "load IA32_EFER", always switch EFER
2026 * atomically, since it's faster than switching it manually.
2028 if (cpu_has_load_ia32_efer
||
2029 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2030 if (!(guest_efer
& EFER_LMA
))
2031 guest_efer
&= ~EFER_LME
;
2032 if (guest_efer
!= host_efer
)
2033 add_atomic_switch_msr(vmx
, MSR_EFER
,
2034 guest_efer
, host_efer
);
2037 guest_efer
&= ~ignore_bits
;
2038 guest_efer
|= host_efer
& ignore_bits
;
2040 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2041 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2047 #ifdef CONFIG_X86_32
2049 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2050 * VMCS rather than the segment table. KVM uses this helper to figure
2051 * out the current bases to poke them into the VMCS before entry.
2053 static unsigned long segment_base(u16 selector
)
2055 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2056 struct desc_struct
*table
;
2059 if (!(selector
& ~SEGMENT_RPL_MASK
))
2062 table
= (struct desc_struct
*)gdt
->address
;
2064 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2065 u16 ldt_selector
= kvm_read_ldt();
2067 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2070 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2072 v
= get_desc_base(&table
[selector
>> 3]);
2077 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2079 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2082 if (vmx
->host_state
.loaded
)
2085 vmx
->host_state
.loaded
= 1;
2087 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2088 * allow segment selectors with cpl > 0 or ti == 1.
2090 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2091 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2092 savesegment(fs
, vmx
->host_state
.fs_sel
);
2093 if (!(vmx
->host_state
.fs_sel
& 7)) {
2094 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2095 vmx
->host_state
.fs_reload_needed
= 0;
2097 vmcs_write16(HOST_FS_SELECTOR
, 0);
2098 vmx
->host_state
.fs_reload_needed
= 1;
2100 savesegment(gs
, vmx
->host_state
.gs_sel
);
2101 if (!(vmx
->host_state
.gs_sel
& 7))
2102 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2104 vmcs_write16(HOST_GS_SELECTOR
, 0);
2105 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2108 #ifdef CONFIG_X86_64
2109 savesegment(ds
, vmx
->host_state
.ds_sel
);
2110 savesegment(es
, vmx
->host_state
.es_sel
);
2113 #ifdef CONFIG_X86_64
2114 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2115 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2117 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2118 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2121 #ifdef CONFIG_X86_64
2122 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2123 if (is_long_mode(&vmx
->vcpu
))
2124 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2126 if (boot_cpu_has(X86_FEATURE_MPX
))
2127 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2128 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2129 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2130 vmx
->guest_msrs
[i
].data
,
2131 vmx
->guest_msrs
[i
].mask
);
2134 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2136 if (!vmx
->host_state
.loaded
)
2139 ++vmx
->vcpu
.stat
.host_state_reload
;
2140 vmx
->host_state
.loaded
= 0;
2141 #ifdef CONFIG_X86_64
2142 if (is_long_mode(&vmx
->vcpu
))
2143 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2145 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2146 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2147 #ifdef CONFIG_X86_64
2148 load_gs_index(vmx
->host_state
.gs_sel
);
2150 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2153 if (vmx
->host_state
.fs_reload_needed
)
2154 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2155 #ifdef CONFIG_X86_64
2156 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2157 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2158 loadsegment(es
, vmx
->host_state
.es_sel
);
2161 invalidate_tss_limit();
2162 #ifdef CONFIG_X86_64
2163 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2165 if (vmx
->host_state
.msr_host_bndcfgs
)
2166 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2167 load_gdt(this_cpu_ptr(&host_gdt
));
2170 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2173 __vmx_load_host_state(vmx
);
2177 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2179 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2180 struct pi_desc old
, new;
2183 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2184 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2185 !kvm_vcpu_apicv_active(vcpu
))
2189 old
.control
= new.control
= pi_desc
->control
;
2192 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2193 * are two possible cases:
2194 * 1. After running 'pre_block', context switch
2195 * happened. For this case, 'sn' was set in
2196 * vmx_vcpu_put(), so we need to clear it here.
2197 * 2. After running 'pre_block', we were blocked,
2198 * and woken up by some other guy. For this case,
2199 * we don't need to do anything, 'pi_post_block'
2200 * will do everything for us. However, we cannot
2201 * check whether it is case #1 or case #2 here
2202 * (maybe, not needed), so we also clear sn here,
2203 * I think it is not a big deal.
2205 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2206 if (vcpu
->cpu
!= cpu
) {
2207 dest
= cpu_physical_id(cpu
);
2209 if (x2apic_enabled())
2212 new.ndst
= (dest
<< 8) & 0xFF00;
2215 /* set 'NV' to 'notification vector' */
2216 new.nv
= POSTED_INTR_VECTOR
;
2219 /* Allow posting non-urgent interrupts */
2221 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2222 new.control
) != old
.control
);
2225 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2227 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2228 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2232 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2233 * vcpu mutex is already taken.
2235 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2237 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2238 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2239 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2242 kvm_cpu_vmxon(phys_addr
);
2243 else if (!already_loaded
)
2244 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2246 if (!already_loaded
) {
2247 local_irq_disable();
2248 crash_disable_local_vmclear(cpu
);
2251 * Read loaded_vmcs->cpu should be before fetching
2252 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2253 * See the comments in __loaded_vmcs_clear().
2257 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2258 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2259 crash_enable_local_vmclear(cpu
);
2263 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2264 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2265 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2268 if (!already_loaded
) {
2269 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2270 unsigned long sysenter_esp
;
2272 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2275 * Linux uses per-cpu TSS and GDT, so set these when switching
2276 * processors. See 22.2.4.
2278 vmcs_writel(HOST_TR_BASE
,
2279 (unsigned long)this_cpu_ptr(&cpu_tss
));
2280 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
);
2283 * VM exits change the host TR limit to 0x67 after a VM
2284 * exit. This is okay, since 0x67 covers everything except
2285 * the IO bitmap and have have code to handle the IO bitmap
2286 * being lost after a VM exit.
2288 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2290 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2291 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2293 vmx
->loaded_vmcs
->cpu
= cpu
;
2296 /* Setup TSC multiplier */
2297 if (kvm_has_tsc_control
&&
2298 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2299 decache_tsc_multiplier(vmx
);
2301 vmx_vcpu_pi_load(vcpu
, cpu
);
2302 vmx
->host_pkru
= read_pkru();
2305 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2307 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2309 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2310 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2311 !kvm_vcpu_apicv_active(vcpu
))
2314 /* Set SN when the vCPU is preempted */
2315 if (vcpu
->preempted
)
2319 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2321 vmx_vcpu_pi_put(vcpu
);
2323 __vmx_load_host_state(to_vmx(vcpu
));
2324 if (!vmm_exclusive
) {
2325 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2331 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2334 * Return the cr0 value that a nested guest would read. This is a combination
2335 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2336 * its hypervisor (cr0_read_shadow).
2338 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2340 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2341 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2343 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2345 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2346 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2349 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2351 unsigned long rflags
, save_rflags
;
2353 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2354 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2355 rflags
= vmcs_readl(GUEST_RFLAGS
);
2356 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2357 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2358 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2359 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2361 to_vmx(vcpu
)->rflags
= rflags
;
2363 return to_vmx(vcpu
)->rflags
;
2366 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2368 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2369 to_vmx(vcpu
)->rflags
= rflags
;
2370 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2371 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2372 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2374 vmcs_writel(GUEST_RFLAGS
, rflags
);
2377 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2379 return to_vmx(vcpu
)->guest_pkru
;
2382 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2384 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2387 if (interruptibility
& GUEST_INTR_STATE_STI
)
2388 ret
|= KVM_X86_SHADOW_INT_STI
;
2389 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2390 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2395 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2397 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2398 u32 interruptibility
= interruptibility_old
;
2400 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2402 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2403 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2404 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2405 interruptibility
|= GUEST_INTR_STATE_STI
;
2407 if ((interruptibility
!= interruptibility_old
))
2408 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2411 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2415 rip
= kvm_rip_read(vcpu
);
2416 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2417 kvm_rip_write(vcpu
, rip
);
2419 /* skipping an emulated instruction also counts */
2420 vmx_set_interrupt_shadow(vcpu
, 0);
2424 * KVM wants to inject page-faults which it got to the guest. This function
2425 * checks whether in a nested guest, we need to inject them to L1 or L2.
2427 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2429 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2431 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2434 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2435 vmcs_read32(VM_EXIT_INTR_INFO
),
2436 vmcs_readl(EXIT_QUALIFICATION
));
2440 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2441 bool has_error_code
, u32 error_code
,
2444 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2445 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2447 if (!reinject
&& is_guest_mode(vcpu
) &&
2448 nested_vmx_check_exception(vcpu
, nr
))
2451 if (has_error_code
) {
2452 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2453 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2456 if (vmx
->rmode
.vm86_active
) {
2458 if (kvm_exception_is_soft(nr
))
2459 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2460 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2461 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2465 if (kvm_exception_is_soft(nr
)) {
2466 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2467 vmx
->vcpu
.arch
.event_exit_inst_len
);
2468 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2470 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2472 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2475 static bool vmx_rdtscp_supported(void)
2477 return cpu_has_vmx_rdtscp();
2480 static bool vmx_invpcid_supported(void)
2482 return cpu_has_vmx_invpcid() && enable_ept
;
2486 * Swap MSR entry in host/guest MSR entry array.
2488 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2490 struct shared_msr_entry tmp
;
2492 tmp
= vmx
->guest_msrs
[to
];
2493 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2494 vmx
->guest_msrs
[from
] = tmp
;
2497 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2499 unsigned long *msr_bitmap
;
2501 if (is_guest_mode(vcpu
))
2502 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2503 else if (cpu_has_secondary_exec_ctrls() &&
2504 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2505 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2506 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2507 if (is_long_mode(vcpu
))
2508 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2510 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2512 if (is_long_mode(vcpu
))
2513 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2515 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2518 if (is_long_mode(vcpu
))
2519 msr_bitmap
= vmx_msr_bitmap_longmode
;
2521 msr_bitmap
= vmx_msr_bitmap_legacy
;
2524 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2528 * Set up the vmcs to automatically save and restore system
2529 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2530 * mode, as fiddling with msrs is very expensive.
2532 static void setup_msrs(struct vcpu_vmx
*vmx
)
2534 int save_nmsrs
, index
;
2537 #ifdef CONFIG_X86_64
2538 if (is_long_mode(&vmx
->vcpu
)) {
2539 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2541 move_msr_up(vmx
, index
, save_nmsrs
++);
2542 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2544 move_msr_up(vmx
, index
, save_nmsrs
++);
2545 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2547 move_msr_up(vmx
, index
, save_nmsrs
++);
2548 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2549 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2550 move_msr_up(vmx
, index
, save_nmsrs
++);
2552 * MSR_STAR is only needed on long mode guests, and only
2553 * if efer.sce is enabled.
2555 index
= __find_msr_index(vmx
, MSR_STAR
);
2556 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2557 move_msr_up(vmx
, index
, save_nmsrs
++);
2560 index
= __find_msr_index(vmx
, MSR_EFER
);
2561 if (index
>= 0 && update_transition_efer(vmx
, index
))
2562 move_msr_up(vmx
, index
, save_nmsrs
++);
2564 vmx
->save_nmsrs
= save_nmsrs
;
2566 if (cpu_has_vmx_msr_bitmap())
2567 vmx_set_msr_bitmap(&vmx
->vcpu
);
2571 * reads and returns guest's timestamp counter "register"
2572 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2573 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2575 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2577 u64 host_tsc
, tsc_offset
;
2580 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2581 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2585 * writes 'offset' into guest's timestamp counter offset register
2587 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2589 if (is_guest_mode(vcpu
)) {
2591 * We're here if L1 chose not to trap WRMSR to TSC. According
2592 * to the spec, this should set L1's TSC; The offset that L1
2593 * set for L2 remains unchanged, and still needs to be added
2594 * to the newly set TSC to get L2's TSC.
2596 struct vmcs12
*vmcs12
;
2597 /* recalculate vmcs02.TSC_OFFSET: */
2598 vmcs12
= get_vmcs12(vcpu
);
2599 vmcs_write64(TSC_OFFSET
, offset
+
2600 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2601 vmcs12
->tsc_offset
: 0));
2603 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2604 vmcs_read64(TSC_OFFSET
), offset
);
2605 vmcs_write64(TSC_OFFSET
, offset
);
2609 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2611 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2612 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2616 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2617 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2618 * all guests if the "nested" module option is off, and can also be disabled
2619 * for a single guest by disabling its VMX cpuid bit.
2621 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2623 return nested
&& guest_cpuid_has_vmx(vcpu
);
2627 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2628 * returned for the various VMX controls MSRs when nested VMX is enabled.
2629 * The same values should also be used to verify that vmcs12 control fields are
2630 * valid during nested entry from L1 to L2.
2631 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2632 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2633 * bit in the high half is on if the corresponding bit in the control field
2634 * may be on. See also vmx_control_verify().
2636 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2639 * Note that as a general rule, the high half of the MSRs (bits in
2640 * the control fields which may be 1) should be initialized by the
2641 * intersection of the underlying hardware's MSR (i.e., features which
2642 * can be supported) and the list of features we want to expose -
2643 * because they are known to be properly supported in our code.
2644 * Also, usually, the low half of the MSRs (bits which must be 1) can
2645 * be set to 0, meaning that L1 may turn off any of these bits. The
2646 * reason is that if one of these bits is necessary, it will appear
2647 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2648 * fields of vmcs01 and vmcs02, will turn these bits off - and
2649 * nested_vmx_exit_handled() will not pass related exits to L1.
2650 * These rules have exceptions below.
2653 /* pin-based controls */
2654 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2655 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2656 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2657 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2658 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2659 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2660 PIN_BASED_EXT_INTR_MASK
|
2661 PIN_BASED_NMI_EXITING
|
2662 PIN_BASED_VIRTUAL_NMIS
;
2663 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2664 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2665 PIN_BASED_VMX_PREEMPTION_TIMER
;
2666 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2667 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2668 PIN_BASED_POSTED_INTR
;
2671 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2672 vmx
->nested
.nested_vmx_exit_ctls_low
,
2673 vmx
->nested
.nested_vmx_exit_ctls_high
);
2674 vmx
->nested
.nested_vmx_exit_ctls_low
=
2675 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2677 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2678 #ifdef CONFIG_X86_64
2679 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2681 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2682 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2683 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2684 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2685 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2687 if (kvm_mpx_supported())
2688 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2690 /* We support free control of debug control saving. */
2691 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2693 /* entry controls */
2694 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2695 vmx
->nested
.nested_vmx_entry_ctls_low
,
2696 vmx
->nested
.nested_vmx_entry_ctls_high
);
2697 vmx
->nested
.nested_vmx_entry_ctls_low
=
2698 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2699 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2700 #ifdef CONFIG_X86_64
2701 VM_ENTRY_IA32E_MODE
|
2703 VM_ENTRY_LOAD_IA32_PAT
;
2704 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2705 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2706 if (kvm_mpx_supported())
2707 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2709 /* We support free control of debug control loading. */
2710 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2712 /* cpu-based controls */
2713 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2714 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2715 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2716 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2717 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2718 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2719 CPU_BASED_VIRTUAL_INTR_PENDING
|
2720 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2721 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2722 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2723 CPU_BASED_CR3_STORE_EXITING
|
2724 #ifdef CONFIG_X86_64
2725 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2727 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2728 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2729 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2730 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2731 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2733 * We can allow some features even when not supported by the
2734 * hardware. For example, L1 can specify an MSR bitmap - and we
2735 * can use it to avoid exits to L1 - even when L0 runs L2
2736 * without MSR bitmaps.
2738 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2739 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2740 CPU_BASED_USE_MSR_BITMAPS
;
2742 /* We support free control of CR3 access interception. */
2743 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2744 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2746 /* secondary cpu-based controls */
2747 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2748 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2749 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2750 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2751 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2752 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2753 SECONDARY_EXEC_RDTSCP
|
2754 SECONDARY_EXEC_DESC
|
2755 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2756 SECONDARY_EXEC_ENABLE_VPID
|
2757 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2758 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2759 SECONDARY_EXEC_WBINVD_EXITING
|
2760 SECONDARY_EXEC_XSAVES
;
2763 /* nested EPT: emulate EPT also to L1 */
2764 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2765 SECONDARY_EXEC_ENABLE_EPT
;
2766 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2767 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2769 if (cpu_has_vmx_ept_execute_only())
2770 vmx
->nested
.nested_vmx_ept_caps
|=
2771 VMX_EPT_EXECUTE_ONLY_BIT
;
2772 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2773 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2774 VMX_EPT_EXTENT_CONTEXT_BIT
;
2776 vmx
->nested
.nested_vmx_ept_caps
= 0;
2779 * Old versions of KVM use the single-context version without
2780 * checking for support, so declare that it is supported even
2781 * though it is treated as global context. The alternative is
2782 * not failing the single-context invvpid, and it is worse.
2785 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2786 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2788 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2790 if (enable_unrestricted_guest
)
2791 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2792 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2794 /* miscellaneous data */
2795 rdmsr(MSR_IA32_VMX_MISC
,
2796 vmx
->nested
.nested_vmx_misc_low
,
2797 vmx
->nested
.nested_vmx_misc_high
);
2798 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2799 vmx
->nested
.nested_vmx_misc_low
|=
2800 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2801 VMX_MISC_ACTIVITY_HLT
;
2802 vmx
->nested
.nested_vmx_misc_high
= 0;
2805 * This MSR reports some information about VMX support. We
2806 * should return information about the VMX we emulate for the
2807 * guest, and the VMCS structure we give it - not about the
2808 * VMX support of the underlying hardware.
2810 vmx
->nested
.nested_vmx_basic
=
2812 VMX_BASIC_TRUE_CTLS
|
2813 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2814 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2816 if (cpu_has_vmx_basic_inout())
2817 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2820 * These MSRs specify bits which the guest must keep fixed on
2821 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2822 * We picked the standard core2 setting.
2824 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2825 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2826 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2827 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2829 /* These MSRs specify bits which the guest must keep fixed off. */
2830 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2831 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2833 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2834 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2838 * if fixed0[i] == 1: val[i] must be 1
2839 * if fixed1[i] == 0: val[i] must be 0
2841 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2843 return ((val
& fixed1
) | fixed0
) == val
;
2846 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2848 return fixed_bits_valid(control
, low
, high
);
2851 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2853 return low
| ((u64
)high
<< 32);
2856 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2861 return (superset
| subset
) == superset
;
2864 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2866 const u64 feature_and_reserved
=
2867 /* feature (except bit 48; see below) */
2868 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2870 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2871 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2873 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2877 * KVM does not emulate a version of VMX that constrains physical
2878 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2880 if (data
& BIT_ULL(48))
2883 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2884 vmx_basic_vmcs_revision_id(data
))
2887 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2890 vmx
->nested
.nested_vmx_basic
= data
;
2895 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2900 switch (msr_index
) {
2901 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2902 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2903 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2905 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2906 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2907 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2909 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2910 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2911 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2913 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2914 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2915 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2917 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2918 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2919 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2925 supported
= vmx_control_msr(*lowp
, *highp
);
2927 /* Check must-be-1 bits are still 1. */
2928 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2931 /* Check must-be-0 bits are still 0. */
2932 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2936 *highp
= data
>> 32;
2940 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2942 const u64 feature_and_reserved_bits
=
2944 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2945 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2947 GENMASK_ULL(13, 9) | BIT_ULL(31);
2950 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
2951 vmx
->nested
.nested_vmx_misc_high
);
2953 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2956 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
2957 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2958 vmx_misc_preemption_timer_rate(data
) !=
2959 vmx_misc_preemption_timer_rate(vmx_misc
))
2962 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2965 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2968 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2971 vmx
->nested
.nested_vmx_misc_low
= data
;
2972 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
2976 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2978 u64 vmx_ept_vpid_cap
;
2980 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
2981 vmx
->nested
.nested_vmx_vpid_caps
);
2983 /* Every bit is either reserved or a feature bit. */
2984 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2987 vmx
->nested
.nested_vmx_ept_caps
= data
;
2988 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
2992 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2996 switch (msr_index
) {
2997 case MSR_IA32_VMX_CR0_FIXED0
:
2998 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3000 case MSR_IA32_VMX_CR4_FIXED0
:
3001 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3008 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3009 * must be 1 in the restored value.
3011 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3019 * Called when userspace is restoring VMX MSRs.
3021 * Returns 0 on success, non-0 otherwise.
3023 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3025 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3027 switch (msr_index
) {
3028 case MSR_IA32_VMX_BASIC
:
3029 return vmx_restore_vmx_basic(vmx
, data
);
3030 case MSR_IA32_VMX_PINBASED_CTLS
:
3031 case MSR_IA32_VMX_PROCBASED_CTLS
:
3032 case MSR_IA32_VMX_EXIT_CTLS
:
3033 case MSR_IA32_VMX_ENTRY_CTLS
:
3035 * The "non-true" VMX capability MSRs are generated from the
3036 * "true" MSRs, so we do not support restoring them directly.
3038 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3039 * should restore the "true" MSRs with the must-be-1 bits
3040 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3041 * DEFAULT SETTINGS".
3044 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3045 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3046 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3047 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3048 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3049 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3050 case MSR_IA32_VMX_MISC
:
3051 return vmx_restore_vmx_misc(vmx
, data
);
3052 case MSR_IA32_VMX_CR0_FIXED0
:
3053 case MSR_IA32_VMX_CR4_FIXED0
:
3054 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3055 case MSR_IA32_VMX_CR0_FIXED1
:
3056 case MSR_IA32_VMX_CR4_FIXED1
:
3058 * These MSRs are generated based on the vCPU's CPUID, so we
3059 * do not support restoring them directly.
3062 case MSR_IA32_VMX_EPT_VPID_CAP
:
3063 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3064 case MSR_IA32_VMX_VMCS_ENUM
:
3065 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3069 * The rest of the VMX capability MSRs do not support restore.
3075 /* Returns 0 on success, non-0 otherwise. */
3076 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3078 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3080 switch (msr_index
) {
3081 case MSR_IA32_VMX_BASIC
:
3082 *pdata
= vmx
->nested
.nested_vmx_basic
;
3084 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3085 case MSR_IA32_VMX_PINBASED_CTLS
:
3086 *pdata
= vmx_control_msr(
3087 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3088 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3089 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3090 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3092 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3093 case MSR_IA32_VMX_PROCBASED_CTLS
:
3094 *pdata
= vmx_control_msr(
3095 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3096 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3097 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3098 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3100 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3101 case MSR_IA32_VMX_EXIT_CTLS
:
3102 *pdata
= vmx_control_msr(
3103 vmx
->nested
.nested_vmx_exit_ctls_low
,
3104 vmx
->nested
.nested_vmx_exit_ctls_high
);
3105 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3106 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3108 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3109 case MSR_IA32_VMX_ENTRY_CTLS
:
3110 *pdata
= vmx_control_msr(
3111 vmx
->nested
.nested_vmx_entry_ctls_low
,
3112 vmx
->nested
.nested_vmx_entry_ctls_high
);
3113 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3114 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3116 case MSR_IA32_VMX_MISC
:
3117 *pdata
= vmx_control_msr(
3118 vmx
->nested
.nested_vmx_misc_low
,
3119 vmx
->nested
.nested_vmx_misc_high
);
3121 case MSR_IA32_VMX_CR0_FIXED0
:
3122 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3124 case MSR_IA32_VMX_CR0_FIXED1
:
3125 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3127 case MSR_IA32_VMX_CR4_FIXED0
:
3128 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3130 case MSR_IA32_VMX_CR4_FIXED1
:
3131 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3133 case MSR_IA32_VMX_VMCS_ENUM
:
3134 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3136 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3137 *pdata
= vmx_control_msr(
3138 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3139 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3141 case MSR_IA32_VMX_EPT_VPID_CAP
:
3142 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3143 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3152 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3155 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3157 return !(val
& ~valid_bits
);
3161 * Reads an msr value (of 'msr_index') into 'pdata'.
3162 * Returns 0 on success, non-0 otherwise.
3163 * Assumes vcpu_load() was already called.
3165 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3167 struct shared_msr_entry
*msr
;
3169 switch (msr_info
->index
) {
3170 #ifdef CONFIG_X86_64
3172 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3175 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3177 case MSR_KERNEL_GS_BASE
:
3178 vmx_load_host_state(to_vmx(vcpu
));
3179 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3183 return kvm_get_msr_common(vcpu
, msr_info
);
3185 msr_info
->data
= guest_read_tsc(vcpu
);
3187 case MSR_IA32_SYSENTER_CS
:
3188 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3190 case MSR_IA32_SYSENTER_EIP
:
3191 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3193 case MSR_IA32_SYSENTER_ESP
:
3194 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3196 case MSR_IA32_BNDCFGS
:
3197 if (!kvm_mpx_supported())
3199 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3201 case MSR_IA32_MCG_EXT_CTL
:
3202 if (!msr_info
->host_initiated
&&
3203 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3204 FEATURE_CONTROL_LMCE
))
3206 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3208 case MSR_IA32_FEATURE_CONTROL
:
3209 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3211 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3212 if (!nested_vmx_allowed(vcpu
))
3214 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3216 if (!vmx_xsaves_supported())
3218 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3221 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3223 /* Otherwise falls through */
3225 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3227 msr_info
->data
= msr
->data
;
3230 return kvm_get_msr_common(vcpu
, msr_info
);
3236 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3239 * Writes msr value into into the appropriate "register".
3240 * Returns 0 on success, non-0 otherwise.
3241 * Assumes vcpu_load() was already called.
3243 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3245 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3246 struct shared_msr_entry
*msr
;
3248 u32 msr_index
= msr_info
->index
;
3249 u64 data
= msr_info
->data
;
3251 switch (msr_index
) {
3253 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3255 #ifdef CONFIG_X86_64
3257 vmx_segment_cache_clear(vmx
);
3258 vmcs_writel(GUEST_FS_BASE
, data
);
3261 vmx_segment_cache_clear(vmx
);
3262 vmcs_writel(GUEST_GS_BASE
, data
);
3264 case MSR_KERNEL_GS_BASE
:
3265 vmx_load_host_state(vmx
);
3266 vmx
->msr_guest_kernel_gs_base
= data
;
3269 case MSR_IA32_SYSENTER_CS
:
3270 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3272 case MSR_IA32_SYSENTER_EIP
:
3273 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3275 case MSR_IA32_SYSENTER_ESP
:
3276 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3278 case MSR_IA32_BNDCFGS
:
3279 if (!kvm_mpx_supported())
3281 vmcs_write64(GUEST_BNDCFGS
, data
);
3284 kvm_write_tsc(vcpu
, msr_info
);
3286 case MSR_IA32_CR_PAT
:
3287 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3288 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3290 vmcs_write64(GUEST_IA32_PAT
, data
);
3291 vcpu
->arch
.pat
= data
;
3294 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3296 case MSR_IA32_TSC_ADJUST
:
3297 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3299 case MSR_IA32_MCG_EXT_CTL
:
3300 if ((!msr_info
->host_initiated
&&
3301 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3302 FEATURE_CONTROL_LMCE
)) ||
3303 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3305 vcpu
->arch
.mcg_ext_ctl
= data
;
3307 case MSR_IA32_FEATURE_CONTROL
:
3308 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3309 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3310 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3312 vmx
->msr_ia32_feature_control
= data
;
3313 if (msr_info
->host_initiated
&& data
== 0)
3314 vmx_leave_nested(vcpu
);
3316 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3317 if (!msr_info
->host_initiated
)
3318 return 1; /* they are read-only */
3319 if (!nested_vmx_allowed(vcpu
))
3321 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3323 if (!vmx_xsaves_supported())
3326 * The only supported bit as of Skylake is bit 8, but
3327 * it is not supported on KVM.
3331 vcpu
->arch
.ia32_xss
= data
;
3332 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3333 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3334 vcpu
->arch
.ia32_xss
, host_xss
);
3336 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3339 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3341 /* Check reserved bit, higher 32 bits should be zero */
3342 if ((data
>> 32) != 0)
3344 /* Otherwise falls through */
3346 msr
= find_msr_entry(vmx
, msr_index
);
3348 u64 old_msr_data
= msr
->data
;
3350 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3352 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3356 msr
->data
= old_msr_data
;
3360 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3366 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3368 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3371 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3374 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3376 case VCPU_EXREG_PDPTR
:
3378 ept_save_pdptrs(vcpu
);
3385 static __init
int cpu_has_kvm_support(void)
3387 return cpu_has_vmx();
3390 static __init
int vmx_disabled_by_bios(void)
3394 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3395 if (msr
& FEATURE_CONTROL_LOCKED
) {
3396 /* launched w/ TXT and VMX disabled */
3397 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3400 /* launched w/o TXT and VMX only enabled w/ TXT */
3401 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3402 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3403 && !tboot_enabled()) {
3404 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3405 "activate TXT before enabling KVM\n");
3408 /* launched w/o TXT and VMX disabled */
3409 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3410 && !tboot_enabled())
3417 static void kvm_cpu_vmxon(u64 addr
)
3419 intel_pt_handle_vmx(1);
3421 asm volatile (ASM_VMX_VMXON_RAX
3422 : : "a"(&addr
), "m"(addr
)
3426 static int hardware_enable(void)
3428 int cpu
= raw_smp_processor_id();
3429 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3432 if (cr4_read_shadow() & X86_CR4_VMXE
)
3435 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3436 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3437 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3440 * Now we can enable the vmclear operation in kdump
3441 * since the loaded_vmcss_on_cpu list on this cpu
3442 * has been initialized.
3444 * Though the cpu is not in VMX operation now, there
3445 * is no problem to enable the vmclear operation
3446 * for the loaded_vmcss_on_cpu list is empty!
3448 crash_enable_local_vmclear(cpu
);
3450 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3452 test_bits
= FEATURE_CONTROL_LOCKED
;
3453 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3454 if (tboot_enabled())
3455 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3457 if ((old
& test_bits
) != test_bits
) {
3458 /* enable and lock */
3459 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3461 cr4_set_bits(X86_CR4_VMXE
);
3463 if (vmm_exclusive
) {
3464 kvm_cpu_vmxon(phys_addr
);
3468 native_store_gdt(this_cpu_ptr(&host_gdt
));
3473 static void vmclear_local_loaded_vmcss(void)
3475 int cpu
= raw_smp_processor_id();
3476 struct loaded_vmcs
*v
, *n
;
3478 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3479 loaded_vmcss_on_cpu_link
)
3480 __loaded_vmcs_clear(v
);
3484 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3487 static void kvm_cpu_vmxoff(void)
3489 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3491 intel_pt_handle_vmx(0);
3494 static void hardware_disable(void)
3496 if (vmm_exclusive
) {
3497 vmclear_local_loaded_vmcss();
3500 cr4_clear_bits(X86_CR4_VMXE
);
3503 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3504 u32 msr
, u32
*result
)
3506 u32 vmx_msr_low
, vmx_msr_high
;
3507 u32 ctl
= ctl_min
| ctl_opt
;
3509 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3511 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3512 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3514 /* Ensure minimum (required) set of control bits are supported. */
3522 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3524 u32 vmx_msr_low
, vmx_msr_high
;
3526 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3527 return vmx_msr_high
& ctl
;
3530 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3532 u32 vmx_msr_low
, vmx_msr_high
;
3533 u32 min
, opt
, min2
, opt2
;
3534 u32 _pin_based_exec_control
= 0;
3535 u32 _cpu_based_exec_control
= 0;
3536 u32 _cpu_based_2nd_exec_control
= 0;
3537 u32 _vmexit_control
= 0;
3538 u32 _vmentry_control
= 0;
3540 min
= CPU_BASED_HLT_EXITING
|
3541 #ifdef CONFIG_X86_64
3542 CPU_BASED_CR8_LOAD_EXITING
|
3543 CPU_BASED_CR8_STORE_EXITING
|
3545 CPU_BASED_CR3_LOAD_EXITING
|
3546 CPU_BASED_CR3_STORE_EXITING
|
3547 CPU_BASED_USE_IO_BITMAPS
|
3548 CPU_BASED_MOV_DR_EXITING
|
3549 CPU_BASED_USE_TSC_OFFSETING
|
3550 CPU_BASED_MWAIT_EXITING
|
3551 CPU_BASED_MONITOR_EXITING
|
3552 CPU_BASED_INVLPG_EXITING
|
3553 CPU_BASED_RDPMC_EXITING
;
3555 opt
= CPU_BASED_TPR_SHADOW
|
3556 CPU_BASED_USE_MSR_BITMAPS
|
3557 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3558 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3559 &_cpu_based_exec_control
) < 0)
3561 #ifdef CONFIG_X86_64
3562 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3563 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3564 ~CPU_BASED_CR8_STORE_EXITING
;
3566 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3568 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3569 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3570 SECONDARY_EXEC_WBINVD_EXITING
|
3571 SECONDARY_EXEC_ENABLE_VPID
|
3572 SECONDARY_EXEC_ENABLE_EPT
|
3573 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3574 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3575 SECONDARY_EXEC_RDTSCP
|
3576 SECONDARY_EXEC_ENABLE_INVPCID
|
3577 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3578 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3579 SECONDARY_EXEC_SHADOW_VMCS
|
3580 SECONDARY_EXEC_XSAVES
|
3581 SECONDARY_EXEC_ENABLE_PML
|
3582 SECONDARY_EXEC_TSC_SCALING
;
3583 if (adjust_vmx_controls(min2
, opt2
,
3584 MSR_IA32_VMX_PROCBASED_CTLS2
,
3585 &_cpu_based_2nd_exec_control
) < 0)
3588 #ifndef CONFIG_X86_64
3589 if (!(_cpu_based_2nd_exec_control
&
3590 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3591 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3594 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3595 _cpu_based_2nd_exec_control
&= ~(
3596 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3597 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3598 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3600 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3601 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3603 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3604 CPU_BASED_CR3_STORE_EXITING
|
3605 CPU_BASED_INVLPG_EXITING
);
3606 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3607 vmx_capability
.ept
, vmx_capability
.vpid
);
3610 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3611 #ifdef CONFIG_X86_64
3612 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3614 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3615 VM_EXIT_CLEAR_BNDCFGS
;
3616 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3617 &_vmexit_control
) < 0)
3620 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3621 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3622 PIN_BASED_VMX_PREEMPTION_TIMER
;
3623 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3624 &_pin_based_exec_control
) < 0)
3627 if (cpu_has_broken_vmx_preemption_timer())
3628 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3629 if (!(_cpu_based_2nd_exec_control
&
3630 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3631 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3633 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3634 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3635 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3636 &_vmentry_control
) < 0)
3639 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3641 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3642 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3645 #ifdef CONFIG_X86_64
3646 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3647 if (vmx_msr_high
& (1u<<16))
3651 /* Require Write-Back (WB) memory type for VMCS accesses. */
3652 if (((vmx_msr_high
>> 18) & 15) != 6)
3655 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3656 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3657 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3658 vmcs_conf
->revision_id
= vmx_msr_low
;
3660 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3661 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3662 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3663 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3664 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3666 cpu_has_load_ia32_efer
=
3667 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3668 VM_ENTRY_LOAD_IA32_EFER
)
3669 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3670 VM_EXIT_LOAD_IA32_EFER
);
3672 cpu_has_load_perf_global_ctrl
=
3673 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3674 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3675 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3676 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3679 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3680 * but due to errata below it can't be used. Workaround is to use
3681 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3683 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3688 * BC86,AAY89,BD102 (model 44)
3692 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3693 switch (boot_cpu_data
.x86_model
) {
3699 cpu_has_load_perf_global_ctrl
= false;
3700 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3701 "does not work properly. Using workaround\n");
3708 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3709 rdmsrl(MSR_IA32_XSS
, host_xss
);
3714 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3716 int node
= cpu_to_node(cpu
);
3720 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3723 vmcs
= page_address(pages
);
3724 memset(vmcs
, 0, vmcs_config
.size
);
3725 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3729 static struct vmcs
*alloc_vmcs(void)
3731 return alloc_vmcs_cpu(raw_smp_processor_id());
3734 static void free_vmcs(struct vmcs
*vmcs
)
3736 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3740 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3742 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3744 if (!loaded_vmcs
->vmcs
)
3746 loaded_vmcs_clear(loaded_vmcs
);
3747 free_vmcs(loaded_vmcs
->vmcs
);
3748 loaded_vmcs
->vmcs
= NULL
;
3749 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3752 static void free_kvm_area(void)
3756 for_each_possible_cpu(cpu
) {
3757 free_vmcs(per_cpu(vmxarea
, cpu
));
3758 per_cpu(vmxarea
, cpu
) = NULL
;
3762 static void init_vmcs_shadow_fields(void)
3766 /* No checks for read only fields yet */
3768 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3769 switch (shadow_read_write_fields
[i
]) {
3771 if (!kvm_mpx_supported())
3779 shadow_read_write_fields
[j
] =
3780 shadow_read_write_fields
[i
];
3783 max_shadow_read_write_fields
= j
;
3785 /* shadowed fields guest access without vmexit */
3786 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3787 clear_bit(shadow_read_write_fields
[i
],
3788 vmx_vmwrite_bitmap
);
3789 clear_bit(shadow_read_write_fields
[i
],
3792 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3793 clear_bit(shadow_read_only_fields
[i
],
3797 static __init
int alloc_kvm_area(void)
3801 for_each_possible_cpu(cpu
) {
3804 vmcs
= alloc_vmcs_cpu(cpu
);
3810 per_cpu(vmxarea
, cpu
) = vmcs
;
3815 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3817 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3820 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3821 struct kvm_segment
*save
)
3823 if (!emulate_invalid_guest_state
) {
3825 * CS and SS RPL should be equal during guest entry according
3826 * to VMX spec, but in reality it is not always so. Since vcpu
3827 * is in the middle of the transition from real mode to
3828 * protected mode it is safe to assume that RPL 0 is a good
3831 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3832 save
->selector
&= ~SEGMENT_RPL_MASK
;
3833 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3836 vmx_set_segment(vcpu
, save
, seg
);
3839 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3841 unsigned long flags
;
3842 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3845 * Update real mode segment cache. It may be not up-to-date if sement
3846 * register was written while vcpu was in a guest mode.
3848 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3849 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3850 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3851 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3852 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3853 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3855 vmx
->rmode
.vm86_active
= 0;
3857 vmx_segment_cache_clear(vmx
);
3859 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3861 flags
= vmcs_readl(GUEST_RFLAGS
);
3862 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3863 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3864 vmcs_writel(GUEST_RFLAGS
, flags
);
3866 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3867 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3869 update_exception_bitmap(vcpu
);
3871 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3872 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3873 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3874 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3875 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3876 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3879 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3881 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3882 struct kvm_segment var
= *save
;
3885 if (seg
== VCPU_SREG_CS
)
3888 if (!emulate_invalid_guest_state
) {
3889 var
.selector
= var
.base
>> 4;
3890 var
.base
= var
.base
& 0xffff0;
3900 if (save
->base
& 0xf)
3901 printk_once(KERN_WARNING
"kvm: segment base is not "
3902 "paragraph aligned when entering "
3903 "protected mode (seg=%d)", seg
);
3906 vmcs_write16(sf
->selector
, var
.selector
);
3907 vmcs_writel(sf
->base
, var
.base
);
3908 vmcs_write32(sf
->limit
, var
.limit
);
3909 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3912 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3914 unsigned long flags
;
3915 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3917 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3918 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3919 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3920 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3921 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3922 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3923 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3925 vmx
->rmode
.vm86_active
= 1;
3928 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3929 * vcpu. Warn the user that an update is overdue.
3931 if (!vcpu
->kvm
->arch
.tss_addr
)
3932 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3933 "called before entering vcpu\n");
3935 vmx_segment_cache_clear(vmx
);
3937 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3938 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3939 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3941 flags
= vmcs_readl(GUEST_RFLAGS
);
3942 vmx
->rmode
.save_rflags
= flags
;
3944 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3946 vmcs_writel(GUEST_RFLAGS
, flags
);
3947 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3948 update_exception_bitmap(vcpu
);
3950 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3951 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3952 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3953 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3954 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3955 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3957 kvm_mmu_reset_context(vcpu
);
3960 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3962 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3963 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3969 * Force kernel_gs_base reloading before EFER changes, as control
3970 * of this msr depends on is_long_mode().
3972 vmx_load_host_state(to_vmx(vcpu
));
3973 vcpu
->arch
.efer
= efer
;
3974 if (efer
& EFER_LMA
) {
3975 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3978 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3980 msr
->data
= efer
& ~EFER_LME
;
3985 #ifdef CONFIG_X86_64
3987 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3991 vmx_segment_cache_clear(to_vmx(vcpu
));
3993 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3994 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3995 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3997 vmcs_write32(GUEST_TR_AR_BYTES
,
3998 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3999 | VMX_AR_TYPE_BUSY_64_TSS
);
4001 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4004 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4006 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4007 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4012 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4014 vpid_sync_context(vpid
);
4016 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4018 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
4022 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4024 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4027 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4030 vmx_flush_tlb(vcpu
);
4033 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4035 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4037 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4038 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4041 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4043 if (enable_ept
&& is_paging(vcpu
))
4044 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4045 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4048 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4050 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4052 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4053 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4056 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4058 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4060 if (!test_bit(VCPU_EXREG_PDPTR
,
4061 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4064 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4065 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4066 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4067 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4068 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4072 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4074 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4076 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4077 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4078 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4079 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4080 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4083 __set_bit(VCPU_EXREG_PDPTR
,
4084 (unsigned long *)&vcpu
->arch
.regs_avail
);
4085 __set_bit(VCPU_EXREG_PDPTR
,
4086 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4089 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4091 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4092 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4093 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4095 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4096 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4097 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4098 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4100 return fixed_bits_valid(val
, fixed0
, fixed1
);
4103 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4105 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4106 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4108 return fixed_bits_valid(val
, fixed0
, fixed1
);
4111 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4113 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4114 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4116 return fixed_bits_valid(val
, fixed0
, fixed1
);
4119 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4120 #define nested_guest_cr4_valid nested_cr4_valid
4121 #define nested_host_cr4_valid nested_cr4_valid
4123 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4125 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4127 struct kvm_vcpu
*vcpu
)
4129 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4130 vmx_decache_cr3(vcpu
);
4131 if (!(cr0
& X86_CR0_PG
)) {
4132 /* From paging/starting to nonpaging */
4133 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4134 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4135 (CPU_BASED_CR3_LOAD_EXITING
|
4136 CPU_BASED_CR3_STORE_EXITING
));
4137 vcpu
->arch
.cr0
= cr0
;
4138 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4139 } else if (!is_paging(vcpu
)) {
4140 /* From nonpaging to paging */
4141 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4142 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4143 ~(CPU_BASED_CR3_LOAD_EXITING
|
4144 CPU_BASED_CR3_STORE_EXITING
));
4145 vcpu
->arch
.cr0
= cr0
;
4146 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4149 if (!(cr0
& X86_CR0_WP
))
4150 *hw_cr0
&= ~X86_CR0_WP
;
4153 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4156 unsigned long hw_cr0
;
4158 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4159 if (enable_unrestricted_guest
)
4160 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4162 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4164 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4167 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4171 #ifdef CONFIG_X86_64
4172 if (vcpu
->arch
.efer
& EFER_LME
) {
4173 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4175 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4181 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4183 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4184 vmcs_writel(GUEST_CR0
, hw_cr0
);
4185 vcpu
->arch
.cr0
= cr0
;
4187 /* depends on vcpu->arch.cr0 to be set to a new value */
4188 vmx
->emulation_required
= emulation_required(vcpu
);
4191 static u64
construct_eptp(unsigned long root_hpa
)
4195 /* TODO write the value reading from MSR */
4196 eptp
= VMX_EPT_DEFAULT_MT
|
4197 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4198 if (enable_ept_ad_bits
)
4199 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4200 eptp
|= (root_hpa
& PAGE_MASK
);
4205 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4207 unsigned long guest_cr3
;
4212 eptp
= construct_eptp(cr3
);
4213 vmcs_write64(EPT_POINTER
, eptp
);
4214 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4215 guest_cr3
= kvm_read_cr3(vcpu
);
4217 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4218 ept_load_pdptrs(vcpu
);
4221 vmx_flush_tlb(vcpu
);
4222 vmcs_writel(GUEST_CR3
, guest_cr3
);
4225 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4228 * Pass through host's Machine Check Enable value to hw_cr4, which
4229 * is in force while we are in guest mode. Do not let guests control
4230 * this bit, even if host CR4.MCE == 0.
4232 unsigned long hw_cr4
=
4233 (cr4_read_shadow() & X86_CR4_MCE
) |
4234 (cr4
& ~X86_CR4_MCE
) |
4235 (to_vmx(vcpu
)->rmode
.vm86_active
?
4236 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4238 if (cr4
& X86_CR4_VMXE
) {
4240 * To use VMXON (and later other VMX instructions), a guest
4241 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4242 * So basically the check on whether to allow nested VMX
4245 if (!nested_vmx_allowed(vcpu
))
4249 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4252 vcpu
->arch
.cr4
= cr4
;
4254 if (!is_paging(vcpu
)) {
4255 hw_cr4
&= ~X86_CR4_PAE
;
4256 hw_cr4
|= X86_CR4_PSE
;
4257 } else if (!(cr4
& X86_CR4_PAE
)) {
4258 hw_cr4
&= ~X86_CR4_PAE
;
4262 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4264 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4265 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4266 * to be manually disabled when guest switches to non-paging
4269 * If !enable_unrestricted_guest, the CPU is always running
4270 * with CR0.PG=1 and CR4 needs to be modified.
4271 * If enable_unrestricted_guest, the CPU automatically
4272 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4274 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4276 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4277 vmcs_writel(GUEST_CR4
, hw_cr4
);
4281 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4282 struct kvm_segment
*var
, int seg
)
4284 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4287 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4288 *var
= vmx
->rmode
.segs
[seg
];
4289 if (seg
== VCPU_SREG_TR
4290 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4292 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4293 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4296 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4297 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4298 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4299 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4300 var
->unusable
= (ar
>> 16) & 1;
4301 var
->type
= ar
& 15;
4302 var
->s
= (ar
>> 4) & 1;
4303 var
->dpl
= (ar
>> 5) & 3;
4305 * Some userspaces do not preserve unusable property. Since usable
4306 * segment has to be present according to VMX spec we can use present
4307 * property to amend userspace bug by making unusable segment always
4308 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4309 * segment as unusable.
4311 var
->present
= !var
->unusable
;
4312 var
->avl
= (ar
>> 12) & 1;
4313 var
->l
= (ar
>> 13) & 1;
4314 var
->db
= (ar
>> 14) & 1;
4315 var
->g
= (ar
>> 15) & 1;
4318 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4320 struct kvm_segment s
;
4322 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4323 vmx_get_segment(vcpu
, &s
, seg
);
4326 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4329 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4333 if (unlikely(vmx
->rmode
.vm86_active
))
4336 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4337 return VMX_AR_DPL(ar
);
4341 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4345 if (var
->unusable
|| !var
->present
)
4348 ar
= var
->type
& 15;
4349 ar
|= (var
->s
& 1) << 4;
4350 ar
|= (var
->dpl
& 3) << 5;
4351 ar
|= (var
->present
& 1) << 7;
4352 ar
|= (var
->avl
& 1) << 12;
4353 ar
|= (var
->l
& 1) << 13;
4354 ar
|= (var
->db
& 1) << 14;
4355 ar
|= (var
->g
& 1) << 15;
4361 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4362 struct kvm_segment
*var
, int seg
)
4364 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4365 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4367 vmx_segment_cache_clear(vmx
);
4369 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4370 vmx
->rmode
.segs
[seg
] = *var
;
4371 if (seg
== VCPU_SREG_TR
)
4372 vmcs_write16(sf
->selector
, var
->selector
);
4374 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4378 vmcs_writel(sf
->base
, var
->base
);
4379 vmcs_write32(sf
->limit
, var
->limit
);
4380 vmcs_write16(sf
->selector
, var
->selector
);
4383 * Fix the "Accessed" bit in AR field of segment registers for older
4385 * IA32 arch specifies that at the time of processor reset the
4386 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4387 * is setting it to 0 in the userland code. This causes invalid guest
4388 * state vmexit when "unrestricted guest" mode is turned on.
4389 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4390 * tree. Newer qemu binaries with that qemu fix would not need this
4393 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4394 var
->type
|= 0x1; /* Accessed */
4396 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4399 vmx
->emulation_required
= emulation_required(vcpu
);
4402 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4404 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4406 *db
= (ar
>> 14) & 1;
4407 *l
= (ar
>> 13) & 1;
4410 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4412 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4413 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4416 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4418 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4419 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4422 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4424 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4425 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4428 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4430 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4431 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4434 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4436 struct kvm_segment var
;
4439 vmx_get_segment(vcpu
, &var
, seg
);
4441 if (seg
== VCPU_SREG_CS
)
4443 ar
= vmx_segment_access_rights(&var
);
4445 if (var
.base
!= (var
.selector
<< 4))
4447 if (var
.limit
!= 0xffff)
4455 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4457 struct kvm_segment cs
;
4458 unsigned int cs_rpl
;
4460 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4461 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4465 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4469 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4470 if (cs
.dpl
> cs_rpl
)
4473 if (cs
.dpl
!= cs_rpl
)
4479 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4483 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4485 struct kvm_segment ss
;
4486 unsigned int ss_rpl
;
4488 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4489 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4493 if (ss
.type
!= 3 && ss
.type
!= 7)
4497 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4505 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4507 struct kvm_segment var
;
4510 vmx_get_segment(vcpu
, &var
, seg
);
4511 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4519 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4520 if (var
.dpl
< rpl
) /* DPL < RPL */
4524 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4530 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4532 struct kvm_segment tr
;
4534 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4538 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4540 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4548 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4550 struct kvm_segment ldtr
;
4552 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4556 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4566 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4568 struct kvm_segment cs
, ss
;
4570 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4571 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4573 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4574 (ss
.selector
& SEGMENT_RPL_MASK
));
4578 * Check if guest state is valid. Returns true if valid, false if
4580 * We assume that registers are always usable
4582 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4584 if (enable_unrestricted_guest
)
4587 /* real mode guest state checks */
4588 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4589 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4591 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4593 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4595 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4597 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4599 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4602 /* protected mode guest state checks */
4603 if (!cs_ss_rpl_check(vcpu
))
4605 if (!code_segment_valid(vcpu
))
4607 if (!stack_segment_valid(vcpu
))
4609 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4611 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4613 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4615 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4617 if (!tr_valid(vcpu
))
4619 if (!ldtr_valid(vcpu
))
4623 * - Add checks on RIP
4624 * - Add checks on RFLAGS
4630 static int init_rmode_tss(struct kvm
*kvm
)
4636 idx
= srcu_read_lock(&kvm
->srcu
);
4637 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4638 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4641 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4642 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4643 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4646 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4649 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4653 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4654 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4657 srcu_read_unlock(&kvm
->srcu
, idx
);
4661 static int init_rmode_identity_map(struct kvm
*kvm
)
4664 kvm_pfn_t identity_map_pfn
;
4670 /* Protect kvm->arch.ept_identity_pagetable_done. */
4671 mutex_lock(&kvm
->slots_lock
);
4673 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4676 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4678 r
= alloc_identity_pagetable(kvm
);
4682 idx
= srcu_read_lock(&kvm
->srcu
);
4683 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4686 /* Set up identity-mapping pagetable for EPT in real mode */
4687 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4688 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4689 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4690 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4691 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4695 kvm
->arch
.ept_identity_pagetable_done
= true;
4698 srcu_read_unlock(&kvm
->srcu
, idx
);
4701 mutex_unlock(&kvm
->slots_lock
);
4705 static void seg_setup(int seg
)
4707 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4710 vmcs_write16(sf
->selector
, 0);
4711 vmcs_writel(sf
->base
, 0);
4712 vmcs_write32(sf
->limit
, 0xffff);
4714 if (seg
== VCPU_SREG_CS
)
4715 ar
|= 0x08; /* code segment */
4717 vmcs_write32(sf
->ar_bytes
, ar
);
4720 static int alloc_apic_access_page(struct kvm
*kvm
)
4725 mutex_lock(&kvm
->slots_lock
);
4726 if (kvm
->arch
.apic_access_page_done
)
4728 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4729 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4733 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4734 if (is_error_page(page
)) {
4740 * Do not pin the page in memory, so that memory hot-unplug
4741 * is able to migrate it.
4744 kvm
->arch
.apic_access_page_done
= true;
4746 mutex_unlock(&kvm
->slots_lock
);
4750 static int alloc_identity_pagetable(struct kvm
*kvm
)
4752 /* Called with kvm->slots_lock held. */
4756 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4758 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4759 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4764 static int allocate_vpid(void)
4770 spin_lock(&vmx_vpid_lock
);
4771 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4772 if (vpid
< VMX_NR_VPIDS
)
4773 __set_bit(vpid
, vmx_vpid_bitmap
);
4776 spin_unlock(&vmx_vpid_lock
);
4780 static void free_vpid(int vpid
)
4782 if (!enable_vpid
|| vpid
== 0)
4784 spin_lock(&vmx_vpid_lock
);
4785 __clear_bit(vpid
, vmx_vpid_bitmap
);
4786 spin_unlock(&vmx_vpid_lock
);
4789 #define MSR_TYPE_R 1
4790 #define MSR_TYPE_W 2
4791 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4794 int f
= sizeof(unsigned long);
4796 if (!cpu_has_vmx_msr_bitmap())
4800 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4801 * have the write-low and read-high bitmap offsets the wrong way round.
4802 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4804 if (msr
<= 0x1fff) {
4805 if (type
& MSR_TYPE_R
)
4807 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4809 if (type
& MSR_TYPE_W
)
4811 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4813 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4815 if (type
& MSR_TYPE_R
)
4817 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4819 if (type
& MSR_TYPE_W
)
4821 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4827 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4828 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4830 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4831 unsigned long *msr_bitmap_nested
,
4834 int f
= sizeof(unsigned long);
4836 if (!cpu_has_vmx_msr_bitmap()) {
4842 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4843 * have the write-low and read-high bitmap offsets the wrong way round.
4844 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4846 if (msr
<= 0x1fff) {
4847 if (type
& MSR_TYPE_R
&&
4848 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4850 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4852 if (type
& MSR_TYPE_W
&&
4853 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4855 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4857 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4859 if (type
& MSR_TYPE_R
&&
4860 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4862 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4864 if (type
& MSR_TYPE_W
&&
4865 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4867 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4872 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4875 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4876 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4878 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4881 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4884 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4886 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4889 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4891 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4896 static bool vmx_get_enable_apicv(void)
4898 return enable_apicv
;
4901 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4908 if (vmx
->nested
.pi_desc
&&
4909 vmx
->nested
.pi_pending
) {
4910 vmx
->nested
.pi_pending
= false;
4911 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4914 max_irr
= find_last_bit(
4915 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4920 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4921 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4922 kunmap(vmx
->nested
.virtual_apic_page
);
4924 status
= vmcs_read16(GUEST_INTR_STATUS
);
4925 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4927 status
|= (u8
)max_irr
;
4928 vmcs_write16(GUEST_INTR_STATUS
, status
);
4933 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4936 if (vcpu
->mode
== IN_GUEST_MODE
) {
4937 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4940 * Currently, we don't support urgent interrupt,
4941 * all interrupts are recognized as non-urgent
4942 * interrupt, so we cannot post interrupts when
4945 * If the vcpu is in guest mode, it means it is
4946 * running instead of being scheduled out and
4947 * waiting in the run queue, and that's the only
4948 * case when 'SN' is set currently, warning if
4951 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4953 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4954 POSTED_INTR_VECTOR
);
4961 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4966 if (is_guest_mode(vcpu
) &&
4967 vector
== vmx
->nested
.posted_intr_nv
) {
4968 /* the PIR and ON have been set by L1. */
4969 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4971 * If a posted intr is not recognized by hardware,
4972 * we will accomplish it in the next vmentry.
4974 vmx
->nested
.pi_pending
= true;
4975 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4981 * Send interrupt to vcpu via posted interrupt way.
4982 * 1. If target vcpu is running(non-root mode), send posted interrupt
4983 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4984 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4985 * interrupt from PIR in next vmentry.
4987 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4989 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4992 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4996 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4999 /* If a previous notification has sent the IPI, nothing to do. */
5000 if (pi_test_and_set_on(&vmx
->pi_desc
))
5003 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
))
5004 kvm_vcpu_kick(vcpu
);
5008 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5009 * will not change in the lifetime of the guest.
5010 * Note that host-state that does change is set elsewhere. E.g., host-state
5011 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5013 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5018 unsigned long cr0
, cr4
;
5021 WARN_ON(cr0
& X86_CR0_TS
);
5022 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5023 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5025 /* Save the most likely value for this task's CR4 in the VMCS. */
5026 cr4
= cr4_read_shadow();
5027 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5028 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5030 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5031 #ifdef CONFIG_X86_64
5033 * Load null selectors, so we can avoid reloading them in
5034 * __vmx_load_host_state(), in case userspace uses the null selectors
5035 * too (the expected case).
5037 vmcs_write16(HOST_DS_SELECTOR
, 0);
5038 vmcs_write16(HOST_ES_SELECTOR
, 0);
5040 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5041 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5043 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5044 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5046 native_store_idt(&dt
);
5047 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5048 vmx
->host_idt_base
= dt
.address
;
5050 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5052 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5053 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5054 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5055 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5057 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5058 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5059 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5063 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5065 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5067 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5068 if (is_guest_mode(&vmx
->vcpu
))
5069 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5070 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5071 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5074 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5076 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5078 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5079 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5080 /* Enable the preemption timer dynamically */
5081 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5082 return pin_based_exec_ctrl
;
5085 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5087 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5089 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5090 if (cpu_has_secondary_exec_ctrls()) {
5091 if (kvm_vcpu_apicv_active(vcpu
))
5092 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5093 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5094 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5096 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5097 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5098 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5101 if (cpu_has_vmx_msr_bitmap())
5102 vmx_set_msr_bitmap(vcpu
);
5105 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5107 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5109 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5110 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5112 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5113 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5114 #ifdef CONFIG_X86_64
5115 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5116 CPU_BASED_CR8_LOAD_EXITING
;
5120 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5121 CPU_BASED_CR3_LOAD_EXITING
|
5122 CPU_BASED_INVLPG_EXITING
;
5123 return exec_control
;
5126 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5128 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5129 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5130 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5132 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5134 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5135 enable_unrestricted_guest
= 0;
5136 /* Enable INVPCID for non-ept guests may cause performance regression. */
5137 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5139 if (!enable_unrestricted_guest
)
5140 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5142 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5143 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5144 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5145 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5146 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5147 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5149 We can NOT enable shadow_vmcs here because we don't have yet
5152 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5155 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5157 return exec_control
;
5160 static void ept_set_mmio_spte_mask(void)
5163 * EPT Misconfigurations can be generated if the value of bits 2:0
5164 * of an EPT paging-structure entry is 110b (write/execute).
5166 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE
);
5169 #define VMX_XSS_EXIT_BITMAP 0
5171 * Sets up the vmcs for emulated real mode.
5173 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5175 #ifdef CONFIG_X86_64
5181 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5182 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5184 if (enable_shadow_vmcs
) {
5185 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5186 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5188 if (cpu_has_vmx_msr_bitmap())
5189 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5191 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5194 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5195 vmx
->hv_deadline_tsc
= -1;
5197 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5199 if (cpu_has_secondary_exec_ctrls()) {
5200 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5201 vmx_secondary_exec_control(vmx
));
5204 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5205 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5206 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5207 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5208 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5210 vmcs_write16(GUEST_INTR_STATUS
, 0);
5212 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5213 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5217 vmcs_write32(PLE_GAP
, ple_gap
);
5218 vmx
->ple_window
= ple_window
;
5219 vmx
->ple_window_dirty
= true;
5222 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5223 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5224 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5226 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5227 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5228 vmx_set_constant_host_state(vmx
);
5229 #ifdef CONFIG_X86_64
5230 rdmsrl(MSR_FS_BASE
, a
);
5231 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5232 rdmsrl(MSR_GS_BASE
, a
);
5233 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5235 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5236 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5239 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5240 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5241 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5242 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5243 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5245 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5246 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5248 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5249 u32 index
= vmx_msr_index
[i
];
5250 u32 data_low
, data_high
;
5253 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5255 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5257 vmx
->guest_msrs
[j
].index
= i
;
5258 vmx
->guest_msrs
[j
].data
= 0;
5259 vmx
->guest_msrs
[j
].mask
= -1ull;
5264 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5266 /* 22.2.1, 20.8.1 */
5267 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5269 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5270 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5272 set_cr4_guest_host_mask(vmx
);
5274 if (vmx_xsaves_supported())
5275 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5278 ASSERT(vmx
->pml_pg
);
5279 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5280 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5286 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5288 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5289 struct msr_data apic_base_msr
;
5292 vmx
->rmode
.vm86_active
= 0;
5294 vmx
->soft_vnmi_blocked
= 0;
5296 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5297 kvm_set_cr8(vcpu
, 0);
5300 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5301 MSR_IA32_APICBASE_ENABLE
;
5302 if (kvm_vcpu_is_reset_bsp(vcpu
))
5303 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5304 apic_base_msr
.host_initiated
= true;
5305 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5308 vmx_segment_cache_clear(vmx
);
5310 seg_setup(VCPU_SREG_CS
);
5311 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5312 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5314 seg_setup(VCPU_SREG_DS
);
5315 seg_setup(VCPU_SREG_ES
);
5316 seg_setup(VCPU_SREG_FS
);
5317 seg_setup(VCPU_SREG_GS
);
5318 seg_setup(VCPU_SREG_SS
);
5320 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5321 vmcs_writel(GUEST_TR_BASE
, 0);
5322 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5323 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5325 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5326 vmcs_writel(GUEST_LDTR_BASE
, 0);
5327 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5328 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5331 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5332 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5333 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5334 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5337 vmcs_writel(GUEST_RFLAGS
, 0x02);
5338 kvm_rip_write(vcpu
, 0xfff0);
5340 vmcs_writel(GUEST_GDTR_BASE
, 0);
5341 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5343 vmcs_writel(GUEST_IDTR_BASE
, 0);
5344 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5346 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5347 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5348 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5352 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5354 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5355 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5356 if (cpu_need_tpr_shadow(vcpu
))
5357 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5358 __pa(vcpu
->arch
.apic
->regs
));
5359 vmcs_write32(TPR_THRESHOLD
, 0);
5362 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5364 if (kvm_vcpu_apicv_active(vcpu
))
5365 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5368 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5370 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5371 vmx
->vcpu
.arch
.cr0
= cr0
;
5372 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5373 vmx_set_cr4(vcpu
, 0);
5374 vmx_set_efer(vcpu
, 0);
5376 update_exception_bitmap(vcpu
);
5378 vpid_sync_context(vmx
->vpid
);
5382 * In nested virtualization, check if L1 asked to exit on external interrupts.
5383 * For most existing hypervisors, this will always return true.
5385 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5387 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5388 PIN_BASED_EXT_INTR_MASK
;
5392 * In nested virtualization, check if L1 has set
5393 * VM_EXIT_ACK_INTR_ON_EXIT
5395 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5397 return get_vmcs12(vcpu
)->vm_exit_controls
&
5398 VM_EXIT_ACK_INTR_ON_EXIT
;
5401 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5403 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5404 PIN_BASED_NMI_EXITING
;
5407 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5409 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5410 CPU_BASED_VIRTUAL_INTR_PENDING
);
5413 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5415 if (!cpu_has_virtual_nmis() ||
5416 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5417 enable_irq_window(vcpu
);
5421 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5422 CPU_BASED_VIRTUAL_NMI_PENDING
);
5425 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5427 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5429 int irq
= vcpu
->arch
.interrupt
.nr
;
5431 trace_kvm_inj_virq(irq
);
5433 ++vcpu
->stat
.irq_injections
;
5434 if (vmx
->rmode
.vm86_active
) {
5436 if (vcpu
->arch
.interrupt
.soft
)
5437 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5438 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5439 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5442 intr
= irq
| INTR_INFO_VALID_MASK
;
5443 if (vcpu
->arch
.interrupt
.soft
) {
5444 intr
|= INTR_TYPE_SOFT_INTR
;
5445 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5446 vmx
->vcpu
.arch
.event_exit_inst_len
);
5448 intr
|= INTR_TYPE_EXT_INTR
;
5449 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5452 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5456 if (!is_guest_mode(vcpu
)) {
5457 if (!cpu_has_virtual_nmis()) {
5459 * Tracking the NMI-blocked state in software is built upon
5460 * finding the next open IRQ window. This, in turn, depends on
5461 * well-behaving guests: They have to keep IRQs disabled at
5462 * least as long as the NMI handler runs. Otherwise we may
5463 * cause NMI nesting, maybe breaking the guest. But as this is
5464 * highly unlikely, we can live with the residual risk.
5466 vmx
->soft_vnmi_blocked
= 1;
5467 vmx
->vnmi_blocked_time
= 0;
5470 ++vcpu
->stat
.nmi_injections
;
5471 vmx
->nmi_known_unmasked
= false;
5474 if (vmx
->rmode
.vm86_active
) {
5475 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5476 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5480 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5481 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5484 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5486 if (!cpu_has_virtual_nmis())
5487 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5488 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5490 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5493 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5495 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5497 if (!cpu_has_virtual_nmis()) {
5498 if (vmx
->soft_vnmi_blocked
!= masked
) {
5499 vmx
->soft_vnmi_blocked
= masked
;
5500 vmx
->vnmi_blocked_time
= 0;
5503 vmx
->nmi_known_unmasked
= !masked
;
5505 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5506 GUEST_INTR_STATE_NMI
);
5508 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5509 GUEST_INTR_STATE_NMI
);
5513 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5515 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5518 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5521 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5522 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5523 | GUEST_INTR_STATE_NMI
));
5526 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5528 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5529 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5530 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5531 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5534 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5538 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5542 kvm
->arch
.tss_addr
= addr
;
5543 return init_rmode_tss(kvm
);
5546 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5551 * Update instruction length as we may reinject the exception
5552 * from user space while in guest debugging mode.
5554 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5555 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5556 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5560 if (vcpu
->guest_debug
&
5561 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5578 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5579 int vec
, u32 err_code
)
5582 * Instruction with address size override prefix opcode 0x67
5583 * Cause the #SS fault with 0 error code in VM86 mode.
5585 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5586 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5587 if (vcpu
->arch
.halt_request
) {
5588 vcpu
->arch
.halt_request
= 0;
5589 return kvm_vcpu_halt(vcpu
);
5597 * Forward all other exceptions that are valid in real mode.
5598 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5599 * the required debugging infrastructure rework.
5601 kvm_queue_exception(vcpu
, vec
);
5606 * Trigger machine check on the host. We assume all the MSRs are already set up
5607 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5608 * We pass a fake environment to the machine check handler because we want
5609 * the guest to be always treated like user space, no matter what context
5610 * it used internally.
5612 static void kvm_machine_check(void)
5614 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5615 struct pt_regs regs
= {
5616 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5617 .flags
= X86_EFLAGS_IF
,
5620 do_machine_check(®s
, 0);
5624 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5626 /* already handled by vcpu_run */
5630 static int handle_exception(struct kvm_vcpu
*vcpu
)
5632 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5633 struct kvm_run
*kvm_run
= vcpu
->run
;
5634 u32 intr_info
, ex_no
, error_code
;
5635 unsigned long cr2
, rip
, dr6
;
5637 enum emulation_result er
;
5639 vect_info
= vmx
->idt_vectoring_info
;
5640 intr_info
= vmx
->exit_intr_info
;
5642 if (is_machine_check(intr_info
))
5643 return handle_machine_check(vcpu
);
5645 if (is_nmi(intr_info
))
5646 return 1; /* already handled by vmx_vcpu_run() */
5648 if (is_invalid_opcode(intr_info
)) {
5649 if (is_guest_mode(vcpu
)) {
5650 kvm_queue_exception(vcpu
, UD_VECTOR
);
5653 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5654 if (er
!= EMULATE_DONE
)
5655 kvm_queue_exception(vcpu
, UD_VECTOR
);
5660 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5661 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5664 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5665 * MMIO, it is better to report an internal error.
5666 * See the comments in vmx_handle_exit.
5668 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5669 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5670 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5671 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5672 vcpu
->run
->internal
.ndata
= 3;
5673 vcpu
->run
->internal
.data
[0] = vect_info
;
5674 vcpu
->run
->internal
.data
[1] = intr_info
;
5675 vcpu
->run
->internal
.data
[2] = error_code
;
5679 if (is_page_fault(intr_info
)) {
5680 /* EPT won't cause page fault directly */
5682 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5683 trace_kvm_page_fault(cr2
, error_code
);
5685 if (kvm_event_needs_reinjection(vcpu
))
5686 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5687 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5690 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5692 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5693 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5697 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5700 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5701 if (!(vcpu
->guest_debug
&
5702 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5703 vcpu
->arch
.dr6
&= ~15;
5704 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5705 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5706 skip_emulated_instruction(vcpu
);
5708 kvm_queue_exception(vcpu
, DB_VECTOR
);
5711 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5712 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5716 * Update instruction length as we may reinject #BP from
5717 * user space while in guest debugging mode. Reading it for
5718 * #DB as well causes no harm, it is not used in that case.
5720 vmx
->vcpu
.arch
.event_exit_inst_len
=
5721 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5722 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5723 rip
= kvm_rip_read(vcpu
);
5724 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5725 kvm_run
->debug
.arch
.exception
= ex_no
;
5728 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5729 kvm_run
->ex
.exception
= ex_no
;
5730 kvm_run
->ex
.error_code
= error_code
;
5736 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5738 ++vcpu
->stat
.irq_exits
;
5742 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5744 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5748 static int handle_io(struct kvm_vcpu
*vcpu
)
5750 unsigned long exit_qualification
;
5751 int size
, in
, string
, ret
;
5754 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5755 string
= (exit_qualification
& 16) != 0;
5756 in
= (exit_qualification
& 8) != 0;
5758 ++vcpu
->stat
.io_exits
;
5761 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5763 port
= exit_qualification
>> 16;
5764 size
= (exit_qualification
& 7) + 1;
5766 ret
= kvm_skip_emulated_instruction(vcpu
);
5769 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5770 * KVM_EXIT_DEBUG here.
5772 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5776 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5779 * Patch in the VMCALL instruction:
5781 hypercall
[0] = 0x0f;
5782 hypercall
[1] = 0x01;
5783 hypercall
[2] = 0xc1;
5786 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5787 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5789 if (is_guest_mode(vcpu
)) {
5790 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5791 unsigned long orig_val
= val
;
5794 * We get here when L2 changed cr0 in a way that did not change
5795 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5796 * but did change L0 shadowed bits. So we first calculate the
5797 * effective cr0 value that L1 would like to write into the
5798 * hardware. It consists of the L2-owned bits from the new
5799 * value combined with the L1-owned bits from L1's guest_cr0.
5801 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5802 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5804 if (!nested_guest_cr0_valid(vcpu
, val
))
5807 if (kvm_set_cr0(vcpu
, val
))
5809 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5812 if (to_vmx(vcpu
)->nested
.vmxon
&&
5813 !nested_host_cr0_valid(vcpu
, val
))
5816 return kvm_set_cr0(vcpu
, val
);
5820 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5822 if (is_guest_mode(vcpu
)) {
5823 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5824 unsigned long orig_val
= val
;
5826 /* analogously to handle_set_cr0 */
5827 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5828 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5829 if (kvm_set_cr4(vcpu
, val
))
5831 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5834 return kvm_set_cr4(vcpu
, val
);
5837 static int handle_cr(struct kvm_vcpu
*vcpu
)
5839 unsigned long exit_qualification
, val
;
5845 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5846 cr
= exit_qualification
& 15;
5847 reg
= (exit_qualification
>> 8) & 15;
5848 switch ((exit_qualification
>> 4) & 3) {
5849 case 0: /* mov to cr */
5850 val
= kvm_register_readl(vcpu
, reg
);
5851 trace_kvm_cr_write(cr
, val
);
5854 err
= handle_set_cr0(vcpu
, val
);
5855 return kvm_complete_insn_gp(vcpu
, err
);
5857 err
= kvm_set_cr3(vcpu
, val
);
5858 return kvm_complete_insn_gp(vcpu
, err
);
5860 err
= handle_set_cr4(vcpu
, val
);
5861 return kvm_complete_insn_gp(vcpu
, err
);
5863 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5865 err
= kvm_set_cr8(vcpu
, cr8
);
5866 ret
= kvm_complete_insn_gp(vcpu
, err
);
5867 if (lapic_in_kernel(vcpu
))
5869 if (cr8_prev
<= cr8
)
5872 * TODO: we might be squashing a
5873 * KVM_GUESTDBG_SINGLESTEP-triggered
5874 * KVM_EXIT_DEBUG here.
5876 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5882 WARN_ONCE(1, "Guest should always own CR0.TS");
5883 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5884 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5885 return kvm_skip_emulated_instruction(vcpu
);
5886 case 1: /*mov from cr*/
5889 val
= kvm_read_cr3(vcpu
);
5890 kvm_register_write(vcpu
, reg
, val
);
5891 trace_kvm_cr_read(cr
, val
);
5892 return kvm_skip_emulated_instruction(vcpu
);
5894 val
= kvm_get_cr8(vcpu
);
5895 kvm_register_write(vcpu
, reg
, val
);
5896 trace_kvm_cr_read(cr
, val
);
5897 return kvm_skip_emulated_instruction(vcpu
);
5901 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5902 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5903 kvm_lmsw(vcpu
, val
);
5905 return kvm_skip_emulated_instruction(vcpu
);
5909 vcpu
->run
->exit_reason
= 0;
5910 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5911 (int)(exit_qualification
>> 4) & 3, cr
);
5915 static int handle_dr(struct kvm_vcpu
*vcpu
)
5917 unsigned long exit_qualification
;
5920 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5921 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5923 /* First, if DR does not exist, trigger UD */
5924 if (!kvm_require_dr(vcpu
, dr
))
5927 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5928 if (!kvm_require_cpl(vcpu
, 0))
5930 dr7
= vmcs_readl(GUEST_DR7
);
5933 * As the vm-exit takes precedence over the debug trap, we
5934 * need to emulate the latter, either for the host or the
5935 * guest debugging itself.
5937 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5938 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5939 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5940 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5941 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5942 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5945 vcpu
->arch
.dr6
&= ~15;
5946 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5947 kvm_queue_exception(vcpu
, DB_VECTOR
);
5952 if (vcpu
->guest_debug
== 0) {
5953 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5954 CPU_BASED_MOV_DR_EXITING
);
5957 * No more DR vmexits; force a reload of the debug registers
5958 * and reenter on this instruction. The next vmexit will
5959 * retrieve the full state of the debug registers.
5961 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5965 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5966 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5969 if (kvm_get_dr(vcpu
, dr
, &val
))
5971 kvm_register_write(vcpu
, reg
, val
);
5973 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5976 return kvm_skip_emulated_instruction(vcpu
);
5979 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5981 return vcpu
->arch
.dr6
;
5984 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5988 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5990 get_debugreg(vcpu
->arch
.db
[0], 0);
5991 get_debugreg(vcpu
->arch
.db
[1], 1);
5992 get_debugreg(vcpu
->arch
.db
[2], 2);
5993 get_debugreg(vcpu
->arch
.db
[3], 3);
5994 get_debugreg(vcpu
->arch
.dr6
, 6);
5995 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5997 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5998 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6001 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6003 vmcs_writel(GUEST_DR7
, val
);
6006 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6008 return kvm_emulate_cpuid(vcpu
);
6011 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6013 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6014 struct msr_data msr_info
;
6016 msr_info
.index
= ecx
;
6017 msr_info
.host_initiated
= false;
6018 if (vmx_get_msr(vcpu
, &msr_info
)) {
6019 trace_kvm_msr_read_ex(ecx
);
6020 kvm_inject_gp(vcpu
, 0);
6024 trace_kvm_msr_read(ecx
, msr_info
.data
);
6026 /* FIXME: handling of bits 32:63 of rax, rdx */
6027 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6028 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6029 return kvm_skip_emulated_instruction(vcpu
);
6032 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6034 struct msr_data msr
;
6035 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6036 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6037 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6041 msr
.host_initiated
= false;
6042 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6043 trace_kvm_msr_write_ex(ecx
, data
);
6044 kvm_inject_gp(vcpu
, 0);
6048 trace_kvm_msr_write(ecx
, data
);
6049 return kvm_skip_emulated_instruction(vcpu
);
6052 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6054 kvm_apic_update_ppr(vcpu
);
6058 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6060 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6061 CPU_BASED_VIRTUAL_INTR_PENDING
);
6063 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6065 ++vcpu
->stat
.irq_window_exits
;
6069 static int handle_halt(struct kvm_vcpu
*vcpu
)
6071 return kvm_emulate_halt(vcpu
);
6074 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6076 return kvm_emulate_hypercall(vcpu
);
6079 static int handle_invd(struct kvm_vcpu
*vcpu
)
6081 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6084 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6086 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6088 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6089 return kvm_skip_emulated_instruction(vcpu
);
6092 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6096 err
= kvm_rdpmc(vcpu
);
6097 return kvm_complete_insn_gp(vcpu
, err
);
6100 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6102 return kvm_emulate_wbinvd(vcpu
);
6105 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6107 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6108 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6110 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6111 return kvm_skip_emulated_instruction(vcpu
);
6115 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6117 kvm_skip_emulated_instruction(vcpu
);
6118 WARN(1, "this should never happen\n");
6122 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6124 kvm_skip_emulated_instruction(vcpu
);
6125 WARN(1, "this should never happen\n");
6129 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6131 if (likely(fasteoi
)) {
6132 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6133 int access_type
, offset
;
6135 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6136 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6138 * Sane guest uses MOV to write EOI, with written value
6139 * not cared. So make a short-circuit here by avoiding
6140 * heavy instruction emulation.
6142 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6143 (offset
== APIC_EOI
)) {
6144 kvm_lapic_set_eoi(vcpu
);
6145 return kvm_skip_emulated_instruction(vcpu
);
6148 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6151 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6153 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6154 int vector
= exit_qualification
& 0xff;
6156 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6157 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6161 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6163 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6164 u32 offset
= exit_qualification
& 0xfff;
6166 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6167 kvm_apic_write_nodecode(vcpu
, offset
);
6171 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6173 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6174 unsigned long exit_qualification
;
6175 bool has_error_code
= false;
6178 int reason
, type
, idt_v
, idt_index
;
6180 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6181 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6182 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6184 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6186 reason
= (u32
)exit_qualification
>> 30;
6187 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6189 case INTR_TYPE_NMI_INTR
:
6190 vcpu
->arch
.nmi_injected
= false;
6191 vmx_set_nmi_mask(vcpu
, true);
6193 case INTR_TYPE_EXT_INTR
:
6194 case INTR_TYPE_SOFT_INTR
:
6195 kvm_clear_interrupt_queue(vcpu
);
6197 case INTR_TYPE_HARD_EXCEPTION
:
6198 if (vmx
->idt_vectoring_info
&
6199 VECTORING_INFO_DELIVER_CODE_MASK
) {
6200 has_error_code
= true;
6202 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6205 case INTR_TYPE_SOFT_EXCEPTION
:
6206 kvm_clear_exception_queue(vcpu
);
6212 tss_selector
= exit_qualification
;
6214 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6215 type
!= INTR_TYPE_EXT_INTR
&&
6216 type
!= INTR_TYPE_NMI_INTR
))
6217 skip_emulated_instruction(vcpu
);
6219 if (kvm_task_switch(vcpu
, tss_selector
,
6220 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6221 has_error_code
, error_code
) == EMULATE_FAIL
) {
6222 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6223 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6224 vcpu
->run
->internal
.ndata
= 0;
6229 * TODO: What about debug traps on tss switch?
6230 * Are we supposed to inject them and update dr6?
6236 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6238 unsigned long exit_qualification
;
6243 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6245 gla_validity
= (exit_qualification
>> 7) & 0x3;
6246 if (gla_validity
== 0x2) {
6247 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6248 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6249 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6250 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6251 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6252 (long unsigned int)exit_qualification
);
6253 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6254 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6259 * EPT violation happened while executing iret from NMI,
6260 * "blocked by NMI" bit has to be set before next VM entry.
6261 * There are errata that may cause this bit to not be set:
6264 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6265 cpu_has_virtual_nmis() &&
6266 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6267 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6269 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6270 trace_kvm_page_fault(gpa
, exit_qualification
);
6272 /* Is it a read fault? */
6273 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6274 ? PFERR_USER_MASK
: 0;
6275 /* Is it a write fault? */
6276 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6277 ? PFERR_WRITE_MASK
: 0;
6278 /* Is it a fetch fault? */
6279 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6280 ? PFERR_FETCH_MASK
: 0;
6281 /* ept page table entry is present? */
6282 error_code
|= (exit_qualification
&
6283 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6284 EPT_VIOLATION_EXECUTABLE
))
6285 ? PFERR_PRESENT_MASK
: 0;
6287 vcpu
->arch
.gpa_available
= true;
6288 vcpu
->arch
.exit_qualification
= exit_qualification
;
6290 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6293 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6298 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6299 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6300 trace_kvm_fast_mmio(gpa
);
6301 return kvm_skip_emulated_instruction(vcpu
);
6304 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6305 vcpu
->arch
.gpa_available
= true;
6306 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6307 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6310 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6311 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6313 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6316 /* It is the real ept misconfig */
6319 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6320 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6325 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6327 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6328 CPU_BASED_VIRTUAL_NMI_PENDING
);
6329 ++vcpu
->stat
.nmi_window_exits
;
6330 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6335 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6337 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6338 enum emulation_result err
= EMULATE_DONE
;
6341 bool intr_window_requested
;
6342 unsigned count
= 130;
6344 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6345 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6347 while (vmx
->emulation_required
&& count
-- != 0) {
6348 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6349 return handle_interrupt_window(&vmx
->vcpu
);
6351 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6354 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6356 if (err
== EMULATE_USER_EXIT
) {
6357 ++vcpu
->stat
.mmio_exits
;
6362 if (err
!= EMULATE_DONE
) {
6363 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6364 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6365 vcpu
->run
->internal
.ndata
= 0;
6369 if (vcpu
->arch
.halt_request
) {
6370 vcpu
->arch
.halt_request
= 0;
6371 ret
= kvm_vcpu_halt(vcpu
);
6375 if (signal_pending(current
))
6385 static int __grow_ple_window(int val
)
6387 if (ple_window_grow
< 1)
6390 val
= min(val
, ple_window_actual_max
);
6392 if (ple_window_grow
< ple_window
)
6393 val
*= ple_window_grow
;
6395 val
+= ple_window_grow
;
6400 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6405 if (modifier
< ple_window
)
6410 return max(val
, minimum
);
6413 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6415 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6416 int old
= vmx
->ple_window
;
6418 vmx
->ple_window
= __grow_ple_window(old
);
6420 if (vmx
->ple_window
!= old
)
6421 vmx
->ple_window_dirty
= true;
6423 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6426 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6429 int old
= vmx
->ple_window
;
6431 vmx
->ple_window
= __shrink_ple_window(old
,
6432 ple_window_shrink
, ple_window
);
6434 if (vmx
->ple_window
!= old
)
6435 vmx
->ple_window_dirty
= true;
6437 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6441 * ple_window_actual_max is computed to be one grow_ple_window() below
6442 * ple_window_max. (See __grow_ple_window for the reason.)
6443 * This prevents overflows, because ple_window_max is int.
6444 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6446 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6448 static void update_ple_window_actual_max(void)
6450 ple_window_actual_max
=
6451 __shrink_ple_window(max(ple_window_max
, ple_window
),
6452 ple_window_grow
, INT_MIN
);
6456 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6458 static void wakeup_handler(void)
6460 struct kvm_vcpu
*vcpu
;
6461 int cpu
= smp_processor_id();
6463 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6464 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6465 blocked_vcpu_list
) {
6466 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6468 if (pi_test_on(pi_desc
) == 1)
6469 kvm_vcpu_kick(vcpu
);
6471 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6474 void vmx_enable_tdp(void)
6476 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6477 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6478 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6479 0ull, VMX_EPT_EXECUTABLE_MASK
,
6480 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6481 enable_ept_ad_bits
? 0ull : VMX_EPT_RWX_MASK
);
6483 ept_set_mmio_spte_mask();
6487 static __init
int hardware_setup(void)
6489 int r
= -ENOMEM
, i
, msr
;
6491 rdmsrl_safe(MSR_EFER
, &host_efer
);
6493 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6494 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6496 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6497 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6502 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6503 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6504 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6507 * Allow direct access to the PC debug port (it is often used for I/O
6508 * delays, but the vmexits simply slow things down).
6510 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6511 clear_bit(0x80, vmx_io_bitmap_a
);
6513 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6515 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6516 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6518 if (setup_vmcs_config(&vmcs_config
) < 0) {
6523 if (boot_cpu_has(X86_FEATURE_NX
))
6524 kvm_enable_efer_bits(EFER_NX
);
6526 if (!cpu_has_vmx_vpid())
6528 if (!cpu_has_vmx_shadow_vmcs())
6529 enable_shadow_vmcs
= 0;
6530 if (enable_shadow_vmcs
)
6531 init_vmcs_shadow_fields();
6533 if (!cpu_has_vmx_ept() ||
6534 !cpu_has_vmx_ept_4levels()) {
6536 enable_unrestricted_guest
= 0;
6537 enable_ept_ad_bits
= 0;
6540 if (!cpu_has_vmx_ept_ad_bits())
6541 enable_ept_ad_bits
= 0;
6543 if (!cpu_has_vmx_unrestricted_guest())
6544 enable_unrestricted_guest
= 0;
6546 if (!cpu_has_vmx_flexpriority())
6547 flexpriority_enabled
= 0;
6550 * set_apic_access_page_addr() is used to reload apic access
6551 * page upon invalidation. No need to do anything if not
6552 * using the APIC_ACCESS_ADDR VMCS field.
6554 if (!flexpriority_enabled
)
6555 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6557 if (!cpu_has_vmx_tpr_shadow())
6558 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6560 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6561 kvm_disable_largepages();
6563 if (!cpu_has_vmx_ple())
6566 if (!cpu_has_vmx_apicv()) {
6568 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6571 if (cpu_has_vmx_tsc_scaling()) {
6572 kvm_has_tsc_control
= true;
6573 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6574 kvm_tsc_scaling_ratio_frac_bits
= 48;
6577 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6578 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6579 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6580 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6581 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6582 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6583 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6585 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6586 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6587 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6588 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6589 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6590 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6591 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6592 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6594 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6596 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6597 if (msr
== 0x839 /* TMCCT */)
6599 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6603 * TPR reads and writes can be virtualized even if virtual interrupt
6604 * delivery is not in use.
6606 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6607 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6610 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6612 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6619 update_ple_window_actual_max();
6622 * Only enable PML when hardware supports PML feature, and both EPT
6623 * and EPT A/D bit features are enabled -- PML depends on them to work.
6625 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6629 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6630 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6631 kvm_x86_ops
->flush_log_dirty
= NULL
;
6632 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6635 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6638 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6639 cpu_preemption_timer_multi
=
6640 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6642 kvm_x86_ops
->set_hv_timer
= NULL
;
6643 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6646 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6648 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6650 return alloc_kvm_area();
6653 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6654 free_page((unsigned long)vmx_bitmap
[i
]);
6659 static __exit
void hardware_unsetup(void)
6663 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6664 free_page((unsigned long)vmx_bitmap
[i
]);
6670 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6671 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6673 static int handle_pause(struct kvm_vcpu
*vcpu
)
6676 grow_ple_window(vcpu
);
6678 kvm_vcpu_on_spin(vcpu
);
6679 return kvm_skip_emulated_instruction(vcpu
);
6682 static int handle_nop(struct kvm_vcpu
*vcpu
)
6684 return kvm_skip_emulated_instruction(vcpu
);
6687 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6689 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6690 return handle_nop(vcpu
);
6693 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6698 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6700 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6701 return handle_nop(vcpu
);
6705 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6706 * We could reuse a single VMCS for all the L2 guests, but we also want the
6707 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6708 * allows keeping them loaded on the processor, and in the future will allow
6709 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6710 * every entry if they never change.
6711 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6712 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6714 * The following functions allocate and free a vmcs02 in this pool.
6717 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6718 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6720 struct vmcs02_list
*item
;
6721 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6722 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6723 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6724 return &item
->vmcs02
;
6727 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6728 /* Recycle the least recently used VMCS. */
6729 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6730 struct vmcs02_list
, list
);
6731 item
->vmptr
= vmx
->nested
.current_vmptr
;
6732 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6733 return &item
->vmcs02
;
6736 /* Create a new VMCS */
6737 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6740 item
->vmcs02
.vmcs
= alloc_vmcs();
6741 item
->vmcs02
.shadow_vmcs
= NULL
;
6742 if (!item
->vmcs02
.vmcs
) {
6746 loaded_vmcs_init(&item
->vmcs02
);
6747 item
->vmptr
= vmx
->nested
.current_vmptr
;
6748 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6749 vmx
->nested
.vmcs02_num
++;
6750 return &item
->vmcs02
;
6753 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6754 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6756 struct vmcs02_list
*item
;
6757 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6758 if (item
->vmptr
== vmptr
) {
6759 free_loaded_vmcs(&item
->vmcs02
);
6760 list_del(&item
->list
);
6762 vmx
->nested
.vmcs02_num
--;
6768 * Free all VMCSs saved for this vcpu, except the one pointed by
6769 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6770 * must be &vmx->vmcs01.
6772 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6774 struct vmcs02_list
*item
, *n
;
6776 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6777 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6779 * Something will leak if the above WARN triggers. Better than
6782 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6785 free_loaded_vmcs(&item
->vmcs02
);
6786 list_del(&item
->list
);
6788 vmx
->nested
.vmcs02_num
--;
6793 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6794 * set the success or error code of an emulated VMX instruction, as specified
6795 * by Vol 2B, VMX Instruction Reference, "Conventions".
6797 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6799 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6800 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6801 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6804 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6806 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6807 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6808 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6812 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6813 u32 vm_instruction_error
)
6815 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6817 * failValid writes the error number to the current VMCS, which
6818 * can't be done there isn't a current VMCS.
6820 nested_vmx_failInvalid(vcpu
);
6823 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6824 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6825 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6827 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6829 * We don't need to force a shadow sync because
6830 * VM_INSTRUCTION_ERROR is not shadowed
6834 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6836 /* TODO: not to reset guest simply here. */
6837 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6838 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6841 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6843 struct vcpu_vmx
*vmx
=
6844 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6846 vmx
->nested
.preemption_timer_expired
= true;
6847 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6848 kvm_vcpu_kick(&vmx
->vcpu
);
6850 return HRTIMER_NORESTART
;
6854 * Decode the memory-address operand of a vmx instruction, as recorded on an
6855 * exit caused by such an instruction (run by a guest hypervisor).
6856 * On success, returns 0. When the operand is invalid, returns 1 and throws
6859 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6860 unsigned long exit_qualification
,
6861 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6865 struct kvm_segment s
;
6868 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6869 * Execution", on an exit, vmx_instruction_info holds most of the
6870 * addressing components of the operand. Only the displacement part
6871 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6872 * For how an actual address is calculated from all these components,
6873 * refer to Vol. 1, "Operand Addressing".
6875 int scaling
= vmx_instruction_info
& 3;
6876 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6877 bool is_reg
= vmx_instruction_info
& (1u << 10);
6878 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6879 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6880 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6881 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6882 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6885 kvm_queue_exception(vcpu
, UD_VECTOR
);
6889 /* Addr = segment_base + offset */
6890 /* offset = base + [index * scale] + displacement */
6891 off
= exit_qualification
; /* holds the displacement */
6893 off
+= kvm_register_read(vcpu
, base_reg
);
6895 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6896 vmx_get_segment(vcpu
, &s
, seg_reg
);
6897 *ret
= s
.base
+ off
;
6899 if (addr_size
== 1) /* 32 bit */
6902 /* Checks for #GP/#SS exceptions. */
6904 if (is_long_mode(vcpu
)) {
6905 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6906 * non-canonical form. This is the only check on the memory
6907 * destination for long mode!
6909 exn
= is_noncanonical_address(*ret
);
6910 } else if (is_protmode(vcpu
)) {
6911 /* Protected mode: apply checks for segment validity in the
6913 * - segment type check (#GP(0) may be thrown)
6914 * - usability check (#GP(0)/#SS(0))
6915 * - limit check (#GP(0)/#SS(0))
6918 /* #GP(0) if the destination operand is located in a
6919 * read-only data segment or any code segment.
6921 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6923 /* #GP(0) if the source operand is located in an
6924 * execute-only code segment
6926 exn
= ((s
.type
& 0xa) == 8);
6928 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6931 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6933 exn
= (s
.unusable
!= 0);
6934 /* Protected mode: #GP(0)/#SS(0) if the memory
6935 * operand is outside the segment limit.
6937 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6940 kvm_queue_exception_e(vcpu
,
6941 seg_reg
== VCPU_SREG_SS
?
6942 SS_VECTOR
: GP_VECTOR
,
6951 * This function performs the various checks including
6952 * - if it's 4KB aligned
6953 * - No bits beyond the physical address width are set
6954 * - Returns 0 on success or else 1
6955 * (Intel SDM Section 30.3)
6957 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6962 struct x86_exception e
;
6964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6965 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6967 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6968 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6971 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6972 sizeof(vmptr
), &e
)) {
6973 kvm_inject_page_fault(vcpu
, &e
);
6977 switch (exit_reason
) {
6978 case EXIT_REASON_VMON
:
6981 * The first 4 bytes of VMXON region contain the supported
6982 * VMCS revision identifier
6984 * Note - IA32_VMX_BASIC[48] will never be 1
6985 * for the nested case;
6986 * which replaces physical address width with 32
6989 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6990 nested_vmx_failInvalid(vcpu
);
6991 return kvm_skip_emulated_instruction(vcpu
);
6994 page
= nested_get_page(vcpu
, vmptr
);
6996 nested_vmx_failInvalid(vcpu
);
6997 return kvm_skip_emulated_instruction(vcpu
);
6999 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7001 nested_release_page_clean(page
);
7002 nested_vmx_failInvalid(vcpu
);
7003 return kvm_skip_emulated_instruction(vcpu
);
7006 nested_release_page_clean(page
);
7007 vmx
->nested
.vmxon_ptr
= vmptr
;
7009 case EXIT_REASON_VMCLEAR
:
7010 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
7011 nested_vmx_failValid(vcpu
,
7012 VMXERR_VMCLEAR_INVALID_ADDRESS
);
7013 return kvm_skip_emulated_instruction(vcpu
);
7016 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7017 nested_vmx_failValid(vcpu
,
7018 VMXERR_VMCLEAR_VMXON_POINTER
);
7019 return kvm_skip_emulated_instruction(vcpu
);
7022 case EXIT_REASON_VMPTRLD
:
7023 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
7024 nested_vmx_failValid(vcpu
,
7025 VMXERR_VMPTRLD_INVALID_ADDRESS
);
7026 return kvm_skip_emulated_instruction(vcpu
);
7029 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7030 nested_vmx_failValid(vcpu
,
7031 VMXERR_VMPTRLD_VMXON_POINTER
);
7032 return kvm_skip_emulated_instruction(vcpu
);
7036 return 1; /* shouldn't happen */
7044 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7046 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7047 struct vmcs
*shadow_vmcs
;
7049 if (cpu_has_vmx_msr_bitmap()) {
7050 vmx
->nested
.msr_bitmap
=
7051 (unsigned long *)__get_free_page(GFP_KERNEL
);
7052 if (!vmx
->nested
.msr_bitmap
)
7053 goto out_msr_bitmap
;
7056 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7057 if (!vmx
->nested
.cached_vmcs12
)
7058 goto out_cached_vmcs12
;
7060 if (enable_shadow_vmcs
) {
7061 shadow_vmcs
= alloc_vmcs();
7063 goto out_shadow_vmcs
;
7064 /* mark vmcs as shadow */
7065 shadow_vmcs
->revision_id
|= (1u << 31);
7066 /* init shadow vmcs */
7067 vmcs_clear(shadow_vmcs
);
7068 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7071 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7072 vmx
->nested
.vmcs02_num
= 0;
7074 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7075 HRTIMER_MODE_REL_PINNED
);
7076 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7078 vmx
->nested
.vmxon
= true;
7082 kfree(vmx
->nested
.cached_vmcs12
);
7085 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7092 * Emulate the VMXON instruction.
7093 * Currently, we just remember that VMX is active, and do not save or even
7094 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7095 * do not currently need to store anything in that guest-allocated memory
7096 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7097 * argument is different from the VMXON pointer (which the spec says they do).
7099 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7102 struct kvm_segment cs
;
7103 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7104 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7105 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7107 /* The Intel VMX Instruction Reference lists a bunch of bits that
7108 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7109 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7110 * Otherwise, we should fail with #UD. We test these now:
7112 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
7113 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
7114 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
7115 kvm_queue_exception(vcpu
, UD_VECTOR
);
7119 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7120 if (is_long_mode(vcpu
) && !cs
.l
) {
7121 kvm_queue_exception(vcpu
, UD_VECTOR
);
7125 if (vmx_get_cpl(vcpu
)) {
7126 kvm_inject_gp(vcpu
, 0);
7130 if (vmx
->nested
.vmxon
) {
7131 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7132 return kvm_skip_emulated_instruction(vcpu
);
7135 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7136 != VMXON_NEEDED_FEATURES
) {
7137 kvm_inject_gp(vcpu
, 0);
7141 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
7144 ret
= enter_vmx_operation(vcpu
);
7148 nested_vmx_succeed(vcpu
);
7149 return kvm_skip_emulated_instruction(vcpu
);
7153 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7154 * for running VMX instructions (except VMXON, whose prerequisites are
7155 * slightly different). It also specifies what exception to inject otherwise.
7157 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7159 struct kvm_segment cs
;
7160 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7162 if (!vmx
->nested
.vmxon
) {
7163 kvm_queue_exception(vcpu
, UD_VECTOR
);
7167 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7168 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
7169 (is_long_mode(vcpu
) && !cs
.l
)) {
7170 kvm_queue_exception(vcpu
, UD_VECTOR
);
7174 if (vmx_get_cpl(vcpu
)) {
7175 kvm_inject_gp(vcpu
, 0);
7182 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7184 if (vmx
->nested
.current_vmptr
== -1ull)
7187 /* current_vmptr and current_vmcs12 are always set/reset together */
7188 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7191 if (enable_shadow_vmcs
) {
7192 /* copy to memory all shadowed fields in case
7193 they were modified */
7194 copy_shadow_to_vmcs12(vmx
);
7195 vmx
->nested
.sync_shadow_vmcs
= false;
7196 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7197 SECONDARY_EXEC_SHADOW_VMCS
);
7198 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7200 vmx
->nested
.posted_intr_nv
= -1;
7202 /* Flush VMCS12 to guest memory */
7203 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7206 kunmap(vmx
->nested
.current_vmcs12_page
);
7207 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7208 vmx
->nested
.current_vmptr
= -1ull;
7209 vmx
->nested
.current_vmcs12
= NULL
;
7213 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7214 * just stops using VMX.
7216 static void free_nested(struct vcpu_vmx
*vmx
)
7218 if (!vmx
->nested
.vmxon
)
7221 vmx
->nested
.vmxon
= false;
7222 free_vpid(vmx
->nested
.vpid02
);
7223 nested_release_vmcs12(vmx
);
7224 if (vmx
->nested
.msr_bitmap
) {
7225 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7226 vmx
->nested
.msr_bitmap
= NULL
;
7228 if (enable_shadow_vmcs
) {
7229 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7230 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7231 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7233 kfree(vmx
->nested
.cached_vmcs12
);
7234 /* Unpin physical memory we referred to in current vmcs02 */
7235 if (vmx
->nested
.apic_access_page
) {
7236 nested_release_page(vmx
->nested
.apic_access_page
);
7237 vmx
->nested
.apic_access_page
= NULL
;
7239 if (vmx
->nested
.virtual_apic_page
) {
7240 nested_release_page(vmx
->nested
.virtual_apic_page
);
7241 vmx
->nested
.virtual_apic_page
= NULL
;
7243 if (vmx
->nested
.pi_desc_page
) {
7244 kunmap(vmx
->nested
.pi_desc_page
);
7245 nested_release_page(vmx
->nested
.pi_desc_page
);
7246 vmx
->nested
.pi_desc_page
= NULL
;
7247 vmx
->nested
.pi_desc
= NULL
;
7250 nested_free_all_saved_vmcss(vmx
);
7253 /* Emulate the VMXOFF instruction */
7254 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7256 if (!nested_vmx_check_permission(vcpu
))
7258 free_nested(to_vmx(vcpu
));
7259 nested_vmx_succeed(vcpu
);
7260 return kvm_skip_emulated_instruction(vcpu
);
7263 /* Emulate the VMCLEAR instruction */
7264 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7266 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7270 if (!nested_vmx_check_permission(vcpu
))
7273 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7276 if (vmptr
== vmx
->nested
.current_vmptr
)
7277 nested_release_vmcs12(vmx
);
7279 kvm_vcpu_write_guest(vcpu
,
7280 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7281 &zero
, sizeof(zero
));
7283 nested_free_vmcs02(vmx
, vmptr
);
7285 nested_vmx_succeed(vcpu
);
7286 return kvm_skip_emulated_instruction(vcpu
);
7289 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7291 /* Emulate the VMLAUNCH instruction */
7292 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7294 return nested_vmx_run(vcpu
, true);
7297 /* Emulate the VMRESUME instruction */
7298 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7301 return nested_vmx_run(vcpu
, false);
7304 enum vmcs_field_type
{
7305 VMCS_FIELD_TYPE_U16
= 0,
7306 VMCS_FIELD_TYPE_U64
= 1,
7307 VMCS_FIELD_TYPE_U32
= 2,
7308 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7311 static inline int vmcs_field_type(unsigned long field
)
7313 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7314 return VMCS_FIELD_TYPE_U32
;
7315 return (field
>> 13) & 0x3 ;
7318 static inline int vmcs_field_readonly(unsigned long field
)
7320 return (((field
>> 10) & 0x3) == 1);
7324 * Read a vmcs12 field. Since these can have varying lengths and we return
7325 * one type, we chose the biggest type (u64) and zero-extend the return value
7326 * to that size. Note that the caller, handle_vmread, might need to use only
7327 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7328 * 64-bit fields are to be returned).
7330 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7331 unsigned long field
, u64
*ret
)
7333 short offset
= vmcs_field_to_offset(field
);
7339 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7341 switch (vmcs_field_type(field
)) {
7342 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7343 *ret
= *((natural_width
*)p
);
7345 case VMCS_FIELD_TYPE_U16
:
7348 case VMCS_FIELD_TYPE_U32
:
7351 case VMCS_FIELD_TYPE_U64
:
7361 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7362 unsigned long field
, u64 field_value
){
7363 short offset
= vmcs_field_to_offset(field
);
7364 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7368 switch (vmcs_field_type(field
)) {
7369 case VMCS_FIELD_TYPE_U16
:
7370 *(u16
*)p
= field_value
;
7372 case VMCS_FIELD_TYPE_U32
:
7373 *(u32
*)p
= field_value
;
7375 case VMCS_FIELD_TYPE_U64
:
7376 *(u64
*)p
= field_value
;
7378 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7379 *(natural_width
*)p
= field_value
;
7388 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7391 unsigned long field
;
7393 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7394 const unsigned long *fields
= shadow_read_write_fields
;
7395 const int num_fields
= max_shadow_read_write_fields
;
7399 vmcs_load(shadow_vmcs
);
7401 for (i
= 0; i
< num_fields
; i
++) {
7403 switch (vmcs_field_type(field
)) {
7404 case VMCS_FIELD_TYPE_U16
:
7405 field_value
= vmcs_read16(field
);
7407 case VMCS_FIELD_TYPE_U32
:
7408 field_value
= vmcs_read32(field
);
7410 case VMCS_FIELD_TYPE_U64
:
7411 field_value
= vmcs_read64(field
);
7413 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7414 field_value
= vmcs_readl(field
);
7420 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7423 vmcs_clear(shadow_vmcs
);
7424 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7429 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7431 const unsigned long *fields
[] = {
7432 shadow_read_write_fields
,
7433 shadow_read_only_fields
7435 const int max_fields
[] = {
7436 max_shadow_read_write_fields
,
7437 max_shadow_read_only_fields
7440 unsigned long field
;
7441 u64 field_value
= 0;
7442 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7444 vmcs_load(shadow_vmcs
);
7446 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7447 for (i
= 0; i
< max_fields
[q
]; i
++) {
7448 field
= fields
[q
][i
];
7449 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7451 switch (vmcs_field_type(field
)) {
7452 case VMCS_FIELD_TYPE_U16
:
7453 vmcs_write16(field
, (u16
)field_value
);
7455 case VMCS_FIELD_TYPE_U32
:
7456 vmcs_write32(field
, (u32
)field_value
);
7458 case VMCS_FIELD_TYPE_U64
:
7459 vmcs_write64(field
, (u64
)field_value
);
7461 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7462 vmcs_writel(field
, (long)field_value
);
7471 vmcs_clear(shadow_vmcs
);
7472 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7476 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7477 * used before) all generate the same failure when it is missing.
7479 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7481 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7482 if (vmx
->nested
.current_vmptr
== -1ull) {
7483 nested_vmx_failInvalid(vcpu
);
7489 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7491 unsigned long field
;
7493 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7494 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7497 if (!nested_vmx_check_permission(vcpu
))
7500 if (!nested_vmx_check_vmcs12(vcpu
))
7501 return kvm_skip_emulated_instruction(vcpu
);
7503 /* Decode instruction info and find the field to read */
7504 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7505 /* Read the field, zero-extended to a u64 field_value */
7506 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7507 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7508 return kvm_skip_emulated_instruction(vcpu
);
7511 * Now copy part of this value to register or memory, as requested.
7512 * Note that the number of bits actually copied is 32 or 64 depending
7513 * on the guest's mode (32 or 64 bit), not on the given field's length.
7515 if (vmx_instruction_info
& (1u << 10)) {
7516 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7519 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7520 vmx_instruction_info
, true, &gva
))
7522 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7523 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7524 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7527 nested_vmx_succeed(vcpu
);
7528 return kvm_skip_emulated_instruction(vcpu
);
7532 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7534 unsigned long field
;
7536 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7537 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7538 /* The value to write might be 32 or 64 bits, depending on L1's long
7539 * mode, and eventually we need to write that into a field of several
7540 * possible lengths. The code below first zero-extends the value to 64
7541 * bit (field_value), and then copies only the appropriate number of
7542 * bits into the vmcs12 field.
7544 u64 field_value
= 0;
7545 struct x86_exception e
;
7547 if (!nested_vmx_check_permission(vcpu
))
7550 if (!nested_vmx_check_vmcs12(vcpu
))
7551 return kvm_skip_emulated_instruction(vcpu
);
7553 if (vmx_instruction_info
& (1u << 10))
7554 field_value
= kvm_register_readl(vcpu
,
7555 (((vmx_instruction_info
) >> 3) & 0xf));
7557 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7558 vmx_instruction_info
, false, &gva
))
7560 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7561 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7562 kvm_inject_page_fault(vcpu
, &e
);
7568 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7569 if (vmcs_field_readonly(field
)) {
7570 nested_vmx_failValid(vcpu
,
7571 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7572 return kvm_skip_emulated_instruction(vcpu
);
7575 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7576 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7577 return kvm_skip_emulated_instruction(vcpu
);
7580 nested_vmx_succeed(vcpu
);
7581 return kvm_skip_emulated_instruction(vcpu
);
7584 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7586 vmx
->nested
.current_vmptr
= vmptr
;
7587 if (enable_shadow_vmcs
) {
7588 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7589 SECONDARY_EXEC_SHADOW_VMCS
);
7590 vmcs_write64(VMCS_LINK_POINTER
,
7591 __pa(vmx
->vmcs01
.shadow_vmcs
));
7592 vmx
->nested
.sync_shadow_vmcs
= true;
7596 /* Emulate the VMPTRLD instruction */
7597 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7602 if (!nested_vmx_check_permission(vcpu
))
7605 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7608 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7609 struct vmcs12
*new_vmcs12
;
7611 page
= nested_get_page(vcpu
, vmptr
);
7613 nested_vmx_failInvalid(vcpu
);
7614 return kvm_skip_emulated_instruction(vcpu
);
7616 new_vmcs12
= kmap(page
);
7617 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7619 nested_release_page_clean(page
);
7620 nested_vmx_failValid(vcpu
,
7621 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7622 return kvm_skip_emulated_instruction(vcpu
);
7625 nested_release_vmcs12(vmx
);
7626 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7627 vmx
->nested
.current_vmcs12_page
= page
;
7629 * Load VMCS12 from guest memory since it is not already
7632 memcpy(vmx
->nested
.cached_vmcs12
,
7633 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7634 set_current_vmptr(vmx
, vmptr
);
7637 nested_vmx_succeed(vcpu
);
7638 return kvm_skip_emulated_instruction(vcpu
);
7641 /* Emulate the VMPTRST instruction */
7642 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7644 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7645 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7647 struct x86_exception e
;
7649 if (!nested_vmx_check_permission(vcpu
))
7652 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7653 vmx_instruction_info
, true, &vmcs_gva
))
7655 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7656 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7657 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7659 kvm_inject_page_fault(vcpu
, &e
);
7662 nested_vmx_succeed(vcpu
);
7663 return kvm_skip_emulated_instruction(vcpu
);
7666 /* Emulate the INVEPT instruction */
7667 static int handle_invept(struct kvm_vcpu
*vcpu
)
7669 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7670 u32 vmx_instruction_info
, types
;
7673 struct x86_exception e
;
7678 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7679 SECONDARY_EXEC_ENABLE_EPT
) ||
7680 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7681 kvm_queue_exception(vcpu
, UD_VECTOR
);
7685 if (!nested_vmx_check_permission(vcpu
))
7688 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7689 kvm_queue_exception(vcpu
, UD_VECTOR
);
7693 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7694 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7696 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7698 if (type
>= 32 || !(types
& (1 << type
))) {
7699 nested_vmx_failValid(vcpu
,
7700 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7701 return kvm_skip_emulated_instruction(vcpu
);
7704 /* According to the Intel VMX instruction reference, the memory
7705 * operand is read even if it isn't needed (e.g., for type==global)
7707 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7708 vmx_instruction_info
, false, &gva
))
7710 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7711 sizeof(operand
), &e
)) {
7712 kvm_inject_page_fault(vcpu
, &e
);
7717 case VMX_EPT_EXTENT_GLOBAL
:
7719 * TODO: track mappings and invalidate
7720 * single context requests appropriately
7722 case VMX_EPT_EXTENT_CONTEXT
:
7723 kvm_mmu_sync_roots(vcpu
);
7724 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7725 nested_vmx_succeed(vcpu
);
7732 return kvm_skip_emulated_instruction(vcpu
);
7735 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7738 u32 vmx_instruction_info
;
7739 unsigned long type
, types
;
7741 struct x86_exception e
;
7744 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7745 SECONDARY_EXEC_ENABLE_VPID
) ||
7746 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7747 kvm_queue_exception(vcpu
, UD_VECTOR
);
7751 if (!nested_vmx_check_permission(vcpu
))
7754 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7755 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7757 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7758 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7760 if (type
>= 32 || !(types
& (1 << type
))) {
7761 nested_vmx_failValid(vcpu
,
7762 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7763 return kvm_skip_emulated_instruction(vcpu
);
7766 /* according to the intel vmx instruction reference, the memory
7767 * operand is read even if it isn't needed (e.g., for type==global)
7769 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7770 vmx_instruction_info
, false, &gva
))
7772 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7774 kvm_inject_page_fault(vcpu
, &e
);
7779 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7780 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7781 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7783 nested_vmx_failValid(vcpu
,
7784 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7785 return kvm_skip_emulated_instruction(vcpu
);
7788 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7792 return kvm_skip_emulated_instruction(vcpu
);
7795 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7796 nested_vmx_succeed(vcpu
);
7798 return kvm_skip_emulated_instruction(vcpu
);
7801 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7803 unsigned long exit_qualification
;
7805 trace_kvm_pml_full(vcpu
->vcpu_id
);
7807 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7810 * PML buffer FULL happened while executing iret from NMI,
7811 * "blocked by NMI" bit has to be set before next VM entry.
7813 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7814 cpu_has_virtual_nmis() &&
7815 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7816 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7817 GUEST_INTR_STATE_NMI
);
7820 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7821 * here.., and there's no userspace involvement needed for PML.
7826 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7828 kvm_lapic_expired_hv_timer(vcpu
);
7833 * The exit handlers return 1 if the exit was handled fully and guest execution
7834 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7835 * to be done to userspace and return 0.
7837 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7838 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7839 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7840 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7841 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7842 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7843 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7844 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7845 [EXIT_REASON_CPUID
] = handle_cpuid
,
7846 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7847 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7848 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7849 [EXIT_REASON_HLT
] = handle_halt
,
7850 [EXIT_REASON_INVD
] = handle_invd
,
7851 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7852 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7853 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7854 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7855 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7856 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7857 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7858 [EXIT_REASON_VMREAD
] = handle_vmread
,
7859 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7860 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7861 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7862 [EXIT_REASON_VMON
] = handle_vmon
,
7863 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7864 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7865 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7866 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7867 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7868 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7869 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7870 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7871 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7872 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7873 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7874 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7875 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7876 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7877 [EXIT_REASON_INVEPT
] = handle_invept
,
7878 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7879 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7880 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7881 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7882 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7885 static const int kvm_vmx_max_exit_handlers
=
7886 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7888 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7889 struct vmcs12
*vmcs12
)
7891 unsigned long exit_qualification
;
7892 gpa_t bitmap
, last_bitmap
;
7897 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7898 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7900 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7902 port
= exit_qualification
>> 16;
7903 size
= (exit_qualification
& 7) + 1;
7905 last_bitmap
= (gpa_t
)-1;
7910 bitmap
= vmcs12
->io_bitmap_a
;
7911 else if (port
< 0x10000)
7912 bitmap
= vmcs12
->io_bitmap_b
;
7915 bitmap
+= (port
& 0x7fff) / 8;
7917 if (last_bitmap
!= bitmap
)
7918 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7920 if (b
& (1 << (port
& 7)))
7925 last_bitmap
= bitmap
;
7932 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7933 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7934 * disinterest in the current event (read or write a specific MSR) by using an
7935 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7937 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7938 struct vmcs12
*vmcs12
, u32 exit_reason
)
7940 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7943 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7947 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7948 * for the four combinations of read/write and low/high MSR numbers.
7949 * First we need to figure out which of the four to use:
7951 bitmap
= vmcs12
->msr_bitmap
;
7952 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7954 if (msr_index
>= 0xc0000000) {
7955 msr_index
-= 0xc0000000;
7959 /* Then read the msr_index'th bit from this bitmap: */
7960 if (msr_index
< 1024*8) {
7962 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7964 return 1 & (b
>> (msr_index
& 7));
7966 return true; /* let L1 handle the wrong parameter */
7970 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7971 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7972 * intercept (via guest_host_mask etc.) the current event.
7974 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7975 struct vmcs12
*vmcs12
)
7977 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7978 int cr
= exit_qualification
& 15;
7979 int reg
= (exit_qualification
>> 8) & 15;
7980 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7982 switch ((exit_qualification
>> 4) & 3) {
7983 case 0: /* mov to cr */
7986 if (vmcs12
->cr0_guest_host_mask
&
7987 (val
^ vmcs12
->cr0_read_shadow
))
7991 if ((vmcs12
->cr3_target_count
>= 1 &&
7992 vmcs12
->cr3_target_value0
== val
) ||
7993 (vmcs12
->cr3_target_count
>= 2 &&
7994 vmcs12
->cr3_target_value1
== val
) ||
7995 (vmcs12
->cr3_target_count
>= 3 &&
7996 vmcs12
->cr3_target_value2
== val
) ||
7997 (vmcs12
->cr3_target_count
>= 4 &&
7998 vmcs12
->cr3_target_value3
== val
))
8000 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8004 if (vmcs12
->cr4_guest_host_mask
&
8005 (vmcs12
->cr4_read_shadow
^ val
))
8009 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8015 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8016 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8019 case 1: /* mov from cr */
8022 if (vmcs12
->cpu_based_vm_exec_control
&
8023 CPU_BASED_CR3_STORE_EXITING
)
8027 if (vmcs12
->cpu_based_vm_exec_control
&
8028 CPU_BASED_CR8_STORE_EXITING
)
8035 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8036 * cr0. Other attempted changes are ignored, with no exit.
8038 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8039 (val
^ vmcs12
->cr0_read_shadow
))
8041 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8042 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8051 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8052 * should handle it ourselves in L0 (and then continue L2). Only call this
8053 * when in is_guest_mode (L2).
8055 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
8057 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8059 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8060 u32 exit_reason
= vmx
->exit_reason
;
8062 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8063 vmcs_readl(EXIT_QUALIFICATION
),
8064 vmx
->idt_vectoring_info
,
8066 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8069 if (vmx
->nested
.nested_run_pending
)
8072 if (unlikely(vmx
->fail
)) {
8073 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8074 vmcs_read32(VM_INSTRUCTION_ERROR
));
8078 switch (exit_reason
) {
8079 case EXIT_REASON_EXCEPTION_NMI
:
8080 if (is_nmi(intr_info
))
8082 else if (is_page_fault(intr_info
))
8084 else if (is_no_device(intr_info
) &&
8085 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8087 else if (is_debug(intr_info
) &&
8089 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8091 else if (is_breakpoint(intr_info
) &&
8092 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8094 return vmcs12
->exception_bitmap
&
8095 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8096 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8098 case EXIT_REASON_TRIPLE_FAULT
:
8100 case EXIT_REASON_PENDING_INTERRUPT
:
8101 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8102 case EXIT_REASON_NMI_WINDOW
:
8103 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8104 case EXIT_REASON_TASK_SWITCH
:
8106 case EXIT_REASON_CPUID
:
8108 case EXIT_REASON_HLT
:
8109 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8110 case EXIT_REASON_INVD
:
8112 case EXIT_REASON_INVLPG
:
8113 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8114 case EXIT_REASON_RDPMC
:
8115 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8116 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8117 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8118 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8119 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8120 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8121 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8122 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8123 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8125 * VMX instructions trap unconditionally. This allows L1 to
8126 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8129 case EXIT_REASON_CR_ACCESS
:
8130 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8131 case EXIT_REASON_DR_ACCESS
:
8132 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8133 case EXIT_REASON_IO_INSTRUCTION
:
8134 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8135 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8136 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8137 case EXIT_REASON_MSR_READ
:
8138 case EXIT_REASON_MSR_WRITE
:
8139 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8140 case EXIT_REASON_INVALID_STATE
:
8142 case EXIT_REASON_MWAIT_INSTRUCTION
:
8143 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8144 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8145 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8146 case EXIT_REASON_MONITOR_INSTRUCTION
:
8147 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8148 case EXIT_REASON_PAUSE_INSTRUCTION
:
8149 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8150 nested_cpu_has2(vmcs12
,
8151 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8152 case EXIT_REASON_MCE_DURING_VMENTRY
:
8154 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8155 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8156 case EXIT_REASON_APIC_ACCESS
:
8157 return nested_cpu_has2(vmcs12
,
8158 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8159 case EXIT_REASON_APIC_WRITE
:
8160 case EXIT_REASON_EOI_INDUCED
:
8161 /* apic_write and eoi_induced should exit unconditionally. */
8163 case EXIT_REASON_EPT_VIOLATION
:
8165 * L0 always deals with the EPT violation. If nested EPT is
8166 * used, and the nested mmu code discovers that the address is
8167 * missing in the guest EPT table (EPT12), the EPT violation
8168 * will be injected with nested_ept_inject_page_fault()
8171 case EXIT_REASON_EPT_MISCONFIG
:
8173 * L2 never uses directly L1's EPT, but rather L0's own EPT
8174 * table (shadow on EPT) or a merged EPT table that L0 built
8175 * (EPT on EPT). So any problems with the structure of the
8176 * table is L0's fault.
8179 case EXIT_REASON_WBINVD
:
8180 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8181 case EXIT_REASON_XSETBV
:
8183 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8185 * This should never happen, since it is not possible to
8186 * set XSS to a non-zero value---neither in L1 nor in L2.
8187 * If if it were, XSS would have to be checked against
8188 * the XSS exit bitmap in vmcs12.
8190 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8191 case EXIT_REASON_PREEMPTION_TIMER
:
8198 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8200 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8201 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8204 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8207 __free_page(vmx
->pml_pg
);
8212 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8214 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8218 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8220 /* Do nothing if PML buffer is empty */
8221 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8224 /* PML index always points to next available PML buffer entity */
8225 if (pml_idx
>= PML_ENTITY_NUM
)
8230 pml_buf
= page_address(vmx
->pml_pg
);
8231 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8234 gpa
= pml_buf
[pml_idx
];
8235 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8236 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8239 /* reset PML index */
8240 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8244 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8245 * Called before reporting dirty_bitmap to userspace.
8247 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8250 struct kvm_vcpu
*vcpu
;
8252 * We only need to kick vcpu out of guest mode here, as PML buffer
8253 * is flushed at beginning of all VMEXITs, and it's obvious that only
8254 * vcpus running in guest are possible to have unflushed GPAs in PML
8257 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8258 kvm_vcpu_kick(vcpu
);
8261 static void vmx_dump_sel(char *name
, uint32_t sel
)
8263 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8264 name
, vmcs_read16(sel
),
8265 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8266 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8267 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8270 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8272 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8273 name
, vmcs_read32(limit
),
8274 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8277 static void dump_vmcs(void)
8279 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8280 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8281 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8282 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8283 u32 secondary_exec_control
= 0;
8284 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8285 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8288 if (cpu_has_secondary_exec_ctrls())
8289 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8291 pr_err("*** Guest State ***\n");
8292 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8293 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8294 vmcs_readl(CR0_GUEST_HOST_MASK
));
8295 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8296 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8297 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8298 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8299 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8301 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8302 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8303 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8304 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8306 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8307 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8308 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8309 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8310 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8311 vmcs_readl(GUEST_SYSENTER_ESP
),
8312 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8313 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8314 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8315 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8316 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8317 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8318 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8319 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8320 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8321 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8322 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8323 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8324 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8325 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8326 efer
, vmcs_read64(GUEST_IA32_PAT
));
8327 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8328 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8329 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8330 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8331 pr_err("PerfGlobCtl = 0x%016llx\n",
8332 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8333 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8334 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8335 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8336 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8337 vmcs_read32(GUEST_ACTIVITY_STATE
));
8338 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8339 pr_err("InterruptStatus = %04x\n",
8340 vmcs_read16(GUEST_INTR_STATUS
));
8342 pr_err("*** Host State ***\n");
8343 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8344 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8345 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8346 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8347 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8348 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8349 vmcs_read16(HOST_TR_SELECTOR
));
8350 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8351 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8352 vmcs_readl(HOST_TR_BASE
));
8353 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8354 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8355 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8356 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8357 vmcs_readl(HOST_CR4
));
8358 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8359 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8360 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8361 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8362 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8363 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8364 vmcs_read64(HOST_IA32_EFER
),
8365 vmcs_read64(HOST_IA32_PAT
));
8366 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8367 pr_err("PerfGlobCtl = 0x%016llx\n",
8368 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8370 pr_err("*** Control State ***\n");
8371 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8372 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8373 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8374 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8375 vmcs_read32(EXCEPTION_BITMAP
),
8376 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8377 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8378 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8379 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8380 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8381 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8382 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8383 vmcs_read32(VM_EXIT_INTR_INFO
),
8384 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8385 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8386 pr_err(" reason=%08x qualification=%016lx\n",
8387 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8388 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8389 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8390 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8391 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8392 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8393 pr_err("TSC Multiplier = 0x%016llx\n",
8394 vmcs_read64(TSC_MULTIPLIER
));
8395 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8396 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8397 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8398 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8399 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8400 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8401 n
= vmcs_read32(CR3_TARGET_COUNT
);
8402 for (i
= 0; i
+ 1 < n
; i
+= 4)
8403 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8404 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8405 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8407 pr_err("CR3 target%u=%016lx\n",
8408 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8409 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8410 pr_err("PLE Gap=%08x Window=%08x\n",
8411 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8412 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8413 pr_err("Virtual processor ID = 0x%04x\n",
8414 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8418 * The guest has exited. See if we can fix it or if we need userspace
8421 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8424 u32 exit_reason
= vmx
->exit_reason
;
8425 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8427 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8428 vcpu
->arch
.gpa_available
= false;
8431 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8432 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8433 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8434 * mode as if vcpus is in root mode, the PML buffer must has been
8438 vmx_flush_pml_buffer(vcpu
);
8440 /* If guest state is invalid, start emulating */
8441 if (vmx
->emulation_required
)
8442 return handle_invalid_guest_state(vcpu
);
8444 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8445 nested_vmx_vmexit(vcpu
, exit_reason
,
8446 vmcs_read32(VM_EXIT_INTR_INFO
),
8447 vmcs_readl(EXIT_QUALIFICATION
));
8451 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8453 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8454 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8459 if (unlikely(vmx
->fail
)) {
8460 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8461 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8462 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8468 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8469 * delivery event since it indicates guest is accessing MMIO.
8470 * The vm-exit can be triggered again after return to guest that
8471 * will cause infinite loop.
8473 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8474 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8475 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8476 exit_reason
!= EXIT_REASON_PML_FULL
&&
8477 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8478 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8479 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8480 vcpu
->run
->internal
.ndata
= 2;
8481 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8482 vcpu
->run
->internal
.data
[1] = exit_reason
;
8486 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8487 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8488 get_vmcs12(vcpu
))))) {
8489 if (vmx_interrupt_allowed(vcpu
)) {
8490 vmx
->soft_vnmi_blocked
= 0;
8491 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8492 vcpu
->arch
.nmi_pending
) {
8494 * This CPU don't support us in finding the end of an
8495 * NMI-blocked window if the guest runs with IRQs
8496 * disabled. So we pull the trigger after 1 s of
8497 * futile waiting, but inform the user about this.
8499 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8500 "state on VCPU %d after 1 s timeout\n",
8501 __func__
, vcpu
->vcpu_id
);
8502 vmx
->soft_vnmi_blocked
= 0;
8506 if (exit_reason
< kvm_vmx_max_exit_handlers
8507 && kvm_vmx_exit_handlers
[exit_reason
])
8508 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8510 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8512 kvm_queue_exception(vcpu
, UD_VECTOR
);
8517 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8519 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8521 if (is_guest_mode(vcpu
) &&
8522 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8525 if (irr
== -1 || tpr
< irr
) {
8526 vmcs_write32(TPR_THRESHOLD
, 0);
8530 vmcs_write32(TPR_THRESHOLD
, irr
);
8533 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8535 u32 sec_exec_control
;
8537 /* Postpone execution until vmcs01 is the current VMCS. */
8538 if (is_guest_mode(vcpu
)) {
8539 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8543 if (!cpu_has_vmx_virtualize_x2apic_mode())
8546 if (!cpu_need_tpr_shadow(vcpu
))
8549 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8552 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8553 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8555 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8556 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8557 vmx_flush_tlb_ept_only(vcpu
);
8559 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8561 vmx_set_msr_bitmap(vcpu
);
8564 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8566 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8569 * Currently we do not handle the nested case where L2 has an
8570 * APIC access page of its own; that page is still pinned.
8571 * Hence, we skip the case where the VCPU is in guest mode _and_
8572 * L1 prepared an APIC access page for L2.
8574 * For the case where L1 and L2 share the same APIC access page
8575 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8576 * in the vmcs12), this function will only update either the vmcs01
8577 * or the vmcs02. If the former, the vmcs02 will be updated by
8578 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8579 * the next L2->L1 exit.
8581 if (!is_guest_mode(vcpu
) ||
8582 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8583 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8584 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8585 vmx_flush_tlb_ept_only(vcpu
);
8589 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8597 status
= vmcs_read16(GUEST_INTR_STATUS
);
8599 if (max_isr
!= old
) {
8601 status
|= max_isr
<< 8;
8602 vmcs_write16(GUEST_INTR_STATUS
, status
);
8606 static void vmx_set_rvi(int vector
)
8614 status
= vmcs_read16(GUEST_INTR_STATUS
);
8615 old
= (u8
)status
& 0xff;
8616 if ((u8
)vector
!= old
) {
8618 status
|= (u8
)vector
;
8619 vmcs_write16(GUEST_INTR_STATUS
, status
);
8623 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8625 if (!is_guest_mode(vcpu
)) {
8626 vmx_set_rvi(max_irr
);
8634 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8637 if (nested_exit_on_intr(vcpu
))
8641 * Else, fall back to pre-APICv interrupt injection since L2
8642 * is run without virtual interrupt delivery.
8644 if (!kvm_event_needs_reinjection(vcpu
) &&
8645 vmx_interrupt_allowed(vcpu
)) {
8646 kvm_queue_interrupt(vcpu
, max_irr
, false);
8647 vmx_inject_irq(vcpu
);
8651 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8653 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8656 WARN_ON(!vcpu
->arch
.apicv_active
);
8657 if (pi_test_on(&vmx
->pi_desc
)) {
8658 pi_clear_on(&vmx
->pi_desc
);
8660 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8661 * But on x86 this is just a compiler barrier anyway.
8663 smp_mb__after_atomic();
8664 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8666 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8668 vmx_hwapic_irr_update(vcpu
, max_irr
);
8672 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8674 if (!kvm_vcpu_apicv_active(vcpu
))
8677 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8678 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8679 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8680 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8683 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8685 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8687 pi_clear_on(&vmx
->pi_desc
);
8688 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8691 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8695 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8696 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8699 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8700 exit_intr_info
= vmx
->exit_intr_info
;
8702 /* Handle machine checks before interrupts are enabled */
8703 if (is_machine_check(exit_intr_info
))
8704 kvm_machine_check();
8706 /* We need to handle NMIs before interrupts are enabled */
8707 if (is_nmi(exit_intr_info
)) {
8708 kvm_before_handle_nmi(&vmx
->vcpu
);
8710 kvm_after_handle_nmi(&vmx
->vcpu
);
8714 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8716 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8717 register void *__sp
asm(_ASM_SP
);
8719 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8720 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8721 unsigned int vector
;
8722 unsigned long entry
;
8724 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8725 #ifdef CONFIG_X86_64
8729 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8730 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8731 entry
= gate_offset(*desc
);
8733 #ifdef CONFIG_X86_64
8734 "mov %%" _ASM_SP
", %[sp]\n\t"
8735 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8740 __ASM_SIZE(push
) " $%c[cs]\n\t"
8741 "call *%[entry]\n\t"
8743 #ifdef CONFIG_X86_64
8749 [ss
]"i"(__KERNEL_DS
),
8750 [cs
]"i"(__KERNEL_CS
)
8755 static bool vmx_has_high_real_mode_segbase(void)
8757 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8760 static bool vmx_mpx_supported(void)
8762 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8763 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8766 static bool vmx_xsaves_supported(void)
8768 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8769 SECONDARY_EXEC_XSAVES
;
8772 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8777 bool idtv_info_valid
;
8779 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8781 if (cpu_has_virtual_nmis()) {
8782 if (vmx
->nmi_known_unmasked
)
8785 * Can't use vmx->exit_intr_info since we're not sure what
8786 * the exit reason is.
8788 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8789 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8790 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8792 * SDM 3: 27.7.1.2 (September 2008)
8793 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8794 * a guest IRET fault.
8795 * SDM 3: 23.2.2 (September 2008)
8796 * Bit 12 is undefined in any of the following cases:
8797 * If the VM exit sets the valid bit in the IDT-vectoring
8798 * information field.
8799 * If the VM exit is due to a double fault.
8801 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8802 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8803 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8804 GUEST_INTR_STATE_NMI
);
8806 vmx
->nmi_known_unmasked
=
8807 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8808 & GUEST_INTR_STATE_NMI
);
8809 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8810 vmx
->vnmi_blocked_time
+=
8811 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8814 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8815 u32 idt_vectoring_info
,
8816 int instr_len_field
,
8817 int error_code_field
)
8821 bool idtv_info_valid
;
8823 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8825 vcpu
->arch
.nmi_injected
= false;
8826 kvm_clear_exception_queue(vcpu
);
8827 kvm_clear_interrupt_queue(vcpu
);
8829 if (!idtv_info_valid
)
8832 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8834 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8835 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8838 case INTR_TYPE_NMI_INTR
:
8839 vcpu
->arch
.nmi_injected
= true;
8841 * SDM 3: 27.7.1.2 (September 2008)
8842 * Clear bit "block by NMI" before VM entry if a NMI
8845 vmx_set_nmi_mask(vcpu
, false);
8847 case INTR_TYPE_SOFT_EXCEPTION
:
8848 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8850 case INTR_TYPE_HARD_EXCEPTION
:
8851 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8852 u32 err
= vmcs_read32(error_code_field
);
8853 kvm_requeue_exception_e(vcpu
, vector
, err
);
8855 kvm_requeue_exception(vcpu
, vector
);
8857 case INTR_TYPE_SOFT_INTR
:
8858 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8860 case INTR_TYPE_EXT_INTR
:
8861 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8868 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8870 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8871 VM_EXIT_INSTRUCTION_LEN
,
8872 IDT_VECTORING_ERROR_CODE
);
8875 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8877 __vmx_complete_interrupts(vcpu
,
8878 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8879 VM_ENTRY_INSTRUCTION_LEN
,
8880 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8882 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8885 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8888 struct perf_guest_switch_msr
*msrs
;
8890 msrs
= perf_guest_get_msrs(&nr_msrs
);
8895 for (i
= 0; i
< nr_msrs
; i
++)
8896 if (msrs
[i
].host
== msrs
[i
].guest
)
8897 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8899 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8903 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8905 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8909 if (vmx
->hv_deadline_tsc
== -1)
8913 if (vmx
->hv_deadline_tsc
> tscl
)
8914 /* sure to be 32 bit only because checked on set_hv_timer */
8915 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8916 cpu_preemption_timer_multi
);
8920 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8923 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8925 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8926 unsigned long debugctlmsr
, cr4
;
8928 /* Record the guest's net vcpu time for enforced NMI injections. */
8929 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8930 vmx
->entry_time
= ktime_get();
8932 /* Don't enter VMX if guest state is invalid, let the exit handler
8933 start emulation until we arrive back to a valid state */
8934 if (vmx
->emulation_required
)
8937 if (vmx
->ple_window_dirty
) {
8938 vmx
->ple_window_dirty
= false;
8939 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8942 if (vmx
->nested
.sync_shadow_vmcs
) {
8943 copy_vmcs12_to_shadow(vmx
);
8944 vmx
->nested
.sync_shadow_vmcs
= false;
8947 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8948 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8949 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8950 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8952 cr4
= cr4_read_shadow();
8953 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8954 vmcs_writel(HOST_CR4
, cr4
);
8955 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8958 /* When single-stepping over STI and MOV SS, we must clear the
8959 * corresponding interruptibility bits in the guest state. Otherwise
8960 * vmentry fails as it then expects bit 14 (BS) in pending debug
8961 * exceptions being set, but that's not correct for the guest debugging
8963 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8964 vmx_set_interrupt_shadow(vcpu
, 0);
8966 if (vmx
->guest_pkru_valid
)
8967 __write_pkru(vmx
->guest_pkru
);
8969 atomic_switch_perf_msrs(vmx
);
8970 debugctlmsr
= get_debugctlmsr();
8972 vmx_arm_hv_timer(vcpu
);
8974 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8976 /* Store host registers */
8977 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8978 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8979 "push %%" _ASM_CX
" \n\t"
8980 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8982 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8983 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8985 /* Reload cr2 if changed */
8986 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8987 "mov %%cr2, %%" _ASM_DX
" \n\t"
8988 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8990 "mov %%" _ASM_AX
", %%cr2 \n\t"
8992 /* Check if vmlaunch of vmresume is needed */
8993 "cmpl $0, %c[launched](%0) \n\t"
8994 /* Load guest registers. Don't clobber flags. */
8995 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8996 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8997 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8998 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8999 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9000 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9001 #ifdef CONFIG_X86_64
9002 "mov %c[r8](%0), %%r8 \n\t"
9003 "mov %c[r9](%0), %%r9 \n\t"
9004 "mov %c[r10](%0), %%r10 \n\t"
9005 "mov %c[r11](%0), %%r11 \n\t"
9006 "mov %c[r12](%0), %%r12 \n\t"
9007 "mov %c[r13](%0), %%r13 \n\t"
9008 "mov %c[r14](%0), %%r14 \n\t"
9009 "mov %c[r15](%0), %%r15 \n\t"
9011 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9013 /* Enter guest mode */
9015 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9017 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9019 /* Save guest registers, load host registers, keep flags */
9020 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9022 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9023 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9024 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9025 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9026 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9027 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9028 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9029 #ifdef CONFIG_X86_64
9030 "mov %%r8, %c[r8](%0) \n\t"
9031 "mov %%r9, %c[r9](%0) \n\t"
9032 "mov %%r10, %c[r10](%0) \n\t"
9033 "mov %%r11, %c[r11](%0) \n\t"
9034 "mov %%r12, %c[r12](%0) \n\t"
9035 "mov %%r13, %c[r13](%0) \n\t"
9036 "mov %%r14, %c[r14](%0) \n\t"
9037 "mov %%r15, %c[r15](%0) \n\t"
9039 "mov %%cr2, %%" _ASM_AX
" \n\t"
9040 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9042 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9043 "setbe %c[fail](%0) \n\t"
9044 ".pushsection .rodata \n\t"
9045 ".global vmx_return \n\t"
9046 "vmx_return: " _ASM_PTR
" 2b \n\t"
9048 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9049 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9050 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9051 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9052 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9053 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9054 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9055 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9056 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9057 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9058 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9059 #ifdef CONFIG_X86_64
9060 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9061 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9062 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9063 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9064 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9065 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9066 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9067 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9069 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9070 [wordsize
]"i"(sizeof(ulong
))
9072 #ifdef CONFIG_X86_64
9073 , "rax", "rbx", "rdi", "rsi"
9074 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9076 , "eax", "ebx", "edi", "esi"
9080 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9082 update_debugctlmsr(debugctlmsr
);
9084 #ifndef CONFIG_X86_64
9086 * The sysexit path does not restore ds/es, so we must set them to
9087 * a reasonable value ourselves.
9089 * We can't defer this to vmx_load_host_state() since that function
9090 * may be executed in interrupt context, which saves and restore segments
9091 * around it, nullifying its effect.
9093 loadsegment(ds
, __USER_DS
);
9094 loadsegment(es
, __USER_DS
);
9097 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9098 | (1 << VCPU_EXREG_RFLAGS
)
9099 | (1 << VCPU_EXREG_PDPTR
)
9100 | (1 << VCPU_EXREG_SEGMENTS
)
9101 | (1 << VCPU_EXREG_CR3
));
9102 vcpu
->arch
.regs_dirty
= 0;
9104 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9106 vmx
->loaded_vmcs
->launched
= 1;
9108 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9111 * eager fpu is enabled if PKEY is supported and CR4 is switched
9112 * back on host, so it is safe to read guest PKRU from current
9115 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9116 vmx
->guest_pkru
= __read_pkru();
9117 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9118 vmx
->guest_pkru_valid
= true;
9119 __write_pkru(vmx
->host_pkru
);
9121 vmx
->guest_pkru_valid
= false;
9125 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9126 * we did not inject a still-pending event to L1 now because of
9127 * nested_run_pending, we need to re-enable this bit.
9129 if (vmx
->nested
.nested_run_pending
)
9130 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9132 vmx
->nested
.nested_run_pending
= 0;
9134 vmx_complete_atomic_exit(vmx
);
9135 vmx_recover_nmi_blocking(vmx
);
9136 vmx_complete_interrupts(vmx
);
9139 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
9141 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9144 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
9148 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9150 vmx_vcpu_load(vcpu
, cpu
);
9156 * Ensure that the current vmcs of the logical processor is the
9157 * vmcs01 of the vcpu before calling free_nested().
9159 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9161 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9164 r
= vcpu_load(vcpu
);
9166 vmx_load_vmcs01(vcpu
);
9171 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9173 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9176 vmx_destroy_pml_buffer(vmx
);
9177 free_vpid(vmx
->vpid
);
9178 leave_guest_mode(vcpu
);
9179 vmx_free_vcpu_nested(vcpu
);
9180 free_loaded_vmcs(vmx
->loaded_vmcs
);
9181 kfree(vmx
->guest_msrs
);
9182 kvm_vcpu_uninit(vcpu
);
9183 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9186 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9189 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9193 return ERR_PTR(-ENOMEM
);
9195 vmx
->vpid
= allocate_vpid();
9197 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9204 * If PML is turned on, failure on enabling PML just results in failure
9205 * of creating the vcpu, therefore we can simplify PML logic (by
9206 * avoiding dealing with cases, such as enabling PML partially on vcpus
9207 * for the guest, etc.
9210 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9215 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9216 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9219 if (!vmx
->guest_msrs
)
9222 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9223 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9224 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9225 if (!vmx
->loaded_vmcs
->vmcs
)
9228 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9229 loaded_vmcs_init(vmx
->loaded_vmcs
);
9234 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9235 vmx
->vcpu
.cpu
= cpu
;
9236 err
= vmx_vcpu_setup(vmx
);
9237 vmx_vcpu_put(&vmx
->vcpu
);
9241 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9242 err
= alloc_apic_access_page(kvm
);
9248 if (!kvm
->arch
.ept_identity_map_addr
)
9249 kvm
->arch
.ept_identity_map_addr
=
9250 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9251 err
= init_rmode_identity_map(kvm
);
9257 nested_vmx_setup_ctls_msrs(vmx
);
9258 vmx
->nested
.vpid02
= allocate_vpid();
9261 vmx
->nested
.posted_intr_nv
= -1;
9262 vmx
->nested
.current_vmptr
= -1ull;
9263 vmx
->nested
.current_vmcs12
= NULL
;
9265 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9270 free_vpid(vmx
->nested
.vpid02
);
9271 free_loaded_vmcs(vmx
->loaded_vmcs
);
9273 kfree(vmx
->guest_msrs
);
9275 vmx_destroy_pml_buffer(vmx
);
9277 kvm_vcpu_uninit(&vmx
->vcpu
);
9279 free_vpid(vmx
->vpid
);
9280 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9281 return ERR_PTR(err
);
9284 static void __init
vmx_check_processor_compat(void *rtn
)
9286 struct vmcs_config vmcs_conf
;
9289 if (setup_vmcs_config(&vmcs_conf
) < 0)
9291 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9292 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9293 smp_processor_id());
9298 static int get_ept_level(void)
9300 return VMX_EPT_DEFAULT_GAW
+ 1;
9303 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9308 /* For VT-d and EPT combination
9309 * 1. MMIO: always map as UC
9311 * a. VT-d without snooping control feature: can't guarantee the
9312 * result, try to trust guest.
9313 * b. VT-d with snooping control feature: snooping control feature of
9314 * VT-d engine can guarantee the cache correctness. Just set it
9315 * to WB to keep consistent with host. So the same as item 3.
9316 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9317 * consistent with host MTRR
9320 cache
= MTRR_TYPE_UNCACHABLE
;
9324 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9325 ipat
= VMX_EPT_IPAT_BIT
;
9326 cache
= MTRR_TYPE_WRBACK
;
9330 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9331 ipat
= VMX_EPT_IPAT_BIT
;
9332 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9333 cache
= MTRR_TYPE_WRBACK
;
9335 cache
= MTRR_TYPE_UNCACHABLE
;
9339 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9342 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9345 static int vmx_get_lpage_level(void)
9347 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9348 return PT_DIRECTORY_LEVEL
;
9350 /* For shadow and EPT supported 1GB page */
9351 return PT_PDPE_LEVEL
;
9354 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9357 * These bits in the secondary execution controls field
9358 * are dynamic, the others are mostly based on the hypervisor
9359 * architecture and the guest's CPUID. Do not touch the
9363 SECONDARY_EXEC_SHADOW_VMCS
|
9364 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9365 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9367 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9369 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9370 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9374 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9375 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9377 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9379 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9380 struct kvm_cpuid_entry2
*entry
;
9382 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9383 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9385 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9386 if (entry && (entry->_reg & (_cpuid_mask))) \
9387 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9390 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9391 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9392 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9393 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9394 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9395 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9396 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9397 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9398 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9399 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9400 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9401 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9402 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9403 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9404 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9406 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9407 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9408 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9409 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9410 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9411 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9412 cr4_fixed1_update(bit(11), ecx
, bit(2));
9414 #undef cr4_fixed1_update
9417 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9419 struct kvm_cpuid_entry2
*best
;
9420 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9421 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9423 if (vmx_rdtscp_supported()) {
9424 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9425 if (!rdtscp_enabled
)
9426 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9430 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9431 SECONDARY_EXEC_RDTSCP
;
9433 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9434 ~SECONDARY_EXEC_RDTSCP
;
9438 /* Exposing INVPCID only when PCID is exposed */
9439 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9440 if (vmx_invpcid_supported() &&
9441 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9442 !guest_cpuid_has_pcid(vcpu
))) {
9443 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9446 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9449 if (cpu_has_secondary_exec_ctrls())
9450 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9452 if (nested_vmx_allowed(vcpu
))
9453 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9454 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9456 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9457 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9459 if (nested_vmx_allowed(vcpu
))
9460 nested_vmx_cr_fixed1_bits_update(vcpu
);
9463 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9465 if (func
== 1 && nested
)
9466 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9469 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9470 struct x86_exception
*fault
)
9472 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9475 if (fault
->error_code
& PFERR_RSVD_MASK
)
9476 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9478 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9479 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9480 vmcs12
->guest_physical_address
= fault
->address
;
9483 /* Callbacks for nested_ept_init_mmu_context: */
9485 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9487 /* return the page table to be shadowed - in our case, EPT12 */
9488 return get_vmcs12(vcpu
)->ept_pointer
;
9491 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9493 WARN_ON(mmu_is_nested(vcpu
));
9494 kvm_init_shadow_ept_mmu(vcpu
,
9495 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9496 VMX_EPT_EXECUTE_ONLY_BIT
);
9497 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9498 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9499 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9501 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9504 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9506 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9509 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9512 bool inequality
, bit
;
9514 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9516 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9517 vmcs12
->page_fault_error_code_match
;
9518 return inequality
^ bit
;
9521 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9522 struct x86_exception
*fault
)
9524 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9526 WARN_ON(!is_guest_mode(vcpu
));
9528 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9529 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9530 vmcs_read32(VM_EXIT_INTR_INFO
),
9531 vmcs_readl(EXIT_QUALIFICATION
));
9533 kvm_inject_page_fault(vcpu
, fault
);
9536 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9537 struct vmcs12
*vmcs12
);
9539 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9540 struct vmcs12
*vmcs12
)
9542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9545 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9547 * Translate L1 physical address to host physical
9548 * address for vmcs02. Keep the page pinned, so this
9549 * physical address remains valid. We keep a reference
9550 * to it so we can release it later.
9552 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9553 nested_release_page(vmx
->nested
.apic_access_page
);
9554 vmx
->nested
.apic_access_page
=
9555 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9557 * If translation failed, no matter: This feature asks
9558 * to exit when accessing the given address, and if it
9559 * can never be accessed, this feature won't do
9562 if (vmx
->nested
.apic_access_page
) {
9563 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9564 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9566 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9567 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9569 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9570 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9571 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9572 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9573 kvm_vcpu_reload_apic_access_page(vcpu
);
9576 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9577 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9578 nested_release_page(vmx
->nested
.virtual_apic_page
);
9579 vmx
->nested
.virtual_apic_page
=
9580 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9583 * If translation failed, VM entry will fail because
9584 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9585 * Failing the vm entry is _not_ what the processor
9586 * does but it's basically the only possibility we
9587 * have. We could still enter the guest if CR8 load
9588 * exits are enabled, CR8 store exits are enabled, and
9589 * virtualize APIC access is disabled; in this case
9590 * the processor would never use the TPR shadow and we
9591 * could simply clear the bit from the execution
9592 * control. But such a configuration is useless, so
9593 * let's keep the code simple.
9595 if (vmx
->nested
.virtual_apic_page
) {
9596 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9597 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9601 if (nested_cpu_has_posted_intr(vmcs12
)) {
9602 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9603 kunmap(vmx
->nested
.pi_desc_page
);
9604 nested_release_page(vmx
->nested
.pi_desc_page
);
9606 vmx
->nested
.pi_desc_page
=
9607 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9608 vmx
->nested
.pi_desc
=
9609 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9610 if (!vmx
->nested
.pi_desc
) {
9611 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9614 vmx
->nested
.pi_desc
=
9615 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9616 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9618 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9619 page_to_phys(vmx
->nested
.pi_desc_page
) +
9620 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9623 if (cpu_has_vmx_msr_bitmap() &&
9624 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9625 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9628 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9629 CPU_BASED_USE_MSR_BITMAPS
);
9632 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9634 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9635 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9637 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9640 /* Make sure short timeouts reliably trigger an immediate vmexit.
9641 * hrtimer_start does not guarantee this. */
9642 if (preemption_timeout
<= 1) {
9643 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9647 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9648 preemption_timeout
*= 1000000;
9649 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9650 hrtimer_start(&vmx
->nested
.preemption_timer
,
9651 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9654 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9655 struct vmcs12
*vmcs12
)
9660 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9663 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9667 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9669 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9670 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9677 * Merge L0's and L1's MSR bitmap, return false to indicate that
9678 * we do not use the hardware.
9680 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9681 struct vmcs12
*vmcs12
)
9685 unsigned long *msr_bitmap_l1
;
9686 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9688 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9689 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9692 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9695 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9697 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9699 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9700 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9701 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9702 nested_vmx_disable_intercept_for_msr(
9703 msr_bitmap_l1
, msr_bitmap_l0
,
9706 nested_vmx_disable_intercept_for_msr(
9707 msr_bitmap_l1
, msr_bitmap_l0
,
9708 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9709 MSR_TYPE_R
| MSR_TYPE_W
);
9711 if (nested_cpu_has_vid(vmcs12
)) {
9712 nested_vmx_disable_intercept_for_msr(
9713 msr_bitmap_l1
, msr_bitmap_l0
,
9714 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9716 nested_vmx_disable_intercept_for_msr(
9717 msr_bitmap_l1
, msr_bitmap_l0
,
9718 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9723 nested_release_page_clean(page
);
9728 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9729 struct vmcs12
*vmcs12
)
9731 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9732 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9733 !nested_cpu_has_vid(vmcs12
) &&
9734 !nested_cpu_has_posted_intr(vmcs12
))
9738 * If virtualize x2apic mode is enabled,
9739 * virtualize apic access must be disabled.
9741 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9742 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9746 * If virtual interrupt delivery is enabled,
9747 * we must exit on external interrupts.
9749 if (nested_cpu_has_vid(vmcs12
) &&
9750 !nested_exit_on_intr(vcpu
))
9754 * bits 15:8 should be zero in posted_intr_nv,
9755 * the descriptor address has been already checked
9756 * in nested_get_vmcs12_pages.
9758 if (nested_cpu_has_posted_intr(vmcs12
) &&
9759 (!nested_cpu_has_vid(vmcs12
) ||
9760 !nested_exit_intr_ack_set(vcpu
) ||
9761 vmcs12
->posted_intr_nv
& 0xff00))
9764 /* tpr shadow is needed by all apicv features. */
9765 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9771 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9772 unsigned long count_field
,
9773 unsigned long addr_field
)
9778 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9779 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9785 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9786 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9787 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9788 pr_debug_ratelimited(
9789 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9790 addr_field
, maxphyaddr
, count
, addr
);
9796 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9797 struct vmcs12
*vmcs12
)
9799 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9800 vmcs12
->vm_exit_msr_store_count
== 0 &&
9801 vmcs12
->vm_entry_msr_load_count
== 0)
9802 return 0; /* Fast path */
9803 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9804 VM_EXIT_MSR_LOAD_ADDR
) ||
9805 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9806 VM_EXIT_MSR_STORE_ADDR
) ||
9807 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9808 VM_ENTRY_MSR_LOAD_ADDR
))
9813 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9814 struct vmx_msr_entry
*e
)
9816 /* x2APIC MSR accesses are not allowed */
9817 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9819 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9820 e
->index
== MSR_IA32_UCODE_REV
)
9822 if (e
->reserved
!= 0)
9827 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9828 struct vmx_msr_entry
*e
)
9830 if (e
->index
== MSR_FS_BASE
||
9831 e
->index
== MSR_GS_BASE
||
9832 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9833 nested_vmx_msr_check_common(vcpu
, e
))
9838 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9839 struct vmx_msr_entry
*e
)
9841 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9842 nested_vmx_msr_check_common(vcpu
, e
))
9848 * Load guest's/host's msr at nested entry/exit.
9849 * return 0 for success, entry index for failure.
9851 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9854 struct vmx_msr_entry e
;
9855 struct msr_data msr
;
9857 msr
.host_initiated
= false;
9858 for (i
= 0; i
< count
; i
++) {
9859 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9861 pr_debug_ratelimited(
9862 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9863 __func__
, i
, gpa
+ i
* sizeof(e
));
9866 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9867 pr_debug_ratelimited(
9868 "%s check failed (%u, 0x%x, 0x%x)\n",
9869 __func__
, i
, e
.index
, e
.reserved
);
9872 msr
.index
= e
.index
;
9874 if (kvm_set_msr(vcpu
, &msr
)) {
9875 pr_debug_ratelimited(
9876 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9877 __func__
, i
, e
.index
, e
.value
);
9886 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9889 struct vmx_msr_entry e
;
9891 for (i
= 0; i
< count
; i
++) {
9892 struct msr_data msr_info
;
9893 if (kvm_vcpu_read_guest(vcpu
,
9894 gpa
+ i
* sizeof(e
),
9895 &e
, 2 * sizeof(u32
))) {
9896 pr_debug_ratelimited(
9897 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9898 __func__
, i
, gpa
+ i
* sizeof(e
));
9901 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9902 pr_debug_ratelimited(
9903 "%s check failed (%u, 0x%x, 0x%x)\n",
9904 __func__
, i
, e
.index
, e
.reserved
);
9907 msr_info
.host_initiated
= false;
9908 msr_info
.index
= e
.index
;
9909 if (kvm_get_msr(vcpu
, &msr_info
)) {
9910 pr_debug_ratelimited(
9911 "%s cannot read MSR (%u, 0x%x)\n",
9912 __func__
, i
, e
.index
);
9915 if (kvm_vcpu_write_guest(vcpu
,
9916 gpa
+ i
* sizeof(e
) +
9917 offsetof(struct vmx_msr_entry
, value
),
9918 &msr_info
.data
, sizeof(msr_info
.data
))) {
9919 pr_debug_ratelimited(
9920 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9921 __func__
, i
, e
.index
, msr_info
.data
);
9928 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9930 unsigned long invalid_mask
;
9932 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9933 return (val
& invalid_mask
) == 0;
9937 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9938 * emulating VM entry into a guest with EPT enabled.
9939 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9940 * is assigned to entry_failure_code on failure.
9942 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
9943 u32
*entry_failure_code
)
9945 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
9946 if (!nested_cr3_valid(vcpu
, cr3
)) {
9947 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
9952 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9953 * must not be dereferenced.
9955 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
9957 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
9958 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
9963 vcpu
->arch
.cr3
= cr3
;
9964 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
9967 kvm_mmu_reset_context(vcpu
);
9972 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9973 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9974 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9975 * guest in a way that will both be appropriate to L1's requests, and our
9976 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9977 * function also has additional necessary side-effects, like setting various
9978 * vcpu->arch fields.
9979 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9980 * is assigned to entry_failure_code on failure.
9982 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9983 bool from_vmentry
, u32
*entry_failure_code
)
9985 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9987 bool nested_ept_enabled
= false;
9989 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9990 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9991 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9992 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9993 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9994 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9995 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9996 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9997 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9998 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9999 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10000 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10001 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10002 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10003 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10004 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10005 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10006 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10007 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10008 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10009 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10010 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10011 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10012 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10013 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10014 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10015 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10016 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10017 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10018 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10019 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10020 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10021 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10022 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10023 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10024 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10026 if (from_vmentry
&&
10027 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10028 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10029 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10031 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10032 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10034 if (from_vmentry
) {
10035 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10036 vmcs12
->vm_entry_intr_info_field
);
10037 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10038 vmcs12
->vm_entry_exception_error_code
);
10039 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10040 vmcs12
->vm_entry_instruction_len
);
10041 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10042 vmcs12
->guest_interruptibility_info
);
10044 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10046 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10047 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10048 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10049 vmcs12
->guest_pending_dbg_exceptions
);
10050 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10051 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10053 if (nested_cpu_has_xsaves(vmcs12
))
10054 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10055 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10057 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10059 /* Preemption timer setting is only taken from vmcs01. */
10060 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10061 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10062 if (vmx
->hv_deadline_tsc
== -1)
10063 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10065 /* Posted interrupts setting is only taken from vmcs12. */
10066 if (nested_cpu_has_posted_intr(vmcs12
)) {
10068 * Note that we use L0's vector here and in
10069 * vmx_deliver_nested_posted_interrupt.
10071 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10072 vmx
->nested
.pi_pending
= false;
10073 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
10075 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10078 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10080 vmx
->nested
.preemption_timer_expired
= false;
10081 if (nested_cpu_has_preemption_timer(vmcs12
))
10082 vmx_start_preemption_timer(vcpu
);
10085 * Whether page-faults are trapped is determined by a combination of
10086 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10087 * If enable_ept, L0 doesn't care about page faults and we should
10088 * set all of these to L1's desires. However, if !enable_ept, L0 does
10089 * care about (at least some) page faults, and because it is not easy
10090 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10091 * to exit on each and every L2 page fault. This is done by setting
10092 * MASK=MATCH=0 and (see below) EB.PF=1.
10093 * Note that below we don't need special code to set EB.PF beyond the
10094 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10095 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10096 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10098 * A problem with this approach (when !enable_ept) is that L1 may be
10099 * injected with more page faults than it asked for. This could have
10100 * caused problems, but in practice existing hypervisors don't care.
10101 * To fix this, we will need to emulate the PFEC checking (on the L1
10102 * page tables), using walk_addr(), when injecting PFs to L1.
10104 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10105 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10106 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10107 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10109 if (cpu_has_secondary_exec_ctrls()) {
10110 exec_control
= vmx_secondary_exec_control(vmx
);
10112 /* Take the following fields only from vmcs12 */
10113 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10114 SECONDARY_EXEC_RDTSCP
|
10115 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10116 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10117 if (nested_cpu_has(vmcs12
,
10118 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
10119 exec_control
|= vmcs12
->secondary_vm_exec_control
;
10121 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10122 vmcs_write64(EOI_EXIT_BITMAP0
,
10123 vmcs12
->eoi_exit_bitmap0
);
10124 vmcs_write64(EOI_EXIT_BITMAP1
,
10125 vmcs12
->eoi_exit_bitmap1
);
10126 vmcs_write64(EOI_EXIT_BITMAP2
,
10127 vmcs12
->eoi_exit_bitmap2
);
10128 vmcs_write64(EOI_EXIT_BITMAP3
,
10129 vmcs12
->eoi_exit_bitmap3
);
10130 vmcs_write16(GUEST_INTR_STATUS
,
10131 vmcs12
->guest_intr_status
);
10134 nested_ept_enabled
= (exec_control
& SECONDARY_EXEC_ENABLE_EPT
) != 0;
10137 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10138 * nested_get_vmcs12_pages will either fix it up or
10139 * remove the VM execution control.
10141 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10142 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10144 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10149 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10150 * Some constant fields are set here by vmx_set_constant_host_state().
10151 * Other fields are different per CPU, and will be set later when
10152 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10154 vmx_set_constant_host_state(vmx
);
10157 * Set the MSR load/store lists to match L0's settings.
10159 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10160 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10161 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10162 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10163 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10166 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10167 * entry, but only if the current (host) sp changed from the value
10168 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10169 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10170 * here we just force the write to happen on entry.
10174 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10175 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10176 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10177 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10178 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10181 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10182 * nested_get_vmcs12_pages can't fix it up, the illegal value
10183 * will result in a VM entry failure.
10185 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10186 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10187 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10191 * Merging of IO bitmap not currently supported.
10192 * Rather, exit every time.
10194 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10195 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10197 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10199 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10200 * bitwise-or of what L1 wants to trap for L2, and what we want to
10201 * trap. Note that CR0.TS also needs updating - we do this later.
10203 update_exception_bitmap(vcpu
);
10204 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10205 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10207 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10208 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10209 * bits are further modified by vmx_set_efer() below.
10211 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10213 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10214 * emulated by vmx_set_efer(), below.
10216 vm_entry_controls_init(vmx
,
10217 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10218 ~VM_ENTRY_IA32E_MODE
) |
10219 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10221 if (from_vmentry
&&
10222 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10223 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10224 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10225 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10226 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10229 set_cr4_guest_host_mask(vmx
);
10231 if (from_vmentry
&&
10232 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10233 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10235 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10236 vmcs_write64(TSC_OFFSET
,
10237 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10239 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10240 if (kvm_has_tsc_control
)
10241 decache_tsc_multiplier(vmx
);
10245 * There is no direct mapping between vpid02 and vpid12, the
10246 * vpid02 is per-vCPU for L0 and reused while the value of
10247 * vpid12 is changed w/ one invvpid during nested vmentry.
10248 * The vpid12 is allocated by L1 for L2, so it will not
10249 * influence global bitmap(for vpid01 and vpid02 allocation)
10250 * even if spawn a lot of nested vCPUs.
10252 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10253 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10254 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10255 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10256 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10259 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10260 vmx_flush_tlb(vcpu
);
10265 if (nested_cpu_has_ept(vmcs12
)) {
10266 kvm_mmu_unload(vcpu
);
10267 nested_ept_init_mmu_context(vcpu
);
10268 } else if (nested_cpu_has2(vmcs12
,
10269 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10270 vmx_flush_tlb_ept_only(vcpu
);
10274 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10275 * bits which we consider mandatory enabled.
10276 * The CR0_READ_SHADOW is what L2 should have expected to read given
10277 * the specifications by L1; It's not enough to take
10278 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10279 * have more bits than L1 expected.
10281 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10282 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10284 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10285 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10287 if (from_vmentry
&&
10288 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10289 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10290 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10291 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10293 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10294 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10295 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10297 /* Shadow page tables on either EPT or shadow page tables. */
10298 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_ept_enabled
,
10299 entry_failure_code
))
10303 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10306 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10309 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10310 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10311 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10312 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10315 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10316 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10320 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10322 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10324 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10325 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10326 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10328 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10329 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10331 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10332 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10334 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10335 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10337 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10338 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10339 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10340 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10341 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10342 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10343 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10344 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10345 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10346 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10347 vmx
->nested
.nested_vmx_exit_ctls_low
,
10348 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10349 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10350 vmx
->nested
.nested_vmx_entry_ctls_low
,
10351 vmx
->nested
.nested_vmx_entry_ctls_high
))
10352 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10354 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10355 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10356 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10357 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10362 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10367 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10369 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10370 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10373 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10374 vmcs12
->vmcs_link_pointer
!= -1ull) {
10375 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10380 * If the load IA32_EFER VM-entry control is 1, the following checks
10381 * are performed on the field for the IA32_EFER MSR:
10382 * - Bits reserved in the IA32_EFER MSR must be 0.
10383 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10384 * the IA-32e mode guest VM-exit control. It must also be identical
10385 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10388 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10389 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10390 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10391 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10392 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10393 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10394 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10399 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10400 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10401 * the values of the LMA and LME bits in the field must each be that of
10402 * the host address-space size VM-exit control.
10404 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10405 ia32e
= (vmcs12
->vm_exit_controls
&
10406 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10407 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10408 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10409 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10416 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10418 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10419 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10420 struct loaded_vmcs
*vmcs02
;
10425 vmcs02
= nested_get_current_vmcs02(vmx
);
10429 enter_guest_mode(vcpu
);
10431 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10432 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10435 vmx
->loaded_vmcs
= vmcs02
;
10436 vmx_vcpu_put(vcpu
);
10437 vmx_vcpu_load(vcpu
, cpu
);
10441 vmx_segment_cache_clear(vmx
);
10443 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10444 leave_guest_mode(vcpu
);
10445 vmx_load_vmcs01(vcpu
);
10446 nested_vmx_entry_failure(vcpu
, vmcs12
,
10447 EXIT_REASON_INVALID_STATE
, exit_qual
);
10451 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10453 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10454 vmcs12
->vm_entry_msr_load_addr
,
10455 vmcs12
->vm_entry_msr_load_count
);
10456 if (msr_entry_idx
) {
10457 leave_guest_mode(vcpu
);
10458 vmx_load_vmcs01(vcpu
);
10459 nested_vmx_entry_failure(vcpu
, vmcs12
,
10460 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10464 vmcs12
->launch_state
= 1;
10467 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10468 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10469 * returned as far as L1 is concerned. It will only return (and set
10470 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10476 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10477 * for running an L2 nested guest.
10479 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10481 struct vmcs12
*vmcs12
;
10482 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10486 if (!nested_vmx_check_permission(vcpu
))
10489 if (!nested_vmx_check_vmcs12(vcpu
))
10492 vmcs12
= get_vmcs12(vcpu
);
10494 if (enable_shadow_vmcs
)
10495 copy_shadow_to_vmcs12(vmx
);
10498 * The nested entry process starts with enforcing various prerequisites
10499 * on vmcs12 as required by the Intel SDM, and act appropriately when
10500 * they fail: As the SDM explains, some conditions should cause the
10501 * instruction to fail, while others will cause the instruction to seem
10502 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10503 * To speed up the normal (success) code path, we should avoid checking
10504 * for misconfigurations which will anyway be caught by the processor
10505 * when using the merged vmcs02.
10507 if (vmcs12
->launch_state
== launch
) {
10508 nested_vmx_failValid(vcpu
,
10509 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10510 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10514 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10516 nested_vmx_failValid(vcpu
, ret
);
10521 * After this point, the trap flag no longer triggers a singlestep trap
10522 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10523 * This is not 100% correct; for performance reasons, we delegate most
10524 * of the checks on host state to the processor. If those fail,
10525 * the singlestep trap is missed.
10527 skip_emulated_instruction(vcpu
);
10529 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10531 nested_vmx_entry_failure(vcpu
, vmcs12
,
10532 EXIT_REASON_INVALID_STATE
, exit_qual
);
10537 * We're finally done with prerequisite checking, and can start with
10538 * the nested entry.
10541 ret
= enter_vmx_non_root_mode(vcpu
, true);
10545 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10546 return kvm_vcpu_halt(vcpu
);
10548 vmx
->nested
.nested_run_pending
= 1;
10553 return kvm_skip_emulated_instruction(vcpu
);
10557 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10558 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10559 * This function returns the new value we should put in vmcs12.guest_cr0.
10560 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10561 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10562 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10563 * didn't trap the bit, because if L1 did, so would L0).
10564 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10565 * been modified by L2, and L1 knows it. So just leave the old value of
10566 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10567 * isn't relevant, because if L0 traps this bit it can set it to anything.
10568 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10569 * changed these bits, and therefore they need to be updated, but L0
10570 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10571 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10573 static inline unsigned long
10574 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10577 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10578 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10579 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10580 vcpu
->arch
.cr0_guest_owned_bits
));
10583 static inline unsigned long
10584 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10587 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10588 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10589 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10590 vcpu
->arch
.cr4_guest_owned_bits
));
10593 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10594 struct vmcs12
*vmcs12
)
10599 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10600 nr
= vcpu
->arch
.exception
.nr
;
10601 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10603 if (kvm_exception_is_soft(nr
)) {
10604 vmcs12
->vm_exit_instruction_len
=
10605 vcpu
->arch
.event_exit_inst_len
;
10606 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10608 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10610 if (vcpu
->arch
.exception
.has_error_code
) {
10611 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10612 vmcs12
->idt_vectoring_error_code
=
10613 vcpu
->arch
.exception
.error_code
;
10616 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10617 } else if (vcpu
->arch
.nmi_injected
) {
10618 vmcs12
->idt_vectoring_info_field
=
10619 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10620 } else if (vcpu
->arch
.interrupt
.pending
) {
10621 nr
= vcpu
->arch
.interrupt
.nr
;
10622 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10624 if (vcpu
->arch
.interrupt
.soft
) {
10625 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10626 vmcs12
->vm_entry_instruction_len
=
10627 vcpu
->arch
.event_exit_inst_len
;
10629 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10631 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10635 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10637 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10639 if (vcpu
->arch
.exception
.pending
||
10640 vcpu
->arch
.nmi_injected
||
10641 vcpu
->arch
.interrupt
.pending
)
10644 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10645 vmx
->nested
.preemption_timer_expired
) {
10646 if (vmx
->nested
.nested_run_pending
)
10648 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10652 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10653 if (vmx
->nested
.nested_run_pending
)
10655 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10656 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10657 INTR_INFO_VALID_MASK
, 0);
10659 * The NMI-triggered VM exit counts as injection:
10660 * clear this one and block further NMIs.
10662 vcpu
->arch
.nmi_pending
= 0;
10663 vmx_set_nmi_mask(vcpu
, true);
10667 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10668 nested_exit_on_intr(vcpu
)) {
10669 if (vmx
->nested
.nested_run_pending
)
10671 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10675 vmx_complete_nested_posted_interrupt(vcpu
);
10679 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10681 ktime_t remaining
=
10682 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10685 if (ktime_to_ns(remaining
) <= 0)
10688 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10689 do_div(value
, 1000000);
10690 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10694 * Update the guest state fields of vmcs12 to reflect changes that
10695 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10696 * VM-entry controls is also updated, since this is really a guest
10699 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10701 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10702 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10704 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10705 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10706 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10708 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10709 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10710 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10711 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10712 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10713 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10714 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10715 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10716 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10717 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10718 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10719 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10720 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10721 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10722 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10723 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10724 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10725 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10726 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10727 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10728 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10729 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10730 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10731 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10732 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10733 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10734 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10735 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10736 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10737 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10738 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10739 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10740 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10741 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10742 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10743 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10745 vmcs12
->guest_interruptibility_info
=
10746 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10747 vmcs12
->guest_pending_dbg_exceptions
=
10748 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10749 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10750 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10752 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10754 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10755 if (vmcs12
->vm_exit_controls
&
10756 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10757 vmcs12
->vmx_preemption_timer_value
=
10758 vmx_get_preemption_timer_value(vcpu
);
10759 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10763 * In some cases (usually, nested EPT), L2 is allowed to change its
10764 * own CR3 without exiting. If it has changed it, we must keep it.
10765 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10766 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10768 * Additionally, restore L2's PDPTR to vmcs12.
10771 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10772 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10773 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10774 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10775 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10778 if (nested_cpu_has_ept(vmcs12
))
10779 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10781 if (nested_cpu_has_vid(vmcs12
))
10782 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10784 vmcs12
->vm_entry_controls
=
10785 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10786 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10788 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10789 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10790 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10793 /* TODO: These cannot have changed unless we have MSR bitmaps and
10794 * the relevant bit asks not to trap the change */
10795 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10796 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10797 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10798 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10799 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10800 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10801 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10802 if (kvm_mpx_supported())
10803 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10804 if (nested_cpu_has_xsaves(vmcs12
))
10805 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10809 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10810 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10811 * and this function updates it to reflect the changes to the guest state while
10812 * L2 was running (and perhaps made some exits which were handled directly by L0
10813 * without going back to L1), and to reflect the exit reason.
10814 * Note that we do not have to copy here all VMCS fields, just those that
10815 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10816 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10817 * which already writes to vmcs12 directly.
10819 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10820 u32 exit_reason
, u32 exit_intr_info
,
10821 unsigned long exit_qualification
)
10823 /* update guest state fields: */
10824 sync_vmcs12(vcpu
, vmcs12
);
10826 /* update exit information fields: */
10828 vmcs12
->vm_exit_reason
= exit_reason
;
10829 vmcs12
->exit_qualification
= exit_qualification
;
10831 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10832 if ((vmcs12
->vm_exit_intr_info
&
10833 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10834 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10835 vmcs12
->vm_exit_intr_error_code
=
10836 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10837 vmcs12
->idt_vectoring_info_field
= 0;
10838 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10839 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10841 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10842 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10843 * instead of reading the real value. */
10844 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10847 * Transfer the event that L0 or L1 may wanted to inject into
10848 * L2 to IDT_VECTORING_INFO_FIELD.
10850 vmcs12_save_pending_event(vcpu
, vmcs12
);
10854 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10855 * preserved above and would only end up incorrectly in L1.
10857 vcpu
->arch
.nmi_injected
= false;
10858 kvm_clear_exception_queue(vcpu
);
10859 kvm_clear_interrupt_queue(vcpu
);
10863 * A part of what we need to when the nested L2 guest exits and we want to
10864 * run its L1 parent, is to reset L1's guest state to the host state specified
10866 * This function is to be called not only on normal nested exit, but also on
10867 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10868 * Failures During or After Loading Guest State").
10869 * This function should be called when the active VMCS is L1's (vmcs01).
10871 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10872 struct vmcs12
*vmcs12
)
10874 struct kvm_segment seg
;
10875 u32 entry_failure_code
;
10877 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10878 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10879 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10880 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10882 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10883 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10885 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10886 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10887 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10889 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10890 * actually changed, because vmx_set_cr0 refers to efer set above.
10892 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10893 * (KVM doesn't change it);
10895 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10896 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10898 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10899 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10900 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10902 nested_ept_uninit_mmu_context(vcpu
);
10905 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10906 * couldn't have changed.
10908 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10909 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10912 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10916 * Trivially support vpid by letting L2s share their parent
10917 * L1's vpid. TODO: move to a more elaborate solution, giving
10918 * each L2 its own vpid and exposing the vpid feature to L1.
10920 vmx_flush_tlb(vcpu
);
10924 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10925 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10926 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10927 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10928 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10930 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10931 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10932 vmcs_write64(GUEST_BNDCFGS
, 0);
10934 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10935 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10936 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10938 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10939 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10940 vmcs12
->host_ia32_perf_global_ctrl
);
10942 /* Set L1 segment info according to Intel SDM
10943 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10944 seg
= (struct kvm_segment
) {
10946 .limit
= 0xFFFFFFFF,
10947 .selector
= vmcs12
->host_cs_selector
,
10953 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10957 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10958 seg
= (struct kvm_segment
) {
10960 .limit
= 0xFFFFFFFF,
10967 seg
.selector
= vmcs12
->host_ds_selector
;
10968 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10969 seg
.selector
= vmcs12
->host_es_selector
;
10970 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10971 seg
.selector
= vmcs12
->host_ss_selector
;
10972 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10973 seg
.selector
= vmcs12
->host_fs_selector
;
10974 seg
.base
= vmcs12
->host_fs_base
;
10975 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10976 seg
.selector
= vmcs12
->host_gs_selector
;
10977 seg
.base
= vmcs12
->host_gs_base
;
10978 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10979 seg
= (struct kvm_segment
) {
10980 .base
= vmcs12
->host_tr_base
,
10982 .selector
= vmcs12
->host_tr_selector
,
10986 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10988 kvm_set_dr(vcpu
, 7, 0x400);
10989 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10991 if (cpu_has_vmx_msr_bitmap())
10992 vmx_set_msr_bitmap(vcpu
);
10994 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10995 vmcs12
->vm_exit_msr_load_count
))
10996 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11000 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11001 * and modify vmcs12 to make it see what it would expect to see there if
11002 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11004 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11005 u32 exit_intr_info
,
11006 unsigned long exit_qualification
)
11008 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11009 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11010 u32 vm_inst_error
= 0;
11012 /* trying to cancel vmlaunch/vmresume is a bug */
11013 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11015 leave_guest_mode(vcpu
);
11016 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11017 exit_qualification
);
11019 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11020 vmcs12
->vm_exit_msr_store_count
))
11021 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11023 if (unlikely(vmx
->fail
))
11024 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11026 vmx_load_vmcs01(vcpu
);
11028 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
11029 && nested_exit_intr_ack_set(vcpu
)) {
11030 int irq
= kvm_cpu_get_interrupt(vcpu
);
11032 vmcs12
->vm_exit_intr_info
= irq
|
11033 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11036 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11037 vmcs12
->exit_qualification
,
11038 vmcs12
->idt_vectoring_info_field
,
11039 vmcs12
->vm_exit_intr_info
,
11040 vmcs12
->vm_exit_intr_error_code
,
11043 vm_entry_controls_reset_shadow(vmx
);
11044 vm_exit_controls_reset_shadow(vmx
);
11045 vmx_segment_cache_clear(vmx
);
11047 /* if no vmcs02 cache requested, remove the one we used */
11048 if (VMCS02_POOL_SIZE
== 0)
11049 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11051 load_vmcs12_host_state(vcpu
, vmcs12
);
11053 /* Update any VMCS fields that might have changed while L2 ran */
11054 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11055 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11056 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11057 if (vmx
->hv_deadline_tsc
== -1)
11058 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11059 PIN_BASED_VMX_PREEMPTION_TIMER
);
11061 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11062 PIN_BASED_VMX_PREEMPTION_TIMER
);
11063 if (kvm_has_tsc_control
)
11064 decache_tsc_multiplier(vmx
);
11066 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11067 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11068 vmx_set_virtual_x2apic_mode(vcpu
,
11069 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11070 } else if (!nested_cpu_has_ept(vmcs12
) &&
11071 nested_cpu_has2(vmcs12
,
11072 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11073 vmx_flush_tlb_ept_only(vcpu
);
11076 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11079 /* Unpin physical memory we referred to in vmcs02 */
11080 if (vmx
->nested
.apic_access_page
) {
11081 nested_release_page(vmx
->nested
.apic_access_page
);
11082 vmx
->nested
.apic_access_page
= NULL
;
11084 if (vmx
->nested
.virtual_apic_page
) {
11085 nested_release_page(vmx
->nested
.virtual_apic_page
);
11086 vmx
->nested
.virtual_apic_page
= NULL
;
11088 if (vmx
->nested
.pi_desc_page
) {
11089 kunmap(vmx
->nested
.pi_desc_page
);
11090 nested_release_page(vmx
->nested
.pi_desc_page
);
11091 vmx
->nested
.pi_desc_page
= NULL
;
11092 vmx
->nested
.pi_desc
= NULL
;
11096 * We are now running in L2, mmu_notifier will force to reload the
11097 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11099 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11102 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11103 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11104 * success or failure flag accordingly.
11106 if (unlikely(vmx
->fail
)) {
11108 nested_vmx_failValid(vcpu
, vm_inst_error
);
11110 nested_vmx_succeed(vcpu
);
11111 if (enable_shadow_vmcs
)
11112 vmx
->nested
.sync_shadow_vmcs
= true;
11114 /* in case we halted in L2 */
11115 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11119 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11121 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11123 if (is_guest_mode(vcpu
)) {
11124 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11125 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11127 free_nested(to_vmx(vcpu
));
11131 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11132 * 23.7 "VM-entry failures during or after loading guest state" (this also
11133 * lists the acceptable exit-reason and exit-qualification parameters).
11134 * It should only be called before L2 actually succeeded to run, and when
11135 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11137 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11138 struct vmcs12
*vmcs12
,
11139 u32 reason
, unsigned long qualification
)
11141 load_vmcs12_host_state(vcpu
, vmcs12
);
11142 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11143 vmcs12
->exit_qualification
= qualification
;
11144 nested_vmx_succeed(vcpu
);
11145 if (enable_shadow_vmcs
)
11146 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11149 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11150 struct x86_instruction_info
*info
,
11151 enum x86_intercept_stage stage
)
11153 return X86EMUL_CONTINUE
;
11156 #ifdef CONFIG_X86_64
11157 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11158 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11159 u64 divisor
, u64
*result
)
11161 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11163 /* To avoid the overflow on divq */
11164 if (high
>= divisor
)
11167 /* Low hold the result, high hold rem which is discarded */
11168 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11169 "rm" (divisor
), "0" (low
), "1" (high
));
11175 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11177 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11178 u64 tscl
= rdtsc();
11179 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11180 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11182 /* Convert to host delta tsc if tsc scaling is enabled */
11183 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11184 u64_shl_div_u64(delta_tsc
,
11185 kvm_tsc_scaling_ratio_frac_bits
,
11186 vcpu
->arch
.tsc_scaling_ratio
,
11191 * If the delta tsc can't fit in the 32 bit after the multi shift,
11192 * we can't use the preemption timer.
11193 * It's possible that it fits on later vmentries, but checking
11194 * on every vmentry is costly so we just use an hrtimer.
11196 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11199 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11200 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11201 PIN_BASED_VMX_PREEMPTION_TIMER
);
11205 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11207 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11208 vmx
->hv_deadline_tsc
= -1;
11209 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11210 PIN_BASED_VMX_PREEMPTION_TIMER
);
11214 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11217 shrink_ple_window(vcpu
);
11220 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11221 struct kvm_memory_slot
*slot
)
11223 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11224 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11227 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11228 struct kvm_memory_slot
*slot
)
11230 kvm_mmu_slot_set_dirty(kvm
, slot
);
11233 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11235 kvm_flush_pml_buffers(kvm
);
11238 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11239 struct kvm_memory_slot
*memslot
,
11240 gfn_t offset
, unsigned long mask
)
11242 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11246 * This routine does the following things for vCPU which is going
11247 * to be blocked if VT-d PI is enabled.
11248 * - Store the vCPU to the wakeup list, so when interrupts happen
11249 * we can find the right vCPU to wake up.
11250 * - Change the Posted-interrupt descriptor as below:
11251 * 'NDST' <-- vcpu->pre_pcpu
11252 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11253 * - If 'ON' is set during this process, which means at least one
11254 * interrupt is posted for this vCPU, we cannot block it, in
11255 * this case, return 1, otherwise, return 0.
11258 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11260 unsigned long flags
;
11262 struct pi_desc old
, new;
11263 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11265 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11266 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11267 !kvm_vcpu_apicv_active(vcpu
))
11270 vcpu
->pre_pcpu
= vcpu
->cpu
;
11271 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11272 vcpu
->pre_pcpu
), flags
);
11273 list_add_tail(&vcpu
->blocked_vcpu_list
,
11274 &per_cpu(blocked_vcpu_on_cpu
,
11276 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11277 vcpu
->pre_pcpu
), flags
);
11280 old
.control
= new.control
= pi_desc
->control
;
11283 * We should not block the vCPU if
11284 * an interrupt is posted for it.
11286 if (pi_test_on(pi_desc
) == 1) {
11287 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11288 vcpu
->pre_pcpu
), flags
);
11289 list_del(&vcpu
->blocked_vcpu_list
);
11290 spin_unlock_irqrestore(
11291 &per_cpu(blocked_vcpu_on_cpu_lock
,
11292 vcpu
->pre_pcpu
), flags
);
11293 vcpu
->pre_pcpu
= -1;
11298 WARN((pi_desc
->sn
== 1),
11299 "Warning: SN field of posted-interrupts "
11300 "is set before blocking\n");
11303 * Since vCPU can be preempted during this process,
11304 * vcpu->cpu could be different with pre_pcpu, we
11305 * need to set pre_pcpu as the destination of wakeup
11306 * notification event, then we can find the right vCPU
11307 * to wakeup in wakeup handler if interrupts happen
11308 * when the vCPU is in blocked state.
11310 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11312 if (x2apic_enabled())
11315 new.ndst
= (dest
<< 8) & 0xFF00;
11317 /* set 'NV' to 'wakeup vector' */
11318 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11319 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11320 new.control
) != old
.control
);
11325 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11327 if (pi_pre_block(vcpu
))
11330 if (kvm_lapic_hv_timer_in_use(vcpu
))
11331 kvm_lapic_switch_to_sw_timer(vcpu
);
11336 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11338 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11339 struct pi_desc old
, new;
11341 unsigned long flags
;
11343 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11344 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11345 !kvm_vcpu_apicv_active(vcpu
))
11349 old
.control
= new.control
= pi_desc
->control
;
11351 dest
= cpu_physical_id(vcpu
->cpu
);
11353 if (x2apic_enabled())
11356 new.ndst
= (dest
<< 8) & 0xFF00;
11358 /* Allow posting non-urgent interrupts */
11361 /* set 'NV' to 'notification vector' */
11362 new.nv
= POSTED_INTR_VECTOR
;
11363 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11364 new.control
) != old
.control
);
11366 if(vcpu
->pre_pcpu
!= -1) {
11368 &per_cpu(blocked_vcpu_on_cpu_lock
,
11369 vcpu
->pre_pcpu
), flags
);
11370 list_del(&vcpu
->blocked_vcpu_list
);
11371 spin_unlock_irqrestore(
11372 &per_cpu(blocked_vcpu_on_cpu_lock
,
11373 vcpu
->pre_pcpu
), flags
);
11374 vcpu
->pre_pcpu
= -1;
11378 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11380 if (kvm_x86_ops
->set_hv_timer
)
11381 kvm_lapic_switch_to_hv_timer(vcpu
);
11383 pi_post_block(vcpu
);
11387 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11390 * @host_irq: host irq of the interrupt
11391 * @guest_irq: gsi of the interrupt
11392 * @set: set or unset PI
11393 * returns 0 on success, < 0 on failure
11395 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11396 uint32_t guest_irq
, bool set
)
11398 struct kvm_kernel_irq_routing_entry
*e
;
11399 struct kvm_irq_routing_table
*irq_rt
;
11400 struct kvm_lapic_irq irq
;
11401 struct kvm_vcpu
*vcpu
;
11402 struct vcpu_data vcpu_info
;
11403 int idx
, ret
= -EINVAL
;
11405 if (!kvm_arch_has_assigned_device(kvm
) ||
11406 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11407 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11410 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11411 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11412 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11414 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11415 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11418 * VT-d PI cannot support posting multicast/broadcast
11419 * interrupts to a vCPU, we still use interrupt remapping
11420 * for these kind of interrupts.
11422 * For lowest-priority interrupts, we only support
11423 * those with single CPU as the destination, e.g. user
11424 * configures the interrupts via /proc/irq or uses
11425 * irqbalance to make the interrupts single-CPU.
11427 * We will support full lowest-priority interrupt later.
11430 kvm_set_msi_irq(kvm
, e
, &irq
);
11431 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11433 * Make sure the IRTE is in remapped mode if
11434 * we don't handle it in posted mode.
11436 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11439 "failed to back to remapped mode, irq: %u\n",
11447 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11448 vcpu_info
.vector
= irq
.vector
;
11450 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11451 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11454 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11456 /* suppress notification event before unposting */
11457 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11458 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11459 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11463 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11471 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11475 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11477 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11478 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11479 FEATURE_CONTROL_LMCE
;
11481 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11482 ~FEATURE_CONTROL_LMCE
;
11485 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11486 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11487 .disabled_by_bios
= vmx_disabled_by_bios
,
11488 .hardware_setup
= hardware_setup
,
11489 .hardware_unsetup
= hardware_unsetup
,
11490 .check_processor_compatibility
= vmx_check_processor_compat
,
11491 .hardware_enable
= hardware_enable
,
11492 .hardware_disable
= hardware_disable
,
11493 .cpu_has_accelerated_tpr
= report_flexpriority
,
11494 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11496 .vcpu_create
= vmx_create_vcpu
,
11497 .vcpu_free
= vmx_free_vcpu
,
11498 .vcpu_reset
= vmx_vcpu_reset
,
11500 .prepare_guest_switch
= vmx_save_host_state
,
11501 .vcpu_load
= vmx_vcpu_load
,
11502 .vcpu_put
= vmx_vcpu_put
,
11504 .update_bp_intercept
= update_exception_bitmap
,
11505 .get_msr
= vmx_get_msr
,
11506 .set_msr
= vmx_set_msr
,
11507 .get_segment_base
= vmx_get_segment_base
,
11508 .get_segment
= vmx_get_segment
,
11509 .set_segment
= vmx_set_segment
,
11510 .get_cpl
= vmx_get_cpl
,
11511 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11512 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11513 .decache_cr3
= vmx_decache_cr3
,
11514 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11515 .set_cr0
= vmx_set_cr0
,
11516 .set_cr3
= vmx_set_cr3
,
11517 .set_cr4
= vmx_set_cr4
,
11518 .set_efer
= vmx_set_efer
,
11519 .get_idt
= vmx_get_idt
,
11520 .set_idt
= vmx_set_idt
,
11521 .get_gdt
= vmx_get_gdt
,
11522 .set_gdt
= vmx_set_gdt
,
11523 .get_dr6
= vmx_get_dr6
,
11524 .set_dr6
= vmx_set_dr6
,
11525 .set_dr7
= vmx_set_dr7
,
11526 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11527 .cache_reg
= vmx_cache_reg
,
11528 .get_rflags
= vmx_get_rflags
,
11529 .set_rflags
= vmx_set_rflags
,
11531 .get_pkru
= vmx_get_pkru
,
11533 .tlb_flush
= vmx_flush_tlb
,
11535 .run
= vmx_vcpu_run
,
11536 .handle_exit
= vmx_handle_exit
,
11537 .skip_emulated_instruction
= skip_emulated_instruction
,
11538 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11539 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11540 .patch_hypercall
= vmx_patch_hypercall
,
11541 .set_irq
= vmx_inject_irq
,
11542 .set_nmi
= vmx_inject_nmi
,
11543 .queue_exception
= vmx_queue_exception
,
11544 .cancel_injection
= vmx_cancel_injection
,
11545 .interrupt_allowed
= vmx_interrupt_allowed
,
11546 .nmi_allowed
= vmx_nmi_allowed
,
11547 .get_nmi_mask
= vmx_get_nmi_mask
,
11548 .set_nmi_mask
= vmx_set_nmi_mask
,
11549 .enable_nmi_window
= enable_nmi_window
,
11550 .enable_irq_window
= enable_irq_window
,
11551 .update_cr8_intercept
= update_cr8_intercept
,
11552 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11553 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11554 .get_enable_apicv
= vmx_get_enable_apicv
,
11555 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11556 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11557 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11558 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11559 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11560 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11561 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11563 .set_tss_addr
= vmx_set_tss_addr
,
11564 .get_tdp_level
= get_ept_level
,
11565 .get_mt_mask
= vmx_get_mt_mask
,
11567 .get_exit_info
= vmx_get_exit_info
,
11569 .get_lpage_level
= vmx_get_lpage_level
,
11571 .cpuid_update
= vmx_cpuid_update
,
11573 .rdtscp_supported
= vmx_rdtscp_supported
,
11574 .invpcid_supported
= vmx_invpcid_supported
,
11576 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11578 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11580 .write_tsc_offset
= vmx_write_tsc_offset
,
11582 .set_tdp_cr3
= vmx_set_cr3
,
11584 .check_intercept
= vmx_check_intercept
,
11585 .handle_external_intr
= vmx_handle_external_intr
,
11586 .mpx_supported
= vmx_mpx_supported
,
11587 .xsaves_supported
= vmx_xsaves_supported
,
11589 .check_nested_events
= vmx_check_nested_events
,
11591 .sched_in
= vmx_sched_in
,
11593 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11594 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11595 .flush_log_dirty
= vmx_flush_log_dirty
,
11596 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11598 .pre_block
= vmx_pre_block
,
11599 .post_block
= vmx_post_block
,
11601 .pmu_ops
= &intel_pmu_ops
,
11603 .update_pi_irte
= vmx_update_pi_irte
,
11605 #ifdef CONFIG_X86_64
11606 .set_hv_timer
= vmx_set_hv_timer
,
11607 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11610 .setup_mce
= vmx_setup_mce
,
11613 static int __init
vmx_init(void)
11615 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11616 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11620 #ifdef CONFIG_KEXEC_CORE
11621 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11622 crash_vmclear_local_loaded_vmcss
);
11628 static void __exit
vmx_exit(void)
11630 #ifdef CONFIG_KEXEC_CORE
11631 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11638 module_init(vmx_init
)
11639 module_exit(vmx_exit
)