2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/nospec-branch.h>
54 #include <asm/microcode.h>
59 #define __ex(x) __kvm_handle_fault_on_reboot(x)
60 #define __ex_clear(x, reg) \
61 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
63 MODULE_AUTHOR("Qumranet");
64 MODULE_LICENSE("GPL");
66 static const struct x86_cpu_id vmx_cpu_id
[] = {
67 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
70 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
72 static bool __read_mostly enable_vpid
= 1;
73 module_param_named(vpid
, enable_vpid
, bool, 0444);
75 static bool __read_mostly flexpriority_enabled
= 1;
76 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
78 static bool __read_mostly enable_ept
= 1;
79 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
81 static bool __read_mostly enable_unrestricted_guest
= 1;
82 module_param_named(unrestricted_guest
,
83 enable_unrestricted_guest
, bool, S_IRUGO
);
85 static bool __read_mostly enable_ept_ad_bits
= 1;
86 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
88 static bool __read_mostly emulate_invalid_guest_state
= true;
89 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
91 static bool __read_mostly fasteoi
= 1;
92 module_param(fasteoi
, bool, S_IRUGO
);
94 static bool __read_mostly enable_apicv
= 1;
95 module_param(enable_apicv
, bool, S_IRUGO
);
97 static bool __read_mostly enable_shadow_vmcs
= 1;
98 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
100 * If nested=1, nested virtualization is supported, i.e., guests may use
101 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
102 * use VMX instructions.
104 static bool __read_mostly nested
= 0;
105 module_param(nested
, bool, S_IRUGO
);
107 static u64 __read_mostly host_xss
;
109 static bool __read_mostly enable_pml
= 1;
110 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
112 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
114 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
115 static int __read_mostly cpu_preemption_timer_multi
;
116 static bool __read_mostly enable_preemption_timer
= 1;
118 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
121 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
122 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
123 #define KVM_VM_CR0_ALWAYS_ON \
124 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
125 #define KVM_CR4_GUEST_OWNED_BITS \
126 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
127 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
129 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
130 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
132 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
134 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
137 * Hyper-V requires all of these, so mark them as supported even though
138 * they are just treated the same as all-context.
140 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
141 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
142 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
144 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
147 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
148 * ple_gap: upper bound on the amount of time between two successive
149 * executions of PAUSE in a loop. Also indicate if ple enabled.
150 * According to test, this time is usually smaller than 128 cycles.
151 * ple_window: upper bound on the amount of time a guest is allowed to execute
152 * in a PAUSE loop. Tests indicate that most spinlocks are held for
153 * less than 2^12 cycles
154 * Time is measured based on a counter that runs at the same rate as the TSC,
155 * refer SDM volume 3b section 21.6.13 & 22.1.3.
157 #define KVM_VMX_DEFAULT_PLE_GAP 128
158 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
161 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
162 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
164 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
165 module_param(ple_gap
, int, S_IRUGO
);
167 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
168 module_param(ple_window
, int, S_IRUGO
);
170 /* Default doubles per-vcpu window every exit. */
171 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
172 module_param(ple_window_grow
, int, S_IRUGO
);
174 /* Default resets per-vcpu window every exit to ple_window. */
175 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
176 module_param(ple_window_shrink
, int, S_IRUGO
);
178 /* Default is to compute the maximum so we can never overflow. */
179 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
180 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
181 module_param(ple_window_max
, int, S_IRUGO
);
183 extern const ulong vmx_return
;
185 #define NR_AUTOLOAD_MSRS 8
186 #define VMCS02_POOL_SIZE 1
195 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
196 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
197 * loaded on this CPU (so we can clear them if the CPU goes down).
201 struct vmcs
*shadow_vmcs
;
204 bool nmi_known_unmasked
;
205 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
206 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
207 struct list_head loaded_vmcss_on_cpu_link
;
210 struct shared_msr_entry
{
217 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
218 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
219 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
220 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
221 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
222 * More than one of these structures may exist, if L1 runs multiple L2 guests.
223 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
224 * underlying hardware which will be used to run L2.
225 * This structure is packed to ensure that its layout is identical across
226 * machines (necessary for live migration).
227 * If there are changes in this struct, VMCS12_REVISION must be changed.
229 typedef u64 natural_width
;
230 struct __packed vmcs12
{
231 /* According to the Intel spec, a VMCS region must start with the
232 * following two fields. Then follow implementation-specific data.
237 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
238 u32 padding
[7]; /* room for future expansion */
243 u64 vm_exit_msr_store_addr
;
244 u64 vm_exit_msr_load_addr
;
245 u64 vm_entry_msr_load_addr
;
247 u64 virtual_apic_page_addr
;
248 u64 apic_access_addr
;
249 u64 posted_intr_desc_addr
;
251 u64 eoi_exit_bitmap0
;
252 u64 eoi_exit_bitmap1
;
253 u64 eoi_exit_bitmap2
;
254 u64 eoi_exit_bitmap3
;
256 u64 guest_physical_address
;
257 u64 vmcs_link_pointer
;
259 u64 guest_ia32_debugctl
;
262 u64 guest_ia32_perf_global_ctrl
;
270 u64 host_ia32_perf_global_ctrl
;
271 u64 padding64
[8]; /* room for future expansion */
273 * To allow migration of L1 (complete with its L2 guests) between
274 * machines of different natural widths (32 or 64 bit), we cannot have
275 * unsigned long fields with no explict size. We use u64 (aliased
276 * natural_width) instead. Luckily, x86 is little-endian.
278 natural_width cr0_guest_host_mask
;
279 natural_width cr4_guest_host_mask
;
280 natural_width cr0_read_shadow
;
281 natural_width cr4_read_shadow
;
282 natural_width cr3_target_value0
;
283 natural_width cr3_target_value1
;
284 natural_width cr3_target_value2
;
285 natural_width cr3_target_value3
;
286 natural_width exit_qualification
;
287 natural_width guest_linear_address
;
288 natural_width guest_cr0
;
289 natural_width guest_cr3
;
290 natural_width guest_cr4
;
291 natural_width guest_es_base
;
292 natural_width guest_cs_base
;
293 natural_width guest_ss_base
;
294 natural_width guest_ds_base
;
295 natural_width guest_fs_base
;
296 natural_width guest_gs_base
;
297 natural_width guest_ldtr_base
;
298 natural_width guest_tr_base
;
299 natural_width guest_gdtr_base
;
300 natural_width guest_idtr_base
;
301 natural_width guest_dr7
;
302 natural_width guest_rsp
;
303 natural_width guest_rip
;
304 natural_width guest_rflags
;
305 natural_width guest_pending_dbg_exceptions
;
306 natural_width guest_sysenter_esp
;
307 natural_width guest_sysenter_eip
;
308 natural_width host_cr0
;
309 natural_width host_cr3
;
310 natural_width host_cr4
;
311 natural_width host_fs_base
;
312 natural_width host_gs_base
;
313 natural_width host_tr_base
;
314 natural_width host_gdtr_base
;
315 natural_width host_idtr_base
;
316 natural_width host_ia32_sysenter_esp
;
317 natural_width host_ia32_sysenter_eip
;
318 natural_width host_rsp
;
319 natural_width host_rip
;
320 natural_width paddingl
[8]; /* room for future expansion */
321 u32 pin_based_vm_exec_control
;
322 u32 cpu_based_vm_exec_control
;
323 u32 exception_bitmap
;
324 u32 page_fault_error_code_mask
;
325 u32 page_fault_error_code_match
;
326 u32 cr3_target_count
;
327 u32 vm_exit_controls
;
328 u32 vm_exit_msr_store_count
;
329 u32 vm_exit_msr_load_count
;
330 u32 vm_entry_controls
;
331 u32 vm_entry_msr_load_count
;
332 u32 vm_entry_intr_info_field
;
333 u32 vm_entry_exception_error_code
;
334 u32 vm_entry_instruction_len
;
336 u32 secondary_vm_exec_control
;
337 u32 vm_instruction_error
;
339 u32 vm_exit_intr_info
;
340 u32 vm_exit_intr_error_code
;
341 u32 idt_vectoring_info_field
;
342 u32 idt_vectoring_error_code
;
343 u32 vm_exit_instruction_len
;
344 u32 vmx_instruction_info
;
351 u32 guest_ldtr_limit
;
353 u32 guest_gdtr_limit
;
354 u32 guest_idtr_limit
;
355 u32 guest_es_ar_bytes
;
356 u32 guest_cs_ar_bytes
;
357 u32 guest_ss_ar_bytes
;
358 u32 guest_ds_ar_bytes
;
359 u32 guest_fs_ar_bytes
;
360 u32 guest_gs_ar_bytes
;
361 u32 guest_ldtr_ar_bytes
;
362 u32 guest_tr_ar_bytes
;
363 u32 guest_interruptibility_info
;
364 u32 guest_activity_state
;
365 u32 guest_sysenter_cs
;
366 u32 host_ia32_sysenter_cs
;
367 u32 vmx_preemption_timer_value
;
368 u32 padding32
[7]; /* room for future expansion */
369 u16 virtual_processor_id
;
371 u16 guest_es_selector
;
372 u16 guest_cs_selector
;
373 u16 guest_ss_selector
;
374 u16 guest_ds_selector
;
375 u16 guest_fs_selector
;
376 u16 guest_gs_selector
;
377 u16 guest_ldtr_selector
;
378 u16 guest_tr_selector
;
379 u16 guest_intr_status
;
381 u16 host_es_selector
;
382 u16 host_cs_selector
;
383 u16 host_ss_selector
;
384 u16 host_ds_selector
;
385 u16 host_fs_selector
;
386 u16 host_gs_selector
;
387 u16 host_tr_selector
;
391 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
392 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
393 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
395 #define VMCS12_REVISION 0x11e57ed0
398 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
399 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
400 * current implementation, 4K are reserved to avoid future complications.
402 #define VMCS12_SIZE 0x1000
404 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
406 struct list_head list
;
408 struct loaded_vmcs vmcs02
;
412 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
413 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
416 /* Has the level1 guest done vmxon? */
421 /* The guest-physical address of the current VMCS L1 keeps for L2 */
424 * Cache of the guest's VMCS, existing outside of guest memory.
425 * Loaded from guest memory during VMPTRLD. Flushed to guest
426 * memory during VMCLEAR and VMPTRLD.
428 struct vmcs12
*cached_vmcs12
;
430 * Indicates if the shadow vmcs must be updated with the
431 * data hold by vmcs12
433 bool sync_shadow_vmcs
;
435 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
436 struct list_head vmcs02_pool
;
438 bool change_vmcs01_virtual_x2apic_mode
;
439 /* L2 must run next, and mustn't decide to exit to L1. */
440 bool nested_run_pending
;
442 * Guest pages referred to in vmcs02 with host-physical pointers, so
443 * we must keep them pinned while L2 runs.
445 struct page
*apic_access_page
;
446 struct page
*virtual_apic_page
;
447 struct page
*pi_desc_page
;
448 struct pi_desc
*pi_desc
;
452 unsigned long *msr_bitmap
;
454 struct hrtimer preemption_timer
;
455 bool preemption_timer_expired
;
457 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
464 * We only store the "true" versions of the VMX capability MSRs. We
465 * generate the "non-true" versions by setting the must-be-1 bits
466 * according to the SDM.
468 u32 nested_vmx_procbased_ctls_low
;
469 u32 nested_vmx_procbased_ctls_high
;
470 u32 nested_vmx_secondary_ctls_low
;
471 u32 nested_vmx_secondary_ctls_high
;
472 u32 nested_vmx_pinbased_ctls_low
;
473 u32 nested_vmx_pinbased_ctls_high
;
474 u32 nested_vmx_exit_ctls_low
;
475 u32 nested_vmx_exit_ctls_high
;
476 u32 nested_vmx_entry_ctls_low
;
477 u32 nested_vmx_entry_ctls_high
;
478 u32 nested_vmx_misc_low
;
479 u32 nested_vmx_misc_high
;
480 u32 nested_vmx_ept_caps
;
481 u32 nested_vmx_vpid_caps
;
482 u64 nested_vmx_basic
;
483 u64 nested_vmx_cr0_fixed0
;
484 u64 nested_vmx_cr0_fixed1
;
485 u64 nested_vmx_cr4_fixed0
;
486 u64 nested_vmx_cr4_fixed1
;
487 u64 nested_vmx_vmcs_enum
;
490 #define POSTED_INTR_ON 0
491 #define POSTED_INTR_SN 1
493 /* Posted-Interrupt Descriptor */
495 u32 pir
[8]; /* Posted interrupt requested */
498 /* bit 256 - Outstanding Notification */
500 /* bit 257 - Suppress Notification */
502 /* bit 271:258 - Reserved */
504 /* bit 279:272 - Notification Vector */
506 /* bit 287:280 - Reserved */
508 /* bit 319:288 - Notification Destination */
516 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
518 return test_and_set_bit(POSTED_INTR_ON
,
519 (unsigned long *)&pi_desc
->control
);
522 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
524 return test_and_clear_bit(POSTED_INTR_ON
,
525 (unsigned long *)&pi_desc
->control
);
528 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
530 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
533 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
535 return clear_bit(POSTED_INTR_SN
,
536 (unsigned long *)&pi_desc
->control
);
539 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
541 return set_bit(POSTED_INTR_SN
,
542 (unsigned long *)&pi_desc
->control
);
545 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
547 clear_bit(POSTED_INTR_ON
,
548 (unsigned long *)&pi_desc
->control
);
551 static inline int pi_test_on(struct pi_desc
*pi_desc
)
553 return test_bit(POSTED_INTR_ON
,
554 (unsigned long *)&pi_desc
->control
);
557 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
559 return test_bit(POSTED_INTR_SN
,
560 (unsigned long *)&pi_desc
->control
);
564 struct kvm_vcpu vcpu
;
565 unsigned long host_rsp
;
568 u32 idt_vectoring_info
;
570 struct shared_msr_entry
*guest_msrs
;
573 unsigned long host_idt_base
;
575 u64 msr_host_kernel_gs_base
;
576 u64 msr_guest_kernel_gs_base
;
578 u32 vm_entry_controls_shadow
;
579 u32 vm_exit_controls_shadow
;
581 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
582 * non-nested (L1) guest, it always points to vmcs01. For a nested
583 * guest (L2), it points to a different VMCS.
585 struct loaded_vmcs vmcs01
;
586 struct loaded_vmcs
*loaded_vmcs
;
587 bool __launched
; /* temporary, used in vmx_vcpu_run */
588 struct msr_autoload
{
590 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
591 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
595 u16 fs_sel
, gs_sel
, ldt_sel
;
599 int gs_ldt_reload_needed
;
600 int fs_reload_needed
;
601 u64 msr_host_bndcfgs
;
606 struct kvm_segment segs
[8];
609 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
610 struct kvm_save_segment
{
618 bool emulation_required
;
622 /* Posted interrupt descriptor */
623 struct pi_desc pi_desc
;
625 /* Support for a guest hypervisor (nested VMX) */
626 struct nested_vmx nested
;
628 /* Dynamic PLE window. */
630 bool ple_window_dirty
;
632 /* Support for PML */
633 #define PML_ENTITY_NUM 512
636 /* apic deadline value in host tsc */
639 u64 current_tsc_ratio
;
644 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
645 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
646 * in msr_ia32_feature_control_valid_bits.
648 u64 msr_ia32_feature_control
;
649 u64 msr_ia32_feature_control_valid_bits
;
652 enum segment_cache_field
{
661 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
663 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
666 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
668 return &(to_vmx(vcpu
)->pi_desc
);
671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
672 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
673 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
674 [number##_HIGH] = VMCS12_OFFSET(name)+4
677 static unsigned long shadow_read_only_fields
[] = {
679 * We do NOT shadow fields that are modified when L0
680 * traps and emulates any vmx instruction (e.g. VMPTRLD,
681 * VMXON...) executed by L1.
682 * For example, VM_INSTRUCTION_ERROR is read
683 * by L1 if a vmx instruction fails (part of the error path).
684 * Note the code assumes this logic. If for some reason
685 * we start shadowing these fields then we need to
686 * force a shadow sync when L0 emulates vmx instructions
687 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
688 * by nested_vmx_failValid)
692 VM_EXIT_INSTRUCTION_LEN
,
693 IDT_VECTORING_INFO_FIELD
,
694 IDT_VECTORING_ERROR_CODE
,
695 VM_EXIT_INTR_ERROR_CODE
,
697 GUEST_LINEAR_ADDRESS
,
698 GUEST_PHYSICAL_ADDRESS
700 static int max_shadow_read_only_fields
=
701 ARRAY_SIZE(shadow_read_only_fields
);
703 static unsigned long shadow_read_write_fields
[] = {
710 GUEST_INTERRUPTIBILITY_INFO
,
723 CPU_BASED_VM_EXEC_CONTROL
,
724 VM_ENTRY_EXCEPTION_ERROR_CODE
,
725 VM_ENTRY_INTR_INFO_FIELD
,
726 VM_ENTRY_INSTRUCTION_LEN
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
733 static int max_shadow_read_write_fields
=
734 ARRAY_SIZE(shadow_read_write_fields
);
736 static const unsigned short vmcs_field_to_offset_table
[] = {
737 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
738 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
739 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
740 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
741 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
742 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
743 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
744 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
745 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
746 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
747 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
748 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
749 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
750 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
751 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
752 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
753 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
754 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
755 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
756 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
757 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
758 FIELD64(MSR_BITMAP
, msr_bitmap
),
759 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
760 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
761 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
762 FIELD64(TSC_OFFSET
, tsc_offset
),
763 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
764 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
765 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
766 FIELD64(EPT_POINTER
, ept_pointer
),
767 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
768 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
769 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
770 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
771 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
772 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
773 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
774 FIELD64(PML_ADDRESS
, pml_address
),
775 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
776 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
777 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
778 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
779 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
780 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
781 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
782 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
783 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
784 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
785 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
786 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
787 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
788 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
789 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
790 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
791 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
792 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
793 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
794 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
795 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
796 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
797 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
798 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
799 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
800 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
801 FIELD(TPR_THRESHOLD
, tpr_threshold
),
802 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
803 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
804 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
805 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
806 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
807 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
808 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
809 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
810 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
811 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
812 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
813 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
814 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
815 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
816 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
817 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
818 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
819 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
820 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
821 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
822 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
823 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
824 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
825 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
826 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
827 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
828 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
829 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
830 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
831 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
832 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
833 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
834 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
835 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
836 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
837 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
838 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
839 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
840 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
841 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
842 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
843 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
844 FIELD(GUEST_CR0
, guest_cr0
),
845 FIELD(GUEST_CR3
, guest_cr3
),
846 FIELD(GUEST_CR4
, guest_cr4
),
847 FIELD(GUEST_ES_BASE
, guest_es_base
),
848 FIELD(GUEST_CS_BASE
, guest_cs_base
),
849 FIELD(GUEST_SS_BASE
, guest_ss_base
),
850 FIELD(GUEST_DS_BASE
, guest_ds_base
),
851 FIELD(GUEST_FS_BASE
, guest_fs_base
),
852 FIELD(GUEST_GS_BASE
, guest_gs_base
),
853 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
854 FIELD(GUEST_TR_BASE
, guest_tr_base
),
855 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
856 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
857 FIELD(GUEST_DR7
, guest_dr7
),
858 FIELD(GUEST_RSP
, guest_rsp
),
859 FIELD(GUEST_RIP
, guest_rip
),
860 FIELD(GUEST_RFLAGS
, guest_rflags
),
861 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
862 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
863 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
864 FIELD(HOST_CR0
, host_cr0
),
865 FIELD(HOST_CR3
, host_cr3
),
866 FIELD(HOST_CR4
, host_cr4
),
867 FIELD(HOST_FS_BASE
, host_fs_base
),
868 FIELD(HOST_GS_BASE
, host_gs_base
),
869 FIELD(HOST_TR_BASE
, host_tr_base
),
870 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
871 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
872 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
873 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
874 FIELD(HOST_RSP
, host_rsp
),
875 FIELD(HOST_RIP
, host_rip
),
878 static inline short vmcs_field_to_offset(unsigned long field
)
880 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
882 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
883 vmcs_field_to_offset_table
[field
] == 0)
886 return vmcs_field_to_offset_table
[field
];
889 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
891 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
894 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
896 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
897 if (is_error_page(page
))
903 static void nested_release_page(struct page
*page
)
905 kvm_release_page_dirty(page
);
908 static void nested_release_page_clean(struct page
*page
)
910 kvm_release_page_clean(page
);
913 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
914 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
915 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
916 static bool vmx_xsaves_supported(void);
917 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
918 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
919 struct kvm_segment
*var
, int seg
);
920 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
921 struct kvm_segment
*var
, int seg
);
922 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
923 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
924 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
925 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
926 static int alloc_identity_pagetable(struct kvm
*kvm
);
927 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
928 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
929 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
932 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
933 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
935 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
936 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
938 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
944 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
945 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
950 VMX_MSR_BITMAP_LEGACY
,
951 VMX_MSR_BITMAP_LONGMODE
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
954 VMX_MSR_BITMAP_LEGACY_X2APIC
,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
961 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
963 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
974 static bool cpu_has_load_ia32_efer
;
975 static bool cpu_has_load_perf_global_ctrl
;
977 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
978 static DEFINE_SPINLOCK(vmx_vpid_lock
);
980 static struct vmcs_config
{
985 u32 pin_based_exec_ctrl
;
986 u32 cpu_based_exec_ctrl
;
987 u32 cpu_based_2nd_exec_ctrl
;
992 static struct vmx_capability
{
997 #define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1005 static const struct kvm_vmx_segment_field
{
1010 } kvm_vmx_segment_fields
[] = {
1011 VMX_SEGMENT_FIELD(CS
),
1012 VMX_SEGMENT_FIELD(DS
),
1013 VMX_SEGMENT_FIELD(ES
),
1014 VMX_SEGMENT_FIELD(FS
),
1015 VMX_SEGMENT_FIELD(GS
),
1016 VMX_SEGMENT_FIELD(SS
),
1017 VMX_SEGMENT_FIELD(TR
),
1018 VMX_SEGMENT_FIELD(LDTR
),
1021 static u64 host_efer
;
1023 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027 * away by decrementing the array size.
1029 static const u32 vmx_msr_index
[] = {
1030 #ifdef CONFIG_X86_64
1031 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1033 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1036 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1038 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1039 INTR_INFO_VALID_MASK
)) ==
1040 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1043 static inline bool is_debug(u32 intr_info
)
1045 return is_exception_n(intr_info
, DB_VECTOR
);
1048 static inline bool is_breakpoint(u32 intr_info
)
1050 return is_exception_n(intr_info
, BP_VECTOR
);
1053 static inline bool is_page_fault(u32 intr_info
)
1055 return is_exception_n(intr_info
, PF_VECTOR
);
1058 static inline bool is_no_device(u32 intr_info
)
1060 return is_exception_n(intr_info
, NM_VECTOR
);
1063 static inline bool is_invalid_opcode(u32 intr_info
)
1065 return is_exception_n(intr_info
, UD_VECTOR
);
1068 static inline bool is_external_interrupt(u32 intr_info
)
1070 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1071 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1074 static inline bool is_machine_check(u32 intr_info
)
1076 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1077 INTR_INFO_VALID_MASK
)) ==
1078 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config
.cpu_based_exec_ctrl
&
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms
[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax
= cpuid_eax(0x00000001), i
;
1163 /* Clear the reserved bits */
1164 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1165 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1166 if (eax
== vmx_preemption_cpu_tfms
[i
])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config
.pin_based_exec_ctrl
&
1175 PIN_BASED_VMX_PREEMPTION_TIMER
;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1181 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1219 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1222 static inline bool cpu_has_vmx_invept_context(void)
1224 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1227 static inline bool cpu_has_vmx_invept_global(void)
1229 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1234 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1239 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1242 static inline bool cpu_has_vmx_invvpid(void)
1244 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1247 static inline bool cpu_has_vmx_ept(void)
1249 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1250 SECONDARY_EXEC_ENABLE_EPT
;
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1255 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1256 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1259 static inline bool cpu_has_vmx_ple(void)
1261 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1262 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1265 static inline bool cpu_has_vmx_basic_inout(void)
1267 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1272 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1275 static inline bool cpu_has_vmx_vpid(void)
1277 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1278 SECONDARY_EXEC_ENABLE_VPID
;
1281 static inline bool cpu_has_vmx_rdtscp(void)
1283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1284 SECONDARY_EXEC_RDTSCP
;
1287 static inline bool cpu_has_vmx_invpcid(void)
1289 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1290 SECONDARY_EXEC_ENABLE_INVPCID
;
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_WBINVD_EXITING
;
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1302 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1303 /* check if the cpu supports writing r/o exit information fields */
1304 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1307 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1308 SECONDARY_EXEC_SHADOW_VMCS
;
1311 static inline bool cpu_has_vmx_pml(void)
1313 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1318 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1319 SECONDARY_EXEC_TSC_SCALING
;
1322 static inline bool report_flexpriority(void)
1324 return flexpriority_enabled
;
1327 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1329 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1332 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1334 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1337 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1339 return (vmcs12
->cpu_based_vm_exec_control
&
1340 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1341 (vmcs12
->secondary_vm_exec_control
& bit
);
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1346 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1351 return vmcs12
->pin_based_vm_exec_control
&
1352 PIN_BASED_VMX_PREEMPTION_TIMER
;
1355 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1357 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1362 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1363 vmx_xsaves_supported();
1366 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1371 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1376 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1378 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1381 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1383 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1386 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1388 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1391 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1393 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1396 static inline bool is_nmi(u32 intr_info
)
1398 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1399 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1402 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1404 unsigned long exit_qualification
);
1405 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1406 struct vmcs12
*vmcs12
,
1407 u32 reason
, unsigned long qualification
);
1409 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1413 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1414 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1419 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1425 } operand
= { vpid
, 0, gva
};
1427 asm volatile (__ex(ASM_VMX_INVVPID
)
1428 /* CF==1 or ZF==1 --> rc = -1 */
1429 "; ja 1f ; ud2 ; 1:"
1430 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1433 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1437 } operand
= {eptp
, gpa
};
1439 asm volatile (__ex(ASM_VMX_INVEPT
)
1440 /* CF==1 or ZF==1 --> rc = -1 */
1441 "; ja 1f ; ud2 ; 1:\n"
1442 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1445 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1449 i
= __find_msr_index(vmx
, msr
);
1451 return &vmx
->guest_msrs
[i
];
1455 static void vmcs_clear(struct vmcs
*vmcs
)
1457 u64 phys_addr
= __pa(vmcs
);
1460 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1461 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1464 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1468 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1470 vmcs_clear(loaded_vmcs
->vmcs
);
1471 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1472 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1473 loaded_vmcs
->cpu
= -1;
1474 loaded_vmcs
->launched
= 0;
1477 static void vmcs_load(struct vmcs
*vmcs
)
1479 u64 phys_addr
= __pa(vmcs
);
1482 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1483 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1486 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1491 #ifdef CONFIG_KEXEC_CORE
1493 * This bitmap is used to indicate whether the vmclear
1494 * operation is enabled on all cpus. All disabled by
1497 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1499 static inline void crash_enable_local_vmclear(int cpu
)
1501 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1504 static inline void crash_disable_local_vmclear(int cpu
)
1506 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1509 static inline int crash_local_vmclear_enabled(int cpu
)
1511 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1514 static void crash_vmclear_local_loaded_vmcss(void)
1516 int cpu
= raw_smp_processor_id();
1517 struct loaded_vmcs
*v
;
1519 if (!crash_local_vmclear_enabled(cpu
))
1522 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1523 loaded_vmcss_on_cpu_link
)
1524 vmcs_clear(v
->vmcs
);
1527 static inline void crash_enable_local_vmclear(int cpu
) { }
1528 static inline void crash_disable_local_vmclear(int cpu
) { }
1529 #endif /* CONFIG_KEXEC_CORE */
1531 static void __loaded_vmcs_clear(void *arg
)
1533 struct loaded_vmcs
*loaded_vmcs
= arg
;
1534 int cpu
= raw_smp_processor_id();
1536 if (loaded_vmcs
->cpu
!= cpu
)
1537 return; /* vcpu migration can race with cpu offline */
1538 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1539 per_cpu(current_vmcs
, cpu
) = NULL
;
1540 crash_disable_local_vmclear(cpu
);
1541 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1544 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1545 * is before setting loaded_vmcs->vcpu to -1 which is done in
1546 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1547 * then adds the vmcs into percpu list before it is deleted.
1551 loaded_vmcs_init(loaded_vmcs
);
1552 crash_enable_local_vmclear(cpu
);
1555 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1557 int cpu
= loaded_vmcs
->cpu
;
1560 smp_call_function_single(cpu
,
1561 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1564 static inline void vpid_sync_vcpu_single(int vpid
)
1569 if (cpu_has_vmx_invvpid_single())
1570 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1573 static inline void vpid_sync_vcpu_global(void)
1575 if (cpu_has_vmx_invvpid_global())
1576 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1579 static inline void vpid_sync_context(int vpid
)
1581 if (cpu_has_vmx_invvpid_single())
1582 vpid_sync_vcpu_single(vpid
);
1584 vpid_sync_vcpu_global();
1587 static inline void ept_sync_global(void)
1589 if (cpu_has_vmx_invept_global())
1590 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1593 static inline void ept_sync_context(u64 eptp
)
1596 if (cpu_has_vmx_invept_context())
1597 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1603 static __always_inline
void vmcs_check16(unsigned long field
)
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1606 "16-bit accessor invalid for 64-bit field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1608 "16-bit accessor invalid for 64-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1610 "16-bit accessor invalid for 32-bit high field");
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1612 "16-bit accessor invalid for natural width field");
1615 static __always_inline
void vmcs_check32(unsigned long field
)
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1618 "32-bit accessor invalid for 16-bit field");
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1620 "32-bit accessor invalid for natural width field");
1623 static __always_inline
void vmcs_check64(unsigned long field
)
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1626 "64-bit accessor invalid for 16-bit field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1628 "64-bit accessor invalid for 64-bit high field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1630 "64-bit accessor invalid for 32-bit field");
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1632 "64-bit accessor invalid for natural width field");
1635 static __always_inline
void vmcs_checkl(unsigned long field
)
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1638 "Natural width accessor invalid for 16-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1640 "Natural width accessor invalid for 64-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1642 "Natural width accessor invalid for 64-bit high field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1644 "Natural width accessor invalid for 32-bit field");
1647 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1649 unsigned long value
;
1651 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1652 : "=a"(value
) : "d"(field
) : "cc");
1656 static __always_inline u16
vmcs_read16(unsigned long field
)
1658 vmcs_check16(field
);
1659 return __vmcs_readl(field
);
1662 static __always_inline u32
vmcs_read32(unsigned long field
)
1664 vmcs_check32(field
);
1665 return __vmcs_readl(field
);
1668 static __always_inline u64
vmcs_read64(unsigned long field
)
1670 vmcs_check64(field
);
1671 #ifdef CONFIG_X86_64
1672 return __vmcs_readl(field
);
1674 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1678 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1681 return __vmcs_readl(field
);
1684 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1686 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1687 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1691 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1695 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1696 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1697 if (unlikely(error
))
1698 vmwrite_error(field
, value
);
1701 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1703 vmcs_check16(field
);
1704 __vmcs_writel(field
, value
);
1707 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1709 vmcs_check32(field
);
1710 __vmcs_writel(field
, value
);
1713 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1715 vmcs_check64(field
);
1716 __vmcs_writel(field
, value
);
1717 #ifndef CONFIG_X86_64
1719 __vmcs_writel(field
+1, value
>> 32);
1723 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1726 __vmcs_writel(field
, value
);
1729 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1731 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1732 "vmcs_clear_bits does not support 64-bit fields");
1733 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1736 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1738 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1739 "vmcs_set_bits does not support 64-bit fields");
1740 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1743 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1745 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1748 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1750 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1751 vmx
->vm_entry_controls_shadow
= val
;
1754 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1756 if (vmx
->vm_entry_controls_shadow
!= val
)
1757 vm_entry_controls_init(vmx
, val
);
1760 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1762 return vmx
->vm_entry_controls_shadow
;
1766 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1768 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1771 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1773 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1776 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1778 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1781 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1783 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1784 vmx
->vm_exit_controls_shadow
= val
;
1787 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1789 if (vmx
->vm_exit_controls_shadow
!= val
)
1790 vm_exit_controls_init(vmx
, val
);
1793 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1795 return vmx
->vm_exit_controls_shadow
;
1799 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1801 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1804 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1806 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1809 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1811 vmx
->segment_cache
.bitmask
= 0;
1814 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1818 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1820 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1821 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1822 vmx
->segment_cache
.bitmask
= 0;
1824 ret
= vmx
->segment_cache
.bitmask
& mask
;
1825 vmx
->segment_cache
.bitmask
|= mask
;
1829 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1831 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1833 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1834 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1838 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1840 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1842 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1843 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1847 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1849 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1851 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1852 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1856 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1858 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1860 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1861 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1865 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1869 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1870 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1871 if ((vcpu
->guest_debug
&
1872 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1873 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1874 eb
|= 1u << BP_VECTOR
;
1875 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1878 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1880 /* When we are running a nested L2 guest and L1 specified for it a
1881 * certain exception bitmap, we must trap the same exceptions and pass
1882 * them to L1. When running L2, we will only handle the exceptions
1883 * specified above if L1 did not want them.
1885 if (is_guest_mode(vcpu
))
1886 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1888 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1891 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1892 unsigned long entry
, unsigned long exit
)
1894 vm_entry_controls_clearbit(vmx
, entry
);
1895 vm_exit_controls_clearbit(vmx
, exit
);
1898 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1901 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1905 if (cpu_has_load_ia32_efer
) {
1906 clear_atomic_switch_msr_special(vmx
,
1907 VM_ENTRY_LOAD_IA32_EFER
,
1908 VM_EXIT_LOAD_IA32_EFER
);
1912 case MSR_CORE_PERF_GLOBAL_CTRL
:
1913 if (cpu_has_load_perf_global_ctrl
) {
1914 clear_atomic_switch_msr_special(vmx
,
1915 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1916 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1922 for (i
= 0; i
< m
->nr
; ++i
)
1923 if (m
->guest
[i
].index
== msr
)
1929 m
->guest
[i
] = m
->guest
[m
->nr
];
1930 m
->host
[i
] = m
->host
[m
->nr
];
1931 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1932 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1935 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1936 unsigned long entry
, unsigned long exit
,
1937 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1938 u64 guest_val
, u64 host_val
)
1940 vmcs_write64(guest_val_vmcs
, guest_val
);
1941 vmcs_write64(host_val_vmcs
, host_val
);
1942 vm_entry_controls_setbit(vmx
, entry
);
1943 vm_exit_controls_setbit(vmx
, exit
);
1946 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1947 u64 guest_val
, u64 host_val
)
1950 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1954 if (cpu_has_load_ia32_efer
) {
1955 add_atomic_switch_msr_special(vmx
,
1956 VM_ENTRY_LOAD_IA32_EFER
,
1957 VM_EXIT_LOAD_IA32_EFER
,
1960 guest_val
, host_val
);
1964 case MSR_CORE_PERF_GLOBAL_CTRL
:
1965 if (cpu_has_load_perf_global_ctrl
) {
1966 add_atomic_switch_msr_special(vmx
,
1967 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1968 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1969 GUEST_IA32_PERF_GLOBAL_CTRL
,
1970 HOST_IA32_PERF_GLOBAL_CTRL
,
1971 guest_val
, host_val
);
1975 case MSR_IA32_PEBS_ENABLE
:
1976 /* PEBS needs a quiescent period after being disabled (to write
1977 * a record). Disabling PEBS through VMX MSR swapping doesn't
1978 * provide that period, so a CPU could write host's record into
1981 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1984 for (i
= 0; i
< m
->nr
; ++i
)
1985 if (m
->guest
[i
].index
== msr
)
1988 if (i
== NR_AUTOLOAD_MSRS
) {
1989 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1990 "Can't add msr %x\n", msr
);
1992 } else if (i
== m
->nr
) {
1994 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1995 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1998 m
->guest
[i
].index
= msr
;
1999 m
->guest
[i
].value
= guest_val
;
2000 m
->host
[i
].index
= msr
;
2001 m
->host
[i
].value
= host_val
;
2004 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2006 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2007 u64 ignore_bits
= 0;
2011 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2012 * host CPUID is more efficient than testing guest CPUID
2013 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2015 if (boot_cpu_has(X86_FEATURE_SMEP
))
2016 guest_efer
|= EFER_NX
;
2017 else if (!(guest_efer
& EFER_NX
))
2018 ignore_bits
|= EFER_NX
;
2022 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2024 ignore_bits
|= EFER_SCE
;
2025 #ifdef CONFIG_X86_64
2026 ignore_bits
|= EFER_LMA
| EFER_LME
;
2027 /* SCE is meaningful only in long mode on Intel */
2028 if (guest_efer
& EFER_LMA
)
2029 ignore_bits
&= ~(u64
)EFER_SCE
;
2032 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2035 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2036 * On CPUs that support "load IA32_EFER", always switch EFER
2037 * atomically, since it's faster than switching it manually.
2039 if (cpu_has_load_ia32_efer
||
2040 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2041 if (!(guest_efer
& EFER_LMA
))
2042 guest_efer
&= ~EFER_LME
;
2043 if (guest_efer
!= host_efer
)
2044 add_atomic_switch_msr(vmx
, MSR_EFER
,
2045 guest_efer
, host_efer
);
2048 guest_efer
&= ~ignore_bits
;
2049 guest_efer
|= host_efer
& ignore_bits
;
2051 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2052 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2058 #ifdef CONFIG_X86_32
2060 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2061 * VMCS rather than the segment table. KVM uses this helper to figure
2062 * out the current bases to poke them into the VMCS before entry.
2064 static unsigned long segment_base(u16 selector
)
2066 struct desc_struct
*table
;
2069 if (!(selector
& ~SEGMENT_RPL_MASK
))
2072 table
= get_current_gdt_ro();
2074 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2075 u16 ldt_selector
= kvm_read_ldt();
2077 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2080 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2082 v
= get_desc_base(&table
[selector
>> 3]);
2087 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2089 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2092 if (vmx
->host_state
.loaded
)
2095 vmx
->host_state
.loaded
= 1;
2097 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2098 * allow segment selectors with cpl > 0 or ti == 1.
2100 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2101 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2102 savesegment(fs
, vmx
->host_state
.fs_sel
);
2103 if (!(vmx
->host_state
.fs_sel
& 7)) {
2104 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2105 vmx
->host_state
.fs_reload_needed
= 0;
2107 vmcs_write16(HOST_FS_SELECTOR
, 0);
2108 vmx
->host_state
.fs_reload_needed
= 1;
2110 savesegment(gs
, vmx
->host_state
.gs_sel
);
2111 if (!(vmx
->host_state
.gs_sel
& 7))
2112 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2114 vmcs_write16(HOST_GS_SELECTOR
, 0);
2115 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2118 #ifdef CONFIG_X86_64
2119 savesegment(ds
, vmx
->host_state
.ds_sel
);
2120 savesegment(es
, vmx
->host_state
.es_sel
);
2123 #ifdef CONFIG_X86_64
2124 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2125 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2127 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2128 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2131 #ifdef CONFIG_X86_64
2132 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2133 if (is_long_mode(&vmx
->vcpu
))
2134 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2136 if (boot_cpu_has(X86_FEATURE_MPX
))
2137 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2138 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2139 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2140 vmx
->guest_msrs
[i
].data
,
2141 vmx
->guest_msrs
[i
].mask
);
2144 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2146 if (!vmx
->host_state
.loaded
)
2149 ++vmx
->vcpu
.stat
.host_state_reload
;
2150 vmx
->host_state
.loaded
= 0;
2151 #ifdef CONFIG_X86_64
2152 if (is_long_mode(&vmx
->vcpu
))
2153 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2155 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2156 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2157 #ifdef CONFIG_X86_64
2158 load_gs_index(vmx
->host_state
.gs_sel
);
2160 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2163 if (vmx
->host_state
.fs_reload_needed
)
2164 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2165 #ifdef CONFIG_X86_64
2166 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2167 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2168 loadsegment(es
, vmx
->host_state
.es_sel
);
2171 invalidate_tss_limit();
2172 #ifdef CONFIG_X86_64
2173 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2175 if (vmx
->host_state
.msr_host_bndcfgs
)
2176 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2177 load_fixmap_gdt(raw_smp_processor_id());
2180 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2183 __vmx_load_host_state(vmx
);
2187 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2189 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2190 struct pi_desc old
, new;
2194 * In case of hot-plug or hot-unplug, we may have to undo
2195 * vmx_vcpu_pi_put even if there is no assigned device. And we
2196 * always keep PI.NDST up to date for simplicity: it makes the
2197 * code easier, and CPU migration is not a fast path.
2199 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2203 * First handle the simple case where no cmpxchg is necessary; just
2204 * allow posting non-urgent interrupts.
2206 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2207 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2208 * expects the VCPU to be on the blocked_vcpu_list that matches
2211 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2213 pi_clear_sn(pi_desc
);
2217 /* The full case. */
2219 old
.control
= new.control
= pi_desc
->control
;
2221 dest
= cpu_physical_id(cpu
);
2223 if (x2apic_enabled())
2226 new.ndst
= (dest
<< 8) & 0xFF00;
2229 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2230 new.control
) != old
.control
);
2233 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2235 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2236 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2240 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241 * vcpu mutex is already taken.
2243 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2245 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2246 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2248 if (!already_loaded
) {
2249 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2250 local_irq_disable();
2251 crash_disable_local_vmclear(cpu
);
2254 * Read loaded_vmcs->cpu should be before fetching
2255 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256 * See the comments in __loaded_vmcs_clear().
2260 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2261 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2262 crash_enable_local_vmclear(cpu
);
2266 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2267 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2268 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2269 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
2270 native_wrmsrl(MSR_IA32_PRED_CMD
, FEATURE_SET_IBPB
);
2273 if (!already_loaded
) {
2274 void *gdt
= get_current_gdt_ro();
2275 unsigned long sysenter_esp
;
2277 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2280 * Linux uses per-cpu TSS and GDT, so set these when switching
2281 * processors. See 22.2.4.
2283 vmcs_writel(HOST_TR_BASE
,
2284 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2285 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2288 * VM exits change the host TR limit to 0x67 after a VM
2289 * exit. This is okay, since 0x67 covers everything except
2290 * the IO bitmap and have have code to handle the IO bitmap
2291 * being lost after a VM exit.
2293 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2295 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2296 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2298 vmx
->loaded_vmcs
->cpu
= cpu
;
2301 /* Setup TSC multiplier */
2302 if (kvm_has_tsc_control
&&
2303 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2304 decache_tsc_multiplier(vmx
);
2306 vmx_vcpu_pi_load(vcpu
, cpu
);
2307 vmx
->host_pkru
= read_pkru();
2310 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2312 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2314 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2315 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2316 !kvm_vcpu_apicv_active(vcpu
))
2319 /* Set SN when the vCPU is preempted */
2320 if (vcpu
->preempted
)
2324 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2326 vmx_vcpu_pi_put(vcpu
);
2328 __vmx_load_host_state(to_vmx(vcpu
));
2331 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2333 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2336 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2339 * Return the cr0 value that a nested guest would read. This is a combination
2340 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2341 * its hypervisor (cr0_read_shadow).
2343 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2345 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2346 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2348 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2350 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2351 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2354 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2356 unsigned long rflags
, save_rflags
;
2358 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2359 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2360 rflags
= vmcs_readl(GUEST_RFLAGS
);
2361 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2362 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2363 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2364 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2366 to_vmx(vcpu
)->rflags
= rflags
;
2368 return to_vmx(vcpu
)->rflags
;
2371 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2373 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2375 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2376 to_vmx(vcpu
)->rflags
= rflags
;
2377 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2378 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2379 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2381 vmcs_writel(GUEST_RFLAGS
, rflags
);
2383 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2384 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2387 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2389 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2392 if (interruptibility
& GUEST_INTR_STATE_STI
)
2393 ret
|= KVM_X86_SHADOW_INT_STI
;
2394 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2395 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2400 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2402 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2403 u32 interruptibility
= interruptibility_old
;
2405 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2407 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2408 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2409 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2410 interruptibility
|= GUEST_INTR_STATE_STI
;
2412 if ((interruptibility
!= interruptibility_old
))
2413 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2416 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2420 rip
= kvm_rip_read(vcpu
);
2421 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2422 kvm_rip_write(vcpu
, rip
);
2424 /* skipping an emulated instruction also counts */
2425 vmx_set_interrupt_shadow(vcpu
, 0);
2428 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2429 unsigned long exit_qual
)
2431 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2432 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2433 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2435 if (vcpu
->arch
.exception
.has_error_code
) {
2436 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2437 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2440 if (kvm_exception_is_soft(nr
))
2441 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2443 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2445 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2446 vmx_get_nmi_mask(vcpu
))
2447 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2449 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2453 * KVM wants to inject page-faults which it got to the guest. This function
2454 * checks whether in a nested guest, we need to inject them to L1 or L2.
2456 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2458 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2459 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2461 if (nr
== PF_VECTOR
) {
2462 if (vcpu
->arch
.exception
.nested_apf
) {
2463 nested_vmx_inject_exception_vmexit(vcpu
,
2464 vcpu
->arch
.apf
.nested_apf_token
);
2468 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2469 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2470 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2471 * can be written only when inject_pending_event runs. This should be
2472 * conditional on a new capability---if the capability is disabled,
2473 * kvm_multiple_exception would write the ancillary information to
2474 * CR2 or DR6, for backwards ABI-compatibility.
2476 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2477 vcpu
->arch
.exception
.error_code
)) {
2478 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2482 unsigned long exit_qual
= 0;
2483 if (nr
== DB_VECTOR
)
2484 exit_qual
= vcpu
->arch
.dr6
;
2486 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2487 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2495 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2497 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2498 unsigned nr
= vcpu
->arch
.exception
.nr
;
2499 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2500 bool reinject
= vcpu
->arch
.exception
.reinject
;
2501 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2502 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2504 if (!reinject
&& is_guest_mode(vcpu
) &&
2505 nested_vmx_check_exception(vcpu
))
2508 if (has_error_code
) {
2509 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2510 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2513 if (vmx
->rmode
.vm86_active
) {
2515 if (kvm_exception_is_soft(nr
))
2516 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2517 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2518 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2522 if (kvm_exception_is_soft(nr
)) {
2523 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2524 vmx
->vcpu
.arch
.event_exit_inst_len
);
2525 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2527 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2529 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2532 static bool vmx_rdtscp_supported(void)
2534 return cpu_has_vmx_rdtscp();
2537 static bool vmx_invpcid_supported(void)
2539 return cpu_has_vmx_invpcid() && enable_ept
;
2543 * Swap MSR entry in host/guest MSR entry array.
2545 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2547 struct shared_msr_entry tmp
;
2549 tmp
= vmx
->guest_msrs
[to
];
2550 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2551 vmx
->guest_msrs
[from
] = tmp
;
2554 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2556 unsigned long *msr_bitmap
;
2558 if (is_guest_mode(vcpu
))
2559 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2560 else if (cpu_has_secondary_exec_ctrls() &&
2561 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2562 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2563 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2564 if (is_long_mode(vcpu
))
2565 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2567 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2569 if (is_long_mode(vcpu
))
2570 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2572 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2575 if (is_long_mode(vcpu
))
2576 msr_bitmap
= vmx_msr_bitmap_longmode
;
2578 msr_bitmap
= vmx_msr_bitmap_legacy
;
2581 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2585 * Set up the vmcs to automatically save and restore system
2586 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2587 * mode, as fiddling with msrs is very expensive.
2589 static void setup_msrs(struct vcpu_vmx
*vmx
)
2591 int save_nmsrs
, index
;
2594 #ifdef CONFIG_X86_64
2595 if (is_long_mode(&vmx
->vcpu
)) {
2596 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2598 move_msr_up(vmx
, index
, save_nmsrs
++);
2599 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2601 move_msr_up(vmx
, index
, save_nmsrs
++);
2602 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2604 move_msr_up(vmx
, index
, save_nmsrs
++);
2605 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2606 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2607 move_msr_up(vmx
, index
, save_nmsrs
++);
2609 * MSR_STAR is only needed on long mode guests, and only
2610 * if efer.sce is enabled.
2612 index
= __find_msr_index(vmx
, MSR_STAR
);
2613 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2614 move_msr_up(vmx
, index
, save_nmsrs
++);
2617 index
= __find_msr_index(vmx
, MSR_EFER
);
2618 if (index
>= 0 && update_transition_efer(vmx
, index
))
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2621 vmx
->save_nmsrs
= save_nmsrs
;
2623 if (cpu_has_vmx_msr_bitmap())
2624 vmx_set_msr_bitmap(&vmx
->vcpu
);
2628 * reads and returns guest's timestamp counter "register"
2629 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2630 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2632 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2634 u64 host_tsc
, tsc_offset
;
2637 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2638 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2642 * writes 'offset' into guest's timestamp counter offset register
2644 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2646 if (is_guest_mode(vcpu
)) {
2648 * We're here if L1 chose not to trap WRMSR to TSC. According
2649 * to the spec, this should set L1's TSC; The offset that L1
2650 * set for L2 remains unchanged, and still needs to be added
2651 * to the newly set TSC to get L2's TSC.
2653 struct vmcs12
*vmcs12
;
2654 /* recalculate vmcs02.TSC_OFFSET: */
2655 vmcs12
= get_vmcs12(vcpu
);
2656 vmcs_write64(TSC_OFFSET
, offset
+
2657 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2658 vmcs12
->tsc_offset
: 0));
2660 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2661 vmcs_read64(TSC_OFFSET
), offset
);
2662 vmcs_write64(TSC_OFFSET
, offset
);
2666 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2668 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2669 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2673 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2674 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2675 * all guests if the "nested" module option is off, and can also be disabled
2676 * for a single guest by disabling its VMX cpuid bit.
2678 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2680 return nested
&& guest_cpuid_has_vmx(vcpu
);
2684 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2685 * returned for the various VMX controls MSRs when nested VMX is enabled.
2686 * The same values should also be used to verify that vmcs12 control fields are
2687 * valid during nested entry from L1 to L2.
2688 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2689 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2690 * bit in the high half is on if the corresponding bit in the control field
2691 * may be on. See also vmx_control_verify().
2693 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2696 * Note that as a general rule, the high half of the MSRs (bits in
2697 * the control fields which may be 1) should be initialized by the
2698 * intersection of the underlying hardware's MSR (i.e., features which
2699 * can be supported) and the list of features we want to expose -
2700 * because they are known to be properly supported in our code.
2701 * Also, usually, the low half of the MSRs (bits which must be 1) can
2702 * be set to 0, meaning that L1 may turn off any of these bits. The
2703 * reason is that if one of these bits is necessary, it will appear
2704 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2705 * fields of vmcs01 and vmcs02, will turn these bits off - and
2706 * nested_vmx_exit_reflected() will not pass related exits to L1.
2707 * These rules have exceptions below.
2710 /* pin-based controls */
2711 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2712 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2713 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2714 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2715 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2716 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2717 PIN_BASED_EXT_INTR_MASK
|
2718 PIN_BASED_NMI_EXITING
|
2719 PIN_BASED_VIRTUAL_NMIS
;
2720 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2721 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2722 PIN_BASED_VMX_PREEMPTION_TIMER
;
2723 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2724 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2725 PIN_BASED_POSTED_INTR
;
2728 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2729 vmx
->nested
.nested_vmx_exit_ctls_low
,
2730 vmx
->nested
.nested_vmx_exit_ctls_high
);
2731 vmx
->nested
.nested_vmx_exit_ctls_low
=
2732 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2734 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2735 #ifdef CONFIG_X86_64
2736 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2738 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2739 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2740 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2741 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2742 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2744 if (kvm_mpx_supported())
2745 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2747 /* We support free control of debug control saving. */
2748 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2750 /* entry controls */
2751 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2752 vmx
->nested
.nested_vmx_entry_ctls_low
,
2753 vmx
->nested
.nested_vmx_entry_ctls_high
);
2754 vmx
->nested
.nested_vmx_entry_ctls_low
=
2755 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2756 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2757 #ifdef CONFIG_X86_64
2758 VM_ENTRY_IA32E_MODE
|
2760 VM_ENTRY_LOAD_IA32_PAT
;
2761 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2762 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2763 if (kvm_mpx_supported())
2764 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2766 /* We support free control of debug control loading. */
2767 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2769 /* cpu-based controls */
2770 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2772 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2773 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2774 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2775 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2776 CPU_BASED_VIRTUAL_INTR_PENDING
|
2777 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2778 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2779 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2780 CPU_BASED_CR3_STORE_EXITING
|
2781 #ifdef CONFIG_X86_64
2782 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2784 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2785 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2786 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2787 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2788 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2790 * We can allow some features even when not supported by the
2791 * hardware. For example, L1 can specify an MSR bitmap - and we
2792 * can use it to avoid exits to L1 - even when L0 runs L2
2793 * without MSR bitmaps.
2795 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2796 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2797 CPU_BASED_USE_MSR_BITMAPS
;
2799 /* We support free control of CR3 access interception. */
2800 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2801 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2803 /* secondary cpu-based controls */
2804 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2805 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2806 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2809 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2810 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2811 SECONDARY_EXEC_RDTSCP
|
2812 SECONDARY_EXEC_DESC
|
2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2814 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2816 SECONDARY_EXEC_WBINVD_EXITING
|
2817 SECONDARY_EXEC_XSAVES
;
2820 /* nested EPT: emulate EPT also to L1 */
2821 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2822 SECONDARY_EXEC_ENABLE_EPT
;
2823 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2824 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2825 if (cpu_has_vmx_ept_execute_only())
2826 vmx
->nested
.nested_vmx_ept_caps
|=
2827 VMX_EPT_EXECUTE_ONLY_BIT
;
2828 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2829 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2830 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2831 VMX_EPT_1GB_PAGE_BIT
;
2832 if (enable_ept_ad_bits
) {
2833 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2834 SECONDARY_EXEC_ENABLE_PML
;
2835 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2838 vmx
->nested
.nested_vmx_ept_caps
= 0;
2841 * Old versions of KVM use the single-context version without
2842 * checking for support, so declare that it is supported even
2843 * though it is treated as global context. The alternative is
2844 * not failing the single-context invvpid, and it is worse.
2847 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2848 SECONDARY_EXEC_ENABLE_VPID
;
2849 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2850 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2852 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2854 if (enable_unrestricted_guest
)
2855 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2856 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2858 /* miscellaneous data */
2859 rdmsr(MSR_IA32_VMX_MISC
,
2860 vmx
->nested
.nested_vmx_misc_low
,
2861 vmx
->nested
.nested_vmx_misc_high
);
2862 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2863 vmx
->nested
.nested_vmx_misc_low
|=
2864 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2865 VMX_MISC_ACTIVITY_HLT
;
2866 vmx
->nested
.nested_vmx_misc_high
= 0;
2869 * This MSR reports some information about VMX support. We
2870 * should return information about the VMX we emulate for the
2871 * guest, and the VMCS structure we give it - not about the
2872 * VMX support of the underlying hardware.
2874 vmx
->nested
.nested_vmx_basic
=
2876 VMX_BASIC_TRUE_CTLS
|
2877 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2878 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2880 if (cpu_has_vmx_basic_inout())
2881 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2884 * These MSRs specify bits which the guest must keep fixed on
2885 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2886 * We picked the standard core2 setting.
2888 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2889 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2890 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2891 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2893 /* These MSRs specify bits which the guest must keep fixed off. */
2894 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2895 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2897 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2898 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2902 * if fixed0[i] == 1: val[i] must be 1
2903 * if fixed1[i] == 0: val[i] must be 0
2905 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2907 return ((val
& fixed1
) | fixed0
) == val
;
2910 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2912 return fixed_bits_valid(control
, low
, high
);
2915 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2917 return low
| ((u64
)high
<< 32);
2920 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2925 return (superset
| subset
) == superset
;
2928 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2930 const u64 feature_and_reserved
=
2931 /* feature (except bit 48; see below) */
2932 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2934 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2935 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2937 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2941 * KVM does not emulate a version of VMX that constrains physical
2942 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2944 if (data
& BIT_ULL(48))
2947 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2948 vmx_basic_vmcs_revision_id(data
))
2951 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2954 vmx
->nested
.nested_vmx_basic
= data
;
2959 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2964 switch (msr_index
) {
2965 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2966 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2967 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2969 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2970 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2971 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2973 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2974 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2975 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2977 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2978 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2979 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2981 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2982 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2983 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2989 supported
= vmx_control_msr(*lowp
, *highp
);
2991 /* Check must-be-1 bits are still 1. */
2992 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2995 /* Check must-be-0 bits are still 0. */
2996 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3000 *highp
= data
>> 32;
3004 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3006 const u64 feature_and_reserved_bits
=
3008 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3009 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3011 GENMASK_ULL(13, 9) | BIT_ULL(31);
3014 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3015 vmx
->nested
.nested_vmx_misc_high
);
3017 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3020 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3021 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3022 vmx_misc_preemption_timer_rate(data
) !=
3023 vmx_misc_preemption_timer_rate(vmx_misc
))
3026 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3029 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3032 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3035 vmx
->nested
.nested_vmx_misc_low
= data
;
3036 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3040 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3042 u64 vmx_ept_vpid_cap
;
3044 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3045 vmx
->nested
.nested_vmx_vpid_caps
);
3047 /* Every bit is either reserved or a feature bit. */
3048 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3051 vmx
->nested
.nested_vmx_ept_caps
= data
;
3052 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3056 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3060 switch (msr_index
) {
3061 case MSR_IA32_VMX_CR0_FIXED0
:
3062 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3064 case MSR_IA32_VMX_CR4_FIXED0
:
3065 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3072 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3073 * must be 1 in the restored value.
3075 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3083 * Called when userspace is restoring VMX MSRs.
3085 * Returns 0 on success, non-0 otherwise.
3087 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3089 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3091 switch (msr_index
) {
3092 case MSR_IA32_VMX_BASIC
:
3093 return vmx_restore_vmx_basic(vmx
, data
);
3094 case MSR_IA32_VMX_PINBASED_CTLS
:
3095 case MSR_IA32_VMX_PROCBASED_CTLS
:
3096 case MSR_IA32_VMX_EXIT_CTLS
:
3097 case MSR_IA32_VMX_ENTRY_CTLS
:
3099 * The "non-true" VMX capability MSRs are generated from the
3100 * "true" MSRs, so we do not support restoring them directly.
3102 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3103 * should restore the "true" MSRs with the must-be-1 bits
3104 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3105 * DEFAULT SETTINGS".
3108 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3109 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3110 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3111 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3112 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3113 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3114 case MSR_IA32_VMX_MISC
:
3115 return vmx_restore_vmx_misc(vmx
, data
);
3116 case MSR_IA32_VMX_CR0_FIXED0
:
3117 case MSR_IA32_VMX_CR4_FIXED0
:
3118 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3119 case MSR_IA32_VMX_CR0_FIXED1
:
3120 case MSR_IA32_VMX_CR4_FIXED1
:
3122 * These MSRs are generated based on the vCPU's CPUID, so we
3123 * do not support restoring them directly.
3126 case MSR_IA32_VMX_EPT_VPID_CAP
:
3127 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3128 case MSR_IA32_VMX_VMCS_ENUM
:
3129 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3133 * The rest of the VMX capability MSRs do not support restore.
3139 /* Returns 0 on success, non-0 otherwise. */
3140 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3142 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3144 switch (msr_index
) {
3145 case MSR_IA32_VMX_BASIC
:
3146 *pdata
= vmx
->nested
.nested_vmx_basic
;
3148 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3149 case MSR_IA32_VMX_PINBASED_CTLS
:
3150 *pdata
= vmx_control_msr(
3151 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3152 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3153 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3154 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3156 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3157 case MSR_IA32_VMX_PROCBASED_CTLS
:
3158 *pdata
= vmx_control_msr(
3159 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3160 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3161 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3162 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3164 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3165 case MSR_IA32_VMX_EXIT_CTLS
:
3166 *pdata
= vmx_control_msr(
3167 vmx
->nested
.nested_vmx_exit_ctls_low
,
3168 vmx
->nested
.nested_vmx_exit_ctls_high
);
3169 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3170 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3172 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3173 case MSR_IA32_VMX_ENTRY_CTLS
:
3174 *pdata
= vmx_control_msr(
3175 vmx
->nested
.nested_vmx_entry_ctls_low
,
3176 vmx
->nested
.nested_vmx_entry_ctls_high
);
3177 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3178 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3180 case MSR_IA32_VMX_MISC
:
3181 *pdata
= vmx_control_msr(
3182 vmx
->nested
.nested_vmx_misc_low
,
3183 vmx
->nested
.nested_vmx_misc_high
);
3185 case MSR_IA32_VMX_CR0_FIXED0
:
3186 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3188 case MSR_IA32_VMX_CR0_FIXED1
:
3189 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3191 case MSR_IA32_VMX_CR4_FIXED0
:
3192 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3194 case MSR_IA32_VMX_CR4_FIXED1
:
3195 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3197 case MSR_IA32_VMX_VMCS_ENUM
:
3198 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3200 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3201 *pdata
= vmx_control_msr(
3202 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3203 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3205 case MSR_IA32_VMX_EPT_VPID_CAP
:
3206 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3207 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3216 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3219 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3221 return !(val
& ~valid_bits
);
3225 * Reads an msr value (of 'msr_index') into 'pdata'.
3226 * Returns 0 on success, non-0 otherwise.
3227 * Assumes vcpu_load() was already called.
3229 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3231 struct shared_msr_entry
*msr
;
3233 switch (msr_info
->index
) {
3234 #ifdef CONFIG_X86_64
3236 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3239 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3241 case MSR_KERNEL_GS_BASE
:
3242 vmx_load_host_state(to_vmx(vcpu
));
3243 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3247 return kvm_get_msr_common(vcpu
, msr_info
);
3249 msr_info
->data
= guest_read_tsc(vcpu
);
3251 case MSR_IA32_SPEC_CTRL
:
3252 msr_info
->data
= vcpu
->arch
.spec_ctrl
;
3254 case MSR_IA32_SYSENTER_CS
:
3255 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3257 case MSR_IA32_SYSENTER_EIP
:
3258 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3260 case MSR_IA32_SYSENTER_ESP
:
3261 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3263 case MSR_IA32_BNDCFGS
:
3264 if (!kvm_mpx_supported() ||
3265 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3267 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3269 case MSR_IA32_MCG_EXT_CTL
:
3270 if (!msr_info
->host_initiated
&&
3271 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3272 FEATURE_CONTROL_LMCE
))
3274 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3276 case MSR_IA32_FEATURE_CONTROL
:
3277 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3279 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3280 if (!nested_vmx_allowed(vcpu
))
3282 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3284 if (!vmx_xsaves_supported())
3286 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3289 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3291 /* Otherwise falls through */
3293 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3295 msr_info
->data
= msr
->data
;
3298 return kvm_get_msr_common(vcpu
, msr_info
);
3304 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3307 * Writes msr value into into the appropriate "register".
3308 * Returns 0 on success, non-0 otherwise.
3309 * Assumes vcpu_load() was already called.
3311 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3314 struct shared_msr_entry
*msr
;
3316 u32 msr_index
= msr_info
->index
;
3317 u64 data
= msr_info
->data
;
3319 switch (msr_index
) {
3321 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3323 #ifdef CONFIG_X86_64
3325 vmx_segment_cache_clear(vmx
);
3326 vmcs_writel(GUEST_FS_BASE
, data
);
3329 vmx_segment_cache_clear(vmx
);
3330 vmcs_writel(GUEST_GS_BASE
, data
);
3332 case MSR_KERNEL_GS_BASE
:
3333 vmx_load_host_state(vmx
);
3334 vmx
->msr_guest_kernel_gs_base
= data
;
3337 case MSR_IA32_SYSENTER_CS
:
3338 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3340 case MSR_IA32_SYSENTER_EIP
:
3341 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3343 case MSR_IA32_SYSENTER_ESP
:
3344 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3346 case MSR_IA32_BNDCFGS
:
3347 if (!kvm_mpx_supported() ||
3348 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3350 if (is_noncanonical_address(data
& PAGE_MASK
) ||
3351 (data
& MSR_IA32_BNDCFGS_RSVD
))
3353 vmcs_write64(GUEST_BNDCFGS
, data
);
3356 kvm_write_tsc(vcpu
, msr_info
);
3358 case MSR_IA32_SPEC_CTRL
:
3359 vcpu
->arch
.spec_ctrl
= msr_info
->data
;
3361 case MSR_IA32_CR_PAT
:
3362 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3363 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3365 vmcs_write64(GUEST_IA32_PAT
, data
);
3366 vcpu
->arch
.pat
= data
;
3369 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3371 case MSR_IA32_TSC_ADJUST
:
3372 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3374 case MSR_IA32_MCG_EXT_CTL
:
3375 if ((!msr_info
->host_initiated
&&
3376 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3377 FEATURE_CONTROL_LMCE
)) ||
3378 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3380 vcpu
->arch
.mcg_ext_ctl
= data
;
3382 case MSR_IA32_FEATURE_CONTROL
:
3383 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3384 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3385 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3387 vmx
->msr_ia32_feature_control
= data
;
3388 if (msr_info
->host_initiated
&& data
== 0)
3389 vmx_leave_nested(vcpu
);
3391 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3392 if (!msr_info
->host_initiated
)
3393 return 1; /* they are read-only */
3394 if (!nested_vmx_allowed(vcpu
))
3396 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3398 if (!vmx_xsaves_supported())
3401 * The only supported bit as of Skylake is bit 8, but
3402 * it is not supported on KVM.
3406 vcpu
->arch
.ia32_xss
= data
;
3407 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3408 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3409 vcpu
->arch
.ia32_xss
, host_xss
);
3411 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3414 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3416 /* Check reserved bit, higher 32 bits should be zero */
3417 if ((data
>> 32) != 0)
3419 /* Otherwise falls through */
3421 msr
= find_msr_entry(vmx
, msr_index
);
3423 u64 old_msr_data
= msr
->data
;
3425 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3427 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3431 msr
->data
= old_msr_data
;
3435 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3441 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3443 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3446 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3449 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3451 case VCPU_EXREG_PDPTR
:
3453 ept_save_pdptrs(vcpu
);
3460 static __init
int cpu_has_kvm_support(void)
3462 return cpu_has_vmx();
3465 static __init
int vmx_disabled_by_bios(void)
3469 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3470 if (msr
& FEATURE_CONTROL_LOCKED
) {
3471 /* launched w/ TXT and VMX disabled */
3472 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3475 /* launched w/o TXT and VMX only enabled w/ TXT */
3476 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3477 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3478 && !tboot_enabled()) {
3479 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3480 "activate TXT before enabling KVM\n");
3483 /* launched w/o TXT and VMX disabled */
3484 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3485 && !tboot_enabled())
3492 static void kvm_cpu_vmxon(u64 addr
)
3494 cr4_set_bits(X86_CR4_VMXE
);
3495 intel_pt_handle_vmx(1);
3497 asm volatile (ASM_VMX_VMXON_RAX
3498 : : "a"(&addr
), "m"(addr
)
3502 static int hardware_enable(void)
3504 int cpu
= raw_smp_processor_id();
3505 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3508 if (cr4_read_shadow() & X86_CR4_VMXE
)
3511 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3512 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3513 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3516 * Now we can enable the vmclear operation in kdump
3517 * since the loaded_vmcss_on_cpu list on this cpu
3518 * has been initialized.
3520 * Though the cpu is not in VMX operation now, there
3521 * is no problem to enable the vmclear operation
3522 * for the loaded_vmcss_on_cpu list is empty!
3524 crash_enable_local_vmclear(cpu
);
3526 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3528 test_bits
= FEATURE_CONTROL_LOCKED
;
3529 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3530 if (tboot_enabled())
3531 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3533 if ((old
& test_bits
) != test_bits
) {
3534 /* enable and lock */
3535 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3537 kvm_cpu_vmxon(phys_addr
);
3543 static void vmclear_local_loaded_vmcss(void)
3545 int cpu
= raw_smp_processor_id();
3546 struct loaded_vmcs
*v
, *n
;
3548 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3549 loaded_vmcss_on_cpu_link
)
3550 __loaded_vmcs_clear(v
);
3554 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3557 static void kvm_cpu_vmxoff(void)
3559 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3561 intel_pt_handle_vmx(0);
3562 cr4_clear_bits(X86_CR4_VMXE
);
3565 static void hardware_disable(void)
3567 vmclear_local_loaded_vmcss();
3571 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3572 u32 msr
, u32
*result
)
3574 u32 vmx_msr_low
, vmx_msr_high
;
3575 u32 ctl
= ctl_min
| ctl_opt
;
3577 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3579 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3580 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3582 /* Ensure minimum (required) set of control bits are supported. */
3590 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3592 u32 vmx_msr_low
, vmx_msr_high
;
3594 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3595 return vmx_msr_high
& ctl
;
3598 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3600 u32 vmx_msr_low
, vmx_msr_high
;
3601 u32 min
, opt
, min2
, opt2
;
3602 u32 _pin_based_exec_control
= 0;
3603 u32 _cpu_based_exec_control
= 0;
3604 u32 _cpu_based_2nd_exec_control
= 0;
3605 u32 _vmexit_control
= 0;
3606 u32 _vmentry_control
= 0;
3608 min
= CPU_BASED_HLT_EXITING
|
3609 #ifdef CONFIG_X86_64
3610 CPU_BASED_CR8_LOAD_EXITING
|
3611 CPU_BASED_CR8_STORE_EXITING
|
3613 CPU_BASED_CR3_LOAD_EXITING
|
3614 CPU_BASED_CR3_STORE_EXITING
|
3615 CPU_BASED_USE_IO_BITMAPS
|
3616 CPU_BASED_MOV_DR_EXITING
|
3617 CPU_BASED_USE_TSC_OFFSETING
|
3618 CPU_BASED_INVLPG_EXITING
|
3619 CPU_BASED_RDPMC_EXITING
;
3621 if (!kvm_mwait_in_guest())
3622 min
|= CPU_BASED_MWAIT_EXITING
|
3623 CPU_BASED_MONITOR_EXITING
;
3625 opt
= CPU_BASED_TPR_SHADOW
|
3626 CPU_BASED_USE_MSR_BITMAPS
|
3627 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3628 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3629 &_cpu_based_exec_control
) < 0)
3631 #ifdef CONFIG_X86_64
3632 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3633 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3634 ~CPU_BASED_CR8_STORE_EXITING
;
3636 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3638 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3639 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3640 SECONDARY_EXEC_WBINVD_EXITING
|
3641 SECONDARY_EXEC_ENABLE_VPID
|
3642 SECONDARY_EXEC_ENABLE_EPT
|
3643 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3644 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3645 SECONDARY_EXEC_RDTSCP
|
3646 SECONDARY_EXEC_ENABLE_INVPCID
|
3647 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3648 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3649 SECONDARY_EXEC_SHADOW_VMCS
|
3650 SECONDARY_EXEC_XSAVES
|
3651 SECONDARY_EXEC_ENABLE_PML
|
3652 SECONDARY_EXEC_TSC_SCALING
;
3653 if (adjust_vmx_controls(min2
, opt2
,
3654 MSR_IA32_VMX_PROCBASED_CTLS2
,
3655 &_cpu_based_2nd_exec_control
) < 0)
3658 #ifndef CONFIG_X86_64
3659 if (!(_cpu_based_2nd_exec_control
&
3660 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3661 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3664 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3665 _cpu_based_2nd_exec_control
&= ~(
3666 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3667 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3668 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3670 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3671 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3673 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3674 CPU_BASED_CR3_STORE_EXITING
|
3675 CPU_BASED_INVLPG_EXITING
);
3676 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3677 vmx_capability
.ept
, vmx_capability
.vpid
);
3680 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3681 #ifdef CONFIG_X86_64
3682 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3684 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3685 VM_EXIT_CLEAR_BNDCFGS
;
3686 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3687 &_vmexit_control
) < 0)
3690 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3691 PIN_BASED_VIRTUAL_NMIS
;
3692 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3693 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3694 &_pin_based_exec_control
) < 0)
3697 if (cpu_has_broken_vmx_preemption_timer())
3698 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3699 if (!(_cpu_based_2nd_exec_control
&
3700 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3701 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3703 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3704 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3705 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3706 &_vmentry_control
) < 0)
3709 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3711 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3712 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3715 #ifdef CONFIG_X86_64
3716 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3717 if (vmx_msr_high
& (1u<<16))
3721 /* Require Write-Back (WB) memory type for VMCS accesses. */
3722 if (((vmx_msr_high
>> 18) & 15) != 6)
3725 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3726 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3727 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3728 vmcs_conf
->revision_id
= vmx_msr_low
;
3730 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3731 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3732 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3733 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3734 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3736 cpu_has_load_ia32_efer
=
3737 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3738 VM_ENTRY_LOAD_IA32_EFER
)
3739 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3740 VM_EXIT_LOAD_IA32_EFER
);
3742 cpu_has_load_perf_global_ctrl
=
3743 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3744 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3745 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3746 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3749 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3750 * but due to errata below it can't be used. Workaround is to use
3751 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3753 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3758 * BC86,AAY89,BD102 (model 44)
3762 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3763 switch (boot_cpu_data
.x86_model
) {
3769 cpu_has_load_perf_global_ctrl
= false;
3770 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3771 "does not work properly. Using workaround\n");
3778 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3779 rdmsrl(MSR_IA32_XSS
, host_xss
);
3784 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3786 int node
= cpu_to_node(cpu
);
3790 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3793 vmcs
= page_address(pages
);
3794 memset(vmcs
, 0, vmcs_config
.size
);
3795 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3799 static struct vmcs
*alloc_vmcs(void)
3801 return alloc_vmcs_cpu(raw_smp_processor_id());
3804 static void free_vmcs(struct vmcs
*vmcs
)
3806 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3810 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3812 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3814 if (!loaded_vmcs
->vmcs
)
3816 loaded_vmcs_clear(loaded_vmcs
);
3817 free_vmcs(loaded_vmcs
->vmcs
);
3818 loaded_vmcs
->vmcs
= NULL
;
3819 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3822 static void free_kvm_area(void)
3826 for_each_possible_cpu(cpu
) {
3827 free_vmcs(per_cpu(vmxarea
, cpu
));
3828 per_cpu(vmxarea
, cpu
) = NULL
;
3832 enum vmcs_field_type
{
3833 VMCS_FIELD_TYPE_U16
= 0,
3834 VMCS_FIELD_TYPE_U64
= 1,
3835 VMCS_FIELD_TYPE_U32
= 2,
3836 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3839 static inline int vmcs_field_type(unsigned long field
)
3841 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3842 return VMCS_FIELD_TYPE_U32
;
3843 return (field
>> 13) & 0x3 ;
3846 static inline int vmcs_field_readonly(unsigned long field
)
3848 return (((field
>> 10) & 0x3) == 1);
3851 static void init_vmcs_shadow_fields(void)
3855 /* No checks for read only fields yet */
3857 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3858 switch (shadow_read_write_fields
[i
]) {
3860 if (!kvm_mpx_supported())
3868 shadow_read_write_fields
[j
] =
3869 shadow_read_write_fields
[i
];
3872 max_shadow_read_write_fields
= j
;
3874 /* shadowed fields guest access without vmexit */
3875 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3876 unsigned long field
= shadow_read_write_fields
[i
];
3878 clear_bit(field
, vmx_vmwrite_bitmap
);
3879 clear_bit(field
, vmx_vmread_bitmap
);
3880 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3881 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3882 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3885 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3886 unsigned long field
= shadow_read_only_fields
[i
];
3888 clear_bit(field
, vmx_vmread_bitmap
);
3889 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3890 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3894 static __init
int alloc_kvm_area(void)
3898 for_each_possible_cpu(cpu
) {
3901 vmcs
= alloc_vmcs_cpu(cpu
);
3907 per_cpu(vmxarea
, cpu
) = vmcs
;
3912 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3913 struct kvm_segment
*save
)
3915 if (!emulate_invalid_guest_state
) {
3917 * CS and SS RPL should be equal during guest entry according
3918 * to VMX spec, but in reality it is not always so. Since vcpu
3919 * is in the middle of the transition from real mode to
3920 * protected mode it is safe to assume that RPL 0 is a good
3923 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3924 save
->selector
&= ~SEGMENT_RPL_MASK
;
3925 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3928 vmx_set_segment(vcpu
, save
, seg
);
3931 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3933 unsigned long flags
;
3934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3937 * Update real mode segment cache. It may be not up-to-date if sement
3938 * register was written while vcpu was in a guest mode.
3940 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3941 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3942 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3943 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3944 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3945 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3947 vmx
->rmode
.vm86_active
= 0;
3949 vmx_segment_cache_clear(vmx
);
3951 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3953 flags
= vmcs_readl(GUEST_RFLAGS
);
3954 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3955 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3956 vmcs_writel(GUEST_RFLAGS
, flags
);
3958 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3959 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3961 update_exception_bitmap(vcpu
);
3963 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3964 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3965 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3966 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3967 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3968 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3971 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3973 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3974 struct kvm_segment var
= *save
;
3977 if (seg
== VCPU_SREG_CS
)
3980 if (!emulate_invalid_guest_state
) {
3981 var
.selector
= var
.base
>> 4;
3982 var
.base
= var
.base
& 0xffff0;
3992 if (save
->base
& 0xf)
3993 printk_once(KERN_WARNING
"kvm: segment base is not "
3994 "paragraph aligned when entering "
3995 "protected mode (seg=%d)", seg
);
3998 vmcs_write16(sf
->selector
, var
.selector
);
3999 vmcs_writel(sf
->base
, var
.base
);
4000 vmcs_write32(sf
->limit
, var
.limit
);
4001 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4004 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4006 unsigned long flags
;
4007 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4009 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4010 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4011 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4012 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4013 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4014 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4015 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4017 vmx
->rmode
.vm86_active
= 1;
4020 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4021 * vcpu. Warn the user that an update is overdue.
4023 if (!vcpu
->kvm
->arch
.tss_addr
)
4024 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4025 "called before entering vcpu\n");
4027 vmx_segment_cache_clear(vmx
);
4029 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4030 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4031 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4033 flags
= vmcs_readl(GUEST_RFLAGS
);
4034 vmx
->rmode
.save_rflags
= flags
;
4036 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4038 vmcs_writel(GUEST_RFLAGS
, flags
);
4039 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4040 update_exception_bitmap(vcpu
);
4042 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4043 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4044 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4045 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4046 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4047 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4049 kvm_mmu_reset_context(vcpu
);
4052 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4054 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4055 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4061 * Force kernel_gs_base reloading before EFER changes, as control
4062 * of this msr depends on is_long_mode().
4064 vmx_load_host_state(to_vmx(vcpu
));
4065 vcpu
->arch
.efer
= efer
;
4066 if (efer
& EFER_LMA
) {
4067 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4070 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4072 msr
->data
= efer
& ~EFER_LME
;
4077 #ifdef CONFIG_X86_64
4079 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4083 vmx_segment_cache_clear(to_vmx(vcpu
));
4085 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4086 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4087 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4089 vmcs_write32(GUEST_TR_AR_BYTES
,
4090 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4091 | VMX_AR_TYPE_BUSY_64_TSS
);
4093 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4096 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4098 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4099 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4104 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4107 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4109 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4111 vpid_sync_context(vpid
);
4115 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4117 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4120 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4123 vmx_flush_tlb(vcpu
);
4126 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4128 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4130 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4131 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4134 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4136 if (enable_ept
&& is_paging(vcpu
))
4137 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4138 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4141 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4143 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4145 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4146 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4149 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4151 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4153 if (!test_bit(VCPU_EXREG_PDPTR
,
4154 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4157 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4158 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4159 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4160 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4161 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4165 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4167 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4169 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4170 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4171 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4172 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4173 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4176 __set_bit(VCPU_EXREG_PDPTR
,
4177 (unsigned long *)&vcpu
->arch
.regs_avail
);
4178 __set_bit(VCPU_EXREG_PDPTR
,
4179 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4182 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4184 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4185 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4186 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4188 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4189 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4190 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4191 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4193 return fixed_bits_valid(val
, fixed0
, fixed1
);
4196 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4198 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4199 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4201 return fixed_bits_valid(val
, fixed0
, fixed1
);
4204 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4206 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4207 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4209 return fixed_bits_valid(val
, fixed0
, fixed1
);
4212 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4213 #define nested_guest_cr4_valid nested_cr4_valid
4214 #define nested_host_cr4_valid nested_cr4_valid
4216 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4218 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4220 struct kvm_vcpu
*vcpu
)
4222 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4223 vmx_decache_cr3(vcpu
);
4224 if (!(cr0
& X86_CR0_PG
)) {
4225 /* From paging/starting to nonpaging */
4226 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4227 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4228 (CPU_BASED_CR3_LOAD_EXITING
|
4229 CPU_BASED_CR3_STORE_EXITING
));
4230 vcpu
->arch
.cr0
= cr0
;
4231 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4232 } else if (!is_paging(vcpu
)) {
4233 /* From nonpaging to paging */
4234 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4235 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4236 ~(CPU_BASED_CR3_LOAD_EXITING
|
4237 CPU_BASED_CR3_STORE_EXITING
));
4238 vcpu
->arch
.cr0
= cr0
;
4239 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4242 if (!(cr0
& X86_CR0_WP
))
4243 *hw_cr0
&= ~X86_CR0_WP
;
4246 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4248 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4249 unsigned long hw_cr0
;
4251 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4252 if (enable_unrestricted_guest
)
4253 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4255 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4257 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4260 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4264 #ifdef CONFIG_X86_64
4265 if (vcpu
->arch
.efer
& EFER_LME
) {
4266 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4268 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4274 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4276 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4277 vmcs_writel(GUEST_CR0
, hw_cr0
);
4278 vcpu
->arch
.cr0
= cr0
;
4280 /* depends on vcpu->arch.cr0 to be set to a new value */
4281 vmx
->emulation_required
= emulation_required(vcpu
);
4284 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4288 /* TODO write the value reading from MSR */
4289 eptp
= VMX_EPT_DEFAULT_MT
|
4290 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4291 if (enable_ept_ad_bits
&&
4292 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4293 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4294 eptp
|= (root_hpa
& PAGE_MASK
);
4299 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4301 unsigned long guest_cr3
;
4306 eptp
= construct_eptp(vcpu
, cr3
);
4307 vmcs_write64(EPT_POINTER
, eptp
);
4308 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4309 guest_cr3
= kvm_read_cr3(vcpu
);
4311 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4312 ept_load_pdptrs(vcpu
);
4315 vmx_flush_tlb(vcpu
);
4316 vmcs_writel(GUEST_CR3
, guest_cr3
);
4319 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4322 * Pass through host's Machine Check Enable value to hw_cr4, which
4323 * is in force while we are in guest mode. Do not let guests control
4324 * this bit, even if host CR4.MCE == 0.
4326 unsigned long hw_cr4
=
4327 (cr4_read_shadow() & X86_CR4_MCE
) |
4328 (cr4
& ~X86_CR4_MCE
) |
4329 (to_vmx(vcpu
)->rmode
.vm86_active
?
4330 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4332 if (cr4
& X86_CR4_VMXE
) {
4334 * To use VMXON (and later other VMX instructions), a guest
4335 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4336 * So basically the check on whether to allow nested VMX
4339 if (!nested_vmx_allowed(vcpu
))
4343 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4346 vcpu
->arch
.cr4
= cr4
;
4348 if (!is_paging(vcpu
)) {
4349 hw_cr4
&= ~X86_CR4_PAE
;
4350 hw_cr4
|= X86_CR4_PSE
;
4351 } else if (!(cr4
& X86_CR4_PAE
)) {
4352 hw_cr4
&= ~X86_CR4_PAE
;
4356 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4358 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4359 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4360 * to be manually disabled when guest switches to non-paging
4363 * If !enable_unrestricted_guest, the CPU is always running
4364 * with CR0.PG=1 and CR4 needs to be modified.
4365 * If enable_unrestricted_guest, the CPU automatically
4366 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4368 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4370 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4371 vmcs_writel(GUEST_CR4
, hw_cr4
);
4375 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4376 struct kvm_segment
*var
, int seg
)
4378 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4381 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4382 *var
= vmx
->rmode
.segs
[seg
];
4383 if (seg
== VCPU_SREG_TR
4384 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4386 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4387 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4390 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4391 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4392 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4393 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4394 var
->unusable
= (ar
>> 16) & 1;
4395 var
->type
= ar
& 15;
4396 var
->s
= (ar
>> 4) & 1;
4397 var
->dpl
= (ar
>> 5) & 3;
4399 * Some userspaces do not preserve unusable property. Since usable
4400 * segment has to be present according to VMX spec we can use present
4401 * property to amend userspace bug by making unusable segment always
4402 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4403 * segment as unusable.
4405 var
->present
= !var
->unusable
;
4406 var
->avl
= (ar
>> 12) & 1;
4407 var
->l
= (ar
>> 13) & 1;
4408 var
->db
= (ar
>> 14) & 1;
4409 var
->g
= (ar
>> 15) & 1;
4412 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4414 struct kvm_segment s
;
4416 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4417 vmx_get_segment(vcpu
, &s
, seg
);
4420 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4423 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4427 if (unlikely(vmx
->rmode
.vm86_active
))
4430 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4431 return VMX_AR_DPL(ar
);
4435 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4439 if (var
->unusable
|| !var
->present
)
4442 ar
= var
->type
& 15;
4443 ar
|= (var
->s
& 1) << 4;
4444 ar
|= (var
->dpl
& 3) << 5;
4445 ar
|= (var
->present
& 1) << 7;
4446 ar
|= (var
->avl
& 1) << 12;
4447 ar
|= (var
->l
& 1) << 13;
4448 ar
|= (var
->db
& 1) << 14;
4449 ar
|= (var
->g
& 1) << 15;
4455 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4456 struct kvm_segment
*var
, int seg
)
4458 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4459 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4461 vmx_segment_cache_clear(vmx
);
4463 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4464 vmx
->rmode
.segs
[seg
] = *var
;
4465 if (seg
== VCPU_SREG_TR
)
4466 vmcs_write16(sf
->selector
, var
->selector
);
4468 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4472 vmcs_writel(sf
->base
, var
->base
);
4473 vmcs_write32(sf
->limit
, var
->limit
);
4474 vmcs_write16(sf
->selector
, var
->selector
);
4477 * Fix the "Accessed" bit in AR field of segment registers for older
4479 * IA32 arch specifies that at the time of processor reset the
4480 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4481 * is setting it to 0 in the userland code. This causes invalid guest
4482 * state vmexit when "unrestricted guest" mode is turned on.
4483 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4484 * tree. Newer qemu binaries with that qemu fix would not need this
4487 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4488 var
->type
|= 0x1; /* Accessed */
4490 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4493 vmx
->emulation_required
= emulation_required(vcpu
);
4496 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4498 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4500 *db
= (ar
>> 14) & 1;
4501 *l
= (ar
>> 13) & 1;
4504 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4506 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4507 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4510 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4512 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4513 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4516 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4518 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4519 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4522 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4524 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4525 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4528 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4530 struct kvm_segment var
;
4533 vmx_get_segment(vcpu
, &var
, seg
);
4535 if (seg
== VCPU_SREG_CS
)
4537 ar
= vmx_segment_access_rights(&var
);
4539 if (var
.base
!= (var
.selector
<< 4))
4541 if (var
.limit
!= 0xffff)
4549 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4551 struct kvm_segment cs
;
4552 unsigned int cs_rpl
;
4554 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4555 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4559 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4563 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4564 if (cs
.dpl
> cs_rpl
)
4567 if (cs
.dpl
!= cs_rpl
)
4573 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4577 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4579 struct kvm_segment ss
;
4580 unsigned int ss_rpl
;
4582 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4583 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4587 if (ss
.type
!= 3 && ss
.type
!= 7)
4591 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4599 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4601 struct kvm_segment var
;
4604 vmx_get_segment(vcpu
, &var
, seg
);
4605 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4613 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4614 if (var
.dpl
< rpl
) /* DPL < RPL */
4618 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4624 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4626 struct kvm_segment tr
;
4628 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4632 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4634 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4642 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4644 struct kvm_segment ldtr
;
4646 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4650 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4660 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4662 struct kvm_segment cs
, ss
;
4664 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4665 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4667 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4668 (ss
.selector
& SEGMENT_RPL_MASK
));
4672 * Check if guest state is valid. Returns true if valid, false if
4674 * We assume that registers are always usable
4676 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4678 if (enable_unrestricted_guest
)
4681 /* real mode guest state checks */
4682 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4683 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4685 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4687 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4689 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4691 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4693 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4696 /* protected mode guest state checks */
4697 if (!cs_ss_rpl_check(vcpu
))
4699 if (!code_segment_valid(vcpu
))
4701 if (!stack_segment_valid(vcpu
))
4703 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4705 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4707 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4709 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4711 if (!tr_valid(vcpu
))
4713 if (!ldtr_valid(vcpu
))
4717 * - Add checks on RIP
4718 * - Add checks on RFLAGS
4724 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4726 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4729 static int init_rmode_tss(struct kvm
*kvm
)
4735 idx
= srcu_read_lock(&kvm
->srcu
);
4736 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4737 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4740 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4741 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4742 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4745 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4748 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4752 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4753 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4756 srcu_read_unlock(&kvm
->srcu
, idx
);
4760 static int init_rmode_identity_map(struct kvm
*kvm
)
4763 kvm_pfn_t identity_map_pfn
;
4769 /* Protect kvm->arch.ept_identity_pagetable_done. */
4770 mutex_lock(&kvm
->slots_lock
);
4772 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4775 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4777 r
= alloc_identity_pagetable(kvm
);
4781 idx
= srcu_read_lock(&kvm
->srcu
);
4782 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4785 /* Set up identity-mapping pagetable for EPT in real mode */
4786 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4787 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4788 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4789 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4790 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4794 kvm
->arch
.ept_identity_pagetable_done
= true;
4797 srcu_read_unlock(&kvm
->srcu
, idx
);
4800 mutex_unlock(&kvm
->slots_lock
);
4804 static void seg_setup(int seg
)
4806 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4809 vmcs_write16(sf
->selector
, 0);
4810 vmcs_writel(sf
->base
, 0);
4811 vmcs_write32(sf
->limit
, 0xffff);
4813 if (seg
== VCPU_SREG_CS
)
4814 ar
|= 0x08; /* code segment */
4816 vmcs_write32(sf
->ar_bytes
, ar
);
4819 static int alloc_apic_access_page(struct kvm
*kvm
)
4824 mutex_lock(&kvm
->slots_lock
);
4825 if (kvm
->arch
.apic_access_page_done
)
4827 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4828 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4832 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4833 if (is_error_page(page
)) {
4839 * Do not pin the page in memory, so that memory hot-unplug
4840 * is able to migrate it.
4843 kvm
->arch
.apic_access_page_done
= true;
4845 mutex_unlock(&kvm
->slots_lock
);
4849 static int alloc_identity_pagetable(struct kvm
*kvm
)
4851 /* Called with kvm->slots_lock held. */
4855 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4857 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4858 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4863 static int allocate_vpid(void)
4869 spin_lock(&vmx_vpid_lock
);
4870 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4871 if (vpid
< VMX_NR_VPIDS
)
4872 __set_bit(vpid
, vmx_vpid_bitmap
);
4875 spin_unlock(&vmx_vpid_lock
);
4879 static void free_vpid(int vpid
)
4881 if (!enable_vpid
|| vpid
== 0)
4883 spin_lock(&vmx_vpid_lock
);
4884 __clear_bit(vpid
, vmx_vpid_bitmap
);
4885 spin_unlock(&vmx_vpid_lock
);
4888 #define MSR_TYPE_R 1
4889 #define MSR_TYPE_W 2
4890 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4893 int f
= sizeof(unsigned long);
4895 if (!cpu_has_vmx_msr_bitmap())
4899 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4900 * have the write-low and read-high bitmap offsets the wrong way round.
4901 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4903 if (msr
<= 0x1fff) {
4904 if (type
& MSR_TYPE_R
)
4906 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4908 if (type
& MSR_TYPE_W
)
4910 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4912 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4914 if (type
& MSR_TYPE_R
)
4916 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4918 if (type
& MSR_TYPE_W
)
4920 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4926 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4927 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4929 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4930 unsigned long *msr_bitmap_nested
,
4933 int f
= sizeof(unsigned long);
4935 if (!cpu_has_vmx_msr_bitmap()) {
4941 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4942 * have the write-low and read-high bitmap offsets the wrong way round.
4943 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4945 if (msr
<= 0x1fff) {
4946 if (type
& MSR_TYPE_R
&&
4947 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4949 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4951 if (type
& MSR_TYPE_W
&&
4952 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4954 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4956 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4958 if (type
& MSR_TYPE_R
&&
4959 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4961 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4963 if (type
& MSR_TYPE_W
&&
4964 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4966 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4971 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4974 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4975 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4976 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4977 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4980 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4983 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4985 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4988 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4990 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4995 static bool vmx_get_enable_apicv(void)
4997 return enable_apicv
;
5000 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5002 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5006 * Don't need to mark the APIC access page dirty; it is never
5007 * written to by the CPU during APIC virtualization.
5010 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5011 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5012 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5015 if (nested_cpu_has_posted_intr(vmcs12
)) {
5016 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5017 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5022 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5024 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5029 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5032 vmx
->nested
.pi_pending
= false;
5033 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5036 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5037 if (max_irr
!= 256) {
5038 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5039 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5040 kunmap(vmx
->nested
.virtual_apic_page
);
5042 status
= vmcs_read16(GUEST_INTR_STATUS
);
5043 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5045 status
|= (u8
)max_irr
;
5046 vmcs_write16(GUEST_INTR_STATUS
, status
);
5050 nested_mark_vmcs12_pages_dirty(vcpu
);
5053 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5057 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5059 if (vcpu
->mode
== IN_GUEST_MODE
) {
5061 * The vector of interrupt to be delivered to vcpu had
5062 * been set in PIR before this function.
5064 * Following cases will be reached in this block, and
5065 * we always send a notification event in all cases as
5068 * Case 1: vcpu keeps in non-root mode. Sending a
5069 * notification event posts the interrupt to vcpu.
5071 * Case 2: vcpu exits to root mode and is still
5072 * runnable. PIR will be synced to vIRR before the
5073 * next vcpu entry. Sending a notification event in
5074 * this case has no effect, as vcpu is not in root
5077 * Case 3: vcpu exits to root mode and is blocked.
5078 * vcpu_block() has already synced PIR to vIRR and
5079 * never blocks vcpu if vIRR is not cleared. Therefore,
5080 * a blocked vcpu here does not wait for any requested
5081 * interrupts in PIR, and sending a notification event
5082 * which has no effect is safe here.
5085 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5092 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5095 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5097 if (is_guest_mode(vcpu
) &&
5098 vector
== vmx
->nested
.posted_intr_nv
) {
5099 /* the PIR and ON have been set by L1. */
5100 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5102 * If a posted intr is not recognized by hardware,
5103 * we will accomplish it in the next vmentry.
5105 vmx
->nested
.pi_pending
= true;
5106 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5112 * Send interrupt to vcpu via posted interrupt way.
5113 * 1. If target vcpu is running(non-root mode), send posted interrupt
5114 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5115 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5116 * interrupt from PIR in next vmentry.
5118 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5123 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5127 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5130 /* If a previous notification has sent the IPI, nothing to do. */
5131 if (pi_test_and_set_on(&vmx
->pi_desc
))
5134 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5135 kvm_vcpu_kick(vcpu
);
5139 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5140 * will not change in the lifetime of the guest.
5141 * Note that host-state that does change is set elsewhere. E.g., host-state
5142 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5144 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5149 unsigned long cr0
, cr3
, cr4
;
5152 WARN_ON(cr0
& X86_CR0_TS
);
5153 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5156 * Save the most likely value for this task's CR3 in the VMCS.
5157 * We can't use __get_current_cr3_fast() because we're not atomic.
5160 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5161 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5163 /* Save the most likely value for this task's CR4 in the VMCS. */
5164 cr4
= cr4_read_shadow();
5165 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5166 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5168 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5169 #ifdef CONFIG_X86_64
5171 * Load null selectors, so we can avoid reloading them in
5172 * __vmx_load_host_state(), in case userspace uses the null selectors
5173 * too (the expected case).
5175 vmcs_write16(HOST_DS_SELECTOR
, 0);
5176 vmcs_write16(HOST_ES_SELECTOR
, 0);
5178 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5179 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5181 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5182 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5185 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5186 vmx
->host_idt_base
= dt
.address
;
5188 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5190 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5191 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5192 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5193 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5195 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5196 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5197 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5201 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5203 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5205 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5206 if (is_guest_mode(&vmx
->vcpu
))
5207 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5208 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5209 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5212 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5214 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5216 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5217 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5218 /* Enable the preemption timer dynamically */
5219 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5220 return pin_based_exec_ctrl
;
5223 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5225 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5227 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5228 if (cpu_has_secondary_exec_ctrls()) {
5229 if (kvm_vcpu_apicv_active(vcpu
))
5230 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5231 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5232 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5234 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5235 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5236 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5239 if (cpu_has_vmx_msr_bitmap())
5240 vmx_set_msr_bitmap(vcpu
);
5243 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5245 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5247 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5248 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5250 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5251 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5252 #ifdef CONFIG_X86_64
5253 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5254 CPU_BASED_CR8_LOAD_EXITING
;
5258 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5259 CPU_BASED_CR3_LOAD_EXITING
|
5260 CPU_BASED_INVLPG_EXITING
;
5261 return exec_control
;
5264 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5266 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5267 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5268 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5270 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5272 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5273 enable_unrestricted_guest
= 0;
5274 /* Enable INVPCID for non-ept guests may cause performance regression. */
5275 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5277 if (!enable_unrestricted_guest
)
5278 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5280 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5281 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5282 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5283 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5284 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5285 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5287 We can NOT enable shadow_vmcs here because we don't have yet
5290 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5293 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5295 return exec_control
;
5298 static void ept_set_mmio_spte_mask(void)
5301 * EPT Misconfigurations can be generated if the value of bits 2:0
5302 * of an EPT paging-structure entry is 110b (write/execute).
5304 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5305 VMX_EPT_MISCONFIG_WX_VALUE
);
5308 #define VMX_XSS_EXIT_BITMAP 0
5310 * Sets up the vmcs for emulated real mode.
5312 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5314 #ifdef CONFIG_X86_64
5320 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5321 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5323 if (enable_shadow_vmcs
) {
5324 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5325 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5327 if (cpu_has_vmx_msr_bitmap())
5328 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5330 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5333 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5334 vmx
->hv_deadline_tsc
= -1;
5336 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5338 if (cpu_has_secondary_exec_ctrls()) {
5339 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5340 vmx_secondary_exec_control(vmx
));
5343 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5344 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5345 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5346 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5347 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5349 vmcs_write16(GUEST_INTR_STATUS
, 0);
5351 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5352 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5356 vmcs_write32(PLE_GAP
, ple_gap
);
5357 vmx
->ple_window
= ple_window
;
5358 vmx
->ple_window_dirty
= true;
5361 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5362 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5363 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5365 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5366 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5367 vmx_set_constant_host_state(vmx
);
5368 #ifdef CONFIG_X86_64
5369 rdmsrl(MSR_FS_BASE
, a
);
5370 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5371 rdmsrl(MSR_GS_BASE
, a
);
5372 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5374 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5375 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5378 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5379 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5380 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5381 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5382 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5384 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5385 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5387 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5388 u32 index
= vmx_msr_index
[i
];
5389 u32 data_low
, data_high
;
5392 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5394 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5396 vmx
->guest_msrs
[j
].index
= i
;
5397 vmx
->guest_msrs
[j
].data
= 0;
5398 vmx
->guest_msrs
[j
].mask
= -1ull;
5403 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5405 /* 22.2.1, 20.8.1 */
5406 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5408 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5409 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5411 set_cr4_guest_host_mask(vmx
);
5413 if (vmx_xsaves_supported())
5414 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5417 ASSERT(vmx
->pml_pg
);
5418 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5419 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5425 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5427 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5428 struct msr_data apic_base_msr
;
5431 vmx
->rmode
.vm86_active
= 0;
5433 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5434 kvm_set_cr8(vcpu
, 0);
5437 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5438 MSR_IA32_APICBASE_ENABLE
;
5439 if (kvm_vcpu_is_reset_bsp(vcpu
))
5440 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5441 apic_base_msr
.host_initiated
= true;
5442 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5445 vmx_segment_cache_clear(vmx
);
5447 seg_setup(VCPU_SREG_CS
);
5448 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5449 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5451 seg_setup(VCPU_SREG_DS
);
5452 seg_setup(VCPU_SREG_ES
);
5453 seg_setup(VCPU_SREG_FS
);
5454 seg_setup(VCPU_SREG_GS
);
5455 seg_setup(VCPU_SREG_SS
);
5457 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5458 vmcs_writel(GUEST_TR_BASE
, 0);
5459 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5460 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5462 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5463 vmcs_writel(GUEST_LDTR_BASE
, 0);
5464 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5465 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5468 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5469 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5470 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5471 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5474 vmcs_writel(GUEST_RFLAGS
, 0x02);
5475 kvm_rip_write(vcpu
, 0xfff0);
5477 vmcs_writel(GUEST_GDTR_BASE
, 0);
5478 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5480 vmcs_writel(GUEST_IDTR_BASE
, 0);
5481 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5483 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5485 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5489 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5491 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5492 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5493 if (cpu_need_tpr_shadow(vcpu
))
5494 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5495 __pa(vcpu
->arch
.apic
->regs
));
5496 vmcs_write32(TPR_THRESHOLD
, 0);
5499 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5501 if (kvm_vcpu_apicv_active(vcpu
))
5502 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5505 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5507 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5508 vmx
->vcpu
.arch
.cr0
= cr0
;
5509 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5510 vmx_set_cr4(vcpu
, 0);
5511 vmx_set_efer(vcpu
, 0);
5513 update_exception_bitmap(vcpu
);
5515 vpid_sync_context(vmx
->vpid
);
5519 * In nested virtualization, check if L1 asked to exit on external interrupts.
5520 * For most existing hypervisors, this will always return true.
5522 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5524 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5525 PIN_BASED_EXT_INTR_MASK
;
5529 * In nested virtualization, check if L1 has set
5530 * VM_EXIT_ACK_INTR_ON_EXIT
5532 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5534 return get_vmcs12(vcpu
)->vm_exit_controls
&
5535 VM_EXIT_ACK_INTR_ON_EXIT
;
5538 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5540 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5541 PIN_BASED_NMI_EXITING
;
5544 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5546 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5547 CPU_BASED_VIRTUAL_INTR_PENDING
);
5550 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5552 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5553 enable_irq_window(vcpu
);
5557 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5558 CPU_BASED_VIRTUAL_NMI_PENDING
);
5561 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5563 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5565 int irq
= vcpu
->arch
.interrupt
.nr
;
5567 trace_kvm_inj_virq(irq
);
5569 ++vcpu
->stat
.irq_injections
;
5570 if (vmx
->rmode
.vm86_active
) {
5572 if (vcpu
->arch
.interrupt
.soft
)
5573 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5574 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5575 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5578 intr
= irq
| INTR_INFO_VALID_MASK
;
5579 if (vcpu
->arch
.interrupt
.soft
) {
5580 intr
|= INTR_TYPE_SOFT_INTR
;
5581 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5582 vmx
->vcpu
.arch
.event_exit_inst_len
);
5584 intr
|= INTR_TYPE_EXT_INTR
;
5585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5588 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5592 ++vcpu
->stat
.nmi_injections
;
5593 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5595 if (vmx
->rmode
.vm86_active
) {
5596 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5597 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5602 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5605 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5610 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5612 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5613 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5617 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5619 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5621 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5623 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5624 GUEST_INTR_STATE_NMI
);
5626 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5627 GUEST_INTR_STATE_NMI
);
5630 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5632 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5635 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5636 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5637 | GUEST_INTR_STATE_NMI
));
5640 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5642 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5643 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5644 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5645 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5648 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5652 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5656 kvm
->arch
.tss_addr
= addr
;
5657 return init_rmode_tss(kvm
);
5660 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5665 * Update instruction length as we may reinject the exception
5666 * from user space while in guest debugging mode.
5668 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5669 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5670 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5674 if (vcpu
->guest_debug
&
5675 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5692 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5693 int vec
, u32 err_code
)
5696 * Instruction with address size override prefix opcode 0x67
5697 * Cause the #SS fault with 0 error code in VM86 mode.
5699 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5700 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5701 if (vcpu
->arch
.halt_request
) {
5702 vcpu
->arch
.halt_request
= 0;
5703 return kvm_vcpu_halt(vcpu
);
5711 * Forward all other exceptions that are valid in real mode.
5712 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5713 * the required debugging infrastructure rework.
5715 kvm_queue_exception(vcpu
, vec
);
5720 * Trigger machine check on the host. We assume all the MSRs are already set up
5721 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5722 * We pass a fake environment to the machine check handler because we want
5723 * the guest to be always treated like user space, no matter what context
5724 * it used internally.
5726 static void kvm_machine_check(void)
5728 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5729 struct pt_regs regs
= {
5730 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5731 .flags
= X86_EFLAGS_IF
,
5734 do_machine_check(®s
, 0);
5738 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5740 /* already handled by vcpu_run */
5744 static int handle_exception(struct kvm_vcpu
*vcpu
)
5746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5747 struct kvm_run
*kvm_run
= vcpu
->run
;
5748 u32 intr_info
, ex_no
, error_code
;
5749 unsigned long cr2
, rip
, dr6
;
5751 enum emulation_result er
;
5753 vect_info
= vmx
->idt_vectoring_info
;
5754 intr_info
= vmx
->exit_intr_info
;
5756 if (is_machine_check(intr_info
))
5757 return handle_machine_check(vcpu
);
5759 if (is_nmi(intr_info
))
5760 return 1; /* already handled by vmx_vcpu_run() */
5762 if (is_invalid_opcode(intr_info
)) {
5763 if (is_guest_mode(vcpu
)) {
5764 kvm_queue_exception(vcpu
, UD_VECTOR
);
5767 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5768 if (er
!= EMULATE_DONE
)
5769 kvm_queue_exception(vcpu
, UD_VECTOR
);
5774 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5775 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5778 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5779 * MMIO, it is better to report an internal error.
5780 * See the comments in vmx_handle_exit.
5782 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5783 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5784 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5785 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5786 vcpu
->run
->internal
.ndata
= 3;
5787 vcpu
->run
->internal
.data
[0] = vect_info
;
5788 vcpu
->run
->internal
.data
[1] = intr_info
;
5789 vcpu
->run
->internal
.data
[2] = error_code
;
5793 if (is_page_fault(intr_info
)) {
5794 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5795 /* EPT won't cause page fault directly */
5796 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5797 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5801 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5803 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5804 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5808 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5811 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5812 if (!(vcpu
->guest_debug
&
5813 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5814 vcpu
->arch
.dr6
&= ~15;
5815 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5816 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5817 skip_emulated_instruction(vcpu
);
5819 kvm_queue_exception(vcpu
, DB_VECTOR
);
5822 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5823 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5827 * Update instruction length as we may reinject #BP from
5828 * user space while in guest debugging mode. Reading it for
5829 * #DB as well causes no harm, it is not used in that case.
5831 vmx
->vcpu
.arch
.event_exit_inst_len
=
5832 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5833 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5834 rip
= kvm_rip_read(vcpu
);
5835 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5836 kvm_run
->debug
.arch
.exception
= ex_no
;
5839 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5840 kvm_run
->ex
.exception
= ex_no
;
5841 kvm_run
->ex
.error_code
= error_code
;
5847 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5849 ++vcpu
->stat
.irq_exits
;
5853 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5855 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5859 static int handle_io(struct kvm_vcpu
*vcpu
)
5861 unsigned long exit_qualification
;
5862 int size
, in
, string
, ret
;
5865 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5866 string
= (exit_qualification
& 16) != 0;
5867 in
= (exit_qualification
& 8) != 0;
5869 ++vcpu
->stat
.io_exits
;
5872 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5874 port
= exit_qualification
>> 16;
5875 size
= (exit_qualification
& 7) + 1;
5877 ret
= kvm_skip_emulated_instruction(vcpu
);
5880 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5881 * KVM_EXIT_DEBUG here.
5883 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5887 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5890 * Patch in the VMCALL instruction:
5892 hypercall
[0] = 0x0f;
5893 hypercall
[1] = 0x01;
5894 hypercall
[2] = 0xc1;
5897 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5898 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5900 if (is_guest_mode(vcpu
)) {
5901 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5902 unsigned long orig_val
= val
;
5905 * We get here when L2 changed cr0 in a way that did not change
5906 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5907 * but did change L0 shadowed bits. So we first calculate the
5908 * effective cr0 value that L1 would like to write into the
5909 * hardware. It consists of the L2-owned bits from the new
5910 * value combined with the L1-owned bits from L1's guest_cr0.
5912 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5913 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5915 if (!nested_guest_cr0_valid(vcpu
, val
))
5918 if (kvm_set_cr0(vcpu
, val
))
5920 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5923 if (to_vmx(vcpu
)->nested
.vmxon
&&
5924 !nested_host_cr0_valid(vcpu
, val
))
5927 return kvm_set_cr0(vcpu
, val
);
5931 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5933 if (is_guest_mode(vcpu
)) {
5934 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5935 unsigned long orig_val
= val
;
5937 /* analogously to handle_set_cr0 */
5938 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5939 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5940 if (kvm_set_cr4(vcpu
, val
))
5942 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5945 return kvm_set_cr4(vcpu
, val
);
5948 static int handle_cr(struct kvm_vcpu
*vcpu
)
5950 unsigned long exit_qualification
, val
;
5956 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5957 cr
= exit_qualification
& 15;
5958 reg
= (exit_qualification
>> 8) & 15;
5959 switch ((exit_qualification
>> 4) & 3) {
5960 case 0: /* mov to cr */
5961 val
= kvm_register_readl(vcpu
, reg
);
5962 trace_kvm_cr_write(cr
, val
);
5965 err
= handle_set_cr0(vcpu
, val
);
5966 return kvm_complete_insn_gp(vcpu
, err
);
5968 err
= kvm_set_cr3(vcpu
, val
);
5969 return kvm_complete_insn_gp(vcpu
, err
);
5971 err
= handle_set_cr4(vcpu
, val
);
5972 return kvm_complete_insn_gp(vcpu
, err
);
5974 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5976 err
= kvm_set_cr8(vcpu
, cr8
);
5977 ret
= kvm_complete_insn_gp(vcpu
, err
);
5978 if (lapic_in_kernel(vcpu
))
5980 if (cr8_prev
<= cr8
)
5983 * TODO: we might be squashing a
5984 * KVM_GUESTDBG_SINGLESTEP-triggered
5985 * KVM_EXIT_DEBUG here.
5987 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5993 WARN_ONCE(1, "Guest should always own CR0.TS");
5994 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5995 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5996 return kvm_skip_emulated_instruction(vcpu
);
5997 case 1: /*mov from cr*/
6000 val
= kvm_read_cr3(vcpu
);
6001 kvm_register_write(vcpu
, reg
, val
);
6002 trace_kvm_cr_read(cr
, val
);
6003 return kvm_skip_emulated_instruction(vcpu
);
6005 val
= kvm_get_cr8(vcpu
);
6006 kvm_register_write(vcpu
, reg
, val
);
6007 trace_kvm_cr_read(cr
, val
);
6008 return kvm_skip_emulated_instruction(vcpu
);
6012 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6013 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6014 kvm_lmsw(vcpu
, val
);
6016 return kvm_skip_emulated_instruction(vcpu
);
6020 vcpu
->run
->exit_reason
= 0;
6021 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6022 (int)(exit_qualification
>> 4) & 3, cr
);
6026 static int handle_dr(struct kvm_vcpu
*vcpu
)
6028 unsigned long exit_qualification
;
6031 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6032 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6034 /* First, if DR does not exist, trigger UD */
6035 if (!kvm_require_dr(vcpu
, dr
))
6038 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6039 if (!kvm_require_cpl(vcpu
, 0))
6041 dr7
= vmcs_readl(GUEST_DR7
);
6044 * As the vm-exit takes precedence over the debug trap, we
6045 * need to emulate the latter, either for the host or the
6046 * guest debugging itself.
6048 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6049 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6050 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6051 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6052 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6053 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6056 vcpu
->arch
.dr6
&= ~15;
6057 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6058 kvm_queue_exception(vcpu
, DB_VECTOR
);
6063 if (vcpu
->guest_debug
== 0) {
6064 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6065 CPU_BASED_MOV_DR_EXITING
);
6068 * No more DR vmexits; force a reload of the debug registers
6069 * and reenter on this instruction. The next vmexit will
6070 * retrieve the full state of the debug registers.
6072 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6076 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6077 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6080 if (kvm_get_dr(vcpu
, dr
, &val
))
6082 kvm_register_write(vcpu
, reg
, val
);
6084 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6087 return kvm_skip_emulated_instruction(vcpu
);
6090 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6092 return vcpu
->arch
.dr6
;
6095 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6099 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6101 get_debugreg(vcpu
->arch
.db
[0], 0);
6102 get_debugreg(vcpu
->arch
.db
[1], 1);
6103 get_debugreg(vcpu
->arch
.db
[2], 2);
6104 get_debugreg(vcpu
->arch
.db
[3], 3);
6105 get_debugreg(vcpu
->arch
.dr6
, 6);
6106 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6108 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6109 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6112 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6114 vmcs_writel(GUEST_DR7
, val
);
6117 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6119 return kvm_emulate_cpuid(vcpu
);
6122 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6124 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6125 struct msr_data msr_info
;
6127 msr_info
.index
= ecx
;
6128 msr_info
.host_initiated
= false;
6130 if (vmx_get_msr(vcpu
, &msr_info
)) {
6131 trace_kvm_msr_read_ex(ecx
);
6132 kvm_inject_gp(vcpu
, 0);
6136 trace_kvm_msr_read(ecx
, msr_info
.data
);
6138 /* FIXME: handling of bits 32:63 of rax, rdx */
6139 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6140 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6141 return kvm_skip_emulated_instruction(vcpu
);
6144 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6146 struct msr_data msr
;
6147 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6148 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6149 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6153 msr
.host_initiated
= false;
6154 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6155 trace_kvm_msr_write_ex(ecx
, data
);
6156 kvm_inject_gp(vcpu
, 0);
6160 trace_kvm_msr_write(ecx
, data
);
6161 return kvm_skip_emulated_instruction(vcpu
);
6164 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6166 kvm_apic_update_ppr(vcpu
);
6170 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6172 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6173 CPU_BASED_VIRTUAL_INTR_PENDING
);
6175 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6177 ++vcpu
->stat
.irq_window_exits
;
6181 static int handle_halt(struct kvm_vcpu
*vcpu
)
6183 return kvm_emulate_halt(vcpu
);
6186 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6188 return kvm_emulate_hypercall(vcpu
);
6191 static int handle_invd(struct kvm_vcpu
*vcpu
)
6193 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6196 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6198 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6200 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6201 return kvm_skip_emulated_instruction(vcpu
);
6204 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6208 err
= kvm_rdpmc(vcpu
);
6209 return kvm_complete_insn_gp(vcpu
, err
);
6212 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6214 return kvm_emulate_wbinvd(vcpu
);
6217 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6219 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6220 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6222 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6223 return kvm_skip_emulated_instruction(vcpu
);
6227 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6229 kvm_skip_emulated_instruction(vcpu
);
6230 WARN(1, "this should never happen\n");
6234 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6236 kvm_skip_emulated_instruction(vcpu
);
6237 WARN(1, "this should never happen\n");
6241 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6243 if (likely(fasteoi
)) {
6244 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6245 int access_type
, offset
;
6247 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6248 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6250 * Sane guest uses MOV to write EOI, with written value
6251 * not cared. So make a short-circuit here by avoiding
6252 * heavy instruction emulation.
6254 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6255 (offset
== APIC_EOI
)) {
6256 kvm_lapic_set_eoi(vcpu
);
6257 return kvm_skip_emulated_instruction(vcpu
);
6260 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6263 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6265 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6266 int vector
= exit_qualification
& 0xff;
6268 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6269 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6273 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6275 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6276 u32 offset
= exit_qualification
& 0xfff;
6278 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6279 kvm_apic_write_nodecode(vcpu
, offset
);
6283 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6286 unsigned long exit_qualification
;
6287 bool has_error_code
= false;
6290 int reason
, type
, idt_v
, idt_index
;
6292 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6293 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6294 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6296 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6298 reason
= (u32
)exit_qualification
>> 30;
6299 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6301 case INTR_TYPE_NMI_INTR
:
6302 vcpu
->arch
.nmi_injected
= false;
6303 vmx_set_nmi_mask(vcpu
, true);
6305 case INTR_TYPE_EXT_INTR
:
6306 case INTR_TYPE_SOFT_INTR
:
6307 kvm_clear_interrupt_queue(vcpu
);
6309 case INTR_TYPE_HARD_EXCEPTION
:
6310 if (vmx
->idt_vectoring_info
&
6311 VECTORING_INFO_DELIVER_CODE_MASK
) {
6312 has_error_code
= true;
6314 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6317 case INTR_TYPE_SOFT_EXCEPTION
:
6318 kvm_clear_exception_queue(vcpu
);
6324 tss_selector
= exit_qualification
;
6326 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6327 type
!= INTR_TYPE_EXT_INTR
&&
6328 type
!= INTR_TYPE_NMI_INTR
))
6329 skip_emulated_instruction(vcpu
);
6331 if (kvm_task_switch(vcpu
, tss_selector
,
6332 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6333 has_error_code
, error_code
) == EMULATE_FAIL
) {
6334 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6335 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6336 vcpu
->run
->internal
.ndata
= 0;
6341 * TODO: What about debug traps on tss switch?
6342 * Are we supposed to inject them and update dr6?
6348 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6350 unsigned long exit_qualification
;
6354 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6357 * EPT violation happened while executing iret from NMI,
6358 * "blocked by NMI" bit has to be set before next VM entry.
6359 * There are errata that may cause this bit to not be set:
6362 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6363 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6364 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6366 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6367 trace_kvm_page_fault(gpa
, exit_qualification
);
6369 /* Is it a read fault? */
6370 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6371 ? PFERR_USER_MASK
: 0;
6372 /* Is it a write fault? */
6373 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6374 ? PFERR_WRITE_MASK
: 0;
6375 /* Is it a fetch fault? */
6376 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6377 ? PFERR_FETCH_MASK
: 0;
6378 /* ept page table entry is present? */
6379 error_code
|= (exit_qualification
&
6380 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6381 EPT_VIOLATION_EXECUTABLE
))
6382 ? PFERR_PRESENT_MASK
: 0;
6384 vcpu
->arch
.gpa_available
= true;
6385 vcpu
->arch
.exit_qualification
= exit_qualification
;
6387 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6390 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6395 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6396 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6397 trace_kvm_fast_mmio(gpa
);
6398 return kvm_skip_emulated_instruction(vcpu
);
6401 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6402 vcpu
->arch
.gpa_available
= true;
6403 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6404 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6407 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6408 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6410 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6413 /* It is the real ept misconfig */
6416 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6417 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6422 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6424 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6425 CPU_BASED_VIRTUAL_NMI_PENDING
);
6426 ++vcpu
->stat
.nmi_window_exits
;
6427 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6432 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6434 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6435 enum emulation_result err
= EMULATE_DONE
;
6438 bool intr_window_requested
;
6439 unsigned count
= 130;
6441 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6442 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6444 while (vmx
->emulation_required
&& count
-- != 0) {
6445 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6446 return handle_interrupt_window(&vmx
->vcpu
);
6448 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6451 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6453 if (err
== EMULATE_USER_EXIT
) {
6454 ++vcpu
->stat
.mmio_exits
;
6459 if (err
!= EMULATE_DONE
) {
6460 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6461 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6462 vcpu
->run
->internal
.ndata
= 0;
6466 if (vcpu
->arch
.halt_request
) {
6467 vcpu
->arch
.halt_request
= 0;
6468 ret
= kvm_vcpu_halt(vcpu
);
6472 if (signal_pending(current
))
6482 static int __grow_ple_window(int val
)
6484 if (ple_window_grow
< 1)
6487 val
= min(val
, ple_window_actual_max
);
6489 if (ple_window_grow
< ple_window
)
6490 val
*= ple_window_grow
;
6492 val
+= ple_window_grow
;
6497 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6502 if (modifier
< ple_window
)
6507 return max(val
, minimum
);
6510 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6512 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6513 int old
= vmx
->ple_window
;
6515 vmx
->ple_window
= __grow_ple_window(old
);
6517 if (vmx
->ple_window
!= old
)
6518 vmx
->ple_window_dirty
= true;
6520 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6523 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6525 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6526 int old
= vmx
->ple_window
;
6528 vmx
->ple_window
= __shrink_ple_window(old
,
6529 ple_window_shrink
, ple_window
);
6531 if (vmx
->ple_window
!= old
)
6532 vmx
->ple_window_dirty
= true;
6534 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6538 * ple_window_actual_max is computed to be one grow_ple_window() below
6539 * ple_window_max. (See __grow_ple_window for the reason.)
6540 * This prevents overflows, because ple_window_max is int.
6541 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6543 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6545 static void update_ple_window_actual_max(void)
6547 ple_window_actual_max
=
6548 __shrink_ple_window(max(ple_window_max
, ple_window
),
6549 ple_window_grow
, INT_MIN
);
6553 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6555 static void wakeup_handler(void)
6557 struct kvm_vcpu
*vcpu
;
6558 int cpu
= smp_processor_id();
6560 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6561 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6562 blocked_vcpu_list
) {
6563 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6565 if (pi_test_on(pi_desc
) == 1)
6566 kvm_vcpu_kick(vcpu
);
6568 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6571 void vmx_enable_tdp(void)
6573 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6574 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6575 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6576 0ull, VMX_EPT_EXECUTABLE_MASK
,
6577 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6580 ept_set_mmio_spte_mask();
6584 static __init
int hardware_setup(void)
6586 int r
= -ENOMEM
, i
, msr
;
6588 rdmsrl_safe(MSR_EFER
, &host_efer
);
6590 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6591 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6593 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6594 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6599 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6600 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6601 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6604 * Allow direct access to the PC debug port (it is often used for I/O
6605 * delays, but the vmexits simply slow things down).
6607 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6608 clear_bit(0x80, vmx_io_bitmap_a
);
6610 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6612 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6613 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6615 if (setup_vmcs_config(&vmcs_config
) < 0) {
6620 if (boot_cpu_has(X86_FEATURE_NX
))
6621 kvm_enable_efer_bits(EFER_NX
);
6623 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6624 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6627 if (!cpu_has_vmx_shadow_vmcs())
6628 enable_shadow_vmcs
= 0;
6629 if (enable_shadow_vmcs
)
6630 init_vmcs_shadow_fields();
6632 if (!cpu_has_vmx_ept() ||
6633 !cpu_has_vmx_ept_4levels()) {
6635 enable_unrestricted_guest
= 0;
6636 enable_ept_ad_bits
= 0;
6639 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6640 enable_ept_ad_bits
= 0;
6642 if (!cpu_has_vmx_unrestricted_guest())
6643 enable_unrestricted_guest
= 0;
6645 if (!cpu_has_vmx_flexpriority())
6646 flexpriority_enabled
= 0;
6649 * set_apic_access_page_addr() is used to reload apic access
6650 * page upon invalidation. No need to do anything if not
6651 * using the APIC_ACCESS_ADDR VMCS field.
6653 if (!flexpriority_enabled
)
6654 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6656 if (!cpu_has_vmx_tpr_shadow())
6657 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6659 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6660 kvm_disable_largepages();
6662 if (!cpu_has_vmx_ple())
6665 if (!cpu_has_vmx_apicv()) {
6667 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6670 if (cpu_has_vmx_tsc_scaling()) {
6671 kvm_has_tsc_control
= true;
6672 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6673 kvm_tsc_scaling_ratio_frac_bits
= 48;
6676 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6677 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6678 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6679 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6680 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6681 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6682 vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL
, false);
6683 vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD
, false);
6685 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6686 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6687 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6688 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6689 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6690 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6691 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6692 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6694 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6696 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6697 if (msr
== 0x839 /* TMCCT */)
6699 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6703 * TPR reads and writes can be virtualized even if virtual interrupt
6704 * delivery is not in use.
6706 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6707 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6710 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6712 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6719 update_ple_window_actual_max();
6722 * Only enable PML when hardware supports PML feature, and both EPT
6723 * and EPT A/D bit features are enabled -- PML depends on them to work.
6725 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6729 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6730 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6731 kvm_x86_ops
->flush_log_dirty
= NULL
;
6732 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6735 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6738 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6739 cpu_preemption_timer_multi
=
6740 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6742 kvm_x86_ops
->set_hv_timer
= NULL
;
6743 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6746 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6748 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6750 return alloc_kvm_area();
6753 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6754 free_page((unsigned long)vmx_bitmap
[i
]);
6759 static __exit
void hardware_unsetup(void)
6763 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6764 free_page((unsigned long)vmx_bitmap
[i
]);
6770 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6771 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6773 static int handle_pause(struct kvm_vcpu
*vcpu
)
6776 grow_ple_window(vcpu
);
6778 kvm_vcpu_on_spin(vcpu
);
6779 return kvm_skip_emulated_instruction(vcpu
);
6782 static int handle_nop(struct kvm_vcpu
*vcpu
)
6784 return kvm_skip_emulated_instruction(vcpu
);
6787 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6789 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6790 return handle_nop(vcpu
);
6793 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6798 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6800 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6801 return handle_nop(vcpu
);
6805 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6806 * We could reuse a single VMCS for all the L2 guests, but we also want the
6807 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6808 * allows keeping them loaded on the processor, and in the future will allow
6809 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6810 * every entry if they never change.
6811 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6812 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6814 * The following functions allocate and free a vmcs02 in this pool.
6817 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6818 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6820 struct vmcs02_list
*item
;
6821 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6822 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6823 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6824 return &item
->vmcs02
;
6827 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6828 /* Recycle the least recently used VMCS. */
6829 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6830 struct vmcs02_list
, list
);
6831 item
->vmptr
= vmx
->nested
.current_vmptr
;
6832 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6833 return &item
->vmcs02
;
6836 /* Create a new VMCS */
6837 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6840 item
->vmcs02
.vmcs
= alloc_vmcs();
6841 item
->vmcs02
.shadow_vmcs
= NULL
;
6842 if (!item
->vmcs02
.vmcs
) {
6846 loaded_vmcs_init(&item
->vmcs02
);
6847 item
->vmptr
= vmx
->nested
.current_vmptr
;
6848 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6849 vmx
->nested
.vmcs02_num
++;
6850 return &item
->vmcs02
;
6853 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6854 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6856 struct vmcs02_list
*item
;
6857 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6858 if (item
->vmptr
== vmptr
) {
6859 free_loaded_vmcs(&item
->vmcs02
);
6860 list_del(&item
->list
);
6862 vmx
->nested
.vmcs02_num
--;
6868 * Free all VMCSs saved for this vcpu, except the one pointed by
6869 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6870 * must be &vmx->vmcs01.
6872 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6874 struct vmcs02_list
*item
, *n
;
6876 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6877 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6879 * Something will leak if the above WARN triggers. Better than
6882 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6885 free_loaded_vmcs(&item
->vmcs02
);
6886 list_del(&item
->list
);
6888 vmx
->nested
.vmcs02_num
--;
6893 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6894 * set the success or error code of an emulated VMX instruction, as specified
6895 * by Vol 2B, VMX Instruction Reference, "Conventions".
6897 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6899 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6900 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6901 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6904 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6906 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6907 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6908 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6912 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6913 u32 vm_instruction_error
)
6915 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6917 * failValid writes the error number to the current VMCS, which
6918 * can't be done there isn't a current VMCS.
6920 nested_vmx_failInvalid(vcpu
);
6923 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6924 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6925 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6927 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6929 * We don't need to force a shadow sync because
6930 * VM_INSTRUCTION_ERROR is not shadowed
6934 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6936 /* TODO: not to reset guest simply here. */
6937 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6938 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6941 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6943 struct vcpu_vmx
*vmx
=
6944 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6946 vmx
->nested
.preemption_timer_expired
= true;
6947 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6948 kvm_vcpu_kick(&vmx
->vcpu
);
6950 return HRTIMER_NORESTART
;
6954 * Decode the memory-address operand of a vmx instruction, as recorded on an
6955 * exit caused by such an instruction (run by a guest hypervisor).
6956 * On success, returns 0. When the operand is invalid, returns 1 and throws
6959 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6960 unsigned long exit_qualification
,
6961 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6965 struct kvm_segment s
;
6968 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6969 * Execution", on an exit, vmx_instruction_info holds most of the
6970 * addressing components of the operand. Only the displacement part
6971 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6972 * For how an actual address is calculated from all these components,
6973 * refer to Vol. 1, "Operand Addressing".
6975 int scaling
= vmx_instruction_info
& 3;
6976 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6977 bool is_reg
= vmx_instruction_info
& (1u << 10);
6978 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6979 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6980 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6981 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6982 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6985 kvm_queue_exception(vcpu
, UD_VECTOR
);
6989 /* Addr = segment_base + offset */
6990 /* offset = base + [index * scale] + displacement */
6991 off
= exit_qualification
; /* holds the displacement */
6993 off
+= kvm_register_read(vcpu
, base_reg
);
6995 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6996 vmx_get_segment(vcpu
, &s
, seg_reg
);
6997 *ret
= s
.base
+ off
;
6999 if (addr_size
== 1) /* 32 bit */
7002 /* Checks for #GP/#SS exceptions. */
7004 if (is_long_mode(vcpu
)) {
7005 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7006 * non-canonical form. This is the only check on the memory
7007 * destination for long mode!
7009 exn
= is_noncanonical_address(*ret
);
7010 } else if (is_protmode(vcpu
)) {
7011 /* Protected mode: apply checks for segment validity in the
7013 * - segment type check (#GP(0) may be thrown)
7014 * - usability check (#GP(0)/#SS(0))
7015 * - limit check (#GP(0)/#SS(0))
7018 /* #GP(0) if the destination operand is located in a
7019 * read-only data segment or any code segment.
7021 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7023 /* #GP(0) if the source operand is located in an
7024 * execute-only code segment
7026 exn
= ((s
.type
& 0xa) == 8);
7028 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7031 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7033 exn
= (s
.unusable
!= 0);
7034 /* Protected mode: #GP(0)/#SS(0) if the memory
7035 * operand is outside the segment limit.
7037 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7040 kvm_queue_exception_e(vcpu
,
7041 seg_reg
== VCPU_SREG_SS
?
7042 SS_VECTOR
: GP_VECTOR
,
7050 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7053 struct x86_exception e
;
7055 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7056 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7059 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7060 sizeof(*vmpointer
), &e
)) {
7061 kvm_inject_page_fault(vcpu
, &e
);
7068 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7070 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7071 struct vmcs
*shadow_vmcs
;
7073 if (cpu_has_vmx_msr_bitmap()) {
7074 vmx
->nested
.msr_bitmap
=
7075 (unsigned long *)__get_free_page(GFP_KERNEL
);
7076 if (!vmx
->nested
.msr_bitmap
)
7077 goto out_msr_bitmap
;
7080 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7081 if (!vmx
->nested
.cached_vmcs12
)
7082 goto out_cached_vmcs12
;
7084 if (enable_shadow_vmcs
) {
7085 shadow_vmcs
= alloc_vmcs();
7087 goto out_shadow_vmcs
;
7088 /* mark vmcs as shadow */
7089 shadow_vmcs
->revision_id
|= (1u << 31);
7090 /* init shadow vmcs */
7091 vmcs_clear(shadow_vmcs
);
7092 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7095 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7096 vmx
->nested
.vmcs02_num
= 0;
7098 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7099 HRTIMER_MODE_REL_PINNED
);
7100 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7102 vmx
->nested
.vmxon
= true;
7106 kfree(vmx
->nested
.cached_vmcs12
);
7109 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7116 * Emulate the VMXON instruction.
7117 * Currently, we just remember that VMX is active, and do not save or even
7118 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7119 * do not currently need to store anything in that guest-allocated memory
7120 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7121 * argument is different from the VMXON pointer (which the spec says they do).
7123 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7129 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7130 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7133 * The Intel VMX Instruction Reference lists a bunch of bits that are
7134 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7135 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7136 * Otherwise, we should fail with #UD. But most faulting conditions
7137 * have already been checked by hardware, prior to the VM-exit for
7138 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7139 * that bit set to 1 in non-root mode.
7141 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7142 kvm_queue_exception(vcpu
, UD_VECTOR
);
7146 if (vmx
->nested
.vmxon
) {
7147 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7148 return kvm_skip_emulated_instruction(vcpu
);
7151 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7152 != VMXON_NEEDED_FEATURES
) {
7153 kvm_inject_gp(vcpu
, 0);
7157 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7162 * The first 4 bytes of VMXON region contain the supported
7163 * VMCS revision identifier
7165 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7166 * which replaces physical address width with 32
7168 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7169 nested_vmx_failInvalid(vcpu
);
7170 return kvm_skip_emulated_instruction(vcpu
);
7173 page
= nested_get_page(vcpu
, vmptr
);
7175 nested_vmx_failInvalid(vcpu
);
7176 return kvm_skip_emulated_instruction(vcpu
);
7178 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7180 nested_release_page_clean(page
);
7181 nested_vmx_failInvalid(vcpu
);
7182 return kvm_skip_emulated_instruction(vcpu
);
7185 nested_release_page_clean(page
);
7187 vmx
->nested
.vmxon_ptr
= vmptr
;
7188 ret
= enter_vmx_operation(vcpu
);
7192 nested_vmx_succeed(vcpu
);
7193 return kvm_skip_emulated_instruction(vcpu
);
7197 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7198 * for running VMX instructions (except VMXON, whose prerequisites are
7199 * slightly different). It also specifies what exception to inject otherwise.
7200 * Note that many of these exceptions have priority over VM exits, so they
7201 * don't have to be checked again here.
7203 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7205 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7206 kvm_queue_exception(vcpu
, UD_VECTOR
);
7212 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7214 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7215 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7218 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7220 if (vmx
->nested
.current_vmptr
== -1ull)
7223 if (enable_shadow_vmcs
) {
7224 /* copy to memory all shadowed fields in case
7225 they were modified */
7226 copy_shadow_to_vmcs12(vmx
);
7227 vmx
->nested
.sync_shadow_vmcs
= false;
7228 vmx_disable_shadow_vmcs(vmx
);
7230 vmx
->nested
.posted_intr_nv
= -1;
7232 /* Flush VMCS12 to guest memory */
7233 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7234 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7235 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7237 vmx
->nested
.current_vmptr
= -1ull;
7241 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7242 * just stops using VMX.
7244 static void free_nested(struct vcpu_vmx
*vmx
)
7246 if (!vmx
->nested
.vmxon
)
7249 vmx
->nested
.vmxon
= false;
7250 free_vpid(vmx
->nested
.vpid02
);
7251 vmx
->nested
.posted_intr_nv
= -1;
7252 vmx
->nested
.current_vmptr
= -1ull;
7253 if (vmx
->nested
.msr_bitmap
) {
7254 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7255 vmx
->nested
.msr_bitmap
= NULL
;
7257 if (enable_shadow_vmcs
) {
7258 vmx_disable_shadow_vmcs(vmx
);
7259 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7260 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7261 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7263 kfree(vmx
->nested
.cached_vmcs12
);
7264 /* Unpin physical memory we referred to in current vmcs02 */
7265 if (vmx
->nested
.apic_access_page
) {
7266 nested_release_page(vmx
->nested
.apic_access_page
);
7267 vmx
->nested
.apic_access_page
= NULL
;
7269 if (vmx
->nested
.virtual_apic_page
) {
7270 nested_release_page(vmx
->nested
.virtual_apic_page
);
7271 vmx
->nested
.virtual_apic_page
= NULL
;
7273 if (vmx
->nested
.pi_desc_page
) {
7274 kunmap(vmx
->nested
.pi_desc_page
);
7275 nested_release_page(vmx
->nested
.pi_desc_page
);
7276 vmx
->nested
.pi_desc_page
= NULL
;
7277 vmx
->nested
.pi_desc
= NULL
;
7280 nested_free_all_saved_vmcss(vmx
);
7283 /* Emulate the VMXOFF instruction */
7284 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7286 if (!nested_vmx_check_permission(vcpu
))
7288 free_nested(to_vmx(vcpu
));
7289 nested_vmx_succeed(vcpu
);
7290 return kvm_skip_emulated_instruction(vcpu
);
7293 /* Emulate the VMCLEAR instruction */
7294 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7300 if (!nested_vmx_check_permission(vcpu
))
7303 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7306 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7307 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7308 return kvm_skip_emulated_instruction(vcpu
);
7311 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7312 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7313 return kvm_skip_emulated_instruction(vcpu
);
7316 if (vmptr
== vmx
->nested
.current_vmptr
)
7317 nested_release_vmcs12(vmx
);
7319 kvm_vcpu_write_guest(vcpu
,
7320 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7321 &zero
, sizeof(zero
));
7323 nested_free_vmcs02(vmx
, vmptr
);
7325 nested_vmx_succeed(vcpu
);
7326 return kvm_skip_emulated_instruction(vcpu
);
7329 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7331 /* Emulate the VMLAUNCH instruction */
7332 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7334 return nested_vmx_run(vcpu
, true);
7337 /* Emulate the VMRESUME instruction */
7338 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7341 return nested_vmx_run(vcpu
, false);
7345 * Read a vmcs12 field. Since these can have varying lengths and we return
7346 * one type, we chose the biggest type (u64) and zero-extend the return value
7347 * to that size. Note that the caller, handle_vmread, might need to use only
7348 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7349 * 64-bit fields are to be returned).
7351 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7352 unsigned long field
, u64
*ret
)
7354 short offset
= vmcs_field_to_offset(field
);
7360 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7362 switch (vmcs_field_type(field
)) {
7363 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7364 *ret
= *((natural_width
*)p
);
7366 case VMCS_FIELD_TYPE_U16
:
7369 case VMCS_FIELD_TYPE_U32
:
7372 case VMCS_FIELD_TYPE_U64
:
7382 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7383 unsigned long field
, u64 field_value
){
7384 short offset
= vmcs_field_to_offset(field
);
7385 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7389 switch (vmcs_field_type(field
)) {
7390 case VMCS_FIELD_TYPE_U16
:
7391 *(u16
*)p
= field_value
;
7393 case VMCS_FIELD_TYPE_U32
:
7394 *(u32
*)p
= field_value
;
7396 case VMCS_FIELD_TYPE_U64
:
7397 *(u64
*)p
= field_value
;
7399 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7400 *(natural_width
*)p
= field_value
;
7409 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7412 unsigned long field
;
7414 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7415 const unsigned long *fields
= shadow_read_write_fields
;
7416 const int num_fields
= max_shadow_read_write_fields
;
7420 vmcs_load(shadow_vmcs
);
7422 for (i
= 0; i
< num_fields
; i
++) {
7424 switch (vmcs_field_type(field
)) {
7425 case VMCS_FIELD_TYPE_U16
:
7426 field_value
= vmcs_read16(field
);
7428 case VMCS_FIELD_TYPE_U32
:
7429 field_value
= vmcs_read32(field
);
7431 case VMCS_FIELD_TYPE_U64
:
7432 field_value
= vmcs_read64(field
);
7434 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7435 field_value
= vmcs_readl(field
);
7441 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7444 vmcs_clear(shadow_vmcs
);
7445 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7450 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7452 const unsigned long *fields
[] = {
7453 shadow_read_write_fields
,
7454 shadow_read_only_fields
7456 const int max_fields
[] = {
7457 max_shadow_read_write_fields
,
7458 max_shadow_read_only_fields
7461 unsigned long field
;
7462 u64 field_value
= 0;
7463 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7465 vmcs_load(shadow_vmcs
);
7467 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7468 for (i
= 0; i
< max_fields
[q
]; i
++) {
7469 field
= fields
[q
][i
];
7470 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7472 switch (vmcs_field_type(field
)) {
7473 case VMCS_FIELD_TYPE_U16
:
7474 vmcs_write16(field
, (u16
)field_value
);
7476 case VMCS_FIELD_TYPE_U32
:
7477 vmcs_write32(field
, (u32
)field_value
);
7479 case VMCS_FIELD_TYPE_U64
:
7480 vmcs_write64(field
, (u64
)field_value
);
7482 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7483 vmcs_writel(field
, (long)field_value
);
7492 vmcs_clear(shadow_vmcs
);
7493 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7497 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7498 * used before) all generate the same failure when it is missing.
7500 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7503 if (vmx
->nested
.current_vmptr
== -1ull) {
7504 nested_vmx_failInvalid(vcpu
);
7510 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7512 unsigned long field
;
7514 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7515 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7518 if (!nested_vmx_check_permission(vcpu
))
7521 if (!nested_vmx_check_vmcs12(vcpu
))
7522 return kvm_skip_emulated_instruction(vcpu
);
7524 /* Decode instruction info and find the field to read */
7525 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7526 /* Read the field, zero-extended to a u64 field_value */
7527 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7528 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7529 return kvm_skip_emulated_instruction(vcpu
);
7532 * Now copy part of this value to register or memory, as requested.
7533 * Note that the number of bits actually copied is 32 or 64 depending
7534 * on the guest's mode (32 or 64 bit), not on the given field's length.
7536 if (vmx_instruction_info
& (1u << 10)) {
7537 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7540 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7541 vmx_instruction_info
, true, &gva
))
7543 /* _system ok, as hardware has verified cpl=0 */
7544 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7545 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7548 nested_vmx_succeed(vcpu
);
7549 return kvm_skip_emulated_instruction(vcpu
);
7553 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7555 unsigned long field
;
7557 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7558 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7559 /* The value to write might be 32 or 64 bits, depending on L1's long
7560 * mode, and eventually we need to write that into a field of several
7561 * possible lengths. The code below first zero-extends the value to 64
7562 * bit (field_value), and then copies only the appropriate number of
7563 * bits into the vmcs12 field.
7565 u64 field_value
= 0;
7566 struct x86_exception e
;
7568 if (!nested_vmx_check_permission(vcpu
))
7571 if (!nested_vmx_check_vmcs12(vcpu
))
7572 return kvm_skip_emulated_instruction(vcpu
);
7574 if (vmx_instruction_info
& (1u << 10))
7575 field_value
= kvm_register_readl(vcpu
,
7576 (((vmx_instruction_info
) >> 3) & 0xf));
7578 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7579 vmx_instruction_info
, false, &gva
))
7581 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7582 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7583 kvm_inject_page_fault(vcpu
, &e
);
7589 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7590 if (vmcs_field_readonly(field
)) {
7591 nested_vmx_failValid(vcpu
,
7592 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7593 return kvm_skip_emulated_instruction(vcpu
);
7596 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7597 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7598 return kvm_skip_emulated_instruction(vcpu
);
7601 nested_vmx_succeed(vcpu
);
7602 return kvm_skip_emulated_instruction(vcpu
);
7605 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7607 vmx
->nested
.current_vmptr
= vmptr
;
7608 if (enable_shadow_vmcs
) {
7609 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7610 SECONDARY_EXEC_SHADOW_VMCS
);
7611 vmcs_write64(VMCS_LINK_POINTER
,
7612 __pa(vmx
->vmcs01
.shadow_vmcs
));
7613 vmx
->nested
.sync_shadow_vmcs
= true;
7617 /* Emulate the VMPTRLD instruction */
7618 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7620 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7623 if (!nested_vmx_check_permission(vcpu
))
7626 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7629 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7630 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7631 return kvm_skip_emulated_instruction(vcpu
);
7634 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7635 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7636 return kvm_skip_emulated_instruction(vcpu
);
7639 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7640 struct vmcs12
*new_vmcs12
;
7642 page
= nested_get_page(vcpu
, vmptr
);
7644 nested_vmx_failInvalid(vcpu
);
7645 return kvm_skip_emulated_instruction(vcpu
);
7647 new_vmcs12
= kmap(page
);
7648 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7650 nested_release_page_clean(page
);
7651 nested_vmx_failValid(vcpu
,
7652 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7653 return kvm_skip_emulated_instruction(vcpu
);
7656 nested_release_vmcs12(vmx
);
7658 * Load VMCS12 from guest memory since it is not already
7661 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7663 nested_release_page_clean(page
);
7665 set_current_vmptr(vmx
, vmptr
);
7668 nested_vmx_succeed(vcpu
);
7669 return kvm_skip_emulated_instruction(vcpu
);
7672 /* Emulate the VMPTRST instruction */
7673 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7675 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7676 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7678 struct x86_exception e
;
7680 if (!nested_vmx_check_permission(vcpu
))
7683 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7684 vmx_instruction_info
, true, &vmcs_gva
))
7686 /* ok to use *_system, as hardware has verified cpl=0 */
7687 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7688 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7690 kvm_inject_page_fault(vcpu
, &e
);
7693 nested_vmx_succeed(vcpu
);
7694 return kvm_skip_emulated_instruction(vcpu
);
7697 /* Emulate the INVEPT instruction */
7698 static int handle_invept(struct kvm_vcpu
*vcpu
)
7700 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7701 u32 vmx_instruction_info
, types
;
7704 struct x86_exception e
;
7709 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7710 SECONDARY_EXEC_ENABLE_EPT
) ||
7711 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7712 kvm_queue_exception(vcpu
, UD_VECTOR
);
7716 if (!nested_vmx_check_permission(vcpu
))
7719 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7720 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7722 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7724 if (type
>= 32 || !(types
& (1 << type
))) {
7725 nested_vmx_failValid(vcpu
,
7726 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7727 return kvm_skip_emulated_instruction(vcpu
);
7730 /* According to the Intel VMX instruction reference, the memory
7731 * operand is read even if it isn't needed (e.g., for type==global)
7733 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7734 vmx_instruction_info
, false, &gva
))
7736 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7737 sizeof(operand
), &e
)) {
7738 kvm_inject_page_fault(vcpu
, &e
);
7743 case VMX_EPT_EXTENT_GLOBAL
:
7745 * TODO: track mappings and invalidate
7746 * single context requests appropriately
7748 case VMX_EPT_EXTENT_CONTEXT
:
7749 kvm_mmu_sync_roots(vcpu
);
7750 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7751 nested_vmx_succeed(vcpu
);
7758 return kvm_skip_emulated_instruction(vcpu
);
7761 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7763 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7764 u32 vmx_instruction_info
;
7765 unsigned long type
, types
;
7767 struct x86_exception e
;
7773 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7774 SECONDARY_EXEC_ENABLE_VPID
) ||
7775 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7776 kvm_queue_exception(vcpu
, UD_VECTOR
);
7780 if (!nested_vmx_check_permission(vcpu
))
7783 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7784 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7786 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7787 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7789 if (type
>= 32 || !(types
& (1 << type
))) {
7790 nested_vmx_failValid(vcpu
,
7791 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7792 return kvm_skip_emulated_instruction(vcpu
);
7795 /* according to the intel vmx instruction reference, the memory
7796 * operand is read even if it isn't needed (e.g., for type==global)
7798 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7799 vmx_instruction_info
, false, &gva
))
7801 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7802 sizeof(operand
), &e
)) {
7803 kvm_inject_page_fault(vcpu
, &e
);
7806 if (operand
.vpid
>> 16) {
7807 nested_vmx_failValid(vcpu
,
7808 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7809 return kvm_skip_emulated_instruction(vcpu
);
7813 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7814 if (is_noncanonical_address(operand
.gla
)) {
7815 nested_vmx_failValid(vcpu
,
7816 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7817 return kvm_skip_emulated_instruction(vcpu
);
7820 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7821 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7822 if (!operand
.vpid
) {
7823 nested_vmx_failValid(vcpu
,
7824 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7825 return kvm_skip_emulated_instruction(vcpu
);
7828 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7832 return kvm_skip_emulated_instruction(vcpu
);
7835 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7836 nested_vmx_succeed(vcpu
);
7838 return kvm_skip_emulated_instruction(vcpu
);
7841 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7843 unsigned long exit_qualification
;
7845 trace_kvm_pml_full(vcpu
->vcpu_id
);
7847 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7850 * PML buffer FULL happened while executing iret from NMI,
7851 * "blocked by NMI" bit has to be set before next VM entry.
7853 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7854 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7855 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7856 GUEST_INTR_STATE_NMI
);
7859 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7860 * here.., and there's no userspace involvement needed for PML.
7865 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7867 kvm_lapic_expired_hv_timer(vcpu
);
7872 * The exit handlers return 1 if the exit was handled fully and guest execution
7873 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7874 * to be done to userspace and return 0.
7876 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7877 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7878 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7879 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7880 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7881 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7882 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7883 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7884 [EXIT_REASON_CPUID
] = handle_cpuid
,
7885 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7886 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7887 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7888 [EXIT_REASON_HLT
] = handle_halt
,
7889 [EXIT_REASON_INVD
] = handle_invd
,
7890 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7891 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7892 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7893 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7894 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7895 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7896 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7897 [EXIT_REASON_VMREAD
] = handle_vmread
,
7898 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7899 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7900 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7901 [EXIT_REASON_VMON
] = handle_vmon
,
7902 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7903 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7904 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7905 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7906 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7907 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7908 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7909 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7910 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7911 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7912 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7913 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7914 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7915 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7916 [EXIT_REASON_INVEPT
] = handle_invept
,
7917 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7918 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7919 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7920 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7921 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7924 static const int kvm_vmx_max_exit_handlers
=
7925 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7927 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7928 struct vmcs12
*vmcs12
)
7930 unsigned long exit_qualification
;
7931 gpa_t bitmap
, last_bitmap
;
7936 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7937 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7939 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7941 port
= exit_qualification
>> 16;
7942 size
= (exit_qualification
& 7) + 1;
7944 last_bitmap
= (gpa_t
)-1;
7949 bitmap
= vmcs12
->io_bitmap_a
;
7950 else if (port
< 0x10000)
7951 bitmap
= vmcs12
->io_bitmap_b
;
7954 bitmap
+= (port
& 0x7fff) / 8;
7956 if (last_bitmap
!= bitmap
)
7957 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7959 if (b
& (1 << (port
& 7)))
7964 last_bitmap
= bitmap
;
7971 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7972 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7973 * disinterest in the current event (read or write a specific MSR) by using an
7974 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7976 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7977 struct vmcs12
*vmcs12
, u32 exit_reason
)
7979 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7982 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7986 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7987 * for the four combinations of read/write and low/high MSR numbers.
7988 * First we need to figure out which of the four to use:
7990 bitmap
= vmcs12
->msr_bitmap
;
7991 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7993 if (msr_index
>= 0xc0000000) {
7994 msr_index
-= 0xc0000000;
7998 /* Then read the msr_index'th bit from this bitmap: */
7999 if (msr_index
< 1024*8) {
8001 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8003 return 1 & (b
>> (msr_index
& 7));
8005 return true; /* let L1 handle the wrong parameter */
8009 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8010 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8011 * intercept (via guest_host_mask etc.) the current event.
8013 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8014 struct vmcs12
*vmcs12
)
8016 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8017 int cr
= exit_qualification
& 15;
8021 switch ((exit_qualification
>> 4) & 3) {
8022 case 0: /* mov to cr */
8023 reg
= (exit_qualification
>> 8) & 15;
8024 val
= kvm_register_readl(vcpu
, reg
);
8027 if (vmcs12
->cr0_guest_host_mask
&
8028 (val
^ vmcs12
->cr0_read_shadow
))
8032 if ((vmcs12
->cr3_target_count
>= 1 &&
8033 vmcs12
->cr3_target_value0
== val
) ||
8034 (vmcs12
->cr3_target_count
>= 2 &&
8035 vmcs12
->cr3_target_value1
== val
) ||
8036 (vmcs12
->cr3_target_count
>= 3 &&
8037 vmcs12
->cr3_target_value2
== val
) ||
8038 (vmcs12
->cr3_target_count
>= 4 &&
8039 vmcs12
->cr3_target_value3
== val
))
8041 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8045 if (vmcs12
->cr4_guest_host_mask
&
8046 (vmcs12
->cr4_read_shadow
^ val
))
8050 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8056 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8057 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8060 case 1: /* mov from cr */
8063 if (vmcs12
->cpu_based_vm_exec_control
&
8064 CPU_BASED_CR3_STORE_EXITING
)
8068 if (vmcs12
->cpu_based_vm_exec_control
&
8069 CPU_BASED_CR8_STORE_EXITING
)
8076 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8077 * cr0. Other attempted changes are ignored, with no exit.
8079 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8080 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8081 (val
^ vmcs12
->cr0_read_shadow
))
8083 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8084 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8093 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8094 * should handle it ourselves in L0 (and then continue L2). Only call this
8095 * when in is_guest_mode (L2).
8097 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8099 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8100 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8101 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8103 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8104 vmcs_readl(EXIT_QUALIFICATION
),
8105 vmx
->idt_vectoring_info
,
8107 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8111 * The host physical addresses of some pages of guest memory
8112 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8113 * may write to these pages via their host physical address while
8114 * L2 is running, bypassing any address-translation-based dirty
8115 * tracking (e.g. EPT write protection).
8117 * Mark them dirty on every exit from L2 to prevent them from
8118 * getting out of sync with dirty tracking.
8120 nested_mark_vmcs12_pages_dirty(vcpu
);
8122 if (vmx
->nested
.nested_run_pending
)
8125 if (unlikely(vmx
->fail
)) {
8126 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8127 vmcs_read32(VM_INSTRUCTION_ERROR
));
8131 switch (exit_reason
) {
8132 case EXIT_REASON_EXCEPTION_NMI
:
8133 if (is_nmi(intr_info
))
8135 else if (is_page_fault(intr_info
))
8136 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8137 else if (is_no_device(intr_info
) &&
8138 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8140 else if (is_debug(intr_info
) &&
8142 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8144 else if (is_breakpoint(intr_info
) &&
8145 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8147 return vmcs12
->exception_bitmap
&
8148 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8149 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8151 case EXIT_REASON_TRIPLE_FAULT
:
8153 case EXIT_REASON_PENDING_INTERRUPT
:
8154 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8155 case EXIT_REASON_NMI_WINDOW
:
8156 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8157 case EXIT_REASON_TASK_SWITCH
:
8159 case EXIT_REASON_CPUID
:
8161 case EXIT_REASON_HLT
:
8162 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8163 case EXIT_REASON_INVD
:
8165 case EXIT_REASON_INVLPG
:
8166 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8167 case EXIT_REASON_RDPMC
:
8168 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8169 case EXIT_REASON_RDRAND
:
8170 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8171 case EXIT_REASON_RDSEED
:
8172 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8173 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8174 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8175 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8176 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8177 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8178 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8179 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8180 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8182 * VMX instructions trap unconditionally. This allows L1 to
8183 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8186 case EXIT_REASON_CR_ACCESS
:
8187 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8188 case EXIT_REASON_DR_ACCESS
:
8189 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8190 case EXIT_REASON_IO_INSTRUCTION
:
8191 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8192 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8193 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8194 case EXIT_REASON_MSR_READ
:
8195 case EXIT_REASON_MSR_WRITE
:
8196 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8197 case EXIT_REASON_INVALID_STATE
:
8199 case EXIT_REASON_MWAIT_INSTRUCTION
:
8200 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8201 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8202 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8203 case EXIT_REASON_MONITOR_INSTRUCTION
:
8204 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8205 case EXIT_REASON_PAUSE_INSTRUCTION
:
8206 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8207 nested_cpu_has2(vmcs12
,
8208 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8209 case EXIT_REASON_MCE_DURING_VMENTRY
:
8211 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8212 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8213 case EXIT_REASON_APIC_ACCESS
:
8214 return nested_cpu_has2(vmcs12
,
8215 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8216 case EXIT_REASON_APIC_WRITE
:
8217 case EXIT_REASON_EOI_INDUCED
:
8218 /* apic_write and eoi_induced should exit unconditionally. */
8220 case EXIT_REASON_EPT_VIOLATION
:
8222 * L0 always deals with the EPT violation. If nested EPT is
8223 * used, and the nested mmu code discovers that the address is
8224 * missing in the guest EPT table (EPT12), the EPT violation
8225 * will be injected with nested_ept_inject_page_fault()
8228 case EXIT_REASON_EPT_MISCONFIG
:
8230 * L2 never uses directly L1's EPT, but rather L0's own EPT
8231 * table (shadow on EPT) or a merged EPT table that L0 built
8232 * (EPT on EPT). So any problems with the structure of the
8233 * table is L0's fault.
8236 case EXIT_REASON_WBINVD
:
8237 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8238 case EXIT_REASON_XSETBV
:
8240 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8242 * This should never happen, since it is not possible to
8243 * set XSS to a non-zero value---neither in L1 nor in L2.
8244 * If if it were, XSS would have to be checked against
8245 * the XSS exit bitmap in vmcs12.
8247 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8248 case EXIT_REASON_PREEMPTION_TIMER
:
8250 case EXIT_REASON_PML_FULL
:
8251 /* We emulate PML support to L1. */
8258 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8260 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8263 * At this point, the exit interruption info in exit_intr_info
8264 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8265 * we need to query the in-kernel LAPIC.
8267 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8268 if ((exit_intr_info
&
8269 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8270 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8271 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8272 vmcs12
->vm_exit_intr_error_code
=
8273 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8276 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8277 vmcs_readl(EXIT_QUALIFICATION
));
8281 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8283 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8284 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8287 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8290 __free_page(vmx
->pml_pg
);
8295 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8297 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8301 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8303 /* Do nothing if PML buffer is empty */
8304 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8307 /* PML index always points to next available PML buffer entity */
8308 if (pml_idx
>= PML_ENTITY_NUM
)
8313 pml_buf
= page_address(vmx
->pml_pg
);
8314 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8317 gpa
= pml_buf
[pml_idx
];
8318 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8319 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8322 /* reset PML index */
8323 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8327 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8328 * Called before reporting dirty_bitmap to userspace.
8330 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8333 struct kvm_vcpu
*vcpu
;
8335 * We only need to kick vcpu out of guest mode here, as PML buffer
8336 * is flushed at beginning of all VMEXITs, and it's obvious that only
8337 * vcpus running in guest are possible to have unflushed GPAs in PML
8340 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8341 kvm_vcpu_kick(vcpu
);
8344 static void vmx_dump_sel(char *name
, uint32_t sel
)
8346 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8347 name
, vmcs_read16(sel
),
8348 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8349 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8350 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8353 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8355 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8356 name
, vmcs_read32(limit
),
8357 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8360 static void dump_vmcs(void)
8362 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8363 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8364 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8365 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8366 u32 secondary_exec_control
= 0;
8367 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8368 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8371 if (cpu_has_secondary_exec_ctrls())
8372 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8374 pr_err("*** Guest State ***\n");
8375 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8376 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8377 vmcs_readl(CR0_GUEST_HOST_MASK
));
8378 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8379 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8380 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8381 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8382 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8384 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8385 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8386 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8387 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8389 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8390 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8391 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8392 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8393 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8394 vmcs_readl(GUEST_SYSENTER_ESP
),
8395 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8396 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8397 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8398 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8399 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8400 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8401 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8402 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8403 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8404 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8405 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8406 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8407 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8408 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8409 efer
, vmcs_read64(GUEST_IA32_PAT
));
8410 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8411 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8412 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8413 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8414 pr_err("PerfGlobCtl = 0x%016llx\n",
8415 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8416 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8417 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8418 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8419 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8420 vmcs_read32(GUEST_ACTIVITY_STATE
));
8421 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8422 pr_err("InterruptStatus = %04x\n",
8423 vmcs_read16(GUEST_INTR_STATUS
));
8425 pr_err("*** Host State ***\n");
8426 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8427 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8428 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8429 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8430 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8431 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8432 vmcs_read16(HOST_TR_SELECTOR
));
8433 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8434 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8435 vmcs_readl(HOST_TR_BASE
));
8436 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8437 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8438 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8439 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8440 vmcs_readl(HOST_CR4
));
8441 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8442 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8443 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8444 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8445 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8446 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8447 vmcs_read64(HOST_IA32_EFER
),
8448 vmcs_read64(HOST_IA32_PAT
));
8449 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8450 pr_err("PerfGlobCtl = 0x%016llx\n",
8451 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8453 pr_err("*** Control State ***\n");
8454 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8455 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8456 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8457 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8458 vmcs_read32(EXCEPTION_BITMAP
),
8459 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8460 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8461 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8462 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8463 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8464 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8465 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8466 vmcs_read32(VM_EXIT_INTR_INFO
),
8467 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8468 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8469 pr_err(" reason=%08x qualification=%016lx\n",
8470 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8471 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8472 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8473 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8474 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8475 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8476 pr_err("TSC Multiplier = 0x%016llx\n",
8477 vmcs_read64(TSC_MULTIPLIER
));
8478 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8479 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8480 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8481 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8482 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8483 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8484 n
= vmcs_read32(CR3_TARGET_COUNT
);
8485 for (i
= 0; i
+ 1 < n
; i
+= 4)
8486 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8487 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8488 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8490 pr_err("CR3 target%u=%016lx\n",
8491 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8492 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8493 pr_err("PLE Gap=%08x Window=%08x\n",
8494 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8495 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8496 pr_err("Virtual processor ID = 0x%04x\n",
8497 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8501 * The guest has exited. See if we can fix it or if we need userspace
8504 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8506 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8507 u32 exit_reason
= vmx
->exit_reason
;
8508 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8510 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8511 vcpu
->arch
.gpa_available
= false;
8514 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8515 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8516 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8517 * mode as if vcpus is in root mode, the PML buffer must has been
8521 vmx_flush_pml_buffer(vcpu
);
8523 /* If guest state is invalid, start emulating */
8524 if (vmx
->emulation_required
)
8525 return handle_invalid_guest_state(vcpu
);
8527 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8528 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8530 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8532 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8533 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8538 if (unlikely(vmx
->fail
)) {
8539 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8540 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8541 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8547 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8548 * delivery event since it indicates guest is accessing MMIO.
8549 * The vm-exit can be triggered again after return to guest that
8550 * will cause infinite loop.
8552 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8553 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8554 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8555 exit_reason
!= EXIT_REASON_PML_FULL
&&
8556 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8557 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8558 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8559 vcpu
->run
->internal
.ndata
= 3;
8560 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8561 vcpu
->run
->internal
.data
[1] = exit_reason
;
8562 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8563 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8564 vcpu
->run
->internal
.ndata
++;
8565 vcpu
->run
->internal
.data
[3] =
8566 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8571 if (exit_reason
< kvm_vmx_max_exit_handlers
8572 && kvm_vmx_exit_handlers
[exit_reason
])
8573 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8575 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8577 kvm_queue_exception(vcpu
, UD_VECTOR
);
8582 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8584 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8586 if (is_guest_mode(vcpu
) &&
8587 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8590 if (irr
== -1 || tpr
< irr
) {
8591 vmcs_write32(TPR_THRESHOLD
, 0);
8595 vmcs_write32(TPR_THRESHOLD
, irr
);
8598 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8600 u32 sec_exec_control
;
8602 /* Postpone execution until vmcs01 is the current VMCS. */
8603 if (is_guest_mode(vcpu
)) {
8604 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8608 if (!cpu_has_vmx_virtualize_x2apic_mode())
8611 if (!cpu_need_tpr_shadow(vcpu
))
8614 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8617 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8618 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8620 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8621 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8622 vmx_flush_tlb_ept_only(vcpu
);
8624 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8626 vmx_set_msr_bitmap(vcpu
);
8629 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8631 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8634 * Currently we do not handle the nested case where L2 has an
8635 * APIC access page of its own; that page is still pinned.
8636 * Hence, we skip the case where the VCPU is in guest mode _and_
8637 * L1 prepared an APIC access page for L2.
8639 * For the case where L1 and L2 share the same APIC access page
8640 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8641 * in the vmcs12), this function will only update either the vmcs01
8642 * or the vmcs02. If the former, the vmcs02 will be updated by
8643 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8644 * the next L2->L1 exit.
8646 if (!is_guest_mode(vcpu
) ||
8647 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8648 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8649 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8650 vmx_flush_tlb_ept_only(vcpu
);
8654 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8662 status
= vmcs_read16(GUEST_INTR_STATUS
);
8664 if (max_isr
!= old
) {
8666 status
|= max_isr
<< 8;
8667 vmcs_write16(GUEST_INTR_STATUS
, status
);
8671 static void vmx_set_rvi(int vector
)
8679 status
= vmcs_read16(GUEST_INTR_STATUS
);
8680 old
= (u8
)status
& 0xff;
8681 if ((u8
)vector
!= old
) {
8683 status
|= (u8
)vector
;
8684 vmcs_write16(GUEST_INTR_STATUS
, status
);
8688 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8690 if (!is_guest_mode(vcpu
)) {
8691 vmx_set_rvi(max_irr
);
8699 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8702 if (nested_exit_on_intr(vcpu
))
8706 * Else, fall back to pre-APICv interrupt injection since L2
8707 * is run without virtual interrupt delivery.
8709 if (!kvm_event_needs_reinjection(vcpu
) &&
8710 vmx_interrupt_allowed(vcpu
)) {
8711 kvm_queue_interrupt(vcpu
, max_irr
, false);
8712 vmx_inject_irq(vcpu
);
8716 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8718 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8721 WARN_ON(!vcpu
->arch
.apicv_active
);
8722 if (pi_test_on(&vmx
->pi_desc
)) {
8723 pi_clear_on(&vmx
->pi_desc
);
8725 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8726 * But on x86 this is just a compiler barrier anyway.
8728 smp_mb__after_atomic();
8729 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8731 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8733 vmx_hwapic_irr_update(vcpu
, max_irr
);
8737 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8739 if (!kvm_vcpu_apicv_active(vcpu
))
8742 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8743 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8744 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8745 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8748 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8750 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8752 pi_clear_on(&vmx
->pi_desc
);
8753 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8756 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8758 u32 exit_intr_info
= 0;
8759 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8761 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8762 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8765 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8766 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8767 vmx
->exit_intr_info
= exit_intr_info
;
8769 /* if exit due to PF check for async PF */
8770 if (is_page_fault(exit_intr_info
))
8771 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8773 /* Handle machine checks before interrupts are enabled */
8774 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8775 is_machine_check(exit_intr_info
))
8776 kvm_machine_check();
8778 /* We need to handle NMIs before interrupts are enabled */
8779 if (is_nmi(exit_intr_info
)) {
8780 kvm_before_handle_nmi(&vmx
->vcpu
);
8782 kvm_after_handle_nmi(&vmx
->vcpu
);
8786 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8788 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8790 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8791 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8792 unsigned int vector
;
8793 unsigned long entry
;
8795 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8796 #ifdef CONFIG_X86_64
8800 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8801 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8802 entry
= gate_offset(desc
);
8804 #ifdef CONFIG_X86_64
8805 "mov %%" _ASM_SP
", %[sp]\n\t"
8806 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8811 __ASM_SIZE(push
) " $%c[cs]\n\t"
8812 "call *%[entry]\n\t"
8814 #ifdef CONFIG_X86_64
8820 [ss
]"i"(__KERNEL_DS
),
8821 [cs
]"i"(__KERNEL_CS
)
8825 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8827 static bool vmx_has_high_real_mode_segbase(void)
8829 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8832 static bool vmx_mpx_supported(void)
8834 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8835 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8838 static bool vmx_xsaves_supported(void)
8840 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8841 SECONDARY_EXEC_XSAVES
;
8844 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8849 bool idtv_info_valid
;
8851 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8853 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
8856 * Can't use vmx->exit_intr_info since we're not sure what
8857 * the exit reason is.
8859 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8860 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8861 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8863 * SDM 3: 27.7.1.2 (September 2008)
8864 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8865 * a guest IRET fault.
8866 * SDM 3: 23.2.2 (September 2008)
8867 * Bit 12 is undefined in any of the following cases:
8868 * If the VM exit sets the valid bit in the IDT-vectoring
8869 * information field.
8870 * If the VM exit is due to a double fault.
8872 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8873 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8874 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8875 GUEST_INTR_STATE_NMI
);
8877 vmx
->loaded_vmcs
->nmi_known_unmasked
=
8878 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8879 & GUEST_INTR_STATE_NMI
);
8882 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8883 u32 idt_vectoring_info
,
8884 int instr_len_field
,
8885 int error_code_field
)
8889 bool idtv_info_valid
;
8891 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8893 vcpu
->arch
.nmi_injected
= false;
8894 kvm_clear_exception_queue(vcpu
);
8895 kvm_clear_interrupt_queue(vcpu
);
8897 if (!idtv_info_valid
)
8900 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8902 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8903 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8906 case INTR_TYPE_NMI_INTR
:
8907 vcpu
->arch
.nmi_injected
= true;
8909 * SDM 3: 27.7.1.2 (September 2008)
8910 * Clear bit "block by NMI" before VM entry if a NMI
8913 vmx_set_nmi_mask(vcpu
, false);
8915 case INTR_TYPE_SOFT_EXCEPTION
:
8916 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8918 case INTR_TYPE_HARD_EXCEPTION
:
8919 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8920 u32 err
= vmcs_read32(error_code_field
);
8921 kvm_requeue_exception_e(vcpu
, vector
, err
);
8923 kvm_requeue_exception(vcpu
, vector
);
8925 case INTR_TYPE_SOFT_INTR
:
8926 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8928 case INTR_TYPE_EXT_INTR
:
8929 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8936 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8938 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8939 VM_EXIT_INSTRUCTION_LEN
,
8940 IDT_VECTORING_ERROR_CODE
);
8943 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8945 __vmx_complete_interrupts(vcpu
,
8946 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8947 VM_ENTRY_INSTRUCTION_LEN
,
8948 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8950 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8953 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8956 struct perf_guest_switch_msr
*msrs
;
8958 msrs
= perf_guest_get_msrs(&nr_msrs
);
8963 for (i
= 0; i
< nr_msrs
; i
++)
8964 if (msrs
[i
].host
== msrs
[i
].guest
)
8965 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8967 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8971 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8973 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8977 if (vmx
->hv_deadline_tsc
== -1)
8981 if (vmx
->hv_deadline_tsc
> tscl
)
8982 /* sure to be 32 bit only because checked on set_hv_timer */
8983 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8984 cpu_preemption_timer_multi
);
8988 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8991 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8993 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8994 unsigned long debugctlmsr
, cr3
, cr4
;
8996 /* Don't enter VMX if guest state is invalid, let the exit handler
8997 start emulation until we arrive back to a valid state */
8998 if (vmx
->emulation_required
)
9001 if (vmx
->ple_window_dirty
) {
9002 vmx
->ple_window_dirty
= false;
9003 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9006 if (vmx
->nested
.sync_shadow_vmcs
) {
9007 copy_vmcs12_to_shadow(vmx
);
9008 vmx
->nested
.sync_shadow_vmcs
= false;
9011 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9012 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9013 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9014 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9016 cr3
= __get_current_cr3_fast();
9017 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9018 vmcs_writel(HOST_CR3
, cr3
);
9019 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9022 cr4
= cr4_read_shadow();
9023 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9024 vmcs_writel(HOST_CR4
, cr4
);
9025 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9028 /* When single-stepping over STI and MOV SS, we must clear the
9029 * corresponding interruptibility bits in the guest state. Otherwise
9030 * vmentry fails as it then expects bit 14 (BS) in pending debug
9031 * exceptions being set, but that's not correct for the guest debugging
9033 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9034 vmx_set_interrupt_shadow(vcpu
, 0);
9036 if (static_cpu_has(X86_FEATURE_PKU
) &&
9037 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9038 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9039 __write_pkru(vcpu
->arch
.pkru
);
9041 atomic_switch_perf_msrs(vmx
);
9043 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
9044 add_atomic_switch_msr(vmx
, MSR_IA32_SPEC_CTRL
,
9045 vcpu
->arch
.spec_ctrl
, FEATURE_ENABLE_IBRS
);
9047 debugctlmsr
= get_debugctlmsr();
9049 vmx_arm_hv_timer(vcpu
);
9051 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9053 /* Store host registers */
9054 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9055 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9056 "push %%" _ASM_CX
" \n\t"
9057 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9059 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9060 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9062 /* Reload cr2 if changed */
9063 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9064 "mov %%cr2, %%" _ASM_DX
" \n\t"
9065 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9067 "mov %%" _ASM_AX
", %%cr2 \n\t"
9069 /* Check if vmlaunch of vmresume is needed */
9070 "cmpl $0, %c[launched](%0) \n\t"
9071 /* Load guest registers. Don't clobber flags. */
9072 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9073 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9074 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9075 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9076 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9077 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9078 #ifdef CONFIG_X86_64
9079 "mov %c[r8](%0), %%r8 \n\t"
9080 "mov %c[r9](%0), %%r9 \n\t"
9081 "mov %c[r10](%0), %%r10 \n\t"
9082 "mov %c[r11](%0), %%r11 \n\t"
9083 "mov %c[r12](%0), %%r12 \n\t"
9084 "mov %c[r13](%0), %%r13 \n\t"
9085 "mov %c[r14](%0), %%r14 \n\t"
9086 "mov %c[r15](%0), %%r15 \n\t"
9088 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9090 /* Enter guest mode */
9092 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9094 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9096 /* Save guest registers, load host registers, keep flags */
9097 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9099 "setbe %c[fail](%0)\n\t"
9100 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9101 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9102 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9103 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9104 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9105 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9106 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9107 #ifdef CONFIG_X86_64
9108 "mov %%r8, %c[r8](%0) \n\t"
9109 "mov %%r9, %c[r9](%0) \n\t"
9110 "mov %%r10, %c[r10](%0) \n\t"
9111 "mov %%r11, %c[r11](%0) \n\t"
9112 "mov %%r12, %c[r12](%0) \n\t"
9113 "mov %%r13, %c[r13](%0) \n\t"
9114 "mov %%r14, %c[r14](%0) \n\t"
9115 "mov %%r15, %c[r15](%0) \n\t"
9116 "xor %%r8d, %%r8d \n\t"
9117 "xor %%r9d, %%r9d \n\t"
9118 "xor %%r10d, %%r10d \n\t"
9119 "xor %%r11d, %%r11d \n\t"
9120 "xor %%r12d, %%r12d \n\t"
9121 "xor %%r13d, %%r13d \n\t"
9122 "xor %%r14d, %%r14d \n\t"
9123 "xor %%r15d, %%r15d \n\t"
9125 "mov %%cr2, %%" _ASM_AX
" \n\t"
9126 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9128 "xor %%eax, %%eax \n\t"
9129 "xor %%ebx, %%ebx \n\t"
9130 "xor %%esi, %%esi \n\t"
9131 "xor %%edi, %%edi \n\t"
9132 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9133 ".pushsection .rodata \n\t"
9134 ".global vmx_return \n\t"
9135 "vmx_return: " _ASM_PTR
" 2b \n\t"
9137 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9138 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9139 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9140 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9141 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9142 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9143 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9144 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9145 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9146 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9147 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9148 #ifdef CONFIG_X86_64
9149 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9150 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9151 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9152 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9153 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9154 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9155 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9156 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9158 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9159 [wordsize
]"i"(sizeof(ulong
))
9161 #ifdef CONFIG_X86_64
9162 , "rax", "rbx", "rdi", "rsi"
9163 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9165 , "eax", "ebx", "edi", "esi"
9169 /* Eliminate branch target predictions from guest mode */
9172 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9174 update_debugctlmsr(debugctlmsr
);
9176 #ifndef CONFIG_X86_64
9178 * The sysexit path does not restore ds/es, so we must set them to
9179 * a reasonable value ourselves.
9181 * We can't defer this to vmx_load_host_state() since that function
9182 * may be executed in interrupt context, which saves and restore segments
9183 * around it, nullifying its effect.
9185 loadsegment(ds
, __USER_DS
);
9186 loadsegment(es
, __USER_DS
);
9189 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9190 | (1 << VCPU_EXREG_RFLAGS
)
9191 | (1 << VCPU_EXREG_PDPTR
)
9192 | (1 << VCPU_EXREG_SEGMENTS
)
9193 | (1 << VCPU_EXREG_CR3
));
9194 vcpu
->arch
.regs_dirty
= 0;
9196 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9198 vmx
->loaded_vmcs
->launched
= 1;
9200 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9203 * eager fpu is enabled if PKEY is supported and CR4 is switched
9204 * back on host, so it is safe to read guest PKRU from current
9207 if (static_cpu_has(X86_FEATURE_PKU
) &&
9208 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9209 vcpu
->arch
.pkru
= __read_pkru();
9210 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9211 __write_pkru(vmx
->host_pkru
);
9215 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9216 * we did not inject a still-pending event to L1 now because of
9217 * nested_run_pending, we need to re-enable this bit.
9219 if (vmx
->nested
.nested_run_pending
)
9220 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9222 vmx
->nested
.nested_run_pending
= 0;
9224 vmx_complete_atomic_exit(vmx
);
9225 vmx_recover_nmi_blocking(vmx
);
9226 vmx_complete_interrupts(vmx
);
9228 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9230 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9232 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9235 if (vmx
->loaded_vmcs
== vmcs
)
9239 vmx
->loaded_vmcs
= vmcs
;
9241 vmx_vcpu_load(vcpu
, cpu
);
9247 * Ensure that the current vmcs of the logical processor is the
9248 * vmcs01 of the vcpu before calling free_nested().
9250 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9252 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9255 r
= vcpu_load(vcpu
);
9257 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9262 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9264 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9267 vmx_destroy_pml_buffer(vmx
);
9268 free_vpid(vmx
->vpid
);
9269 leave_guest_mode(vcpu
);
9270 vmx_free_vcpu_nested(vcpu
);
9271 free_loaded_vmcs(vmx
->loaded_vmcs
);
9272 kfree(vmx
->guest_msrs
);
9273 kvm_vcpu_uninit(vcpu
);
9274 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9277 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9280 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9284 return ERR_PTR(-ENOMEM
);
9286 vmx
->vpid
= allocate_vpid();
9288 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9295 * If PML is turned on, failure on enabling PML just results in failure
9296 * of creating the vcpu, therefore we can simplify PML logic (by
9297 * avoiding dealing with cases, such as enabling PML partially on vcpus
9298 * for the guest, etc.
9301 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9306 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9307 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9310 if (!vmx
->guest_msrs
)
9313 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9314 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9315 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9316 if (!vmx
->loaded_vmcs
->vmcs
)
9318 loaded_vmcs_init(vmx
->loaded_vmcs
);
9321 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9322 vmx
->vcpu
.cpu
= cpu
;
9323 err
= vmx_vcpu_setup(vmx
);
9324 vmx_vcpu_put(&vmx
->vcpu
);
9328 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9329 err
= alloc_apic_access_page(kvm
);
9335 if (!kvm
->arch
.ept_identity_map_addr
)
9336 kvm
->arch
.ept_identity_map_addr
=
9337 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9338 err
= init_rmode_identity_map(kvm
);
9344 nested_vmx_setup_ctls_msrs(vmx
);
9345 vmx
->nested
.vpid02
= allocate_vpid();
9348 vmx
->nested
.posted_intr_nv
= -1;
9349 vmx
->nested
.current_vmptr
= -1ull;
9351 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9354 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9355 * or POSTED_INTR_WAKEUP_VECTOR.
9357 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9358 vmx
->pi_desc
.sn
= 1;
9363 free_vpid(vmx
->nested
.vpid02
);
9364 free_loaded_vmcs(vmx
->loaded_vmcs
);
9366 kfree(vmx
->guest_msrs
);
9368 vmx_destroy_pml_buffer(vmx
);
9370 kvm_vcpu_uninit(&vmx
->vcpu
);
9372 free_vpid(vmx
->vpid
);
9373 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9374 return ERR_PTR(err
);
9377 static void __init
vmx_check_processor_compat(void *rtn
)
9379 struct vmcs_config vmcs_conf
;
9382 if (setup_vmcs_config(&vmcs_conf
) < 0)
9384 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9385 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9386 smp_processor_id());
9391 static int get_ept_level(void)
9393 return VMX_EPT_DEFAULT_GAW
+ 1;
9396 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9401 /* For VT-d and EPT combination
9402 * 1. MMIO: always map as UC
9404 * a. VT-d without snooping control feature: can't guarantee the
9405 * result, try to trust guest.
9406 * b. VT-d with snooping control feature: snooping control feature of
9407 * VT-d engine can guarantee the cache correctness. Just set it
9408 * to WB to keep consistent with host. So the same as item 3.
9409 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9410 * consistent with host MTRR
9413 cache
= MTRR_TYPE_UNCACHABLE
;
9417 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9418 ipat
= VMX_EPT_IPAT_BIT
;
9419 cache
= MTRR_TYPE_WRBACK
;
9423 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9424 ipat
= VMX_EPT_IPAT_BIT
;
9425 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9426 cache
= MTRR_TYPE_WRBACK
;
9428 cache
= MTRR_TYPE_UNCACHABLE
;
9432 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9435 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9438 static int vmx_get_lpage_level(void)
9440 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9441 return PT_DIRECTORY_LEVEL
;
9443 /* For shadow and EPT supported 1GB page */
9444 return PT_PDPE_LEVEL
;
9447 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9450 * These bits in the secondary execution controls field
9451 * are dynamic, the others are mostly based on the hypervisor
9452 * architecture and the guest's CPUID. Do not touch the
9456 SECONDARY_EXEC_SHADOW_VMCS
|
9457 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9458 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9460 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9462 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9463 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9467 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9468 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9470 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9473 struct kvm_cpuid_entry2
*entry
;
9475 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9476 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9478 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9479 if (entry && (entry->_reg & (_cpuid_mask))) \
9480 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9483 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9484 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9485 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9486 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9487 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9488 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9489 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9490 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9491 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9492 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9493 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9494 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9495 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9496 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9497 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9499 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9500 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9501 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9502 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9503 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9504 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9505 cr4_fixed1_update(bit(11), ecx
, bit(2));
9507 #undef cr4_fixed1_update
9510 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9512 struct kvm_cpuid_entry2
*best
;
9513 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9514 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9516 if (vmx_rdtscp_supported()) {
9517 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9518 if (!rdtscp_enabled
)
9519 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9523 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9524 SECONDARY_EXEC_RDTSCP
;
9526 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9527 ~SECONDARY_EXEC_RDTSCP
;
9531 /* Exposing INVPCID only when PCID is exposed */
9532 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9533 if (vmx_invpcid_supported() &&
9534 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9535 !guest_cpuid_has_pcid(vcpu
))) {
9536 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9539 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9542 if (cpu_has_secondary_exec_ctrls())
9543 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9545 if (nested_vmx_allowed(vcpu
))
9546 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9547 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9549 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9550 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9552 if (nested_vmx_allowed(vcpu
))
9553 nested_vmx_cr_fixed1_bits_update(vcpu
);
9556 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9558 if (func
== 1 && nested
)
9559 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9562 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9563 struct x86_exception
*fault
)
9565 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9566 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9568 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9570 if (vmx
->nested
.pml_full
) {
9571 exit_reason
= EXIT_REASON_PML_FULL
;
9572 vmx
->nested
.pml_full
= false;
9573 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9574 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9575 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9577 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9579 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9580 vmcs12
->guest_physical_address
= fault
->address
;
9583 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9585 return nested_ept_get_cr3(vcpu
) & VMX_EPT_AD_ENABLE_BIT
;
9588 /* Callbacks for nested_ept_init_mmu_context: */
9590 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9592 /* return the page table to be shadowed - in our case, EPT12 */
9593 return get_vmcs12(vcpu
)->ept_pointer
;
9596 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9600 WARN_ON(mmu_is_nested(vcpu
));
9601 wants_ad
= nested_ept_ad_enabled(vcpu
);
9602 if (wants_ad
&& !enable_ept_ad_bits
)
9605 kvm_mmu_unload(vcpu
);
9606 kvm_init_shadow_ept_mmu(vcpu
,
9607 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9608 VMX_EPT_EXECUTE_ONLY_BIT
,
9610 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9611 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9612 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9614 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9618 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9620 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9623 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9626 bool inequality
, bit
;
9628 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9630 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9631 vmcs12
->page_fault_error_code_match
;
9632 return inequality
^ bit
;
9635 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9636 struct x86_exception
*fault
)
9638 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9640 WARN_ON(!is_guest_mode(vcpu
));
9642 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9643 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9644 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9645 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9646 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9649 kvm_inject_page_fault(vcpu
, fault
);
9653 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9654 struct vmcs12
*vmcs12
);
9656 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9657 struct vmcs12
*vmcs12
)
9659 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9662 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9664 * Translate L1 physical address to host physical
9665 * address for vmcs02. Keep the page pinned, so this
9666 * physical address remains valid. We keep a reference
9667 * to it so we can release it later.
9669 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9670 nested_release_page(vmx
->nested
.apic_access_page
);
9671 vmx
->nested
.apic_access_page
=
9672 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9674 * If translation failed, no matter: This feature asks
9675 * to exit when accessing the given address, and if it
9676 * can never be accessed, this feature won't do
9679 if (vmx
->nested
.apic_access_page
) {
9680 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9681 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9683 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9684 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9686 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9687 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9688 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9689 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9690 kvm_vcpu_reload_apic_access_page(vcpu
);
9693 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9694 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9695 nested_release_page(vmx
->nested
.virtual_apic_page
);
9696 vmx
->nested
.virtual_apic_page
=
9697 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9700 * If translation failed, VM entry will fail because
9701 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9702 * Failing the vm entry is _not_ what the processor
9703 * does but it's basically the only possibility we
9704 * have. We could still enter the guest if CR8 load
9705 * exits are enabled, CR8 store exits are enabled, and
9706 * virtualize APIC access is disabled; in this case
9707 * the processor would never use the TPR shadow and we
9708 * could simply clear the bit from the execution
9709 * control. But such a configuration is useless, so
9710 * let's keep the code simple.
9712 if (vmx
->nested
.virtual_apic_page
) {
9713 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9714 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9718 if (nested_cpu_has_posted_intr(vmcs12
)) {
9719 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9720 kunmap(vmx
->nested
.pi_desc_page
);
9721 nested_release_page(vmx
->nested
.pi_desc_page
);
9723 vmx
->nested
.pi_desc_page
=
9724 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9725 vmx
->nested
.pi_desc
=
9726 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9727 if (!vmx
->nested
.pi_desc
) {
9728 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9731 vmx
->nested
.pi_desc
=
9732 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9733 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9735 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9736 page_to_phys(vmx
->nested
.pi_desc_page
) +
9737 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9740 if (cpu_has_vmx_msr_bitmap() &&
9741 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9742 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9745 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9746 CPU_BASED_USE_MSR_BITMAPS
);
9749 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9751 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9752 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9754 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9757 /* Make sure short timeouts reliably trigger an immediate vmexit.
9758 * hrtimer_start does not guarantee this. */
9759 if (preemption_timeout
<= 1) {
9760 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9764 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9765 preemption_timeout
*= 1000000;
9766 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9767 hrtimer_start(&vmx
->nested
.preemption_timer
,
9768 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9771 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9772 struct vmcs12
*vmcs12
)
9774 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9777 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9778 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9784 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9785 struct vmcs12
*vmcs12
)
9787 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9790 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9797 * Merge L0's and L1's MSR bitmap, return false to indicate that
9798 * we do not use the hardware.
9800 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9801 struct vmcs12
*vmcs12
)
9805 unsigned long *msr_bitmap_l1
;
9806 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9808 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9809 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9812 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9815 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9817 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9819 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9820 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9821 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9822 nested_vmx_disable_intercept_for_msr(
9823 msr_bitmap_l1
, msr_bitmap_l0
,
9826 nested_vmx_disable_intercept_for_msr(
9827 msr_bitmap_l1
, msr_bitmap_l0
,
9828 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9829 MSR_TYPE_R
| MSR_TYPE_W
);
9831 if (nested_cpu_has_vid(vmcs12
)) {
9832 nested_vmx_disable_intercept_for_msr(
9833 msr_bitmap_l1
, msr_bitmap_l0
,
9834 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9836 nested_vmx_disable_intercept_for_msr(
9837 msr_bitmap_l1
, msr_bitmap_l0
,
9838 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9843 nested_release_page_clean(page
);
9848 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9849 struct vmcs12
*vmcs12
)
9851 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9852 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9853 !nested_cpu_has_vid(vmcs12
) &&
9854 !nested_cpu_has_posted_intr(vmcs12
))
9858 * If virtualize x2apic mode is enabled,
9859 * virtualize apic access must be disabled.
9861 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9862 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9866 * If virtual interrupt delivery is enabled,
9867 * we must exit on external interrupts.
9869 if (nested_cpu_has_vid(vmcs12
) &&
9870 !nested_exit_on_intr(vcpu
))
9874 * bits 15:8 should be zero in posted_intr_nv,
9875 * the descriptor address has been already checked
9876 * in nested_get_vmcs12_pages.
9878 if (nested_cpu_has_posted_intr(vmcs12
) &&
9879 (!nested_cpu_has_vid(vmcs12
) ||
9880 !nested_exit_intr_ack_set(vcpu
) ||
9881 vmcs12
->posted_intr_nv
& 0xff00))
9884 /* tpr shadow is needed by all apicv features. */
9885 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9891 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9892 unsigned long count_field
,
9893 unsigned long addr_field
)
9898 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9899 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9905 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9906 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9907 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9908 pr_debug_ratelimited(
9909 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9910 addr_field
, maxphyaddr
, count
, addr
);
9916 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9917 struct vmcs12
*vmcs12
)
9919 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9920 vmcs12
->vm_exit_msr_store_count
== 0 &&
9921 vmcs12
->vm_entry_msr_load_count
== 0)
9922 return 0; /* Fast path */
9923 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9924 VM_EXIT_MSR_LOAD_ADDR
) ||
9925 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9926 VM_EXIT_MSR_STORE_ADDR
) ||
9927 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9928 VM_ENTRY_MSR_LOAD_ADDR
))
9933 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9934 struct vmcs12
*vmcs12
)
9936 u64 address
= vmcs12
->pml_address
;
9937 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9939 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9940 if (!nested_cpu_has_ept(vmcs12
) ||
9941 !IS_ALIGNED(address
, 4096) ||
9942 address
>> maxphyaddr
)
9949 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9950 struct vmx_msr_entry
*e
)
9952 /* x2APIC MSR accesses are not allowed */
9953 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9955 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9956 e
->index
== MSR_IA32_UCODE_REV
)
9958 if (e
->reserved
!= 0)
9963 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9964 struct vmx_msr_entry
*e
)
9966 if (e
->index
== MSR_FS_BASE
||
9967 e
->index
== MSR_GS_BASE
||
9968 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9969 nested_vmx_msr_check_common(vcpu
, e
))
9974 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9975 struct vmx_msr_entry
*e
)
9977 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9978 nested_vmx_msr_check_common(vcpu
, e
))
9984 * Load guest's/host's msr at nested entry/exit.
9985 * return 0 for success, entry index for failure.
9987 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9990 struct vmx_msr_entry e
;
9991 struct msr_data msr
;
9993 msr
.host_initiated
= false;
9994 for (i
= 0; i
< count
; i
++) {
9995 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9997 pr_debug_ratelimited(
9998 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9999 __func__
, i
, gpa
+ i
* sizeof(e
));
10002 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10003 pr_debug_ratelimited(
10004 "%s check failed (%u, 0x%x, 0x%x)\n",
10005 __func__
, i
, e
.index
, e
.reserved
);
10008 msr
.index
= e
.index
;
10009 msr
.data
= e
.value
;
10010 if (kvm_set_msr(vcpu
, &msr
)) {
10011 pr_debug_ratelimited(
10012 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10013 __func__
, i
, e
.index
, e
.value
);
10022 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10025 struct vmx_msr_entry e
;
10027 for (i
= 0; i
< count
; i
++) {
10028 struct msr_data msr_info
;
10029 if (kvm_vcpu_read_guest(vcpu
,
10030 gpa
+ i
* sizeof(e
),
10031 &e
, 2 * sizeof(u32
))) {
10032 pr_debug_ratelimited(
10033 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10034 __func__
, i
, gpa
+ i
* sizeof(e
));
10037 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10038 pr_debug_ratelimited(
10039 "%s check failed (%u, 0x%x, 0x%x)\n",
10040 __func__
, i
, e
.index
, e
.reserved
);
10043 msr_info
.host_initiated
= false;
10044 msr_info
.index
= e
.index
;
10045 if (kvm_get_msr(vcpu
, &msr_info
)) {
10046 pr_debug_ratelimited(
10047 "%s cannot read MSR (%u, 0x%x)\n",
10048 __func__
, i
, e
.index
);
10051 if (kvm_vcpu_write_guest(vcpu
,
10052 gpa
+ i
* sizeof(e
) +
10053 offsetof(struct vmx_msr_entry
, value
),
10054 &msr_info
.data
, sizeof(msr_info
.data
))) {
10055 pr_debug_ratelimited(
10056 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10057 __func__
, i
, e
.index
, msr_info
.data
);
10064 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10066 unsigned long invalid_mask
;
10068 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10069 return (val
& invalid_mask
) == 0;
10073 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10074 * emulating VM entry into a guest with EPT enabled.
10075 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10076 * is assigned to entry_failure_code on failure.
10078 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10079 u32
*entry_failure_code
)
10081 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10082 if (!nested_cr3_valid(vcpu
, cr3
)) {
10083 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10088 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10089 * must not be dereferenced.
10091 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10093 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10094 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10099 vcpu
->arch
.cr3
= cr3
;
10100 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10103 kvm_mmu_reset_context(vcpu
);
10108 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10109 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10110 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10111 * guest in a way that will both be appropriate to L1's requests, and our
10112 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10113 * function also has additional necessary side-effects, like setting various
10114 * vcpu->arch fields.
10115 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10116 * is assigned to entry_failure_code on failure.
10118 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10119 bool from_vmentry
, u32
*entry_failure_code
)
10121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10122 u32 exec_control
, vmcs12_exec_ctrl
;
10124 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10125 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10126 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10127 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10128 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10129 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10130 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10131 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10132 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10133 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10134 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10135 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10136 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10137 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10138 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10139 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10140 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10141 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10142 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10143 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10144 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10145 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10146 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10147 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10148 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10149 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10150 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10151 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10152 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10153 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10154 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10155 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10156 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10157 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10158 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10159 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10161 if (from_vmentry
&&
10162 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10163 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10164 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10166 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10167 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10169 if (from_vmentry
) {
10170 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10171 vmcs12
->vm_entry_intr_info_field
);
10172 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10173 vmcs12
->vm_entry_exception_error_code
);
10174 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10175 vmcs12
->vm_entry_instruction_len
);
10176 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10177 vmcs12
->guest_interruptibility_info
);
10178 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10179 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10181 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10183 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10184 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10185 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10186 vmcs12
->guest_pending_dbg_exceptions
);
10187 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10188 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10190 if (nested_cpu_has_xsaves(vmcs12
))
10191 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10192 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10194 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10196 /* Preemption timer setting is only taken from vmcs01. */
10197 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10198 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10199 if (vmx
->hv_deadline_tsc
== -1)
10200 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10202 /* Posted interrupts setting is only taken from vmcs12. */
10203 if (nested_cpu_has_posted_intr(vmcs12
)) {
10204 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10205 vmx
->nested
.pi_pending
= false;
10206 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10208 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10211 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10213 vmx
->nested
.preemption_timer_expired
= false;
10214 if (nested_cpu_has_preemption_timer(vmcs12
))
10215 vmx_start_preemption_timer(vcpu
);
10218 * Whether page-faults are trapped is determined by a combination of
10219 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10220 * If enable_ept, L0 doesn't care about page faults and we should
10221 * set all of these to L1's desires. However, if !enable_ept, L0 does
10222 * care about (at least some) page faults, and because it is not easy
10223 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10224 * to exit on each and every L2 page fault. This is done by setting
10225 * MASK=MATCH=0 and (see below) EB.PF=1.
10226 * Note that below we don't need special code to set EB.PF beyond the
10227 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10228 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10229 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10231 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10232 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10233 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10234 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10236 if (cpu_has_secondary_exec_ctrls()) {
10237 exec_control
= vmx_secondary_exec_control(vmx
);
10239 /* Take the following fields only from vmcs12 */
10240 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10241 SECONDARY_EXEC_RDTSCP
|
10242 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10243 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10244 if (nested_cpu_has(vmcs12
,
10245 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10246 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10247 ~SECONDARY_EXEC_ENABLE_PML
;
10248 exec_control
|= vmcs12_exec_ctrl
;
10251 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10252 vmcs_write64(EOI_EXIT_BITMAP0
,
10253 vmcs12
->eoi_exit_bitmap0
);
10254 vmcs_write64(EOI_EXIT_BITMAP1
,
10255 vmcs12
->eoi_exit_bitmap1
);
10256 vmcs_write64(EOI_EXIT_BITMAP2
,
10257 vmcs12
->eoi_exit_bitmap2
);
10258 vmcs_write64(EOI_EXIT_BITMAP3
,
10259 vmcs12
->eoi_exit_bitmap3
);
10260 vmcs_write16(GUEST_INTR_STATUS
,
10261 vmcs12
->guest_intr_status
);
10265 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10266 * nested_get_vmcs12_pages will either fix it up or
10267 * remove the VM execution control.
10269 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10270 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10272 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10277 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10278 * Some constant fields are set here by vmx_set_constant_host_state().
10279 * Other fields are different per CPU, and will be set later when
10280 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10282 vmx_set_constant_host_state(vmx
);
10285 * Set the MSR load/store lists to match L0's settings.
10287 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10288 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10289 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10290 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10291 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10294 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10295 * entry, but only if the current (host) sp changed from the value
10296 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10297 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10298 * here we just force the write to happen on entry.
10302 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10303 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10304 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10305 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10306 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10309 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10310 * nested_get_vmcs12_pages can't fix it up, the illegal value
10311 * will result in a VM entry failure.
10313 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10314 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10315 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10317 #ifdef CONFIG_X86_64
10318 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10319 CPU_BASED_CR8_STORE_EXITING
;
10324 * Merging of IO bitmap not currently supported.
10325 * Rather, exit every time.
10327 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10328 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10330 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10332 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10333 * bitwise-or of what L1 wants to trap for L2, and what we want to
10334 * trap. Note that CR0.TS also needs updating - we do this later.
10336 update_exception_bitmap(vcpu
);
10337 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10338 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10340 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10341 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10342 * bits are further modified by vmx_set_efer() below.
10344 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10346 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10347 * emulated by vmx_set_efer(), below.
10349 vm_entry_controls_init(vmx
,
10350 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10351 ~VM_ENTRY_IA32E_MODE
) |
10352 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10354 if (from_vmentry
&&
10355 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10356 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10357 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10358 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10359 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10362 set_cr4_guest_host_mask(vmx
);
10364 if (from_vmentry
&&
10365 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10366 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10368 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10369 vmcs_write64(TSC_OFFSET
,
10370 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10372 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10373 if (kvm_has_tsc_control
)
10374 decache_tsc_multiplier(vmx
);
10378 * There is no direct mapping between vpid02 and vpid12, the
10379 * vpid02 is per-vCPU for L0 and reused while the value of
10380 * vpid12 is changed w/ one invvpid during nested vmentry.
10381 * The vpid12 is allocated by L1 for L2, so it will not
10382 * influence global bitmap(for vpid01 and vpid02 allocation)
10383 * even if spawn a lot of nested vCPUs.
10385 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10386 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10387 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10388 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10389 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10392 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10393 vmx_flush_tlb(vcpu
);
10400 * Conceptually we want to copy the PML address and index from
10401 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10402 * since we always flush the log on each vmexit, this happens
10403 * to be equivalent to simply resetting the fields in vmcs02.
10405 ASSERT(vmx
->pml_pg
);
10406 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10407 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10410 if (nested_cpu_has_ept(vmcs12
)) {
10411 if (nested_ept_init_mmu_context(vcpu
)) {
10412 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10415 } else if (nested_cpu_has2(vmcs12
,
10416 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10417 vmx_flush_tlb_ept_only(vcpu
);
10421 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10422 * bits which we consider mandatory enabled.
10423 * The CR0_READ_SHADOW is what L2 should have expected to read given
10424 * the specifications by L1; It's not enough to take
10425 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10426 * have more bits than L1 expected.
10428 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10429 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10431 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10432 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10434 if (from_vmentry
&&
10435 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10436 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10437 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10438 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10440 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10441 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10442 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10444 /* Shadow page tables on either EPT or shadow page tables. */
10445 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10446 entry_failure_code
))
10450 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10453 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10456 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10457 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10458 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10459 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10462 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10463 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10467 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10471 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10472 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10473 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10475 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10476 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10478 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10479 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10481 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10482 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10484 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10485 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10487 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10488 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10490 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10491 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10492 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10493 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10494 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10495 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10496 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10497 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10498 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10499 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10500 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10501 vmx
->nested
.nested_vmx_exit_ctls_low
,
10502 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10503 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10504 vmx
->nested
.nested_vmx_entry_ctls_low
,
10505 vmx
->nested
.nested_vmx_entry_ctls_high
))
10506 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10508 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10509 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10511 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10512 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10513 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10514 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10519 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10524 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10526 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10527 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10530 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10531 vmcs12
->vmcs_link_pointer
!= -1ull) {
10532 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10537 * If the load IA32_EFER VM-entry control is 1, the following checks
10538 * are performed on the field for the IA32_EFER MSR:
10539 * - Bits reserved in the IA32_EFER MSR must be 0.
10540 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10541 * the IA-32e mode guest VM-exit control. It must also be identical
10542 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10545 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10546 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10547 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10548 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10549 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10550 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10551 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10556 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10557 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10558 * the values of the LMA and LME bits in the field must each be that of
10559 * the host address-space size VM-exit control.
10561 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10562 ia32e
= (vmcs12
->vm_exit_controls
&
10563 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10564 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10565 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10566 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10573 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10575 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10576 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10577 struct loaded_vmcs
*vmcs02
;
10581 vmcs02
= nested_get_current_vmcs02(vmx
);
10585 enter_guest_mode(vcpu
);
10587 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10588 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10590 vmx_switch_vmcs(vcpu
, vmcs02
);
10591 vmx_segment_cache_clear(vmx
);
10593 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10594 leave_guest_mode(vcpu
);
10595 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10596 nested_vmx_entry_failure(vcpu
, vmcs12
,
10597 EXIT_REASON_INVALID_STATE
, exit_qual
);
10601 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10603 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10604 vmcs12
->vm_entry_msr_load_addr
,
10605 vmcs12
->vm_entry_msr_load_count
);
10606 if (msr_entry_idx
) {
10607 leave_guest_mode(vcpu
);
10608 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10609 nested_vmx_entry_failure(vcpu
, vmcs12
,
10610 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10615 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10616 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10617 * returned as far as L1 is concerned. It will only return (and set
10618 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10624 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10625 * for running an L2 nested guest.
10627 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10629 struct vmcs12
*vmcs12
;
10630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10631 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10635 if (!nested_vmx_check_permission(vcpu
))
10638 if (!nested_vmx_check_vmcs12(vcpu
))
10641 vmcs12
= get_vmcs12(vcpu
);
10643 if (enable_shadow_vmcs
)
10644 copy_shadow_to_vmcs12(vmx
);
10647 * The nested entry process starts with enforcing various prerequisites
10648 * on vmcs12 as required by the Intel SDM, and act appropriately when
10649 * they fail: As the SDM explains, some conditions should cause the
10650 * instruction to fail, while others will cause the instruction to seem
10651 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10652 * To speed up the normal (success) code path, we should avoid checking
10653 * for misconfigurations which will anyway be caught by the processor
10654 * when using the merged vmcs02.
10656 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10657 nested_vmx_failValid(vcpu
,
10658 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10662 if (vmcs12
->launch_state
== launch
) {
10663 nested_vmx_failValid(vcpu
,
10664 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10665 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10669 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10671 nested_vmx_failValid(vcpu
, ret
);
10676 * After this point, the trap flag no longer triggers a singlestep trap
10677 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10678 * This is not 100% correct; for performance reasons, we delegate most
10679 * of the checks on host state to the processor. If those fail,
10680 * the singlestep trap is missed.
10682 skip_emulated_instruction(vcpu
);
10684 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10686 nested_vmx_entry_failure(vcpu
, vmcs12
,
10687 EXIT_REASON_INVALID_STATE
, exit_qual
);
10692 * We're finally done with prerequisite checking, and can start with
10693 * the nested entry.
10696 ret
= enter_vmx_non_root_mode(vcpu
, true);
10700 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10701 return kvm_vcpu_halt(vcpu
);
10703 vmx
->nested
.nested_run_pending
= 1;
10708 return kvm_skip_emulated_instruction(vcpu
);
10712 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10713 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10714 * This function returns the new value we should put in vmcs12.guest_cr0.
10715 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10716 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10717 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10718 * didn't trap the bit, because if L1 did, so would L0).
10719 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10720 * been modified by L2, and L1 knows it. So just leave the old value of
10721 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10722 * isn't relevant, because if L0 traps this bit it can set it to anything.
10723 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10724 * changed these bits, and therefore they need to be updated, but L0
10725 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10726 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10728 static inline unsigned long
10729 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10732 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10733 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10734 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10735 vcpu
->arch
.cr0_guest_owned_bits
));
10738 static inline unsigned long
10739 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10742 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10743 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10744 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10745 vcpu
->arch
.cr4_guest_owned_bits
));
10748 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10749 struct vmcs12
*vmcs12
)
10754 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10755 nr
= vcpu
->arch
.exception
.nr
;
10756 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10758 if (kvm_exception_is_soft(nr
)) {
10759 vmcs12
->vm_exit_instruction_len
=
10760 vcpu
->arch
.event_exit_inst_len
;
10761 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10763 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10765 if (vcpu
->arch
.exception
.has_error_code
) {
10766 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10767 vmcs12
->idt_vectoring_error_code
=
10768 vcpu
->arch
.exception
.error_code
;
10771 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10772 } else if (vcpu
->arch
.nmi_injected
) {
10773 vmcs12
->idt_vectoring_info_field
=
10774 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10775 } else if (vcpu
->arch
.interrupt
.pending
) {
10776 nr
= vcpu
->arch
.interrupt
.nr
;
10777 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10779 if (vcpu
->arch
.interrupt
.soft
) {
10780 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10781 vmcs12
->vm_entry_instruction_len
=
10782 vcpu
->arch
.event_exit_inst_len
;
10784 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10786 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10790 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10792 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10794 if (vcpu
->arch
.exception
.pending
||
10795 vcpu
->arch
.nmi_injected
||
10796 vcpu
->arch
.interrupt
.pending
)
10799 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10800 vmx
->nested
.preemption_timer_expired
) {
10801 if (vmx
->nested
.nested_run_pending
)
10803 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10807 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10808 if (vmx
->nested
.nested_run_pending
)
10810 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10811 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10812 INTR_INFO_VALID_MASK
, 0);
10814 * The NMI-triggered VM exit counts as injection:
10815 * clear this one and block further NMIs.
10817 vcpu
->arch
.nmi_pending
= 0;
10818 vmx_set_nmi_mask(vcpu
, true);
10822 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10823 nested_exit_on_intr(vcpu
)) {
10824 if (vmx
->nested
.nested_run_pending
)
10826 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10830 vmx_complete_nested_posted_interrupt(vcpu
);
10834 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10836 ktime_t remaining
=
10837 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10840 if (ktime_to_ns(remaining
) <= 0)
10843 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10844 do_div(value
, 1000000);
10845 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10849 * Update the guest state fields of vmcs12 to reflect changes that
10850 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10851 * VM-entry controls is also updated, since this is really a guest
10854 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10856 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10857 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10859 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10860 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10861 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10863 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10864 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10865 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10866 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10867 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10868 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10869 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10870 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10871 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10872 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10873 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10874 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10875 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10876 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10877 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10878 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10879 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10880 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10881 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10882 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10883 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10884 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10885 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10886 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10887 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10888 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10889 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10890 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10891 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10892 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10893 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10894 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10895 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10896 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10897 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10898 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10900 vmcs12
->guest_interruptibility_info
=
10901 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10902 vmcs12
->guest_pending_dbg_exceptions
=
10903 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10904 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10905 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10907 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10909 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10910 if (vmcs12
->vm_exit_controls
&
10911 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10912 vmcs12
->vmx_preemption_timer_value
=
10913 vmx_get_preemption_timer_value(vcpu
);
10914 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10918 * In some cases (usually, nested EPT), L2 is allowed to change its
10919 * own CR3 without exiting. If it has changed it, we must keep it.
10920 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10921 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10923 * Additionally, restore L2's PDPTR to vmcs12.
10926 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10927 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10928 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10929 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10930 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10933 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10935 if (nested_cpu_has_vid(vmcs12
))
10936 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10938 vmcs12
->vm_entry_controls
=
10939 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10940 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10942 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10943 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10944 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10947 /* TODO: These cannot have changed unless we have MSR bitmaps and
10948 * the relevant bit asks not to trap the change */
10949 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10950 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10951 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10952 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10953 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10954 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10955 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10956 if (kvm_mpx_supported())
10957 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10961 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10962 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10963 * and this function updates it to reflect the changes to the guest state while
10964 * L2 was running (and perhaps made some exits which were handled directly by L0
10965 * without going back to L1), and to reflect the exit reason.
10966 * Note that we do not have to copy here all VMCS fields, just those that
10967 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10968 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10969 * which already writes to vmcs12 directly.
10971 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10972 u32 exit_reason
, u32 exit_intr_info
,
10973 unsigned long exit_qualification
)
10975 /* update guest state fields: */
10976 sync_vmcs12(vcpu
, vmcs12
);
10978 /* update exit information fields: */
10980 vmcs12
->vm_exit_reason
= exit_reason
;
10981 vmcs12
->exit_qualification
= exit_qualification
;
10982 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10984 vmcs12
->idt_vectoring_info_field
= 0;
10985 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10986 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10988 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10989 vmcs12
->launch_state
= 1;
10991 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10992 * instead of reading the real value. */
10993 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10996 * Transfer the event that L0 or L1 may wanted to inject into
10997 * L2 to IDT_VECTORING_INFO_FIELD.
10999 vmcs12_save_pending_event(vcpu
, vmcs12
);
11003 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11004 * preserved above and would only end up incorrectly in L1.
11006 vcpu
->arch
.nmi_injected
= false;
11007 kvm_clear_exception_queue(vcpu
);
11008 kvm_clear_interrupt_queue(vcpu
);
11012 * A part of what we need to when the nested L2 guest exits and we want to
11013 * run its L1 parent, is to reset L1's guest state to the host state specified
11015 * This function is to be called not only on normal nested exit, but also on
11016 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11017 * Failures During or After Loading Guest State").
11018 * This function should be called when the active VMCS is L1's (vmcs01).
11020 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11021 struct vmcs12
*vmcs12
)
11023 struct kvm_segment seg
;
11024 u32 entry_failure_code
;
11026 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11027 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11028 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11029 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11031 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11032 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11034 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11035 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11036 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11038 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11039 * actually changed, because vmx_set_cr0 refers to efer set above.
11041 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11042 * (KVM doesn't change it);
11044 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11045 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11047 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11048 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11049 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11051 nested_ept_uninit_mmu_context(vcpu
);
11054 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11055 * couldn't have changed.
11057 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11058 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11061 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11065 * Trivially support vpid by letting L2s share their parent
11066 * L1's vpid. TODO: move to a more elaborate solution, giving
11067 * each L2 its own vpid and exposing the vpid feature to L1.
11069 vmx_flush_tlb(vcpu
);
11071 /* Restore posted intr vector. */
11072 if (nested_cpu_has_posted_intr(vmcs12
))
11073 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11075 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11076 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11077 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11078 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11079 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11081 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11082 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11083 vmcs_write64(GUEST_BNDCFGS
, 0);
11085 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11086 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11087 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11089 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11090 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11091 vmcs12
->host_ia32_perf_global_ctrl
);
11093 /* Set L1 segment info according to Intel SDM
11094 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11095 seg
= (struct kvm_segment
) {
11097 .limit
= 0xFFFFFFFF,
11098 .selector
= vmcs12
->host_cs_selector
,
11104 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11108 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11109 seg
= (struct kvm_segment
) {
11111 .limit
= 0xFFFFFFFF,
11118 seg
.selector
= vmcs12
->host_ds_selector
;
11119 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11120 seg
.selector
= vmcs12
->host_es_selector
;
11121 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11122 seg
.selector
= vmcs12
->host_ss_selector
;
11123 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11124 seg
.selector
= vmcs12
->host_fs_selector
;
11125 seg
.base
= vmcs12
->host_fs_base
;
11126 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11127 seg
.selector
= vmcs12
->host_gs_selector
;
11128 seg
.base
= vmcs12
->host_gs_base
;
11129 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11130 seg
= (struct kvm_segment
) {
11131 .base
= vmcs12
->host_tr_base
,
11133 .selector
= vmcs12
->host_tr_selector
,
11137 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11139 kvm_set_dr(vcpu
, 7, 0x400);
11140 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11142 if (cpu_has_vmx_msr_bitmap())
11143 vmx_set_msr_bitmap(vcpu
);
11145 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11146 vmcs12
->vm_exit_msr_load_count
))
11147 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11151 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11152 * and modify vmcs12 to make it see what it would expect to see there if
11153 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11155 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11156 u32 exit_intr_info
,
11157 unsigned long exit_qualification
)
11159 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11160 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11161 u32 vm_inst_error
= 0;
11163 /* trying to cancel vmlaunch/vmresume is a bug */
11164 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11166 leave_guest_mode(vcpu
);
11167 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11168 exit_qualification
);
11170 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11171 vmcs12
->vm_exit_msr_store_count
))
11172 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11174 if (unlikely(vmx
->fail
))
11175 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11177 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11180 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11181 * the VM-exit interrupt information (valid interrupt) is always set to
11182 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11183 * kvm_cpu_has_interrupt(). See the commit message for details.
11185 if (nested_exit_intr_ack_set(vcpu
) &&
11186 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11187 kvm_cpu_has_interrupt(vcpu
)) {
11188 int irq
= kvm_cpu_get_interrupt(vcpu
);
11190 vmcs12
->vm_exit_intr_info
= irq
|
11191 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11194 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11195 vmcs12
->exit_qualification
,
11196 vmcs12
->idt_vectoring_info_field
,
11197 vmcs12
->vm_exit_intr_info
,
11198 vmcs12
->vm_exit_intr_error_code
,
11201 vm_entry_controls_reset_shadow(vmx
);
11202 vm_exit_controls_reset_shadow(vmx
);
11203 vmx_segment_cache_clear(vmx
);
11205 /* if no vmcs02 cache requested, remove the one we used */
11206 if (VMCS02_POOL_SIZE
== 0)
11207 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11209 load_vmcs12_host_state(vcpu
, vmcs12
);
11211 /* Update any VMCS fields that might have changed while L2 ran */
11212 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11213 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11214 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11215 if (vmx
->hv_deadline_tsc
== -1)
11216 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11217 PIN_BASED_VMX_PREEMPTION_TIMER
);
11219 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11220 PIN_BASED_VMX_PREEMPTION_TIMER
);
11221 if (kvm_has_tsc_control
)
11222 decache_tsc_multiplier(vmx
);
11224 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11225 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11226 vmx_set_virtual_x2apic_mode(vcpu
,
11227 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11228 } else if (!nested_cpu_has_ept(vmcs12
) &&
11229 nested_cpu_has2(vmcs12
,
11230 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11231 vmx_flush_tlb_ept_only(vcpu
);
11234 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11237 /* Unpin physical memory we referred to in vmcs02 */
11238 if (vmx
->nested
.apic_access_page
) {
11239 nested_release_page(vmx
->nested
.apic_access_page
);
11240 vmx
->nested
.apic_access_page
= NULL
;
11242 if (vmx
->nested
.virtual_apic_page
) {
11243 nested_release_page(vmx
->nested
.virtual_apic_page
);
11244 vmx
->nested
.virtual_apic_page
= NULL
;
11246 if (vmx
->nested
.pi_desc_page
) {
11247 kunmap(vmx
->nested
.pi_desc_page
);
11248 nested_release_page(vmx
->nested
.pi_desc_page
);
11249 vmx
->nested
.pi_desc_page
= NULL
;
11250 vmx
->nested
.pi_desc
= NULL
;
11254 * We are now running in L2, mmu_notifier will force to reload the
11255 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11257 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11260 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11261 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11262 * success or failure flag accordingly.
11264 if (unlikely(vmx
->fail
)) {
11266 nested_vmx_failValid(vcpu
, vm_inst_error
);
11268 nested_vmx_succeed(vcpu
);
11269 if (enable_shadow_vmcs
)
11270 vmx
->nested
.sync_shadow_vmcs
= true;
11272 /* in case we halted in L2 */
11273 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11277 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11279 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11281 if (is_guest_mode(vcpu
)) {
11282 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11283 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11285 free_nested(to_vmx(vcpu
));
11289 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11290 * 23.7 "VM-entry failures during or after loading guest state" (this also
11291 * lists the acceptable exit-reason and exit-qualification parameters).
11292 * It should only be called before L2 actually succeeded to run, and when
11293 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11295 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11296 struct vmcs12
*vmcs12
,
11297 u32 reason
, unsigned long qualification
)
11299 load_vmcs12_host_state(vcpu
, vmcs12
);
11300 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11301 vmcs12
->exit_qualification
= qualification
;
11302 nested_vmx_succeed(vcpu
);
11303 if (enable_shadow_vmcs
)
11304 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11307 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11308 struct x86_instruction_info
*info
,
11309 enum x86_intercept_stage stage
)
11311 return X86EMUL_CONTINUE
;
11314 #ifdef CONFIG_X86_64
11315 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11316 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11317 u64 divisor
, u64
*result
)
11319 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11321 /* To avoid the overflow on divq */
11322 if (high
>= divisor
)
11325 /* Low hold the result, high hold rem which is discarded */
11326 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11327 "rm" (divisor
), "0" (low
), "1" (high
));
11333 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11335 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11336 u64 tscl
= rdtsc();
11337 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11338 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11340 /* Convert to host delta tsc if tsc scaling is enabled */
11341 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11342 u64_shl_div_u64(delta_tsc
,
11343 kvm_tsc_scaling_ratio_frac_bits
,
11344 vcpu
->arch
.tsc_scaling_ratio
,
11349 * If the delta tsc can't fit in the 32 bit after the multi shift,
11350 * we can't use the preemption timer.
11351 * It's possible that it fits on later vmentries, but checking
11352 * on every vmentry is costly so we just use an hrtimer.
11354 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11357 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11358 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11359 PIN_BASED_VMX_PREEMPTION_TIMER
);
11361 return delta_tsc
== 0;
11364 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11366 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11367 vmx
->hv_deadline_tsc
= -1;
11368 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11369 PIN_BASED_VMX_PREEMPTION_TIMER
);
11373 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11376 shrink_ple_window(vcpu
);
11379 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11380 struct kvm_memory_slot
*slot
)
11382 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11383 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11386 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11387 struct kvm_memory_slot
*slot
)
11389 kvm_mmu_slot_set_dirty(kvm
, slot
);
11392 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11394 kvm_flush_pml_buffers(kvm
);
11397 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11399 struct vmcs12
*vmcs12
;
11400 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11402 struct page
*page
= NULL
;
11405 if (is_guest_mode(vcpu
)) {
11406 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11409 * Check if PML is enabled for the nested guest.
11410 * Whether eptp bit 6 is set is already checked
11411 * as part of A/D emulation.
11413 vmcs12
= get_vmcs12(vcpu
);
11414 if (!nested_cpu_has_pml(vmcs12
))
11417 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11418 vmx
->nested
.pml_full
= true;
11422 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11424 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11428 pml_address
= kmap(page
);
11429 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11431 nested_release_page_clean(page
);
11437 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11438 struct kvm_memory_slot
*memslot
,
11439 gfn_t offset
, unsigned long mask
)
11441 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11444 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11446 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11447 struct pi_desc old
, new;
11451 old
.control
= new.control
= pi_desc
->control
;
11452 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11453 "Wakeup handler not enabled while the VCPU is blocked\n");
11455 dest
= cpu_physical_id(vcpu
->cpu
);
11457 if (x2apic_enabled())
11460 new.ndst
= (dest
<< 8) & 0xFF00;
11462 /* set 'NV' to 'notification vector' */
11463 new.nv
= POSTED_INTR_VECTOR
;
11464 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11465 new.control
) != old
.control
);
11467 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11468 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11469 list_del(&vcpu
->blocked_vcpu_list
);
11470 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11471 vcpu
->pre_pcpu
= -1;
11476 * This routine does the following things for vCPU which is going
11477 * to be blocked if VT-d PI is enabled.
11478 * - Store the vCPU to the wakeup list, so when interrupts happen
11479 * we can find the right vCPU to wake up.
11480 * - Change the Posted-interrupt descriptor as below:
11481 * 'NDST' <-- vcpu->pre_pcpu
11482 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11483 * - If 'ON' is set during this process, which means at least one
11484 * interrupt is posted for this vCPU, we cannot block it, in
11485 * this case, return 1, otherwise, return 0.
11488 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11491 struct pi_desc old
, new;
11492 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11494 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11495 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11496 !kvm_vcpu_apicv_active(vcpu
))
11499 WARN_ON(irqs_disabled());
11500 local_irq_disable();
11501 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11502 vcpu
->pre_pcpu
= vcpu
->cpu
;
11503 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11504 list_add_tail(&vcpu
->blocked_vcpu_list
,
11505 &per_cpu(blocked_vcpu_on_cpu
,
11507 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11511 old
.control
= new.control
= pi_desc
->control
;
11513 WARN((pi_desc
->sn
== 1),
11514 "Warning: SN field of posted-interrupts "
11515 "is set before blocking\n");
11518 * Since vCPU can be preempted during this process,
11519 * vcpu->cpu could be different with pre_pcpu, we
11520 * need to set pre_pcpu as the destination of wakeup
11521 * notification event, then we can find the right vCPU
11522 * to wakeup in wakeup handler if interrupts happen
11523 * when the vCPU is in blocked state.
11525 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11527 if (x2apic_enabled())
11530 new.ndst
= (dest
<< 8) & 0xFF00;
11532 /* set 'NV' to 'wakeup vector' */
11533 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11534 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11535 new.control
) != old
.control
);
11537 /* We should not block the vCPU if an interrupt is posted for it. */
11538 if (pi_test_on(pi_desc
) == 1)
11539 __pi_post_block(vcpu
);
11541 local_irq_enable();
11542 return (vcpu
->pre_pcpu
== -1);
11545 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11547 if (pi_pre_block(vcpu
))
11550 if (kvm_lapic_hv_timer_in_use(vcpu
))
11551 kvm_lapic_switch_to_sw_timer(vcpu
);
11556 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11558 if (vcpu
->pre_pcpu
== -1)
11561 WARN_ON(irqs_disabled());
11562 local_irq_disable();
11563 __pi_post_block(vcpu
);
11564 local_irq_enable();
11567 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11569 if (kvm_x86_ops
->set_hv_timer
)
11570 kvm_lapic_switch_to_hv_timer(vcpu
);
11572 pi_post_block(vcpu
);
11576 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11579 * @host_irq: host irq of the interrupt
11580 * @guest_irq: gsi of the interrupt
11581 * @set: set or unset PI
11582 * returns 0 on success, < 0 on failure
11584 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11585 uint32_t guest_irq
, bool set
)
11587 struct kvm_kernel_irq_routing_entry
*e
;
11588 struct kvm_irq_routing_table
*irq_rt
;
11589 struct kvm_lapic_irq irq
;
11590 struct kvm_vcpu
*vcpu
;
11591 struct vcpu_data vcpu_info
;
11594 if (!kvm_arch_has_assigned_device(kvm
) ||
11595 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11596 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11599 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11600 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11601 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11602 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11603 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11604 guest_irq
, irq_rt
->nr_rt_entries
);
11608 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11609 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11612 * VT-d PI cannot support posting multicast/broadcast
11613 * interrupts to a vCPU, we still use interrupt remapping
11614 * for these kind of interrupts.
11616 * For lowest-priority interrupts, we only support
11617 * those with single CPU as the destination, e.g. user
11618 * configures the interrupts via /proc/irq or uses
11619 * irqbalance to make the interrupts single-CPU.
11621 * We will support full lowest-priority interrupt later.
11624 kvm_set_msi_irq(kvm
, e
, &irq
);
11625 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11627 * Make sure the IRTE is in remapped mode if
11628 * we don't handle it in posted mode.
11630 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11633 "failed to back to remapped mode, irq: %u\n",
11641 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11642 vcpu_info
.vector
= irq
.vector
;
11644 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11645 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11648 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11650 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11653 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11661 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11665 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11667 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11668 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11669 FEATURE_CONTROL_LMCE
;
11671 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11672 ~FEATURE_CONTROL_LMCE
;
11675 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11676 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11677 .disabled_by_bios
= vmx_disabled_by_bios
,
11678 .hardware_setup
= hardware_setup
,
11679 .hardware_unsetup
= hardware_unsetup
,
11680 .check_processor_compatibility
= vmx_check_processor_compat
,
11681 .hardware_enable
= hardware_enable
,
11682 .hardware_disable
= hardware_disable
,
11683 .cpu_has_accelerated_tpr
= report_flexpriority
,
11684 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11686 .vcpu_create
= vmx_create_vcpu
,
11687 .vcpu_free
= vmx_free_vcpu
,
11688 .vcpu_reset
= vmx_vcpu_reset
,
11690 .prepare_guest_switch
= vmx_save_host_state
,
11691 .vcpu_load
= vmx_vcpu_load
,
11692 .vcpu_put
= vmx_vcpu_put
,
11694 .update_bp_intercept
= update_exception_bitmap
,
11695 .get_msr
= vmx_get_msr
,
11696 .set_msr
= vmx_set_msr
,
11697 .get_segment_base
= vmx_get_segment_base
,
11698 .get_segment
= vmx_get_segment
,
11699 .set_segment
= vmx_set_segment
,
11700 .get_cpl
= vmx_get_cpl
,
11701 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11702 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11703 .decache_cr3
= vmx_decache_cr3
,
11704 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11705 .set_cr0
= vmx_set_cr0
,
11706 .set_cr3
= vmx_set_cr3
,
11707 .set_cr4
= vmx_set_cr4
,
11708 .set_efer
= vmx_set_efer
,
11709 .get_idt
= vmx_get_idt
,
11710 .set_idt
= vmx_set_idt
,
11711 .get_gdt
= vmx_get_gdt
,
11712 .set_gdt
= vmx_set_gdt
,
11713 .get_dr6
= vmx_get_dr6
,
11714 .set_dr6
= vmx_set_dr6
,
11715 .set_dr7
= vmx_set_dr7
,
11716 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11717 .cache_reg
= vmx_cache_reg
,
11718 .get_rflags
= vmx_get_rflags
,
11719 .set_rflags
= vmx_set_rflags
,
11721 .tlb_flush
= vmx_flush_tlb
,
11723 .run
= vmx_vcpu_run
,
11724 .handle_exit
= vmx_handle_exit
,
11725 .skip_emulated_instruction
= skip_emulated_instruction
,
11726 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11727 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11728 .patch_hypercall
= vmx_patch_hypercall
,
11729 .set_irq
= vmx_inject_irq
,
11730 .set_nmi
= vmx_inject_nmi
,
11731 .queue_exception
= vmx_queue_exception
,
11732 .cancel_injection
= vmx_cancel_injection
,
11733 .interrupt_allowed
= vmx_interrupt_allowed
,
11734 .nmi_allowed
= vmx_nmi_allowed
,
11735 .get_nmi_mask
= vmx_get_nmi_mask
,
11736 .set_nmi_mask
= vmx_set_nmi_mask
,
11737 .enable_nmi_window
= enable_nmi_window
,
11738 .enable_irq_window
= enable_irq_window
,
11739 .update_cr8_intercept
= update_cr8_intercept
,
11740 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11741 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11742 .get_enable_apicv
= vmx_get_enable_apicv
,
11743 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11744 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11745 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11746 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11747 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11748 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11749 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11751 .set_tss_addr
= vmx_set_tss_addr
,
11752 .get_tdp_level
= get_ept_level
,
11753 .get_mt_mask
= vmx_get_mt_mask
,
11755 .get_exit_info
= vmx_get_exit_info
,
11757 .get_lpage_level
= vmx_get_lpage_level
,
11759 .cpuid_update
= vmx_cpuid_update
,
11761 .rdtscp_supported
= vmx_rdtscp_supported
,
11762 .invpcid_supported
= vmx_invpcid_supported
,
11764 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11766 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11768 .write_tsc_offset
= vmx_write_tsc_offset
,
11770 .set_tdp_cr3
= vmx_set_cr3
,
11772 .check_intercept
= vmx_check_intercept
,
11773 .handle_external_intr
= vmx_handle_external_intr
,
11774 .mpx_supported
= vmx_mpx_supported
,
11775 .xsaves_supported
= vmx_xsaves_supported
,
11777 .check_nested_events
= vmx_check_nested_events
,
11779 .sched_in
= vmx_sched_in
,
11781 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11782 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11783 .flush_log_dirty
= vmx_flush_log_dirty
,
11784 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11785 .write_log_dirty
= vmx_write_pml_buffer
,
11787 .pre_block
= vmx_pre_block
,
11788 .post_block
= vmx_post_block
,
11790 .pmu_ops
= &intel_pmu_ops
,
11792 .update_pi_irte
= vmx_update_pi_irte
,
11794 #ifdef CONFIG_X86_64
11795 .set_hv_timer
= vmx_set_hv_timer
,
11796 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11799 .setup_mce
= vmx_setup_mce
,
11802 static int __init
vmx_init(void)
11804 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11805 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11809 #ifdef CONFIG_KEXEC_CORE
11810 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11811 crash_vmclear_local_loaded_vmcss
);
11817 static void __exit
vmx_exit(void)
11819 #ifdef CONFIG_KEXEC_CORE
11820 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11827 module_init(vmx_init
)
11828 module_exit(vmx_exit
)