1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_bios.h"
59 #include "intel_dpll_mgr.h"
61 #include "intel_lrc.h"
62 #include "intel_ringbuffer.h"
65 #include "i915_gem_context.h"
66 #include "i915_gem_fence_reg.h"
67 #include "i915_gem_object.h"
68 #include "i915_gem_gtt.h"
69 #include "i915_gem_render_state.h"
70 #include "i915_gem_request.h"
71 #include "i915_gem_timeline.h"
75 #include "intel_gvt.h"
77 /* General customization:
80 #define DRIVER_NAME "i915"
81 #define DRIVER_DESC "Intel Graphics"
82 #define DRIVER_DATE "20170306"
83 #define DRIVER_TIMESTAMP 1488785683
86 /* Many gcc seem to no see through this and fall over :( */
88 #define WARN_ON(x) ({ \
89 bool __i915_warn_cond = (x); \
90 if (__builtin_constant_p(__i915_warn_cond)) \
91 BUILD_BUG_ON(__i915_warn_cond); \
92 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
94 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
98 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
100 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
101 (long) (x), __func__);
103 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
104 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
105 * which may not necessarily be a user visible problem. This will either
106 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
107 * enable distros and users to tailor their preferred amount of i915 abrt
110 #define I915_STATE_WARN(condition, format...) ({ \
111 int __ret_warn_on = !!(condition); \
112 if (unlikely(__ret_warn_on)) \
113 if (!WARN(i915.verbose_state_checks, format)) \
115 unlikely(__ret_warn_on); \
118 #define I915_STATE_WARN_ON(x) \
119 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
121 bool __i915_inject_load_failure(const char *func
, int line
);
122 #define i915_inject_load_failure() \
123 __i915_inject_load_failure(__func__, __LINE__)
127 } uint_fixed_16_16_t
;
129 #define FP_16_16_MAX ({ \
130 uint_fixed_16_16_t fp; \
135 static inline uint_fixed_16_16_t
u32_to_fixed_16_16(uint32_t val
)
137 uint_fixed_16_16_t fp
;
145 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp
)
147 return DIV_ROUND_UP(fp
.val
, 1 << 16);
150 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp
)
155 static inline uint_fixed_16_16_t
min_fixed_16_16(uint_fixed_16_16_t min1
,
156 uint_fixed_16_16_t min2
)
158 uint_fixed_16_16_t min
;
160 min
.val
= min(min1
.val
, min2
.val
);
164 static inline uint_fixed_16_16_t
max_fixed_16_16(uint_fixed_16_16_t max1
,
165 uint_fixed_16_16_t max2
)
167 uint_fixed_16_16_t max
;
169 max
.val
= max(max1
.val
, max2
.val
);
173 static inline uint_fixed_16_16_t
fixed_16_16_div_round_up(uint32_t val
,
176 uint_fixed_16_16_t fp
, res
;
178 fp
= u32_to_fixed_16_16(val
);
179 res
.val
= DIV_ROUND_UP(fp
.val
, d
);
183 static inline uint_fixed_16_16_t
fixed_16_16_div_round_up_u64(uint32_t val
,
186 uint_fixed_16_16_t res
;
189 interm_val
= (uint64_t)val
<< 16;
190 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
191 WARN_ON(interm_val
>> 32);
192 res
.val
= (uint32_t) interm_val
;
197 static inline uint_fixed_16_16_t
mul_u32_fixed_16_16(uint32_t val
,
198 uint_fixed_16_16_t mul
)
200 uint64_t intermediate_val
;
201 uint_fixed_16_16_t fp
;
203 intermediate_val
= (uint64_t) val
* mul
.val
;
204 WARN_ON(intermediate_val
>> 32);
205 fp
.val
= (uint32_t) intermediate_val
;
209 static inline const char *yesno(bool v
)
211 return v
? "yes" : "no";
214 static inline const char *onoff(bool v
)
216 return v
? "on" : "off";
219 static inline const char *enableddisabled(bool v
)
221 return v
? "enabled" : "disabled";
230 I915_MAX_PIPES
= _PIPE_EDP
232 #define pipe_name(p) ((p) + 'A')
244 static inline const char *transcoder_name(enum transcoder transcoder
)
246 switch (transcoder
) {
255 case TRANSCODER_DSI_A
:
257 case TRANSCODER_DSI_C
:
264 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
266 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
270 * Global legacy plane identifier. Valid only for primary/sprite
271 * planes on pre-g4x, and only for primary planes on g4x+.
278 #define plane_name(p) ((p) + 'A')
280 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
283 * Per-pipe plane identifier.
284 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
285 * number of planes per CRTC. Not all platforms really have this many planes,
286 * which means some arrays of size I915_MAX_PLANES may have unused entries
287 * between the topmost sprite plane and the cursor plane.
289 * This is expected to be passed to various register macros
290 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
301 #define for_each_plane_id_on_crtc(__crtc, __p) \
302 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
303 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
314 #define port_name(p) ((p) + 'A')
316 #define I915_NUM_PHYS_VLV 2
329 enum intel_display_power_domain
{
333 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
334 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
335 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
336 POWER_DOMAIN_TRANSCODER_A
,
337 POWER_DOMAIN_TRANSCODER_B
,
338 POWER_DOMAIN_TRANSCODER_C
,
339 POWER_DOMAIN_TRANSCODER_EDP
,
340 POWER_DOMAIN_TRANSCODER_DSI_A
,
341 POWER_DOMAIN_TRANSCODER_DSI_C
,
342 POWER_DOMAIN_PORT_DDI_A_LANES
,
343 POWER_DOMAIN_PORT_DDI_B_LANES
,
344 POWER_DOMAIN_PORT_DDI_C_LANES
,
345 POWER_DOMAIN_PORT_DDI_D_LANES
,
346 POWER_DOMAIN_PORT_DDI_E_LANES
,
347 POWER_DOMAIN_PORT_DDI_A_IO
,
348 POWER_DOMAIN_PORT_DDI_B_IO
,
349 POWER_DOMAIN_PORT_DDI_C_IO
,
350 POWER_DOMAIN_PORT_DDI_D_IO
,
351 POWER_DOMAIN_PORT_DDI_E_IO
,
352 POWER_DOMAIN_PORT_DSI
,
353 POWER_DOMAIN_PORT_CRT
,
354 POWER_DOMAIN_PORT_OTHER
,
363 POWER_DOMAIN_MODESET
,
369 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
370 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
371 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
372 #define POWER_DOMAIN_TRANSCODER(tran) \
373 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
374 (tran) + POWER_DOMAIN_TRANSCODER_A)
378 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
390 #define for_each_hpd_pin(__pin) \
391 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
393 #define HPD_STORM_DEFAULT_THRESHOLD 5
395 struct i915_hotplug
{
396 struct work_struct hotplug_work
;
399 unsigned long last_jiffies
;
404 HPD_MARK_DISABLED
= 2
406 } stats
[HPD_NUM_PINS
];
408 struct delayed_work reenable_work
;
410 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
413 struct work_struct dig_port_work
;
415 struct work_struct poll_init_work
;
418 unsigned int hpd_storm_threshold
;
421 * if we get a HPD irq from DP and a HPD irq from non-DP
422 * the non-DP HPD could block the workqueue on a mode config
423 * mutex getting, that userspace may have taken. However
424 * userspace is waiting on the DP workqueue to run which is
425 * blocked behind the non-DP one.
427 struct workqueue_struct
*dp_wq
;
430 #define I915_GEM_GPU_DOMAINS \
431 (I915_GEM_DOMAIN_RENDER | \
432 I915_GEM_DOMAIN_SAMPLER | \
433 I915_GEM_DOMAIN_COMMAND | \
434 I915_GEM_DOMAIN_INSTRUCTION | \
435 I915_GEM_DOMAIN_VERTEX)
437 #define for_each_pipe(__dev_priv, __p) \
438 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
439 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
440 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
441 for_each_if ((__mask) & (1 << (__p)))
442 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
444 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
446 #define for_each_sprite(__dev_priv, __p, __s) \
448 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
451 #define for_each_port_masked(__port, __ports_mask) \
452 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
453 for_each_if ((__ports_mask) & (1 << (__port)))
455 #define for_each_crtc(dev, crtc) \
456 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
458 #define for_each_intel_plane(dev, intel_plane) \
459 list_for_each_entry(intel_plane, \
460 &(dev)->mode_config.plane_list, \
463 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
464 list_for_each_entry(intel_plane, \
465 &(dev)->mode_config.plane_list, \
467 for_each_if ((plane_mask) & \
468 (1 << drm_plane_index(&intel_plane->base)))
470 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
471 list_for_each_entry(intel_plane, \
472 &(dev)->mode_config.plane_list, \
474 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
476 #define for_each_intel_crtc(dev, intel_crtc) \
477 list_for_each_entry(intel_crtc, \
478 &(dev)->mode_config.crtc_list, \
481 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
482 list_for_each_entry(intel_crtc, \
483 &(dev)->mode_config.crtc_list, \
485 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
487 #define for_each_intel_encoder(dev, intel_encoder) \
488 list_for_each_entry(intel_encoder, \
489 &(dev)->mode_config.encoder_list, \
492 #define for_each_intel_connector_iter(intel_connector, iter) \
493 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
495 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
496 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
497 for_each_if ((intel_encoder)->base.crtc == (__crtc))
499 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
500 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
501 for_each_if ((intel_connector)->base.encoder == (__encoder))
503 #define for_each_power_domain(domain, mask) \
504 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
505 for_each_if (BIT_ULL(domain) & (mask))
507 #define for_each_power_well(__dev_priv, __power_well) \
508 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
509 (__power_well) - (__dev_priv)->power_domains.power_wells < \
510 (__dev_priv)->power_domains.power_well_count; \
513 #define for_each_power_well_rev(__dev_priv, __power_well) \
514 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
515 (__dev_priv)->power_domains.power_well_count - 1; \
516 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
519 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
520 for_each_power_well(__dev_priv, __power_well) \
521 for_each_if ((__power_well)->domains & (__domain_mask))
523 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
524 for_each_power_well_rev(__dev_priv, __power_well) \
525 for_each_if ((__power_well)->domains & (__domain_mask))
527 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
529 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
530 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
531 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
533 for_each_if (plane_state)
535 struct drm_i915_private
;
536 struct i915_mm_struct
;
537 struct i915_mmu_object
;
539 struct drm_i915_file_private
{
540 struct drm_i915_private
*dev_priv
;
541 struct drm_file
*file
;
545 struct list_head request_list
;
546 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
547 * chosen to prevent the CPU getting more than a frame ahead of the GPU
548 * (when using lax throttling for the frontbuffer). We also use it to
549 * offer free GPU waitboosts for severely congested workloads.
551 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
553 struct idr context_idr
;
555 struct intel_rps_client
{
556 struct list_head link
;
560 unsigned int bsd_engine
;
562 /* Client can have a maximum of 3 contexts banned before
563 * it is denied of creating new contexts. As one context
564 * ban needs 4 consecutive hangs, and more if there is
565 * progress in between, this is a last resort stop gap measure
566 * to limit the badly behaving clients access to gpu.
568 #define I915_MAX_CLIENT_CONTEXT_BANS 3
572 /* Used by dp and fdi links */
573 struct intel_link_m_n
{
581 void intel_link_compute_m_n(int bpp
, int nlanes
,
582 int pixel_clock
, int link_clock
,
583 struct intel_link_m_n
*m_n
);
585 /* Interface history:
588 * 1.2: Add Power Management
589 * 1.3: Add vblank support
590 * 1.4: Fix cmdbuffer path, add heap destroy
591 * 1.5: Add vblank pipe configuration
592 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
593 * - Support vertical blank on secondary display pipe
595 #define DRIVER_MAJOR 1
596 #define DRIVER_MINOR 6
597 #define DRIVER_PATCHLEVEL 0
599 struct opregion_header
;
600 struct opregion_acpi
;
601 struct opregion_swsci
;
602 struct opregion_asle
;
604 struct intel_opregion
{
605 struct opregion_header
*header
;
606 struct opregion_acpi
*acpi
;
607 struct opregion_swsci
*swsci
;
608 u32 swsci_gbda_sub_functions
;
609 u32 swsci_sbcb_sub_functions
;
610 struct opregion_asle
*asle
;
615 struct work_struct asle_work
;
617 #define OPREGION_SIZE (8*1024)
619 struct intel_overlay
;
620 struct intel_overlay_error_state
;
622 struct sdvo_device_mapping
{
631 struct intel_connector
;
632 struct intel_encoder
;
633 struct intel_atomic_state
;
634 struct intel_crtc_state
;
635 struct intel_initial_plane_config
;
639 struct intel_cdclk_state
;
641 struct drm_i915_display_funcs
{
642 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
643 struct intel_cdclk_state
*cdclk_state
);
644 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
645 const struct intel_cdclk_state
*cdclk_state
);
646 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
647 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
648 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
649 struct intel_crtc
*intel_crtc
,
650 struct intel_crtc_state
*newstate
);
651 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
652 struct intel_crtc_state
*cstate
);
653 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
654 struct intel_crtc_state
*cstate
);
655 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
656 struct intel_crtc_state
*cstate
);
657 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
658 void (*update_wm
)(struct intel_crtc
*crtc
);
659 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
660 /* Returns the active state of the crtc, and if the crtc is active,
661 * fills out the pipe-config with the hw state. */
662 bool (*get_pipe_config
)(struct intel_crtc
*,
663 struct intel_crtc_state
*);
664 void (*get_initial_plane_config
)(struct intel_crtc
*,
665 struct intel_initial_plane_config
*);
666 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
667 struct intel_crtc_state
*crtc_state
);
668 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
669 struct drm_atomic_state
*old_state
);
670 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
671 struct drm_atomic_state
*old_state
);
672 void (*update_crtcs
)(struct drm_atomic_state
*state
,
673 unsigned int *crtc_vblank_mask
);
674 void (*audio_codec_enable
)(struct drm_connector
*connector
,
675 struct intel_encoder
*encoder
,
676 const struct drm_display_mode
*adjusted_mode
);
677 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
678 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
679 const struct intel_crtc_state
*crtc_state
);
680 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
681 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
682 struct drm_framebuffer
*fb
,
683 struct drm_i915_gem_object
*obj
,
684 struct drm_i915_gem_request
*req
,
686 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
687 /* clock updates for mode set */
689 /* render clock increase/decrease */
690 /* display clock increase/decrease */
691 /* pll clock increase/decrease */
693 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
694 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
697 enum forcewake_domain_id
{
698 FW_DOMAIN_ID_RENDER
= 0,
699 FW_DOMAIN_ID_BLITTER
,
705 enum forcewake_domains
{
706 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
707 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
708 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
709 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
714 #define FW_REG_READ (1)
715 #define FW_REG_WRITE (2)
717 enum decoupled_power_domain
{
718 GEN9_DECOUPLED_PD_BLITTER
= 0,
719 GEN9_DECOUPLED_PD_RENDER
,
720 GEN9_DECOUPLED_PD_MEDIA
,
721 GEN9_DECOUPLED_PD_ALL
725 GEN9_DECOUPLED_OP_WRITE
= 0,
726 GEN9_DECOUPLED_OP_READ
729 enum forcewake_domains
730 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
731 i915_reg_t reg
, unsigned int op
);
733 struct intel_uncore_funcs
{
734 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
735 enum forcewake_domains domains
);
736 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
737 enum forcewake_domains domains
);
739 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
740 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
741 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
742 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
744 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
745 uint8_t val
, bool trace
);
746 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
747 uint16_t val
, bool trace
);
748 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
749 uint32_t val
, bool trace
);
752 struct intel_forcewake_range
{
756 enum forcewake_domains domains
;
759 struct intel_uncore
{
760 spinlock_t lock
; /** lock is also taken in irq contexts. */
762 const struct intel_forcewake_range
*fw_domains_table
;
763 unsigned int fw_domains_table_entries
;
765 struct notifier_block pmic_bus_access_nb
;
766 struct intel_uncore_funcs funcs
;
770 enum forcewake_domains fw_domains
;
771 enum forcewake_domains fw_domains_active
;
773 struct intel_uncore_forcewake_domain
{
774 struct drm_i915_private
*i915
;
775 enum forcewake_domain_id id
;
776 enum forcewake_domains mask
;
778 struct hrtimer timer
;
785 } fw_domain
[FW_DOMAIN_ID_COUNT
];
787 int unclaimed_mmio_check
;
790 /* Iterate over initialised fw domains */
791 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
792 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
793 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
795 for_each_if ((mask__) & (domain__)->mask)
797 #define for_each_fw_domain(domain__, dev_priv__) \
798 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
800 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
801 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
802 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
805 struct work_struct work
;
807 uint32_t *dmc_payload
;
808 uint32_t dmc_fw_size
;
811 i915_reg_t mmioaddr
[8];
812 uint32_t mmiodata
[8];
814 uint32_t allowed_dc_mask
;
817 #define DEV_INFO_FOR_EACH_FLAG(func) \
820 func(is_alpha_support); \
821 /* Keep has_* in alphabetical order */ \
822 func(has_64bit_reloc); \
823 func(has_aliasing_ppgtt); \
826 func(has_decoupled_mmio); \
829 func(has_fpga_dbg); \
830 func(has_full_ppgtt); \
831 func(has_full_48bit_ppgtt); \
832 func(has_gmbus_irq); \
833 func(has_gmch_display); \
836 func(has_hw_contexts); \
839 func(has_logical_ring_contexts); \
841 func(has_pipe_cxsr); \
842 func(has_pooled_eu); \
846 func(has_resource_streamer); \
847 func(has_runtime_pm); \
849 func(cursor_needs_physical); \
850 func(hws_needs_physical); \
851 func(overlay_needs_physical); \
854 struct sseu_dev_info
{
860 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
863 u8 has_subslice_pg
:1;
867 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
869 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
872 /* Keep in gen based order, and chronological order within a gen */
873 enum intel_platform
{
874 INTEL_PLATFORM_UNINITIALIZED
= 0,
903 struct intel_device_info
{
904 u32 display_mmio_offset
;
907 u8 num_sprites
[I915_MAX_PIPES
];
908 u8 num_scalers
[I915_MAX_PIPES
];
911 enum intel_platform platform
;
912 u8 ring_mask
; /* Rings supported by the HW */
914 #define DEFINE_FLAG(name) u8 name:1
915 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
917 u16 ddb_size
; /* in blocks */
918 /* Register offsets for the various display pipes and transcoders */
919 int pipe_offsets
[I915_MAX_TRANSCODERS
];
920 int trans_offsets
[I915_MAX_TRANSCODERS
];
921 int palette_offsets
[I915_MAX_PIPES
];
922 int cursor_offsets
[I915_MAX_PIPES
];
924 /* Slice/subslice/EU info */
925 struct sseu_dev_info sseu
;
928 u16 degamma_lut_size
;
933 struct intel_display_error_state
;
935 struct i915_gpu_state
{
938 struct timeval boottime
;
939 struct timeval uptime
;
941 struct drm_i915_private
*i915
;
951 struct intel_device_info device_info
;
952 struct i915_params params
;
954 /* Generic register state */
958 u32 gtier
[4], ngtier
;
962 u32 error
; /* gen6+ */
963 u32 err_int
; /* gen7 */
964 u32 fault_data0
; /* gen8, gen9 */
965 u32 fault_data1
; /* gen8, gen9 */
973 u64 fence
[I915_MAX_NUM_FENCES
];
974 struct intel_overlay_error_state
*overlay
;
975 struct intel_display_error_state
*display
;
976 struct drm_i915_error_object
*semaphore
;
977 struct drm_i915_error_object
*guc_log
;
979 struct drm_i915_error_engine
{
981 /* Software tracked state */
984 unsigned long hangcheck_timestamp
;
985 bool hangcheck_stalled
;
986 enum intel_engine_hangcheck_action hangcheck_action
;
987 struct i915_address_space
*vm
;
990 /* position of active request inside the ring */
991 u32 rq_head
, rq_post
, rq_tail
;
993 /* our own tracking of ring head and tail */
1016 u32 rc_psmi
; /* sleep state */
1017 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
1018 struct intel_instdone instdone
;
1020 struct drm_i915_error_context
{
1021 char comm
[TASK_COMM_LEN
];
1030 struct drm_i915_error_object
{
1036 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
1038 struct drm_i915_error_object
*wa_ctx
;
1040 struct drm_i915_error_request
{
1048 } *requests
, execlist
[2];
1050 struct drm_i915_error_waiter
{
1051 char comm
[TASK_COMM_LEN
];
1063 } engine
[I915_NUM_ENGINES
];
1065 struct drm_i915_error_buffer
{
1068 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1072 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1079 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1080 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1081 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1084 enum i915_cache_level
{
1085 I915_CACHE_NONE
= 0,
1086 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1087 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1088 caches, eg sampler/render caches, and the
1089 large Last-Level-Cache. LLC is coherent with
1090 the CPU, but L3 is only visible to the GPU. */
1091 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1094 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1105 /* This is always the inner lock when overlapping with struct_mutex and
1106 * it's the outer lock when overlapping with stolen_lock. */
1109 unsigned int possible_framebuffer_bits
;
1110 unsigned int busy_bits
;
1111 unsigned int visible_pipes_mask
;
1112 struct intel_crtc
*crtc
;
1114 struct drm_mm_node compressed_fb
;
1115 struct drm_mm_node
*compressed_llb
;
1122 bool underrun_detected
;
1123 struct work_struct underrun_work
;
1125 struct intel_fbc_state_cache
{
1126 struct i915_vma
*vma
;
1129 unsigned int mode_flags
;
1130 uint32_t hsw_bdw_pixel_rate
;
1134 unsigned int rotation
;
1141 const struct drm_format_info
*format
;
1142 unsigned int stride
;
1146 struct intel_fbc_reg_params
{
1147 struct i915_vma
*vma
;
1152 unsigned int fence_y_offset
;
1156 const struct drm_format_info
*format
;
1157 unsigned int stride
;
1163 struct intel_fbc_work
{
1165 u32 scheduled_vblank
;
1166 struct work_struct work
;
1169 const char *no_fbc_reason
;
1173 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1174 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1175 * parsing for same resolution.
1177 enum drrs_refresh_rate_type
{
1180 DRRS_MAX_RR
, /* RR count */
1183 enum drrs_support_type
{
1184 DRRS_NOT_SUPPORTED
= 0,
1185 STATIC_DRRS_SUPPORT
= 1,
1186 SEAMLESS_DRRS_SUPPORT
= 2
1192 struct delayed_work work
;
1193 struct intel_dp
*dp
;
1194 unsigned busy_frontbuffer_bits
;
1195 enum drrs_refresh_rate_type refresh_rate_type
;
1196 enum drrs_support_type type
;
1203 struct intel_dp
*enabled
;
1205 struct delayed_work work
;
1206 unsigned busy_frontbuffer_bits
;
1208 bool aux_frame_sync
;
1210 bool y_cord_support
;
1211 bool colorimetry_support
;
1216 PCH_NONE
= 0, /* No PCH present */
1217 PCH_IBX
, /* Ibexpeak PCH */
1218 PCH_CPT
, /* Cougarpoint PCH */
1219 PCH_LPT
, /* Lynxpoint PCH */
1220 PCH_SPT
, /* Sunrisepoint PCH */
1221 PCH_KBP
, /* Kabypoint PCH */
1225 enum intel_sbi_destination
{
1230 #define QUIRK_PIPEA_FORCE (1<<0)
1231 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1232 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1233 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1234 #define QUIRK_PIPEB_FORCE (1<<4)
1235 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1238 struct intel_fbc_work
;
1240 struct intel_gmbus
{
1241 struct i2c_adapter adapter
;
1242 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1245 i915_reg_t gpio_reg
;
1246 struct i2c_algo_bit_data bit_algo
;
1247 struct drm_i915_private
*dev_priv
;
1250 struct i915_suspend_saved_registers
{
1252 u32 saveFBC_CONTROL
;
1253 u32 saveCACHE_MODE_0
;
1254 u32 saveMI_ARB_STATE
;
1258 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1259 u32 savePCH_PORT_HOTPLUG
;
1263 struct vlv_s0ix_state
{
1270 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1271 u32 media_max_req_count
;
1272 u32 gfx_max_req_count
;
1298 u32 rp_down_timeout
;
1304 /* Display 1 CZ domain */
1309 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1311 /* GT SA CZ domain */
1318 /* Display 2 CZ domain */
1322 u32 clock_gate_dis2
;
1325 struct intel_rps_ei
{
1331 struct intel_gen6_power_mgmt
{
1333 * work, interrupts_enabled and pm_iir are protected by
1334 * dev_priv->irq_lock
1336 struct work_struct work
;
1337 bool interrupts_enabled
;
1340 /* PM interrupt bits that should never be masked */
1343 /* Frequencies are stored in potentially platform dependent multiples.
1344 * In other words, *_freq needs to be multiplied by X to be interesting.
1345 * Soft limits are those which are used for the dynamic reclocking done
1346 * by the driver (raise frequencies under heavy loads, and lower for
1347 * lighter loads). Hard limits are those imposed by the hardware.
1349 * A distinction is made for overclocking, which is never enabled by
1350 * default, and is considered to be above the hard limit if it's
1353 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1354 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1355 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1356 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1357 u8 min_freq
; /* AKA RPn. Minimum frequency */
1358 u8 boost_freq
; /* Frequency to request when wait boosting */
1359 u8 idle_freq
; /* Frequency to request when we are idle */
1360 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1361 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1362 u8 rp0_freq
; /* Non-overclocked max frequency. */
1363 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1365 u8 up_threshold
; /* Current %busy required to uplock */
1366 u8 down_threshold
; /* Current %busy required to downclock */
1369 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1371 spinlock_t client_lock
;
1372 struct list_head clients
;
1376 struct delayed_work autoenable_work
;
1379 /* manual wa residency calculations */
1380 struct intel_rps_ei ei
;
1383 * Protects RPS/RC6 register access and PCU communication.
1384 * Must be taken after struct_mutex if nested. Note that
1385 * this lock may be held for long periods of time when
1386 * talking to hw - so only take it when talking to hw!
1388 struct mutex hw_lock
;
1391 /* defined intel_pm.c */
1392 extern spinlock_t mchdev_lock
;
1394 struct intel_ilk_power_mgmt
{
1402 unsigned long last_time1
;
1403 unsigned long chipset_power
;
1406 unsigned long gfx_power
;
1413 struct drm_i915_private
;
1414 struct i915_power_well
;
1416 struct i915_power_well_ops
{
1418 * Synchronize the well's hw state to match the current sw state, for
1419 * example enable/disable it based on the current refcount. Called
1420 * during driver init and resume time, possibly after first calling
1421 * the enable/disable handlers.
1423 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1424 struct i915_power_well
*power_well
);
1426 * Enable the well and resources that depend on it (for example
1427 * interrupts located on the well). Called after the 0->1 refcount
1430 void (*enable
)(struct drm_i915_private
*dev_priv
,
1431 struct i915_power_well
*power_well
);
1433 * Disable the well and resources that depend on it. Called after
1434 * the 1->0 refcount transition.
1436 void (*disable
)(struct drm_i915_private
*dev_priv
,
1437 struct i915_power_well
*power_well
);
1438 /* Returns the hw enabled state. */
1439 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1440 struct i915_power_well
*power_well
);
1443 /* Power well structure for haswell */
1444 struct i915_power_well
{
1447 /* power well enable/disable usage count */
1449 /* cached hw enabled state */
1452 /* unique identifier for this power well */
1455 * Arbitraty data associated with this power well. Platform and power
1459 const struct i915_power_well_ops
*ops
;
1462 struct i915_power_domains
{
1464 * Power wells needed for initialization at driver init and suspend
1465 * time are on. They are kept on until after the first modeset.
1469 int power_well_count
;
1472 int domain_use_count
[POWER_DOMAIN_NUM
];
1473 struct i915_power_well
*power_wells
;
1476 #define MAX_L3_SLICES 2
1477 struct intel_l3_parity
{
1478 u32
*remap_info
[MAX_L3_SLICES
];
1479 struct work_struct error_work
;
1483 struct i915_gem_mm
{
1484 /** Memory allocator for GTT stolen memory */
1485 struct drm_mm stolen
;
1486 /** Protects the usage of the GTT stolen memory allocator. This is
1487 * always the inner lock when overlapping with struct_mutex. */
1488 struct mutex stolen_lock
;
1490 /** List of all objects in gtt_space. Used to restore gtt
1491 * mappings on resume */
1492 struct list_head bound_list
;
1494 * List of objects which are not bound to the GTT (thus
1495 * are idle and not used by the GPU). These objects may or may
1496 * not actually have any pages attached.
1498 struct list_head unbound_list
;
1500 /** List of all objects in gtt_space, currently mmaped by userspace.
1501 * All objects within this list must also be on bound_list.
1503 struct list_head userfault_list
;
1506 * List of objects which are pending destruction.
1508 struct llist_head free_list
;
1509 struct work_struct free_work
;
1511 /** Usable portion of the GTT for GEM */
1512 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1514 /** PPGTT used for aliasing the PPGTT with the GTT */
1515 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1517 struct notifier_block oom_notifier
;
1518 struct notifier_block vmap_notifier
;
1519 struct shrinker shrinker
;
1521 /** LRU list of objects with fence regs on them. */
1522 struct list_head fence_list
;
1525 * Are we in a non-interruptible section of code like
1530 /* the indicator for dispatch video commands on two BSD rings */
1531 atomic_t bsd_engine_dispatch_index
;
1533 /** Bit 6 swizzling required for X tiling */
1534 uint32_t bit_6_swizzle_x
;
1535 /** Bit 6 swizzling required for Y tiling */
1536 uint32_t bit_6_swizzle_y
;
1538 /* accounting, useful for userland debugging */
1539 spinlock_t object_stat_lock
;
1544 struct drm_i915_error_state_buf
{
1545 struct drm_i915_private
*i915
;
1554 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1555 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1557 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1558 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1560 struct i915_gpu_error
{
1561 /* For hangcheck timer */
1562 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1563 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1565 struct delayed_work hangcheck_work
;
1567 /* For reset and error_state handling. */
1569 /* Protected by the above dev->gpu_error.lock. */
1570 struct i915_gpu_state
*first_error
;
1572 unsigned long missed_irq_rings
;
1575 * State variable controlling the reset flow and count
1577 * This is a counter which gets incremented when reset is triggered,
1579 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1580 * meaning that any waiters holding onto the struct_mutex should
1581 * relinquish the lock immediately in order for the reset to start.
1583 * If reset is not completed succesfully, the I915_WEDGE bit is
1584 * set meaning that hardware is terminally sour and there is no
1585 * recovery. All waiters on the reset_queue will be woken when
1588 * This counter is used by the wait_seqno code to notice that reset
1589 * event happened and it needs to restart the entire ioctl (since most
1590 * likely the seqno it waited for won't ever signal anytime soon).
1592 * This is important for lock-free wait paths, where no contended lock
1593 * naturally enforces the correct ordering between the bail-out of the
1594 * waiter and the gpu reset work code.
1596 unsigned long reset_count
;
1598 unsigned long flags
;
1599 #define I915_RESET_IN_PROGRESS 0
1600 #define I915_WEDGED (BITS_PER_LONG - 1)
1603 * Waitqueue to signal when a hang is detected. Used to for waiters
1604 * to release the struct_mutex for the reset to procede.
1606 wait_queue_head_t wait_queue
;
1609 * Waitqueue to signal when the reset has completed. Used by clients
1610 * that wait for dev_priv->mm.wedged to settle.
1612 wait_queue_head_t reset_queue
;
1614 /* For missed irq/seqno simulation. */
1615 unsigned long test_irq_rings
;
1618 enum modeset_restore
{
1619 MODESET_ON_LID_OPEN
,
1624 #define DP_AUX_A 0x40
1625 #define DP_AUX_B 0x10
1626 #define DP_AUX_C 0x20
1627 #define DP_AUX_D 0x30
1629 #define DDC_PIN_B 0x05
1630 #define DDC_PIN_C 0x04
1631 #define DDC_PIN_D 0x06
1633 struct ddi_vbt_port_info
{
1635 * This is an index in the HDMI/DVI DDI buffer translation table.
1636 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1637 * populate this field.
1639 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1640 uint8_t hdmi_level_shift
;
1642 uint8_t supports_dvi
:1;
1643 uint8_t supports_hdmi
:1;
1644 uint8_t supports_dp
:1;
1645 uint8_t supports_edp
:1;
1647 uint8_t alternate_aux_channel
;
1648 uint8_t alternate_ddc_pin
;
1650 uint8_t dp_boost_level
;
1651 uint8_t hdmi_boost_level
;
1654 enum psr_lines_to_wait
{
1655 PSR_0_LINES_TO_WAIT
= 0,
1657 PSR_4_LINES_TO_WAIT
,
1661 struct intel_vbt_data
{
1662 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1663 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1666 unsigned int int_tv_support
:1;
1667 unsigned int lvds_dither
:1;
1668 unsigned int lvds_vbt
:1;
1669 unsigned int int_crt_support
:1;
1670 unsigned int lvds_use_ssc
:1;
1671 unsigned int display_clock_mode
:1;
1672 unsigned int fdi_rx_polarity_inverted
:1;
1673 unsigned int panel_type
:4;
1675 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1677 enum drrs_support_type drrs_type
;
1688 struct edp_power_seq pps
;
1693 bool require_aux_wakeup
;
1695 enum psr_lines_to_wait lines_to_wait
;
1696 int tp1_wakeup_time
;
1697 int tp2_tp3_wakeup_time
;
1703 bool active_low_pwm
;
1704 u8 min_brightness
; /* min_brightness/255 of max */
1705 u8 controller
; /* brightness controller number */
1706 enum intel_backlight_type type
;
1712 struct mipi_config
*config
;
1713 struct mipi_pps_data
*pps
;
1717 const u8
*sequence
[MIPI_SEQ_MAX
];
1723 union child_device_config
*child_dev
;
1725 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1726 struct sdvo_device_mapping sdvo_mappings
[2];
1729 enum intel_ddb_partitioning
{
1731 INTEL_DDB_PART_5_6
, /* IVB+ */
1734 struct intel_wm_level
{
1742 struct ilk_wm_values
{
1743 uint32_t wm_pipe
[3];
1745 uint32_t wm_lp_spr
[3];
1746 uint32_t wm_linetime
[3];
1748 enum intel_ddb_partitioning partitioning
;
1751 struct vlv_pipe_wm
{
1752 uint16_t plane
[I915_MAX_PLANES
];
1760 struct vlv_wm_ddl_values
{
1761 uint8_t plane
[I915_MAX_PLANES
];
1764 struct vlv_wm_values
{
1765 struct vlv_pipe_wm pipe
[3];
1766 struct vlv_sr_wm sr
;
1767 struct vlv_wm_ddl_values ddl
[3];
1772 struct skl_ddb_entry
{
1773 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1776 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1778 return entry
->end
- entry
->start
;
1781 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1782 const struct skl_ddb_entry
*e2
)
1784 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1790 struct skl_ddb_allocation
{
1791 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1792 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1795 struct skl_wm_values
{
1796 unsigned dirty_pipes
;
1797 struct skl_ddb_allocation ddb
;
1800 struct skl_wm_level
{
1802 uint16_t plane_res_b
;
1803 uint8_t plane_res_l
;
1807 * This struct helps tracking the state needed for runtime PM, which puts the
1808 * device in PCI D3 state. Notice that when this happens, nothing on the
1809 * graphics device works, even register access, so we don't get interrupts nor
1812 * Every piece of our code that needs to actually touch the hardware needs to
1813 * either call intel_runtime_pm_get or call intel_display_power_get with the
1814 * appropriate power domain.
1816 * Our driver uses the autosuspend delay feature, which means we'll only really
1817 * suspend if we stay with zero refcount for a certain amount of time. The
1818 * default value is currently very conservative (see intel_runtime_pm_enable), but
1819 * it can be changed with the standard runtime PM files from sysfs.
1821 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1822 * goes back to false exactly before we reenable the IRQs. We use this variable
1823 * to check if someone is trying to enable/disable IRQs while they're supposed
1824 * to be disabled. This shouldn't happen and we'll print some error messages in
1827 * For more, read the Documentation/power/runtime_pm.txt.
1829 struct i915_runtime_pm
{
1830 atomic_t wakeref_count
;
1835 enum intel_pipe_crc_source
{
1836 INTEL_PIPE_CRC_SOURCE_NONE
,
1837 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1838 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1839 INTEL_PIPE_CRC_SOURCE_PF
,
1840 INTEL_PIPE_CRC_SOURCE_PIPE
,
1841 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1842 INTEL_PIPE_CRC_SOURCE_TV
,
1843 INTEL_PIPE_CRC_SOURCE_DP_B
,
1844 INTEL_PIPE_CRC_SOURCE_DP_C
,
1845 INTEL_PIPE_CRC_SOURCE_DP_D
,
1846 INTEL_PIPE_CRC_SOURCE_AUTO
,
1847 INTEL_PIPE_CRC_SOURCE_MAX
,
1850 struct intel_pipe_crc_entry
{
1855 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1856 struct intel_pipe_crc
{
1858 bool opened
; /* exclusive access to the result file */
1859 struct intel_pipe_crc_entry
*entries
;
1860 enum intel_pipe_crc_source source
;
1862 wait_queue_head_t wq
;
1866 struct i915_frontbuffer_tracking
{
1870 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1877 struct i915_wa_reg
{
1880 /* bitmask representing WA bits */
1885 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1886 * allowing it for RCS as we don't foresee any requirement of having
1887 * a whitelist for other engines. When it is really required for
1888 * other engines then the limit need to be increased.
1890 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1892 struct i915_workarounds
{
1893 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1895 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1898 struct i915_virtual_gpu
{
1902 /* used in computing the new watermarks state */
1903 struct intel_wm_config
{
1904 unsigned int num_pipes_active
;
1905 bool sprites_enabled
;
1906 bool sprites_scaled
;
1909 struct i915_oa_format
{
1914 struct i915_oa_reg
{
1919 struct i915_perf_stream
;
1922 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1924 struct i915_perf_stream_ops
{
1926 * @enable: Enables the collection of HW samples, either in response to
1927 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1928 * without `I915_PERF_FLAG_DISABLED`.
1930 void (*enable
)(struct i915_perf_stream
*stream
);
1933 * @disable: Disables the collection of HW samples, either in response
1934 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1937 void (*disable
)(struct i915_perf_stream
*stream
);
1940 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1941 * once there is something ready to read() for the stream
1943 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1948 * @wait_unlocked: For handling a blocking read, wait until there is
1949 * something to ready to read() for the stream. E.g. wait on the same
1950 * wait queue that would be passed to poll_wait().
1952 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1955 * @read: Copy buffered metrics as records to userspace
1956 * **buf**: the userspace, destination buffer
1957 * **count**: the number of bytes to copy, requested by userspace
1958 * **offset**: zero at the start of the read, updated as the read
1959 * proceeds, it represents how many bytes have been copied so far and
1960 * the buffer offset for copying the next record.
1962 * Copy as many buffered i915 perf samples and records for this stream
1963 * to userspace as will fit in the given buffer.
1965 * Only write complete records; returning -%ENOSPC if there isn't room
1966 * for a complete record.
1968 * Return any error condition that results in a short read such as
1969 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1970 * returning to userspace.
1972 int (*read
)(struct i915_perf_stream
*stream
,
1978 * @destroy: Cleanup any stream specific resources.
1980 * The stream will always be disabled before this is called.
1982 void (*destroy
)(struct i915_perf_stream
*stream
);
1986 * struct i915_perf_stream - state for a single open stream FD
1988 struct i915_perf_stream
{
1990 * @dev_priv: i915 drm device
1992 struct drm_i915_private
*dev_priv
;
1995 * @link: Links the stream into ``&drm_i915_private->streams``
1997 struct list_head link
;
2000 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2001 * properties given when opening a stream, representing the contents
2002 * of a single sample as read() by userspace.
2007 * @sample_size: Considering the configured contents of a sample
2008 * combined with the required header size, this is the total size
2009 * of a single sample record.
2014 * @ctx: %NULL if measuring system-wide across all contexts or a
2015 * specific context that is being monitored.
2017 struct i915_gem_context
*ctx
;
2020 * @enabled: Whether the stream is currently enabled, considering
2021 * whether the stream was opened in a disabled state and based
2022 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2027 * @ops: The callbacks providing the implementation of this specific
2028 * type of configured stream.
2030 const struct i915_perf_stream_ops
*ops
;
2034 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2036 struct i915_oa_ops
{
2038 * @init_oa_buffer: Resets the head and tail pointers of the
2039 * circular buffer for periodic OA reports.
2041 * Called when first opening a stream for OA metrics, but also may be
2042 * called in response to an OA buffer overflow or other error
2045 * Note it may be necessary to clear the full OA buffer here as part of
2046 * maintaining the invariable that new reports must be written to
2047 * zeroed memory for us to be able to reliable detect if an expected
2048 * report has not yet landed in memory. (At least on Haswell the OA
2049 * buffer tail pointer is not synchronized with reports being visible
2052 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2055 * @enable_metric_set: Applies any MUX configuration to set up the
2056 * Boolean and Custom (B/C) counters that are part of the counter
2057 * reports being sampled. May apply system constraints such as
2058 * disabling EU clock gating as required.
2060 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
);
2063 * @disable_metric_set: Remove system constraints associated with using
2066 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2069 * @oa_enable: Enable periodic sampling
2071 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2074 * @oa_disable: Disable periodic sampling
2076 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2079 * @read: Copy data from the circular OA buffer into a given userspace
2082 int (*read
)(struct i915_perf_stream
*stream
,
2088 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2090 * This is either called via fops or the poll check hrtimer (atomic
2091 * ctx) without any locks taken.
2093 * It's safe to read OA config state here unlocked, assuming that this
2094 * is only called while the stream is enabled, while the global OA
2095 * configuration can't be modified.
2097 * Efficiency is more important than avoiding some false positives
2098 * here, which will be handled gracefully - likely resulting in an
2099 * %EAGAIN error for userspace.
2101 bool (*oa_buffer_is_empty
)(struct drm_i915_private
*dev_priv
);
2104 struct intel_cdclk_state
{
2105 unsigned int cdclk
, vco
, ref
;
2108 struct drm_i915_private
{
2109 struct drm_device drm
;
2111 struct kmem_cache
*objects
;
2112 struct kmem_cache
*vmas
;
2113 struct kmem_cache
*requests
;
2114 struct kmem_cache
*dependencies
;
2116 const struct intel_device_info info
;
2120 struct intel_uncore uncore
;
2122 struct i915_virtual_gpu vgpu
;
2124 struct intel_gvt
*gvt
;
2126 struct intel_huc huc
;
2127 struct intel_guc guc
;
2129 struct intel_csr csr
;
2131 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2133 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2134 * controller on different i2c buses. */
2135 struct mutex gmbus_mutex
;
2138 * Base address of the gmbus and gpio block.
2140 uint32_t gpio_mmio_base
;
2142 /* MMIO base address for MIPI regs */
2143 uint32_t mipi_mmio_base
;
2145 uint32_t psr_mmio_base
;
2147 uint32_t pps_mmio_base
;
2149 wait_queue_head_t gmbus_wait_queue
;
2151 struct pci_dev
*bridge_dev
;
2152 struct i915_gem_context
*kernel_context
;
2153 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2154 struct i915_vma
*semaphore
;
2156 struct drm_dma_handle
*status_page_dmah
;
2157 struct resource mch_res
;
2159 /* protects the irq masks */
2160 spinlock_t irq_lock
;
2162 /* protects the mmio flip data */
2163 spinlock_t mmio_flip_lock
;
2165 bool display_irqs_enabled
;
2167 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2168 struct pm_qos_request pm_qos
;
2170 /* Sideband mailbox protection */
2171 struct mutex sb_lock
;
2173 /** Cached value of IMR to avoid reads in updating the bitfield */
2176 u32 de_irq_mask
[I915_MAX_PIPES
];
2183 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2185 struct i915_hotplug hotplug
;
2186 struct intel_fbc fbc
;
2187 struct i915_drrs drrs
;
2188 struct intel_opregion opregion
;
2189 struct intel_vbt_data vbt
;
2191 bool preserve_bios_swizzle
;
2194 struct intel_overlay
*overlay
;
2196 /* backlight registers and fields in struct intel_panel */
2197 struct mutex backlight_lock
;
2200 bool no_aux_handshake
;
2202 /* protects panel power sequencer state */
2203 struct mutex pps_mutex
;
2205 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2206 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2208 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2209 unsigned int skl_preferred_vco_freq
;
2210 unsigned int max_cdclk_freq
;
2212 unsigned int max_dotclk_freq
;
2213 unsigned int rawclk_freq
;
2214 unsigned int hpll_freq
;
2215 unsigned int czclk_freq
;
2219 * The current logical cdclk state.
2220 * See intel_atomic_state.cdclk.logical
2222 * For reading holding any crtc lock is sufficient,
2223 * for writing must hold all of them.
2225 struct intel_cdclk_state logical
;
2227 * The current actual cdclk state.
2228 * See intel_atomic_state.cdclk.actual
2230 struct intel_cdclk_state actual
;
2231 /* The current hardware cdclk state */
2232 struct intel_cdclk_state hw
;
2236 * wq - Driver workqueue for GEM.
2238 * NOTE: Work items scheduled here are not allowed to grab any modeset
2239 * locks, for otherwise the flushing done in the pageflip code will
2240 * result in deadlocks.
2242 struct workqueue_struct
*wq
;
2244 /* Display functions */
2245 struct drm_i915_display_funcs display
;
2247 /* PCH chipset type */
2248 enum intel_pch pch_type
;
2249 unsigned short pch_id
;
2251 unsigned long quirks
;
2253 enum modeset_restore modeset_restore
;
2254 struct mutex modeset_restore_lock
;
2255 struct drm_atomic_state
*modeset_restore_state
;
2256 struct drm_modeset_acquire_ctx reset_ctx
;
2258 struct list_head vm_list
; /* Global list of all address spaces */
2259 struct i915_ggtt ggtt
; /* VM representing the global address space */
2261 struct i915_gem_mm mm
;
2262 DECLARE_HASHTABLE(mm_structs
, 7);
2263 struct mutex mm_lock
;
2265 /* The hw wants to have a stable context identifier for the lifetime
2266 * of the context (for OA, PASID, faults, etc). This is limited
2267 * in execlists to 21 bits.
2269 struct ida context_hw_ida
;
2270 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2272 /* Kernel Modesetting */
2274 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2275 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2276 wait_queue_head_t pending_flip_queue
;
2278 #ifdef CONFIG_DEBUG_FS
2279 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2282 /* dpll and cdclk state is protected by connection_mutex */
2283 int num_shared_dpll
;
2284 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2285 const struct intel_dpll_mgr
*dpll_mgr
;
2288 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2289 * Must be global rather than per dpll, because on some platforms
2290 * plls share registers.
2292 struct mutex dpll_lock
;
2294 unsigned int active_crtcs
;
2295 unsigned int min_pixclk
[I915_MAX_PIPES
];
2297 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2299 struct i915_workarounds workarounds
;
2301 struct i915_frontbuffer_tracking fb_tracking
;
2303 struct intel_atomic_helper
{
2304 struct llist_head free_list
;
2305 struct work_struct free_work
;
2310 bool mchbar_need_disable
;
2312 struct intel_l3_parity l3_parity
;
2314 /* Cannot be determined by PCIID. You must always read a register. */
2317 /* gen6+ rps state */
2318 struct intel_gen6_power_mgmt rps
;
2320 /* ilk-only ips/rps state. Everything in here is protected by the global
2321 * mchdev_lock in intel_pm.c */
2322 struct intel_ilk_power_mgmt ips
;
2324 struct i915_power_domains power_domains
;
2326 struct i915_psr psr
;
2328 struct i915_gpu_error gpu_error
;
2330 struct drm_i915_gem_object
*vlv_pctx
;
2332 #ifdef CONFIG_DRM_FBDEV_EMULATION
2333 /* list of fbdev register on this device */
2334 struct intel_fbdev
*fbdev
;
2335 struct work_struct fbdev_suspend_work
;
2338 struct drm_property
*broadcast_rgb_property
;
2339 struct drm_property
*force_audio_property
;
2341 /* hda/i915 audio component */
2342 struct i915_audio_component
*audio_component
;
2343 bool audio_component_registered
;
2345 * av_mutex - mutex for audio/video sync
2348 struct mutex av_mutex
;
2350 uint32_t hw_context_size
;
2351 struct list_head context_list
;
2355 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2356 u32 chv_phy_control
;
2358 * Shadows for CHV DPLL_MD regs to keep the state
2359 * checker somewhat working in the presence hardware
2360 * crappiness (can't read out DPLL_MD for pipes B & C).
2362 u32 chv_dpll_md
[I915_MAX_PIPES
];
2366 bool suspended_to_idle
;
2367 struct i915_suspend_saved_registers regfile
;
2368 struct vlv_s0ix_state vlv_s0ix_state
;
2371 I915_SAGV_UNKNOWN
= 0,
2374 I915_SAGV_NOT_CONTROLLED
2378 /* protects DSPARB registers on pre-g4x/vlv/chv */
2379 spinlock_t dsparb_lock
;
2382 * Raw watermark latency values:
2383 * in 0.1us units for WM0,
2384 * in 0.5us units for WM1+.
2387 uint16_t pri_latency
[5];
2389 uint16_t spr_latency
[5];
2391 uint16_t cur_latency
[5];
2393 * Raw watermark memory latency values
2394 * for SKL for all 8 levels
2397 uint16_t skl_latency
[8];
2399 /* current hardware state */
2401 struct ilk_wm_values hw
;
2402 struct skl_wm_values skl_hw
;
2403 struct vlv_wm_values vlv
;
2409 * Should be held around atomic WM register writing; also
2410 * protects * intel_crtc->wm.active and
2411 * cstate->wm.need_postvbl_update.
2413 struct mutex wm_mutex
;
2416 * Set during HW readout of watermarks/DDB. Some platforms
2417 * need to know when we're still using BIOS-provided values
2418 * (which we don't fully trust).
2420 bool distrust_bios_wm
;
2423 struct i915_runtime_pm pm
;
2428 struct kobject
*metrics_kobj
;
2429 struct ctl_table_header
*sysctl_header
;
2432 struct list_head streams
;
2434 spinlock_t hook_lock
;
2437 struct i915_perf_stream
*exclusive_stream
;
2439 u32 specific_ctx_id
;
2441 struct hrtimer poll_check_timer
;
2442 wait_queue_head_t poll_wq
;
2446 int period_exponent
;
2447 int timestamp_frequency
;
2453 const struct i915_oa_reg
*mux_regs
;
2455 const struct i915_oa_reg
*b_counter_regs
;
2456 int b_counter_regs_len
;
2459 struct i915_vma
*vma
;
2465 u32 gen7_latched_oastatus1
;
2467 struct i915_oa_ops ops
;
2468 const struct i915_oa_format
*oa_formats
;
2473 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2475 void (*resume
)(struct drm_i915_private
*);
2476 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2478 struct list_head timelines
;
2479 struct i915_gem_timeline global_timeline
;
2480 u32 active_requests
;
2483 * Is the GPU currently considered idle, or busy executing
2484 * userspace requests? Whilst idle, we allow runtime power
2485 * management to power down the hardware and display clocks.
2486 * In order to reduce the effect on performance, there
2487 * is a slight delay before we do so.
2492 * We leave the user IRQ off as much as possible,
2493 * but this means that requests will finish and never
2494 * be retired once the system goes idle. Set a timer to
2495 * fire periodically while the ring is running. When it
2496 * fires, go retire requests.
2498 struct delayed_work retire_work
;
2501 * When we detect an idle GPU, we want to turn on
2502 * powersaving features. So once we see that there
2503 * are no more requests outstanding and no more
2504 * arrive within a small period of time, we fire
2505 * off the idle_work.
2507 struct delayed_work idle_work
;
2509 ktime_t last_init_time
;
2512 /* perform PHY state sanity checks? */
2513 bool chv_phy_assert
[2];
2517 /* Used to save the pipe-to-encoder mapping for audio */
2518 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2520 /* necessary resource sharing with HDMI LPE audio driver. */
2522 struct platform_device
*platdev
;
2527 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2528 * will be rejected. Instead look for a better place.
2532 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2534 return container_of(dev
, struct drm_i915_private
, drm
);
2537 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2539 return to_i915(dev_get_drvdata(kdev
));
2542 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2544 return container_of(guc
, struct drm_i915_private
, guc
);
2547 /* Simple iterator over all initialised engines */
2548 #define for_each_engine(engine__, dev_priv__, id__) \
2550 (id__) < I915_NUM_ENGINES; \
2552 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2554 #define __mask_next_bit(mask) ({ \
2555 int __idx = ffs(mask) - 1; \
2556 mask &= ~BIT(__idx); \
2560 /* Iterator over subset of engines selected by mask */
2561 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2562 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2563 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2565 enum hdmi_force_audio
{
2566 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2567 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2568 HDMI_AUDIO_AUTO
, /* trust EDID */
2569 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2572 #define I915_GTT_OFFSET_NONE ((u32)-1)
2575 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2576 * considered to be the frontbuffer for the given plane interface-wise. This
2577 * doesn't mean that the hw necessarily already scans it out, but that any
2578 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2580 * We have one bit per pipe and per scanout plane type.
2582 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2583 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2584 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2585 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2586 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2587 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2588 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2589 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2590 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2591 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2592 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2593 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2596 * Optimised SGL iterator for GEM objects
2598 static __always_inline
struct sgt_iter
{
2599 struct scatterlist
*sgp
;
2606 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2607 struct sgt_iter s
= { .sgp
= sgl
};
2610 s
.max
= s
.curr
= s
.sgp
->offset
;
2611 s
.max
+= s
.sgp
->length
;
2613 s
.dma
= sg_dma_address(s
.sgp
);
2615 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2621 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2624 if (unlikely(sg_is_chain(sg
)))
2625 sg
= sg_chain_ptr(sg
);
2630 * __sg_next - return the next scatterlist entry in a list
2631 * @sg: The current sg entry
2634 * If the entry is the last, return NULL; otherwise, step to the next
2635 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2636 * otherwise just return the pointer to the current element.
2638 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2640 #ifdef CONFIG_DEBUG_SG
2641 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2643 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2647 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2648 * @__dmap: DMA address (output)
2649 * @__iter: 'struct sgt_iter' (iterator state, internal)
2650 * @__sgt: sg_table to iterate over (input)
2652 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2653 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2654 ((__dmap) = (__iter).dma + (__iter).curr); \
2655 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2656 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2659 * for_each_sgt_page - iterate over the pages of the given sg_table
2660 * @__pp: page pointer (output)
2661 * @__iter: 'struct sgt_iter' (iterator state, internal)
2662 * @__sgt: sg_table to iterate over (input)
2664 #define for_each_sgt_page(__pp, __iter, __sgt) \
2665 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2666 ((__pp) = (__iter).pfn == 0 ? NULL : \
2667 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2668 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2669 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2671 static inline const struct intel_device_info
*
2672 intel_info(const struct drm_i915_private
*dev_priv
)
2674 return &dev_priv
->info
;
2677 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2679 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2680 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2682 #define REVID_FOREVER 0xff
2683 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2685 #define GEN_FOREVER (0)
2687 * Returns true if Gen is in inclusive range [Start, End].
2689 * Use GEN_FOREVER for unbound start and or end.
2691 #define IS_GEN(dev_priv, s, e) ({ \
2692 unsigned int __s = (s), __e = (e); \
2693 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2694 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2695 if ((__s) != GEN_FOREVER) \
2697 if ((__e) == GEN_FOREVER) \
2698 __e = BITS_PER_LONG - 1; \
2701 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2705 * Return true if revision is in range [since,until] inclusive.
2707 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2709 #define IS_REVID(p, since, until) \
2710 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2712 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2713 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2714 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2715 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2716 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2717 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2718 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2719 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2720 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2721 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2722 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2723 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2724 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2725 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2726 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2727 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2728 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2729 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2730 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2731 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2732 INTEL_DEVID(dev_priv) == 0x0152 || \
2733 INTEL_DEVID(dev_priv) == 0x015a)
2734 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2735 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2736 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2737 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2738 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2739 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2740 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2741 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2742 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2743 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2744 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2745 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2746 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2747 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2748 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2749 /* ULX machines are also considered ULT. */
2750 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2751 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2752 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2753 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2754 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2755 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2756 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2757 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2758 /* ULX machines are also considered ULT. */
2759 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2760 INTEL_DEVID(dev_priv) == 0x0A1E)
2761 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2762 INTEL_DEVID(dev_priv) == 0x1913 || \
2763 INTEL_DEVID(dev_priv) == 0x1916 || \
2764 INTEL_DEVID(dev_priv) == 0x1921 || \
2765 INTEL_DEVID(dev_priv) == 0x1926)
2766 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2767 INTEL_DEVID(dev_priv) == 0x1915 || \
2768 INTEL_DEVID(dev_priv) == 0x191E)
2769 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2770 INTEL_DEVID(dev_priv) == 0x5913 || \
2771 INTEL_DEVID(dev_priv) == 0x5916 || \
2772 INTEL_DEVID(dev_priv) == 0x5921 || \
2773 INTEL_DEVID(dev_priv) == 0x5926)
2774 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2775 INTEL_DEVID(dev_priv) == 0x5915 || \
2776 INTEL_DEVID(dev_priv) == 0x591E)
2777 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2778 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2779 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2780 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2782 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2784 #define SKL_REVID_A0 0x0
2785 #define SKL_REVID_B0 0x1
2786 #define SKL_REVID_C0 0x2
2787 #define SKL_REVID_D0 0x3
2788 #define SKL_REVID_E0 0x4
2789 #define SKL_REVID_F0 0x5
2790 #define SKL_REVID_G0 0x6
2791 #define SKL_REVID_H0 0x7
2793 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2795 #define BXT_REVID_A0 0x0
2796 #define BXT_REVID_A1 0x1
2797 #define BXT_REVID_B0 0x3
2798 #define BXT_REVID_B_LAST 0x8
2799 #define BXT_REVID_C0 0x9
2801 #define IS_BXT_REVID(dev_priv, since, until) \
2802 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2804 #define KBL_REVID_A0 0x0
2805 #define KBL_REVID_B0 0x1
2806 #define KBL_REVID_C0 0x2
2807 #define KBL_REVID_D0 0x3
2808 #define KBL_REVID_E0 0x4
2810 #define IS_KBL_REVID(dev_priv, since, until) \
2811 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2813 #define GLK_REVID_A0 0x0
2814 #define GLK_REVID_A1 0x1
2816 #define IS_GLK_REVID(dev_priv, since, until) \
2817 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2820 * The genX designation typically refers to the render engine, so render
2821 * capability related checks should use IS_GEN, while display and other checks
2822 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2825 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2826 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2827 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2828 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2829 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2830 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2831 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2832 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2834 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2835 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2836 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2838 #define ENGINE_MASK(id) BIT(id)
2839 #define RENDER_RING ENGINE_MASK(RCS)
2840 #define BSD_RING ENGINE_MASK(VCS)
2841 #define BLT_RING ENGINE_MASK(BCS)
2842 #define VEBOX_RING ENGINE_MASK(VECS)
2843 #define BSD2_RING ENGINE_MASK(VCS2)
2844 #define ALL_ENGINES (~0)
2846 #define HAS_ENGINE(dev_priv, id) \
2847 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2849 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2850 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2851 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2852 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2854 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2855 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2856 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2857 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2858 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2860 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2862 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2863 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2864 ((dev_priv)->info.has_logical_ring_contexts)
2865 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2866 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2867 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2869 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2870 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2871 ((dev_priv)->info.overlay_needs_physical)
2873 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2874 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2876 /* WaRsDisableCoarsePowerGating:skl,bxt */
2877 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2878 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2881 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2882 * even when in MSI mode. This results in spurious interrupt warnings if the
2883 * legacy irq no. is shared with another device. The kernel then disables that
2884 * interrupt source and so prevents the other device from working properly.
2886 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2887 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2889 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2890 * rows, which changed the alignment requirements and fence programming.
2892 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2893 !(IS_I915G(dev_priv) || \
2894 IS_I915GM(dev_priv)))
2895 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2896 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2898 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2899 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2900 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2902 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2904 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2906 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2907 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2908 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2909 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2910 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2912 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2914 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2915 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2918 * For now, anything with a GuC requires uCode loading, and then supports
2919 * command submission once loaded. But these are logically independent
2920 * properties, so we have separate macros to test them.
2922 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2923 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2924 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2925 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2927 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2929 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2931 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2932 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2933 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2934 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2935 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2936 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2937 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2938 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2939 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2940 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2941 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2942 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2944 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2945 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2946 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2947 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2948 #define HAS_PCH_LPT_LP(dev_priv) \
2949 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2950 #define HAS_PCH_LPT_H(dev_priv) \
2951 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2952 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2953 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2954 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2955 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2957 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2959 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2961 /* DPF == dynamic parity feature */
2962 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2963 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2964 2 : HAS_L3_DPF(dev_priv))
2966 #define GT_FREQUENCY_MULTIPLIER 50
2967 #define GEN9_FREQ_SCALER 3
2969 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2971 #include "i915_trace.h"
2973 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2975 #ifdef CONFIG_INTEL_IOMMU
2976 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2982 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2985 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2989 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2990 const char *fmt
, ...);
2992 #define i915_report_error(dev_priv, fmt, ...) \
2993 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2995 #ifdef CONFIG_COMPAT
2996 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2999 #define i915_compat_ioctl NULL
3001 extern const struct dev_pm_ops i915_pm_ops
;
3003 extern int i915_driver_load(struct pci_dev
*pdev
,
3004 const struct pci_device_id
*ent
);
3005 extern void i915_driver_unload(struct drm_device
*dev
);
3006 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3007 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3008 extern void i915_reset(struct drm_i915_private
*dev_priv
);
3009 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3010 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3011 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3012 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3013 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3014 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3015 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3016 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3018 int intel_engines_init_early(struct drm_i915_private
*dev_priv
);
3019 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3021 /* intel_hotplug.c */
3022 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3023 u32 pin_mask
, u32 long_mask
);
3024 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3025 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3026 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3027 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
3028 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3029 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3032 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3034 unsigned long delay
;
3036 if (unlikely(!i915
.enable_hangcheck
))
3039 /* Don't continually defer the hangcheck so that it is always run at
3040 * least once after work has been scheduled on any ring. Otherwise,
3041 * we will ignore a hung ring if a second ring is kept busy.
3044 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3045 queue_delayed_work(system_long_wq
,
3046 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3050 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3052 const char *fmt
, ...);
3054 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3055 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3056 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3058 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
3059 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
3060 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
3061 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
3062 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
3063 extern void intel_uncore_suspend(struct drm_i915_private
*dev_priv
);
3064 extern void intel_uncore_resume_early(struct drm_i915_private
*dev_priv
);
3065 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
3066 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
3067 enum forcewake_domains domains
);
3068 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3069 enum forcewake_domains domains
);
3070 /* Like above but the caller must manage the uncore.lock itself.
3071 * Must be used with I915_READ_FW and friends.
3073 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3074 enum forcewake_domains domains
);
3075 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3076 enum forcewake_domains domains
);
3077 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3079 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3081 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3085 const unsigned long timeout_ms
);
3086 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3090 const unsigned long timeout_ms
);
3092 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3094 return dev_priv
->gvt
;
3097 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3099 return dev_priv
->vgpu
.active
;
3103 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3107 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3110 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3111 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3112 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3115 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3116 uint32_t interrupt_mask
,
3117 uint32_t enabled_irq_mask
);
3119 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3121 ilk_update_display_irq(dev_priv
, bits
, bits
);
3124 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3126 ilk_update_display_irq(dev_priv
, bits
, 0);
3128 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3130 uint32_t interrupt_mask
,
3131 uint32_t enabled_irq_mask
);
3132 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3133 enum pipe pipe
, uint32_t bits
)
3135 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3137 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3138 enum pipe pipe
, uint32_t bits
)
3140 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3142 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3143 uint32_t interrupt_mask
,
3144 uint32_t enabled_irq_mask
);
3146 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3148 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3151 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3153 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3157 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3158 struct drm_file
*file_priv
);
3159 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3160 struct drm_file
*file_priv
);
3161 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3162 struct drm_file
*file_priv
);
3163 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3164 struct drm_file
*file_priv
);
3165 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3166 struct drm_file
*file_priv
);
3167 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3168 struct drm_file
*file_priv
);
3169 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3170 struct drm_file
*file_priv
);
3171 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3172 struct drm_file
*file_priv
);
3173 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3174 struct drm_file
*file_priv
);
3175 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3176 struct drm_file
*file_priv
);
3177 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3178 struct drm_file
*file
);
3179 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3180 struct drm_file
*file
);
3181 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3182 struct drm_file
*file_priv
);
3183 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3184 struct drm_file
*file_priv
);
3185 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3186 struct drm_file
*file_priv
);
3187 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3188 struct drm_file
*file_priv
);
3189 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3190 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3191 struct drm_file
*file
);
3192 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3193 struct drm_file
*file_priv
);
3194 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3195 struct drm_file
*file_priv
);
3196 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3197 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3198 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3199 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3200 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3201 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3203 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3204 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3205 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3206 const struct drm_i915_gem_object_ops
*ops
);
3207 struct drm_i915_gem_object
*
3208 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3209 struct drm_i915_gem_object
*
3210 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3211 const void *data
, size_t size
);
3212 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3213 void i915_gem_free_object(struct drm_gem_object
*obj
);
3215 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3217 /* A single pass should suffice to release all the freed objects (along
3218 * most call paths) , but be a little more paranoid in that freeing
3219 * the objects does take a little amount of time, during which the rcu
3220 * callbacks could have added new objects into the freed list, and
3221 * armed the work again.
3225 } while (flush_work(&i915
->mm
.free_work
));
3228 struct i915_vma
* __must_check
3229 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3230 const struct i915_ggtt_view
*view
,
3235 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3236 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3238 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3240 static inline int __sg_page_count(const struct scatterlist
*sg
)
3242 return sg
->length
>> PAGE_SHIFT
;
3245 struct scatterlist
*
3246 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3247 unsigned int n
, unsigned int *offset
);
3250 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3254 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3258 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3261 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3262 struct sg_table
*pages
);
3263 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3265 static inline int __must_check
3266 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3268 might_lock(&obj
->mm
.lock
);
3270 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3273 return __i915_gem_object_get_pages(obj
);
3277 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3279 GEM_BUG_ON(!obj
->mm
.pages
);
3281 atomic_inc(&obj
->mm
.pages_pin_count
);
3285 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3287 return atomic_read(&obj
->mm
.pages_pin_count
);
3291 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3293 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3294 GEM_BUG_ON(!obj
->mm
.pages
);
3296 atomic_dec(&obj
->mm
.pages_pin_count
);
3300 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3302 __i915_gem_object_unpin_pages(obj
);
3305 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3310 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3311 enum i915_mm_subclass subclass
);
3312 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3314 enum i915_map_type
{
3320 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3321 * @obj: the object to map into kernel address space
3322 * @type: the type of mapping, used to select pgprot_t
3324 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3325 * pages and then returns a contiguous mapping of the backing storage into
3326 * the kernel address space. Based on the @type of mapping, the PTE will be
3327 * set to either WriteBack or WriteCombine (via pgprot_t).
3329 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3330 * mapping is no longer required.
3332 * Returns the pointer through which to access the mapped object, or an
3333 * ERR_PTR() on error.
3335 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3336 enum i915_map_type type
);
3339 * i915_gem_object_unpin_map - releases an earlier mapping
3340 * @obj: the object to unmap
3342 * After pinning the object and mapping its pages, once you are finished
3343 * with your access, call i915_gem_object_unpin_map() to release the pin
3344 * upon the mapping. Once the pin count reaches zero, that mapping may be
3347 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3349 i915_gem_object_unpin_pages(obj
);
3352 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3353 unsigned int *needs_clflush
);
3354 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3355 unsigned int *needs_clflush
);
3356 #define CLFLUSH_BEFORE 0x1
3357 #define CLFLUSH_AFTER 0x2
3358 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3361 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3363 i915_gem_object_unpin_pages(obj
);
3366 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3367 void i915_vma_move_to_active(struct i915_vma
*vma
,
3368 struct drm_i915_gem_request
*req
,
3369 unsigned int flags
);
3370 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3371 struct drm_device
*dev
,
3372 struct drm_mode_create_dumb
*args
);
3373 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3374 uint32_t handle
, uint64_t *offset
);
3375 int i915_gem_mmap_gtt_version(void);
3377 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3378 struct drm_i915_gem_object
*new,
3379 unsigned frontbuffer_bits
);
3381 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3383 struct drm_i915_gem_request
*
3384 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3386 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3388 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3390 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3393 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3395 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3398 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3400 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3403 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3405 return READ_ONCE(error
->reset_count
);
3408 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3409 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3410 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3411 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3413 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3414 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3415 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3416 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3417 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3418 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3419 unsigned int flags
);
3420 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3421 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3422 int i915_gem_fault(struct vm_fault
*vmf
);
3423 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3426 struct intel_rps_client
*rps
);
3427 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3430 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3433 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3436 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3437 struct i915_vma
* __must_check
3438 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3440 const struct i915_ggtt_view
*view
);
3441 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3442 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3444 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3445 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3447 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3448 enum i915_cache_level cache_level
);
3450 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3451 struct dma_buf
*dma_buf
);
3453 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3454 struct drm_gem_object
*gem_obj
, int flags
);
3456 static inline struct i915_hw_ppgtt
*
3457 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3459 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3462 /* i915_gem_fence_reg.c */
3463 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3464 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3466 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3467 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3469 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3470 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3471 struct sg_table
*pages
);
3472 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3473 struct sg_table
*pages
);
3475 static inline struct i915_gem_context
*
3476 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3478 struct i915_gem_context
*ctx
;
3480 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3482 ctx
= idr_find(&file_priv
->context_idr
, id
);
3484 return ERR_PTR(-ENOENT
);
3489 static inline struct i915_gem_context
*
3490 i915_gem_context_get(struct i915_gem_context
*ctx
)
3492 kref_get(&ctx
->ref
);
3496 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3498 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3499 kref_put(&ctx
->ref
, i915_gem_context_free
);
3502 static inline void i915_gem_context_put_unlocked(struct i915_gem_context
*ctx
)
3504 struct mutex
*lock
= &ctx
->i915
->drm
.struct_mutex
;
3506 if (kref_put_mutex(&ctx
->ref
, i915_gem_context_free
, lock
))
3510 static inline struct intel_timeline
*
3511 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3512 struct intel_engine_cs
*engine
)
3514 struct i915_address_space
*vm
;
3516 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3517 return &vm
->timeline
.engine
[engine
->id
];
3520 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3521 struct drm_file
*file
);
3523 /* i915_gem_evict.c */
3524 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3525 u64 min_size
, u64 alignment
,
3526 unsigned cache_level
,
3529 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3530 struct drm_mm_node
*node
,
3531 unsigned int flags
);
3532 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3534 /* belongs in i915_gem_gtt.h */
3535 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3538 if (INTEL_GEN(dev_priv
) < 6)
3539 intel_gtt_chipset_flush();
3542 /* i915_gem_stolen.c */
3543 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3544 struct drm_mm_node
*node
, u64 size
,
3545 unsigned alignment
);
3546 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3547 struct drm_mm_node
*node
, u64 size
,
3548 unsigned alignment
, u64 start
,
3550 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3551 struct drm_mm_node
*node
);
3552 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3553 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3554 struct drm_i915_gem_object
*
3555 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3556 struct drm_i915_gem_object
*
3557 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3562 /* i915_gem_internal.c */
3563 struct drm_i915_gem_object
*
3564 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3567 /* i915_gem_shrinker.c */
3568 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3569 unsigned long target
,
3571 #define I915_SHRINK_PURGEABLE 0x1
3572 #define I915_SHRINK_UNBOUND 0x2
3573 #define I915_SHRINK_BOUND 0x4
3574 #define I915_SHRINK_ACTIVE 0x8
3575 #define I915_SHRINK_VMAPS 0x10
3576 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3577 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3578 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3581 /* i915_gem_tiling.c */
3582 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3584 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3586 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3587 i915_gem_object_is_tiled(obj
);
3590 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3591 unsigned int tiling
, unsigned int stride
);
3592 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3593 unsigned int tiling
, unsigned int stride
);
3595 /* i915_debugfs.c */
3596 #ifdef CONFIG_DEBUG_FS
3597 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3598 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3599 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3601 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3602 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3604 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3607 /* i915_gpu_error.c */
3608 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3611 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3612 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3613 const struct i915_gpu_state
*gpu
);
3614 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3615 struct drm_i915_private
*i915
,
3616 size_t count
, loff_t pos
);
3617 static inline void i915_error_state_buf_release(
3618 struct drm_i915_error_state_buf
*eb
)
3623 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3624 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3626 const char *error_msg
);
3628 static inline struct i915_gpu_state
*
3629 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3631 kref_get(&gpu
->ref
);
3635 void __i915_gpu_state_free(struct kref
*kref
);
3636 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3639 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3642 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3643 void i915_reset_error_state(struct drm_i915_private
*i915
);
3647 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3649 const char *error_msg
)
3653 static inline struct i915_gpu_state
*
3654 i915_first_error_state(struct drm_i915_private
*i915
)
3659 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3665 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3667 /* i915_cmd_parser.c */
3668 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3669 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3670 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3671 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3672 struct drm_i915_gem_object
*batch_obj
,
3673 struct drm_i915_gem_object
*shadow_batch_obj
,
3674 u32 batch_start_offset
,
3679 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3680 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3681 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3682 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3684 /* i915_suspend.c */
3685 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3686 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3689 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3690 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3692 /* intel_lpe_audio.c */
3693 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3694 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3695 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3696 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3697 void *eld
, int port
, int pipe
, int tmds_clk_speed
,
3698 bool dp_output
, int link_rate
);
3701 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3702 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3703 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3706 extern struct i2c_adapter
*
3707 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3708 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3709 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3710 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3712 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3714 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3717 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3718 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3719 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3720 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3721 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3722 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3723 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3724 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3725 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3727 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3731 /* intel_opregion.c */
3733 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3734 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3735 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3736 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3737 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3739 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3741 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3743 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3744 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3745 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3746 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3750 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3755 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3759 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3767 extern void intel_register_dsm_handler(void);
3768 extern void intel_unregister_dsm_handler(void);
3770 static inline void intel_register_dsm_handler(void) { return; }
3771 static inline void intel_unregister_dsm_handler(void) { return; }
3772 #endif /* CONFIG_ACPI */
3774 /* intel_device_info.c */
3775 static inline struct intel_device_info
*
3776 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3778 return (struct intel_device_info
*)&dev_priv
->info
;
3781 const char *intel_platform_name(enum intel_platform platform
);
3782 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3783 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3786 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3787 extern int intel_modeset_init(struct drm_device
*dev
);
3788 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3789 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3790 extern int intel_connector_register(struct drm_connector
*);
3791 extern void intel_connector_unregister(struct drm_connector
*);
3792 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3794 extern void intel_display_resume(struct drm_device
*dev
);
3795 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3796 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3797 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3798 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3799 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3800 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3803 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3804 struct drm_file
*file
);
3807 extern struct intel_overlay_error_state
*
3808 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3809 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3810 struct intel_overlay_error_state
*error
);
3812 extern struct intel_display_error_state
*
3813 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3814 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3815 struct intel_display_error_state
*error
);
3817 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3818 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3819 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
3820 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
3822 /* intel_sideband.c */
3823 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3824 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3825 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3826 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3827 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3828 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3829 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3830 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3831 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3832 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3833 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3834 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3835 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3836 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3837 enum intel_sbi_destination destination
);
3838 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3839 enum intel_sbi_destination destination
);
3840 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3841 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3843 /* intel_dpio_phy.c */
3844 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
3845 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3846 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3847 enum port port
, u32 margin
, u32 scale
,
3848 u32 enable
, u32 deemphasis
);
3849 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3850 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3851 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3853 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3855 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3856 uint8_t lane_count
);
3857 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3858 uint8_t lane_lat_optim_mask
);
3859 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3861 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3862 u32 deemph_reg_value
, u32 margin_reg_value
,
3863 bool uniq_trans_scale
);
3864 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3866 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3867 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3868 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3869 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3871 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3872 u32 demph_reg_value
, u32 preemph_reg_value
,
3873 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3874 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3875 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3876 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3878 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3879 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3881 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3882 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3884 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3885 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3886 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3887 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3889 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3890 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3891 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3892 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3894 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3895 * will be implemented using 2 32-bit writes in an arbitrary order with
3896 * an arbitrary delay between them. This can cause the hardware to
3897 * act upon the intermediate value, possibly leading to corruption and
3898 * machine death. For this reason we do not support I915_WRITE64, or
3899 * dev_priv->uncore.funcs.mmio_writeq.
3901 * When reading a 64-bit value as two 32-bit values, the delay may cause
3902 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3903 * occasionally a 64-bit register does not actualy support a full readq
3904 * and must be read using two 32-bit reads.
3906 * You have been warned.
3908 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3910 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3911 u32 upper, lower, old_upper, loop = 0; \
3912 upper = I915_READ(upper_reg); \
3914 old_upper = upper; \
3915 lower = I915_READ(lower_reg); \
3916 upper = I915_READ(upper_reg); \
3917 } while (upper != old_upper && loop++ < 2); \
3918 (u64)upper << 32 | lower; })
3920 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3921 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3923 #define __raw_read(x, s) \
3924 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3927 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3930 #define __raw_write(x, s) \
3931 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3932 i915_reg_t reg, uint##x##_t val) \
3934 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3949 /* These are untraced mmio-accessors that are only valid to be used inside
3950 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3953 * Think twice, and think again, before using these.
3955 * As an example, these accessors can possibly be used between:
3957 * spin_lock_irq(&dev_priv->uncore.lock);
3958 * intel_uncore_forcewake_get__locked();
3962 * intel_uncore_forcewake_put__locked();
3963 * spin_unlock_irq(&dev_priv->uncore.lock);
3966 * Note: some registers may not need forcewake held, so
3967 * intel_uncore_forcewake_{get,put} can be omitted, see
3968 * intel_uncore_forcewake_for_reg().
3970 * Certain architectures will die if the same cacheline is concurrently accessed
3971 * by different clients (e.g. on Ivybridge). Access to registers should
3972 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3973 * a more localised lock guarding all access to that bank of registers.
3975 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3976 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3977 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3978 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3980 /* "Broadcast RGB" property */
3981 #define INTEL_BROADCAST_RGB_AUTO 0
3982 #define INTEL_BROADCAST_RGB_FULL 1
3983 #define INTEL_BROADCAST_RGB_LIMITED 2
3985 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3987 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3988 return VLV_VGACNTRL
;
3989 else if (INTEL_GEN(dev_priv
) >= 5)
3990 return CPU_VGACNTRL
;
3995 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3997 unsigned long j
= msecs_to_jiffies(m
);
3999 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4002 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4004 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4007 static inline unsigned long
4008 timespec_to_jiffies_timeout(const struct timespec
*value
)
4010 unsigned long j
= timespec_to_jiffies(value
);
4012 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4016 * If you need to wait X milliseconds between events A and B, but event B
4017 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4018 * when event A happened, then just before event B you call this function and
4019 * pass the timestamp as the first argument, and X as the second argument.
4022 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4024 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4027 * Don't re-read the value of "jiffies" every time since it may change
4028 * behind our back and break the math.
4030 tmp_jiffies
= jiffies
;
4031 target_jiffies
= timestamp_jiffies
+
4032 msecs_to_jiffies_timeout(to_wait_ms
);
4034 if (time_after(target_jiffies
, tmp_jiffies
)) {
4035 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4036 while (remaining_jiffies
)
4038 schedule_timeout_uninterruptible(remaining_jiffies
);
4043 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4045 struct intel_engine_cs
*engine
= req
->engine
;
4048 /* Note that the engine may have wrapped around the seqno, and
4049 * so our request->global_seqno will be ahead of the hardware,
4050 * even though it completed the request before wrapping. We catch
4051 * this by kicking all the waiters before resetting the seqno
4052 * in hardware, and also signal the fence.
4054 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4057 /* The request was dequeued before we were awoken. We check after
4058 * inspecting the hw to confirm that this was the same request
4059 * that generated the HWS update. The memory barriers within
4060 * the request execution are sufficient to ensure that a check
4061 * after reading the value from hw matches this request.
4063 seqno
= i915_gem_request_global_seqno(req
);
4067 /* Before we do the heavier coherent read of the seqno,
4068 * check the value (hopefully) in the CPU cacheline.
4070 if (__i915_gem_request_completed(req
, seqno
))
4073 /* Ensure our read of the seqno is coherent so that we
4074 * do not "miss an interrupt" (i.e. if this is the last
4075 * request and the seqno write from the GPU is not visible
4076 * by the time the interrupt fires, we will see that the
4077 * request is incomplete and go back to sleep awaiting
4078 * another interrupt that will never come.)
4080 * Strictly, we only need to do this once after an interrupt,
4081 * but it is easier and safer to do it every time the waiter
4084 if (engine
->irq_seqno_barrier
&&
4085 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4086 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4088 /* The ordering of irq_posted versus applying the barrier
4089 * is crucial. The clearing of the current irq_posted must
4090 * be visible before we perform the barrier operation,
4091 * such that if a subsequent interrupt arrives, irq_posted
4092 * is reasserted and our task rewoken (which causes us to
4093 * do another __i915_request_irq_complete() immediately
4094 * and reapply the barrier). Conversely, if the clear
4095 * occurs after the barrier, then an interrupt that arrived
4096 * whilst we waited on the barrier would not trigger a
4097 * barrier on the next pass, and the read may not see the
4100 engine
->irq_seqno_barrier(engine
);
4102 /* If we consume the irq, but we are no longer the bottom-half,
4103 * the real bottom-half may not have serialised their own
4104 * seqno check with the irq-barrier (i.e. may have inspected
4105 * the seqno before we believe it coherent since they see
4106 * irq_posted == false but we are still running).
4108 spin_lock_irq(&b
->irq_lock
);
4109 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4110 /* Note that if the bottom-half is changed as we
4111 * are sending the wake-up, the new bottom-half will
4112 * be woken by whomever made the change. We only have
4113 * to worry about when we steal the irq-posted for
4116 wake_up_process(b
->irq_wait
->tsk
);
4117 spin_unlock_irq(&b
->irq_lock
);
4119 if (__i915_gem_request_completed(req
, seqno
))
4126 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4127 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4129 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4130 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4131 * perform the operation. To check beforehand, pass in the parameters to
4132 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4133 * you only need to pass in the minor offsets, page-aligned pointers are
4136 * For just checking for SSE4.1, in the foreknowledge that the future use
4137 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4139 #define i915_can_memcpy_from_wc(dst, src, len) \
4140 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4142 #define i915_has_memcpy_from_wc() \
4143 i915_memcpy_from_wc(NULL, NULL, 0)
4146 int remap_io_mapping(struct vm_area_struct
*vma
,
4147 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4148 struct io_mapping
*iomap
);
4150 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object
*obj
)
4152 return (obj
->cache_level
!= I915_CACHE_NONE
||
4153 HAS_LLC(to_i915(obj
->base
.dev
)));