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Linux-2.6.12-rc2
[mirror_ubuntu-artful-kernel.git] / drivers / video / matrox / matroxfb_Ti3026.c
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * (following author is not in any relation with this code, but his code
69 * is included in this driver)
70 *
71 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
72 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
73 *
74 * (following author is not in any relation with this code, but his ideas
75 * were used when writting this driver)
76 *
77 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
78 *
79 */
80
81 /* make checkconfig does not verify included files... */
82 #include <linux/config.h>
83
84 #include "matroxfb_Ti3026.h"
85 #include "matroxfb_misc.h"
86 #include "matroxfb_accel.h"
87 #include <linux/matroxfb.h>
88
89 #ifdef CONFIG_FB_MATROX_MILLENIUM
90 #define outTi3026 matroxfb_DAC_out
91 #define inTi3026 matroxfb_DAC_in
92
93 #define TVP3026_INDEX 0x00
94 #define TVP3026_PALWRADD 0x00
95 #define TVP3026_PALDATA 0x01
96 #define TVP3026_PIXRDMSK 0x02
97 #define TVP3026_PALRDADD 0x03
98 #define TVP3026_CURCOLWRADD 0x04
99 #define TVP3026_CLOVERSCAN 0x00
100 #define TVP3026_CLCOLOR0 0x01
101 #define TVP3026_CLCOLOR1 0x02
102 #define TVP3026_CLCOLOR2 0x03
103 #define TVP3026_CURCOLDATA 0x05
104 #define TVP3026_CURCOLRDADD 0x07
105 #define TVP3026_CURCTRL 0x09
106 #define TVP3026_X_DATAREG 0x0A
107 #define TVP3026_CURRAMDATA 0x0B
108 #define TVP3026_CURPOSXL 0x0C
109 #define TVP3026_CURPOSXH 0x0D
110 #define TVP3026_CURPOSYL 0x0E
111 #define TVP3026_CURPOSYH 0x0F
112
113 #define TVP3026_XSILICONREV 0x01
114 #define TVP3026_XCURCTRL 0x06
115 #define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
116 #define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
117 #define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
118 #define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
119 #define TVP3026_XCURCTRL_BLANK2048 0x00
120 #define TVP3026_XCURCTRL_BLANK4096 0x10
121 #define TVP3026_XCURCTRL_INTERLACED 0x20
122 #define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
123 #define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
124 #define TVP3026_XCURCTRL_INDIRECT 0x00
125 #define TVP3026_XCURCTRL_DIRECT 0x80
126 #define TVP3026_XLATCHCTRL 0x0F
127 #define TVP3026_XLATCHCTRL_1_1 0x06
128 #define TVP3026_XLATCHCTRL_2_1 0x07
129 #define TVP3026_XLATCHCTRL_4_1 0x06
130 #define TVP3026_XLATCHCTRL_8_1 0x06
131 #define TVP3026_XLATCHCTRL_16_1 0x06
132 #define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
133 #define TVP3026A_XLATCHCTRL_8_3 0x07
134 #define TVP3026B_XLATCHCTRL_4_3 0x08
135 #define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
136 #define TVP3026_XTRUECOLORCTRL 0x18
137 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
138 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
139 #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
140 #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
141 #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
142 #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
143 #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
144 #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
145 #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
146 #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
147 #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
148 #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
149 #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
150 #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
151 #define TVP3026_XMUXCTRL 0x19
152 #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
153 #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
154 #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
155 #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
156 #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
157 #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
158 #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
159 #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
160 #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
161 #define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
162 #define TVP3026_XCLKCTRL 0x1A
163 #define TVP3026_XCLKCTRL_DIV1 0x00
164 #define TVP3026_XCLKCTRL_DIV2 0x10
165 #define TVP3026_XCLKCTRL_DIV4 0x20
166 #define TVP3026_XCLKCTRL_DIV8 0x30
167 #define TVP3026_XCLKCTRL_DIV16 0x40
168 #define TVP3026_XCLKCTRL_DIV32 0x50
169 #define TVP3026_XCLKCTRL_DIV64 0x60
170 #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
171 #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
172 #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
173 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
174 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
175 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
176 #define TVP3026_XCLKCTRL_SRC_PLL 0x05
177 #define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
178 #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
179 #define TVP3026_XPALETTEPAGE 0x1C
180 #define TVP3026_XGENCTRL 0x1D
181 #define TVP3026_XGENCTRL_HSYNC_POS 0x00
182 #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
183 #define TVP3026_XGENCTRL_VSYNC_POS 0x00
184 #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
185 #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
186 #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
187 #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
188 #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
189 #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
190 #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
191 #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
192 #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
193 #define TVP3026_XMISCCTRL 0x1E
194 #define TVP3026_XMISCCTRL_DAC_PUP 0x00
195 #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
196 #define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
197 #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
198 #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
199 #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
200 #define TVP3026_XMISCCTRL_PSEL_EN 0x10
201 #define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
202 #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
203 #define TVP3026_XGENIOCTRL 0x2A
204 #define TVP3026_XGENIODATA 0x2B
205 #define TVP3026_XPLLADDR 0x2C
206 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
207 #define TVP3026_XPLLDATA_N 0x00
208 #define TVP3026_XPLLDATA_M 0x01
209 #define TVP3026_XPLLDATA_P 0x02
210 #define TVP3026_XPLLDATA_STAT 0x03
211 #define TVP3026_XPIXPLLDATA 0x2D
212 #define TVP3026_XMEMPLLDATA 0x2E
213 #define TVP3026_XLOOPPLLDATA 0x2F
214 #define TVP3026_XCOLKEYOVRMIN 0x30
215 #define TVP3026_XCOLKEYOVRMAX 0x31
216 #define TVP3026_XCOLKEYREDMIN 0x32
217 #define TVP3026_XCOLKEYREDMAX 0x33
218 #define TVP3026_XCOLKEYGREENMIN 0x34
219 #define TVP3026_XCOLKEYGREENMAX 0x35
220 #define TVP3026_XCOLKEYBLUEMIN 0x36
221 #define TVP3026_XCOLKEYBLUEMAX 0x37
222 #define TVP3026_XCOLKEYCTRL 0x38
223 #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
224 #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
225 #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
226 #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
227 #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
228 #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
229 #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
230 #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
231 #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
232 #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
233 #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
234 #define TVP3026_XMEMPLLCTRL 0x39
235 #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
236 #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
237 #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
238 #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
239 #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
240 #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
241 #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
242 #define TVP3026_XSENSETEST 0x3A
243 #define TVP3026_XTESTMODEDATA 0x3B
244 #define TVP3026_XCRCREML 0x3C
245 #define TVP3026_XCRCREMH 0x3D
246 #define TVP3026_XCRCBITSEL 0x3E
247 #define TVP3026_XID 0x3F
248
249 static const unsigned char DACseq[] =
250 { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
251 TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
252 TVP3026_XPALETTEPAGE,
253 TVP3026_XGENCTRL,
254 TVP3026_XMISCCTRL,
255 TVP3026_XGENIOCTRL,
256 TVP3026_XGENIODATA,
257 TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
258 TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
259 TVP3026_XCOLKEYCTRL,
260 TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
261
262 #define POS3026_XLATCHCTRL 0
263 #define POS3026_XTRUECOLORCTRL 1
264 #define POS3026_XMUXCTRL 2
265 #define POS3026_XCLKCTRL 3
266 #define POS3026_XGENCTRL 5
267 #define POS3026_XMISCCTRL 6
268 #define POS3026_XMEMPLLCTRL 18
269 #define POS3026_XCURCTRL 20
270
271 static const unsigned char MGADACbpp32[] =
272 { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
273 0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
274 0x00,
275 TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
276 TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
277 0x00,
278 0x1E,
279 0xFF, 0xFF, 0xFF, 0xFF,
280 0xFF, 0xFF, 0xFF, 0xFF,
281 TVP3026_XCOLKEYCTRL_ZOOM1,
282 0x00, 0x00, TVP3026_XCURCTRL_DIS };
283
284 static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
285 unsigned int fvco;
286 unsigned int lin, lfeed, lpost;
287
288 DBG(__FUNCTION__)
289
290 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
291 fvco >>= (*post = lpost);
292 *in = 64 - lin;
293 *feed = 64 - lfeed;
294 return fvco;
295 }
296
297 static int Ti3026_setpclk(WPMINFO int clk) {
298 unsigned int f_pll;
299 unsigned int pixfeed, pixin, pixpost;
300 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
301
302 DBG(__FUNCTION__)
303
304 f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
305
306 hw->DACclk[0] = pixin | 0xC0;
307 hw->DACclk[1] = pixfeed;
308 hw->DACclk[2] = pixpost | 0xB0;
309
310 {
311 unsigned int loopfeed, loopin, looppost, loopdiv, z;
312 unsigned int Bpp;
313
314 Bpp = ACCESS_FBINFO(curr.final_bppShift);
315
316 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
317 loopfeed = 3; /* set lm to any possible value */
318 loopin = 3 * 32 / Bpp;
319 } else {
320 loopfeed = 4;
321 loopin = 4 * 32 / Bpp;
322 }
323 z = (110000 * loopin) / (f_pll * loopfeed);
324 loopdiv = 0; /* div 2 */
325 if (z < 2)
326 looppost = 0;
327 else if (z < 4)
328 looppost = 1;
329 else if (z < 8)
330 looppost = 2;
331 else {
332 looppost = 3;
333 loopdiv = z/16;
334 }
335 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
336 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
337 hw->DACclk[4] = (65 - loopfeed) | 0x80;
338 if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
339 if (isInterleave(MINFO))
340 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
341 else {
342 hw->DACclk[4] &= ~0xC0;
343 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
344 }
345 } else {
346 if (isInterleave(MINFO))
347 ; /* default... */
348 else {
349 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
350 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
351 }
352 }
353 hw->DACclk[5] = looppost | 0xF8;
354 if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
355 hw->DACclk[5] ^= 0x40;
356 } else {
357 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
358 hw->DACclk[4] = 65 - loopfeed;
359 hw->DACclk[5] = looppost | 0xF0;
360 }
361 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
362 }
363 return 0;
364 }
365
366 static int Ti3026_init(WPMINFO struct my_timming* m) {
367 u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
368 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
369
370 DBG(__FUNCTION__)
371
372 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
373 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
374 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
375 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
376 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
377 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
378 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
379 break;
380 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
381 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
382 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
383 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
384 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
385 break;
386 case 16:
387 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
388 hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
389 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
390 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
391 break;
392 case 24:
393 /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
394 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
395 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
396 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
397 break;
398 case 32:
399 /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
400 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
401 break;
402 default:
403 return 1; /* TODO: failed */
404 }
405 if (matroxfb_vgaHWinit(PMINFO m)) return 1;
406
407 /* set SYNC */
408 hw->MiscOutReg = 0xCB;
409 if (m->sync & FB_SYNC_HOR_HIGH_ACT)
410 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
411 if (m->sync & FB_SYNC_VERT_HIGH_ACT)
412 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
413 if (m->sync & FB_SYNC_ON_GREEN)
414 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
415
416 /* set DELAY */
417 if (ACCESS_FBINFO(video.len) < 0x400000)
418 hw->CRTCEXT[3] |= 0x08;
419 else if (ACCESS_FBINFO(video.len) > 0x400000)
420 hw->CRTCEXT[3] |= 0x10;
421
422 /* set HWCURSOR */
423 if (m->interlaced) {
424 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
425 }
426 if (m->HTotal >= 1536)
427 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
428
429 /* set interleaving */
430 hw->MXoptionReg &= ~0x00001000;
431 if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
432
433 /* set DAC */
434 Ti3026_setpclk(PMINFO m->pixclock);
435 return 0;
436 }
437
438 static void ti3026_setMCLK(WPMINFO int fout){
439 unsigned int f_pll;
440 unsigned int pclk_m, pclk_n, pclk_p;
441 unsigned int mclk_m, mclk_n, mclk_p;
442 unsigned int rfhcnt, mclk_ctl;
443 int tmout;
444
445 DBG(__FUNCTION__)
446
447 f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
448
449 /* save pclk */
450 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
451 pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
452 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
453 pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
454 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
455 pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
456
457 /* stop pclk */
458 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
459 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
460
461 /* set pclk to new mclk */
462 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
463 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
464 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
465 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
466
467 /* wait for PLL to lock */
468 for (tmout = 500000; tmout; tmout--) {
469 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
470 break;
471 udelay(10);
472 };
473 if (!tmout)
474 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
475
476 /* output pclk on mclk pin */
477 mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
478 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
479 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
480
481 /* stop MCLK */
482 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
483 outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
484
485 /* set mclk to new freq */
486 outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
487 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
488 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
489 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
490
491 /* wait for PLL to lock */
492 for (tmout = 500000; tmout; tmout--) {
493 if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
494 break;
495 udelay(10);
496 }
497 if (!tmout)
498 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
499
500 f_pll = f_pll * 333 / (10000 << mclk_p);
501 if (isMilleniumII(MINFO)) {
502 rfhcnt = (f_pll - 128) / 256;
503 if (rfhcnt > 15)
504 rfhcnt = 15;
505 } else {
506 rfhcnt = (f_pll - 64) / 128;
507 if (rfhcnt > 15)
508 rfhcnt = 0;
509 }
510 ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
511 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
512
513 /* output MCLK to MCLK pin */
514 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
515 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
516
517 /* stop PCLK */
518 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
519 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
520
521 /* restore pclk */
522 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
523 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
524 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
525 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
526
527 /* wait for PLL to lock */
528 for (tmout = 500000; tmout; tmout--) {
529 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
530 break;
531 udelay(10);
532 }
533 if (!tmout)
534 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
535 }
536
537 static void ti3026_ramdac_init(WPMINFO2) {
538
539 DBG(__FUNCTION__)
540
541 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
542 ACCESS_FBINFO(features.pll.ref_freq) = 114545;
543 ACCESS_FBINFO(features.pll.feed_div_min) = 2;
544 ACCESS_FBINFO(features.pll.feed_div_max) = 24;
545 ACCESS_FBINFO(features.pll.in_div_min) = 2;
546 ACCESS_FBINFO(features.pll.in_div_max) = 63;
547 ACCESS_FBINFO(features.pll.post_shift_max) = 3;
548 if (ACCESS_FBINFO(devflags.noinit))
549 return;
550 ti3026_setMCLK(PMINFO 60000);
551 }
552
553 static void Ti3026_restore(WPMINFO2) {
554 int i;
555 unsigned char progdac[6];
556 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
557 CRITFLAGS
558
559 DBG(__FUNCTION__)
560
561 #ifdef DEBUG
562 dprintk(KERN_INFO "EXTVGA regs: ");
563 for (i = 0; i < 6; i++)
564 dprintk("%02X:", hw->CRTCEXT[i]);
565 dprintk("\n");
566 #endif
567
568 CRITBEGIN
569
570 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
571
572 CRITEND
573
574 matroxfb_vgaHWrestore(PMINFO2);
575
576 CRITBEGIN
577
578 ACCESS_FBINFO(crtc1.panpos) = -1;
579 for (i = 0; i < 6; i++)
580 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
581
582 for (i = 0; i < 21; i++) {
583 outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
584 }
585
586 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
587 progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
588 progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
589 outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
590 progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
591 progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
592 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
593 progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
594 progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
595
596 CRITEND
597 if (memcmp(hw->DACclk, progdac, 6)) {
598 /* agrhh... setting up PLL is very slow on Millennium... */
599 /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
600 /* Maybe even we should call schedule() ? */
601
602 CRITBEGIN
603 outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
604 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
605 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
606 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
607
608 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
609 for (i = 0; i < 3; i++)
610 outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
611 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
612 if (hw->MiscOutReg & 0x08) {
613 int tmout;
614 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
615 for (tmout = 500000; tmout; --tmout) {
616 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
617 break;
618 udelay(10);
619 }
620
621 CRITEND
622
623 if (!tmout)
624 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
625 else
626 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
627 CRITBEGIN
628 }
629 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
630 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
631 for (i = 3; i < 6; i++)
632 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
633 CRITEND
634 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
635 int tmout;
636
637 CRITBEGIN
638 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
639 for (tmout = 500000; tmout; --tmout) {
640 if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
641 break;
642 udelay(10);
643 }
644 CRITEND
645 if (!tmout)
646 printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
647 else
648 dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
649 }
650 }
651
652 #ifdef DEBUG
653 dprintk(KERN_DEBUG "3026DACregs ");
654 for (i = 0; i < 21; i++) {
655 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
656 if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
657 }
658 dprintk("\n" KERN_DEBUG "DACclk ");
659 for (i = 0; i < 6; i++)
660 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
661 dprintk("\n");
662 #endif
663 }
664
665 static void Ti3026_reset(WPMINFO2) {
666
667 DBG(__FUNCTION__)
668
669 ti3026_ramdac_init(PMINFO2);
670 }
671
672 static struct matrox_altout ti3026_output = {
673 .name = "Primary output",
674 };
675
676 static int Ti3026_preinit(WPMINFO2) {
677 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
678 1024, 1152, 1280, 1600, 1664, 1920,
679 2048, 0};
680 static const int vxres_mill1[] = { 640, 768, 800, 960,
681 1024, 1152, 1280, 1600, 1920,
682 2048, 0};
683 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
684
685 DBG(__FUNCTION__)
686
687 ACCESS_FBINFO(millenium) = 1;
688 ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
689 ACCESS_FBINFO(capable.cfb4) = 1;
690 ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
691 ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
692
693 ACCESS_FBINFO(outputs[0]).data = MINFO;
694 ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
695 ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
696 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
697
698 if (ACCESS_FBINFO(devflags.noinit))
699 return 0;
700 /* preserve VGA I/O, BIOS and PPC */
701 hw->MXoptionReg &= 0xC0000100;
702 hw->MXoptionReg |= 0x002C0000;
703 if (ACCESS_FBINFO(devflags.novga))
704 hw->MXoptionReg &= ~0x00000100;
705 if (ACCESS_FBINFO(devflags.nobios))
706 hw->MXoptionReg &= ~0x40000000;
707 if (ACCESS_FBINFO(devflags.nopciretry))
708 hw->MXoptionReg |= 0x20000000;
709 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
710
711 ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
712
713 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
714 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
715 outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
716
717 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
718 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
719 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
720
721 mga_outb(M_MISC_REG, 0x67);
722
723 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
724
725 mga_outl(M_RESET, 1);
726 udelay(250);
727 mga_outl(M_RESET, 0);
728 udelay(250);
729 mga_outl(M_MACCESS, 0x00008000);
730 udelay(10);
731 return 0;
732 }
733
734 struct matrox_switch matrox_millennium = {
735 Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore
736 };
737 EXPORT_SYMBOL(matrox_millennium);
738 #endif
739 MODULE_LICENSE("GPL");
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