kernel/irq/generic-chip.c

   1 /*
   2  * Library implementing the most common irq chip callback functions
   3  *
   4  * Copyright (C) 2011, Thomas Gleixner
   5  */
   6 #include <linux/io.h>
   7 #include <linux/irq.h>
   8 #include <linux/slab.h>
   9 #include <linux/export.h>
  10 #include <linux/irqdomain.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/syscore_ops.h>
  14
  15 #include "internals.h"
  16
  17 static LIST_HEAD(gc_list);
  18 static DEFINE_RAW_SPINLOCK(gc_lock);
  19
  20 /**
  21  * irq_gc_noop - NOOP function
  22  * @d: irq_data
  23  */
  24 void irq_gc_noop(struct irq_data *d)
  25 {
  26 }
  27
  28 /**
  29  * irq_gc_mask_disable_reg - Mask chip via disable register
  30  * @d: irq_data
  31  *
  32  * Chip has separate enable/disable registers instead of a single mask
  33  * register.
  34  */
  35 void irq_gc_mask_disable_reg(struct irq_data *d)
  36 {
  37         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  38         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  39         u32 mask = d->mask;
  40
  41         irq_gc_lock(gc);
  42         irq_reg_writel(gc, mask, ct->regs.disable);
  43         *ct->mask_cache &= ~mask;
  44         irq_gc_unlock(gc);
  45 }
  46
  47 /**
  48  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
  49  * @d: irq_data
  50  *
  51  * Chip has a single mask register. Values of this register are cached
  52  * and protected by gc->lock
  53  */
  54 void irq_gc_mask_set_bit(struct irq_data *d)
  55 {
  56         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  57         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  58         u32 mask = d->mask;
  59
  60         irq_gc_lock(gc);
  61         *ct->mask_cache |= mask;
  62         irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
  63         irq_gc_unlock(gc);
  64 }
  65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
  66
  67 /**
  68  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
  69  * @d: irq_data
  70  *
  71  * Chip has a single mask register. Values of this register are cached
  72  * and protected by gc->lock
  73  */
  74 void irq_gc_mask_clr_bit(struct irq_data *d)
  75 {
  76         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  77         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  78         u32 mask = d->mask;
  79
  80         irq_gc_lock(gc);
  81         *ct->mask_cache &= ~mask;
  82         irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
  83         irq_gc_unlock(gc);
  84 }
  85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
  86
  87 /**
  88  * irq_gc_unmask_enable_reg - Unmask chip via enable register
  89  * @d: irq_data
  90  *
  91  * Chip has separate enable/disable registers instead of a single mask
  92  * register.
  93  */
  94 void irq_gc_unmask_enable_reg(struct irq_data *d)
  95 {
  96         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  97         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  98         u32 mask = d->mask;
  99
 100         irq_gc_lock(gc);
 101         irq_reg_writel(gc, mask, ct->regs.enable);
 102         *ct->mask_cache |= mask;
 103         irq_gc_unlock(gc);
 104 }
 105
 106 /**
 107  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 108  * @d: irq_data
 109  */
 110 void irq_gc_ack_set_bit(struct irq_data *d)
 111 {
 112         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 113         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 114         u32 mask = d->mask;
 115
 116         irq_gc_lock(gc);
 117         irq_reg_writel(gc, mask, ct->regs.ack);
 118         irq_gc_unlock(gc);
 119 }
 120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
 121
 122 /**
 123  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 124  * @d: irq_data
 125  */
 126 void irq_gc_ack_clr_bit(struct irq_data *d)
 127 {
 128         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 129         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 130         u32 mask = ~d->mask;
 131
 132         irq_gc_lock(gc);
 133         irq_reg_writel(gc, mask, ct->regs.ack);
 134         irq_gc_unlock(gc);
 135 }
 136
 137 /**
 138  * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
 139  * @d: irq_data
 140  */
 141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
 142 {
 143         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 144         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 145         u32 mask = d->mask;
 146
 147         irq_gc_lock(gc);
 148         irq_reg_writel(gc, mask, ct->regs.mask);
 149         irq_reg_writel(gc, mask, ct->regs.ack);
 150         irq_gc_unlock(gc);
 151 }
 152
 153 /**
 154  * irq_gc_eoi - EOI interrupt
 155  * @d: irq_data
 156  */
 157 void irq_gc_eoi(struct irq_data *d)
 158 {
 159         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 160         struct irq_chip_type *ct = irq_data_get_chip_type(d);
 161         u32 mask = d->mask;
 162
 163         irq_gc_lock(gc);
 164         irq_reg_writel(gc, mask, ct->regs.eoi);
 165         irq_gc_unlock(gc);
 166 }
 167
 168 /**
 169  * irq_gc_set_wake - Set/clr wake bit for an interrupt
 170  * @d:  irq_data
 171  * @on: Indicates whether the wake bit should be set or cleared
 172  *
 173  * For chips where the wake from suspend functionality is not
 174  * configured in a separate register and the wakeup active state is
 175  * just stored in a bitmask.
 176  */
 177 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
 178 {
 179         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 180         u32 mask = d->mask;
 181
 182         if (!(mask & gc->wake_enabled))
 183                 return -EINVAL;
 184
 185         irq_gc_lock(gc);
 186         if (on)
 187                 gc->wake_active |= mask;
 188         else
 189                 gc->wake_active &= ~mask;
 190         irq_gc_unlock(gc);
 191         return 0;
 192 }
 193
 194 static u32 irq_readl_be(void __iomem *addr)
 195 {
 196         return ioread32be(addr);
 197 }
 198
 199 static void irq_writel_be(u32 val, void __iomem *addr)
 200 {
 201         iowrite32be(val, addr);
 202 }
 203
 204 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
 205                            int num_ct, unsigned int irq_base,
 206                            void __iomem *reg_base, irq_flow_handler_t handler)
 207 {
 208         raw_spin_lock_init(&gc->lock);
 209         gc->num_ct = num_ct;
 210         gc->irq_base = irq_base;
 211         gc->reg_base = reg_base;
 212         gc->chip_types->chip.name = name;
 213         gc->chip_types->handler = handler;
 214 }
 215
 216 /**
 217  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 218  * @name:       Name of the irq chip
 219  * @num_ct:     Number of irq_chip_type instances associated with this
 220  * @irq_base:   Interrupt base nr for this chip
 221  * @reg_base:   Register base address (virtual)
 222  * @handler:    Default flow handler associated with this chip
 223  *
 224  * Returns an initialized irq_chip_generic structure. The chip defaults
 225  * to the primary (index 0) irq_chip_type and @handler
 226  */
 227 struct irq_chip_generic *
 228 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
 229                        void __iomem *reg_base, irq_flow_handler_t handler)
 230 {
 231         struct irq_chip_generic *gc;
 232         unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 233
 234         gc = kzalloc(sz, GFP_KERNEL);
 235         if (gc) {
 236                 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
 237                                       handler);
 238         }
 239         return gc;
 240 }
 241 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
 242
 243 static void
 244 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
 245 {
 246         struct irq_chip_type *ct = gc->chip_types;
 247         u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
 248         int i;
 249
 250         for (i = 0; i < gc->num_ct; i++) {
 251                 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
 252                         mskptr = &ct[i].mask_cache_priv;
 253                         mskreg = ct[i].regs.mask;
 254                 }
 255                 ct[i].mask_cache = mskptr;
 256                 if (flags & IRQ_GC_INIT_MASK_CACHE)
 257                         *mskptr = irq_reg_readl(gc, mskreg);
 258         }
 259 }
 260
 261 /**
 262  * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
 263  * @d:                  irq domain for which to allocate chips
 264  * @irqs_per_chip:      Number of interrupts each chip handles (max 32)
 265  * @num_ct:             Number of irq_chip_type instances associated with this
 266  * @name:               Name of the irq chip
 267  * @handler:            Default flow handler associated with these chips
 268  * @clr:                IRQ_* bits to clear in the mapping function
 269  * @set:                IRQ_* bits to set in the mapping function
 270  * @gcflags:            Generic chip specific setup flags
 271  */
 272 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
 273                                      int num_ct, const char *name,
 274                                      irq_flow_handler_t handler,
 275                                      unsigned int clr, unsigned int set,
 276                                      enum irq_gc_flags gcflags)
 277 {
 278         struct irq_domain_chip_generic *dgc;
 279         struct irq_chip_generic *gc;
 280         int numchips, sz, i;
 281         unsigned long flags;
 282         void *tmp;
 283
 284         if (d->gc)
 285                 return -EBUSY;
 286
 287         numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
 288         if (!numchips)
 289                 return -EINVAL;
 290
 291         /* Allocate a pointer, generic chip and chiptypes for each chip */
 292         sz = sizeof(*dgc) + numchips * sizeof(gc);
 293         sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
 294
 295         tmp = dgc = kzalloc(sz, GFP_KERNEL);
 296         if (!dgc)
 297                 return -ENOMEM;
 298         dgc->irqs_per_chip = irqs_per_chip;
 299         dgc->num_chips = numchips;
 300         dgc->irq_flags_to_set = set;
 301         dgc->irq_flags_to_clear = clr;
 302         dgc->gc_flags = gcflags;
 303         d->gc = dgc;
 304
 305         /* Calc pointer to the first generic chip */
 306         tmp += sizeof(*dgc) + numchips * sizeof(gc);
 307         for (i = 0; i < numchips; i++) {
 308                 /* Store the pointer to the generic chip */
 309                 dgc->gc[i] = gc = tmp;
 310                 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
 311                                       NULL, handler);
 312
 313                 gc->domain = d;
 314                 if (gcflags & IRQ_GC_BE_IO) {
 315                         gc->reg_readl = &irq_readl_be;
 316                         gc->reg_writel = &irq_writel_be;
 317                 }
 318
 319                 raw_spin_lock_irqsave(&gc_lock, flags);
 320                 list_add_tail(&gc->list, &gc_list);
 321                 raw_spin_unlock_irqrestore(&gc_lock, flags);
 322                 /* Calc pointer to the next generic chip */
 323                 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
 324         }
 325         return 0;
 326 }
 327 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
 328
 329 static struct irq_chip_generic *
 330 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
 331 {
 332         struct irq_domain_chip_generic *dgc = d->gc;
 333         int idx;
 334
 335         if (!dgc)
 336                 return ERR_PTR(-ENODEV);
 337         idx = hw_irq / dgc->irqs_per_chip;
 338         if (idx >= dgc->num_chips)
 339                 return ERR_PTR(-EINVAL);
 340         return dgc->gc[idx];
 341 }
 342
 343 /**
 344  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 345  * @d:                  irq domain pointer
 346  * @hw_irq:             Hardware interrupt number
 347  */
 348 struct irq_chip_generic *
 349 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
 350 {
 351         struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
 352
 353         return !IS_ERR(gc) ? gc : NULL;
 354 }
 355 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
 356
 357 /*
 358  * Separate lockdep class for interrupt chip which can nest irq_desc
 359  * lock.
 360  */
 361 static struct lock_class_key irq_nested_lock_class;
 362
 363 /*
 364  * irq_map_generic_chip - Map a generic chip for an irq domain
 365  */
 366 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 367                          irq_hw_number_t hw_irq)
 368 {
 369         struct irq_data *data = irq_domain_get_irq_data(d, virq);
 370         struct irq_domain_chip_generic *dgc = d->gc;
 371         struct irq_chip_generic *gc;
 372         struct irq_chip_type *ct;
 373         struct irq_chip *chip;
 374         unsigned long flags;
 375         int idx;
 376
 377         gc = __irq_get_domain_generic_chip(d, hw_irq);
 378         if (IS_ERR(gc))
 379                 return PTR_ERR(gc);
 380
 381         idx = hw_irq % dgc->irqs_per_chip;
 382
 383         if (test_bit(idx, &gc->unused))
 384                 return -ENOTSUPP;
 385
 386         if (test_bit(idx, &gc->installed))
 387                 return -EBUSY;
 388
 389         ct = gc->chip_types;
 390         chip = &ct->chip;
 391
 392         /* We only init the cache for the first mapping of a generic chip */
 393         if (!gc->installed) {
 394                 raw_spin_lock_irqsave(&gc->lock, flags);
 395                 irq_gc_init_mask_cache(gc, dgc->gc_flags);
 396                 raw_spin_unlock_irqrestore(&gc->lock, flags);
 397         }
 398
 399         /* Mark the interrupt as installed */
 400         set_bit(idx, &gc->installed);
 401
 402         if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
 403                 irq_set_lockdep_class(virq, &irq_nested_lock_class);
 404
 405         if (chip->irq_calc_mask)
 406                 chip->irq_calc_mask(data);
 407         else
 408                 data->mask = 1 << idx;
 409
 410         irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
 411         irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
 412         return 0;
 413 }
 414
 415 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
 416 {
 417         struct irq_data *data = irq_domain_get_irq_data(d, virq);
 418         struct irq_domain_chip_generic *dgc = d->gc;
 419         unsigned int hw_irq = data->hwirq;
 420         struct irq_chip_generic *gc;
 421         int irq_idx;
 422
 423         gc = irq_get_domain_generic_chip(d, hw_irq);
 424         if (!gc)
 425                 return;
 426
 427         irq_idx = hw_irq % dgc->irqs_per_chip;
 428
 429         clear_bit(irq_idx, &gc->installed);
 430         irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
 431                             NULL);
 432
 433 }
 434
 435 struct irq_domain_ops irq_generic_chip_ops = {
 436         .map    = irq_map_generic_chip,
 437         .unmap  = irq_unmap_generic_chip,
 438         .xlate  = irq_domain_xlate_onetwocell,
 439 };
 440 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
 441
 442 /**
 443  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 444  * @gc:         Generic irq chip holding all data
 445  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 446  * @flags:      Flags for initialization
 447  * @clr:        IRQ_* bits to clear
 448  * @set:        IRQ_* bits to set
 449  *
 450  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 451  * initializes all interrupts to the primary irq_chip_type and its
 452  * associated handler.
 453  */
 454 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 455                             enum irq_gc_flags flags, unsigned int clr,
 456                             unsigned int set)
 457 {
 458         struct irq_chip_type *ct = gc->chip_types;
 459         struct irq_chip *chip = &ct->chip;
 460         unsigned int i;
 461
 462         raw_spin_lock(&gc_lock);
 463         list_add_tail(&gc->list, &gc_list);
 464         raw_spin_unlock(&gc_lock);
 465
 466         irq_gc_init_mask_cache(gc, flags);
 467
 468         for (i = gc->irq_base; msk; msk >>= 1, i++) {
 469                 if (!(msk & 0x01))
 470                         continue;
 471
 472                 if (flags & IRQ_GC_INIT_NESTED_LOCK)
 473                         irq_set_lockdep_class(i, &irq_nested_lock_class);
 474
 475                 if (!(flags & IRQ_GC_NO_MASK)) {
 476                         struct irq_data *d = irq_get_irq_data(i);
 477
 478                         if (chip->irq_calc_mask)
 479                                 chip->irq_calc_mask(d);
 480                         else
 481                                 d->mask = 1 << (i - gc->irq_base);
 482                 }
 483                 irq_set_chip_and_handler(i, chip, ct->handler);
 484                 irq_set_chip_data(i, gc);
 485                 irq_modify_status(i, clr, set);
 486         }
 487         gc->irq_cnt = i - gc->irq_base;
 488 }
 489 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
 490
 491 /**
 492  * irq_setup_alt_chip - Switch to alternative chip
 493  * @d:          irq_data for this interrupt
 494  * @type:       Flow type to be initialized
 495  *
 496  * Only to be called from chip->irq_set_type() callbacks.
 497  */
 498 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
 499 {
 500         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 501         struct irq_chip_type *ct = gc->chip_types;
 502         unsigned int i;
 503
 504         for (i = 0; i < gc->num_ct; i++, ct++) {
 505                 if (ct->type & type) {
 506                         d->chip = &ct->chip;
 507                         irq_data_to_desc(d)->handle_irq = ct->handler;
 508                         return 0;
 509                 }
 510         }
 511         return -EINVAL;
 512 }
 513 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
 514
 515 /**
 516  * irq_remove_generic_chip - Remove a chip
 517  * @gc:         Generic irq chip holding all data
 518  * @msk:        Bitmask holding the irqs to initialize relative to gc->irq_base
 519  * @clr:        IRQ_* bits to clear
 520  * @set:        IRQ_* bits to set
 521  *
 522  * Remove up to 32 interrupts starting from gc->irq_base.
 523  */
 524 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
 525                              unsigned int clr, unsigned int set)
 526 {
 527         unsigned int i = gc->irq_base;
 528
 529         raw_spin_lock(&gc_lock);
 530         list_del(&gc->list);
 531         raw_spin_unlock(&gc_lock);
 532
 533         for (; msk; msk >>= 1, i++) {
 534                 if (!(msk & 0x01))
 535                         continue;
 536
 537                 /* Remove handler first. That will mask the irq line */
 538                 irq_set_handler(i, NULL);
 539                 irq_set_chip(i, &no_irq_chip);
 540                 irq_set_chip_data(i, NULL);
 541                 irq_modify_status(i, clr, set);
 542         }
 543 }
 544 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
 545
 546 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
 547 {
 548         unsigned int virq;
 549
 550         if (!gc->domain)
 551                 return irq_get_irq_data(gc->irq_base);
 552
 553         /*
 554          * We don't know which of the irqs has been actually
 555          * installed. Use the first one.
 556          */
 557         if (!gc->installed)
 558                 return NULL;
 559
 560         virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
 561         return virq ? irq_get_irq_data(virq) : NULL;
 562 }
 563
 564 #ifdef CONFIG_PM
 565 static int irq_gc_suspend(void)
 566 {
 567         struct irq_chip_generic *gc;
 568
 569         list_for_each_entry(gc, &gc_list, list) {
 570                 struct irq_chip_type *ct = gc->chip_types;
 571
 572                 if (ct->chip.irq_suspend) {
 573                         struct irq_data *data = irq_gc_get_irq_data(gc);
 574
 575                         if (data)
 576                                 ct->chip.irq_suspend(data);
 577                 }
 578
 579                 if (gc->suspend)
 580                         gc->suspend(gc);
 581         }
 582         return 0;
 583 }
 584
 585 static void irq_gc_resume(void)
 586 {
 587         struct irq_chip_generic *gc;
 588
 589         list_for_each_entry(gc, &gc_list, list) {
 590                 struct irq_chip_type *ct = gc->chip_types;
 591
 592                 if (gc->resume)
 593                         gc->resume(gc);
 594
 595                 if (ct->chip.irq_resume) {
 596                         struct irq_data *data = irq_gc_get_irq_data(gc);
 597
 598                         if (data)
 599                                 ct->chip.irq_resume(data);
 600                 }
 601         }
 602 }
 603 #else
 604 #define irq_gc_suspend NULL
 605 #define irq_gc_resume NULL
 606 #endif
 607
 608 static void irq_gc_shutdown(void)
 609 {
 610         struct irq_chip_generic *gc;
 611
 612         list_for_each_entry(gc, &gc_list, list) {
 613                 struct irq_chip_type *ct = gc->chip_types;
 614
 615                 if (ct->chip.irq_pm_shutdown) {
 616                         struct irq_data *data = irq_gc_get_irq_data(gc);
 617
 618                         if (data)
 619                                 ct->chip.irq_pm_shutdown(data);
 620                 }
 621         }
 622 }
 623
 624 static struct syscore_ops irq_gc_syscore_ops = {
 625         .suspend = irq_gc_suspend,
 626         .resume = irq_gc_resume,
 627         .shutdown = irq_gc_shutdown,
 628 };
 629
 630 static int __init irq_gc_init_ops(void)
 631 {
 632         register_syscore_ops(&irq_gc_syscore_ops);
 633         return 0;
 634 }
 635 device_initcall(irq_gc_init_ops);