-Source: http://ports.ubuntu.com/pool/multiverse/v/virtualbox/virtualbox-guest-dkms_5.1.20-dfsg-2_all.deb
-Version: 5.1.20-dfsg-2
+Source: http://ports.ubuntu.com/pool/multiverse/v/virtualbox/virtualbox-guest-dkms_5.1.22-dfsg-1_all.deb
+Version: 5.1.22-dfsg-1
PACKAGE_NAME="virtualbox-guest"
-PACKAGE_VERSION="5.1.20"
+PACKAGE_VERSION="5.1.22"
CLEAN="rm -f *.*o"
BUILT_MODULE_NAME[0]="vboxguest"
BUILT_MODULE_LOCATION[0]="vboxguest"
* @param type The return type of the function declaration.
*/
#if defined(IN_DIS)
-# define DISDECL(type) DECLEXPORT(type) VBOXCALL
+# ifdef IN_DIS_STATIC
+# define DISDECL(type) DECLHIDDEN(type) VBOXCALL
+# else
+# define DISDECL(type) DECLEXPORT(type) VBOXCALL
+# endif
#else
# define DISDECL(type) DECLIMPORT(type) VBOXCALL
#endif
#define VERR_SVM_IPE_4 (-4064)
/** Internal SVM processing error no 5. */
#define VERR_SVM_IPE_5 (-4065)
+/** The nested-guest \#VMEXIT processing failed, initiate shutdown. */
+#define VERR_SVM_VMEXIT_FAILED (-4066)
+/** An operation caused a nested-guest SVM \#VMEXIT. */
+#define VINF_SVM_VMEXIT 4067
/** @} */
#define VERR_HM_INVALID_HM64ON32OP (-4116)
/** Resume guest execution after injecting a double-fault. */
#define VINF_HM_DOUBLE_FAULT 4117
+/** The requested nested-guest VM-exit intercept is not active or not in
+ * nested-guest execution mode. */
+#define VINF_HM_INTERCEPT_NOT_ACTIVE 4118
/** @} */
DECLASM(void) ASMXRstor(struct X86XSAVEAREA const *pXStateArea, uint64_t fComponents);
+struct X86FXSTATE;
+/**
+ * Save FPU and SSE CPU state.
+ * @param pXStateArea Where to save the state.
+ */
+DECLASM(void) ASMFxSave(struct X86FXSTATE *pXStateArea);
+
+/**
+ * Load FPU and SSE CPU state.
+ * @param pXStateArea Where to load the state from.
+ */
+DECLASM(void) ASMFxRstor(struct X86FXSTATE const *pXStateArea);
+
+
/**
* Enables interrupts (EFLAGS.IF).
*/
/** RT_CONCAT6 helper, don't use. */
#define RT_CONCAT6_HLP(a,b,c,d,e,f) a##b##c##d##e##f
+/** @def RT_CONCAT7
+ * Concatenate the expanded arguments without any extra spaces in between.
+ *
+ * @param a The 1st part.
+ * @param b The 2nd part.
+ * @param c The 3rd part.
+ * @param d The 4th part.
+ * @param e The 5th part.
+ * @param f The 6th part.
+ * @param g The 7th part.
+ */
+#define RT_CONCAT7(a,b,c,d,e,f,g) RT_CONCAT7_HLP(a,b,c,d,e,f,g)
+/** RT_CONCAT7 helper, don't use. */
+#define RT_CONCAT7_HLP(a,b,c,d,e,f,g) a##b##c##d##e##f##g
+
+/** @def RT_CONCAT8
+ * Concatenate the expanded arguments without any extra spaces in between.
+ *
+ * @param a The 1st part.
+ * @param b The 2nd part.
+ * @param c The 3rd part.
+ * @param d The 4th part.
+ * @param e The 5th part.
+ * @param f The 6th part.
+ * @param g The 7th part.
+ * @param h The 8th part.
+ */
+#define RT_CONCAT8(a,b,c,d,e,f,g,h) RT_CONCAT8_HLP(a,b,c,d,e,f,g,h)
+/** RT_CONCAT8 helper, don't use. */
+#define RT_CONCAT8_HLP(a,b,c,d,e,f,g,h) a##b##c##d##e##f##g##h
+
+/** @def RT_CONCAT9
+ * Concatenate the expanded arguments without any extra spaces in between.
+ *
+ * @param a The 1st part.
+ * @param b The 2nd part.
+ * @param c The 3rd part.
+ * @param d The 4th part.
+ * @param e The 5th part.
+ * @param f The 6th part.
+ * @param g The 7th part.
+ * @param h The 8th part.
+ * @param i The 9th part.
+ */
+#define RT_CONCAT9(a,b,c,d,e,f,g,h,i) RT_CONCAT9_HLP(a,b,c,d,e,f,g,h,i)
+/** RT_CONCAT9 helper, don't use. */
+#define RT_CONCAT9_HLP(a,b,c,d,e,f,g,h,i) a##b##c##d##e##f##g##h##i
+
/**
* String constant tuple - string constant, strlen(string constant).
*
*/
#define RT_ELEMENTS(aArray) ( sizeof(aArray) / sizeof((aArray)[0]) )
+/** @def RT_FLEXIBLE_ARRAY
+ * What to up inside the square brackets when declaring a structure member
+ * with a flexible size.
+ *
+ * @note Use RT_UOFFSETOF() to calculate the structure size.
+ *
+ * @note Never to a sizeof() on the structure or member!
+ *
+ * @note The member must be the last one.
+ *
+ * @note GCC does not permit using this in a union. So, for unions you must
+ * use RT_FLEXIBLE_ARRAY_IN_UNION instead.
+ *
+ * @note GCC does not permit using this in nested structures, where as MSC
+ * does. So, use RT_FLEXIBLE_ARRAY_NESTED for that.
+ *
+ * @sa RT_FLEXIBLE_ARRAY_NESTED, RT_FLEXIBLE_ARRAY_IN_UNION
+ */
+#if RT_MSC_PREREQ(RT_MSC_VER_VS2005) /** @todo Probably much much earlier. */ \
+ || (defined(__cplusplus) && RT_GNUC_PREREQ(6, 1)) \
+ || defined(__WATCOMC__) /* openwatcom 1.9 supports it, we don't care about older atm. */
+# define RT_FLEXIBLE_ARRAY
+# if defined(__cplusplus) && defined(_MSC_VER)
+# pragma warning(disable:4200) /* -wd4200 does not work with VS2010 */
+# endif
+#elif defined(__STDC_VERSION__)
+# if __STDC_VERSION__ >= 1999901L
+# define RT_FLEXIBLE_ARRAY
+# else
+# define RT_FLEXIBLE_ARRAY 1
+# endif
+#else
+# define RT_FLEXIBLE_ARRAY 1
+#endif
+
+/** @def RT_FLEXIBLE_ARRAY_NESTED
+ * Variant of RT_FLEXIBLE_ARRAY for use in structures that are nested.
+ *
+ * GCC only allow the use of flexible array member in the top structure, whereas
+ * MSC is less strict and let you do struct { struct { char szName[]; } s; };
+ *
+ * @note See notes for RT_FLEXIBLE_ARRAY.
+ *
+ * @note GCC does not permit using this in a union. So, for unions you must
+ * use RT_FLEXIBLE_ARRAY_IN_NESTED_UNION instead.
+ *
+ * @sa RT_FLEXIBLE_ARRAY, RT_FLEXIBLE_ARRAY_IN_NESTED_UNION
+ */
+#ifdef _MSC_VER
+# define RT_FLEXIBLE_ARRAY_NESTED RT_FLEXIBLE_ARRAY
+#else
+# define RT_FLEXIBLE_ARRAY_NESTED 1
+#endif
+
+/** @def RT_FLEXIBLE_ARRAY_IN_UNION
+ * The union version of RT_FLEXIBLE_ARRAY.
+ *
+ * @remarks GCC does not support flexible array members in unions, 6.1.x
+ * actively checks for this. Visual C++ 2010 seems happy with it.
+ *
+ * @note See notes for RT_FLEXIBLE_ARRAY.
+ *
+ * @sa RT_FLEXIBLE_ARRAY, RT_FLEXIBLE_ARRAY_IN_NESTED_UNION
+ */
+#ifdef _MSC_VER
+# define RT_FLEXIBLE_ARRAY_IN_UNION RT_FLEXIBLE_ARRAY
+#else
+# define RT_FLEXIBLE_ARRAY_IN_UNION 1
+#endif
+
+/** @def RT_FLEXIBLE_ARRAY_IN_NESTED_UNION
+ * The union version of RT_FLEXIBLE_ARRAY_NESTED.
+ *
+ * @note See notes for RT_FLEXIBLE_ARRAY.
+ *
+ * @sa RT_FLEXIBLE_ARRAY, RT_FLEXIBLE_ARRAY_IN_NESTED_UNION
+ */
+#ifdef _MSC_VER
+# define RT_FLEXIBLE_ARRAY_IN_NESTED_UNION RT_FLEXIBLE_ARRAY_NESTED
+#else
+# define RT_FLEXIBLE_ARRAY_IN_NESTED_UNION 1
+#endif
+
/**
* Checks if the value is a power of two.
*
/** @def RT_NOREF9
* RT_NOREF_PV shorthand taking nine parameters. */
#define RT_NOREF9(var1, var2, var3, var4, var5, var6, var7, var8, var9) \
- RT_NOREF_PV(var1); RT_NOREF8(var2, var3, var4, var5, var6, var7, var8)
+ RT_NOREF_PV(var1); RT_NOREF8(var2, var3, var4, var5, var6, var7, var8, var9)
/** @def RT_NOREF10
* RT_NOREF_PV shorthand taking ten parameters. */
#define RT_NOREF10(var1, var2, var3, var4, var5, var6, var7, var8, var9, var10) \
# define ASMXRstor_EndProc RT_MANGLER(ASMXRstor_EndProc)
# define ASMXSave RT_MANGLER(ASMXSave)
# define ASMXSave_EndProc RT_MANGLER(ASMXSave_EndProc)
+# define ASMFxRstor RT_MANGLER(ASMFxRstor)
+# define ASMFxRstor_EndProc RT_MANGLER(ASMFxRstor_EndProc)
+# define ASMFxSave RT_MANGLER(ASMFxSave)
+# define ASMFxSave_EndProc RT_MANGLER(ASMFxSave_EndProc)
# define RTAssertAreQuiet RT_MANGLER(RTAssertAreQuiet)
# define RTAssertMayPanic RT_MANGLER(RTAssertMayPanic)
/** @} */
+/** @name CPUID AMD SVM Feature information.
+ * CPUID query with EAX=0x8000000a.
+ * @{
+ */
+/** Bit 0 - NP - Nested Paging supported. */
+#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
+/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
+#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
+/** Bit 2 - SVML - SVM locking bit supported. */
+#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
+/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
+#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
+/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
+#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
+/** Bit 5 - VmcbClean - Support VMCB clean bits. */
+#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
+/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
+ * VMCB.TLB_Control is supported. */
+#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
+/** Bit 7 - DecodeAssist - Indicate decode assist is supported. */
+#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
+/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
+#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
+/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
+ * intercept filter cycle count threshold. */
+#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
+/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
+#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
+/** @} */
+
+
/** @name CR0
* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
* reserved flags.
/** Hypertransport interrupt pending register.
* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
+
+/** SVM Control. */
#define MSR_K8_VM_CR UINT32_C(0xc0010114)
+/** Disables HDT (Hardware Debug Tool) and certain internal debug
+ * features. */
+#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
+/** If set, non-intercepted INIT signals are converted to \#SX
+ * exceptions. */
+#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
+/** Disables A20 masking. */
+#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
+/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
+#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
+/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
+ * clear, EFER.SVME can be written normally. */
#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
#define MSR_K8_IGNNE UINT32_C(0xc0010115)
*/
typedef union X86XMMREG
{
- /** XMM Register view *. */
+ /** XMM Register view. */
uint128_t xmm;
/** 8-bit view. */
uint8_t au8[16];
uint64_t au64[2];
/** 128-bit view. (yeah, very helpful) */
uint128_t au128[1];
+ /** Confusing nested 128-bit union view (this is what xmm should've been). */
+ RTUINT128U uXmm;
} X86XMMREG;
#ifndef VBOX_FOR_DTRACE_LIB
AssertCompileSize(X86XMMREG, 16);
/** @name SSE MXCSR
* @{ */
/** Exception Flag: Invalid operation. */
-#define X86_MXSCR_IE RT_BIT_32(0)
+#define X86_MXCSR_IE RT_BIT_32(0)
/** Exception Flag: Denormalized operand. */
-#define X86_MXSCR_DE RT_BIT_32(1)
+#define X86_MXCSR_DE RT_BIT_32(1)
/** Exception Flag: Zero divide. */
-#define X86_MXSCR_ZE RT_BIT_32(2)
+#define X86_MXCSR_ZE RT_BIT_32(2)
/** Exception Flag: Overflow. */
-#define X86_MXSCR_OE RT_BIT_32(3)
+#define X86_MXCSR_OE RT_BIT_32(3)
/** Exception Flag: Underflow. */
-#define X86_MXSCR_UE RT_BIT_32(4)
+#define X86_MXCSR_UE RT_BIT_32(4)
/** Exception Flag: Precision. */
-#define X86_MXSCR_PE RT_BIT_32(5)
+#define X86_MXCSR_PE RT_BIT_32(5)
/** Denormals are zero. */
-#define X86_MXSCR_DAZ RT_BIT_32(6)
+#define X86_MXCSR_DAZ RT_BIT_32(6)
/** Exception Mask: Invalid operation. */
-#define X86_MXSCR_IM RT_BIT_32(7)
+#define X86_MXCSR_IM RT_BIT_32(7)
/** Exception Mask: Denormalized operand. */
-#define X86_MXSCR_DM RT_BIT_32(8)
+#define X86_MXCSR_DM RT_BIT_32(8)
/** Exception Mask: Zero divide. */
-#define X86_MXSCR_ZM RT_BIT_32(9)
+#define X86_MXCSR_ZM RT_BIT_32(9)
/** Exception Mask: Overflow. */
-#define X86_MXSCR_OM RT_BIT_32(10)
+#define X86_MXCSR_OM RT_BIT_32(10)
/** Exception Mask: Underflow. */
-#define X86_MXSCR_UM RT_BIT_32(11)
+#define X86_MXCSR_UM RT_BIT_32(11)
/** Exception Mask: Precision. */
-#define X86_MXSCR_PM RT_BIT_32(12)
+#define X86_MXCSR_PM RT_BIT_32(12)
/** Rounding control mask. */
-#define X86_MXSCR_RC_MASK UINT16_C(0x6000)
+#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
/** Rounding control: To nearest. */
-#define X86_MXSCR_RC_NEAREST UINT16_C(0x0000)
+#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
/** Rounding control: Down. */
-#define X86_MXSCR_RC_DOWN UINT16_C(0x2000)
+#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
/** Rounding control: Up. */
-#define X86_MXSCR_RC_UP UINT16_C(0x4000)
+#define X86_MXCSR_RC_UP UINT16_C(0x4000)
/** Rounding control: Towards zero. */
-#define X86_MXSCR_RC_ZERO UINT16_C(0x6000)
+#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
/** Flush-to-zero for masked underflow. */
-#define X86_MXSCR_FZ RT_BIT_32(15)
+#define X86_MXCSR_FZ RT_BIT_32(15)
/** Misaligned Exception Mask (AMD MISALIGNSSE). */
-#define X86_MXSCR_MM RT_BIT_32(17)
+#define X86_MXCSR_MM RT_BIT_32(17)
/** @} */
/**
typedef X86XSAVEAREA const *PCX86XSAVEAREA;
-/** @name XSAVE_C_XXX - XSAVE State Components Bits.
+/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
* @{ */
/** Bit 0 - x87 - Legacy FPU state (bit number) */
#define XSAVE_C_X87_BIT 0
#define XSAVE_C_LWP_BIT 62
/** Bit 62 - LWP - Lightweight Profiling (AMD). */
#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
+/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
+#define XSAVE_C_X_BIT 63
+/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
+#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
/** @} */
/** \#VE - Virtualization Exception. */
X86_XCPT_VE = 0x14,
/** \#SX - Security Exception. */
- X86_XCPT_SX = 0x1f
+ X86_XCPT_SX = 0x1e
} X86XCPT;
/** Pointer to a x86 exception code. */
typedef X86XCPT *PX86XCPT;
/** Pointer to a const x86 exception code. */
typedef const X86XCPT *PCX86XCPT;
-/** The maximum exception value. */
-#define X86_XCPT_MAX (X86_XCPT_SX)
+/** The last valid (currently reserved) exception value. */
+#define X86_XCPT_LAST 0x1f
/** @name Trap Error Codes
AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
+/** @def X86_MODRM_MAKE
+ * @param a_Mod The mod value (0..3).
+ * @param a_Reg The register value (0..7).
+ * @param a_RegMem The register or memory value (0..7). */
+# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
#endif
/** @} */
#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
#define X86_OP_PRF_LOCK UINT8_C(0xf0)
-#define X86_OP_PRF_REPZ UINT8_C(0xf2)
-#define X86_OP_PRF_REPNZ UINT8_C(0xf3)
+#define X86_OP_PRF_REPZ UINT8_C(0xf3)
+#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
#define X86_OP_REX_B UINT8_C(0x41)
#define X86_OP_REX_X UINT8_C(0x42)
#define X86_OP_REX_R UINT8_C(0x44)
-#define VBOX_SVN_REV 114628
+#define VBOX_SVN_REV 115126
#define VBOX_VERSION_MAJOR 5
#define VBOX_VERSION_MINOR 1
-#define VBOX_VERSION_BUILD 20
-#define VBOX_VERSION_STRING_RAW "5.1.20"
-#define VBOX_VERSION_STRING "5.1.20_Ubuntu"
+#define VBOX_VERSION_BUILD 22
+#define VBOX_VERSION_STRING_RAW "5.1.22"
+#define VBOX_VERSION_STRING "5.1.22_Ubuntu"
#define VBOX_API_VERSION_STRING "5_1"
#define VBOX_PRIVATE_BUILD_DESC "Private build by root"
-#define VBOX_SVN_REV 114628
+#define VBOX_SVN_REV 115126
#define VBOX_VERSION_MAJOR 5
#define VBOX_VERSION_MINOR 1
-#define VBOX_VERSION_BUILD 20
-#define VBOX_VERSION_STRING_RAW "5.1.20"
-#define VBOX_VERSION_STRING "5.1.20_Ubuntu"
+#define VBOX_VERSION_BUILD 22
+#define VBOX_VERSION_STRING_RAW "5.1.22"
+#define VBOX_VERSION_STRING "5.1.22_Ubuntu"
#define VBOX_API_VERSION_STRING "5_1"
#define VBOX_PRIVATE_BUILD_DESC "Private build by root"
-#define VBOX_SVN_REV 114628
+#define VBOX_SVN_REV 115126
#define VBOX_VERSION_MAJOR 5
#define VBOX_VERSION_MINOR 1
-#define VBOX_VERSION_BUILD 20
-#define VBOX_VERSION_STRING_RAW "5.1.20"
-#define VBOX_VERSION_STRING "5.1.20_Ubuntu"
+#define VBOX_VERSION_BUILD 22
+#define VBOX_VERSION_STRING_RAW "5.1.22"
+#define VBOX_VERSION_STRING "5.1.22_Ubuntu"
#define VBOX_API_VERSION_STRING "5_1"
#define VBOX_PRIVATE_BUILD_DESC "Private build by root"
projects / mirror_ubuntu-artful-kernel.git / commitdiff