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KVM: convert io_bus to SRCU
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
aec51dc4
AK		 42#include <trace/events/kvm.h>
43#undef TRACE_INCLUDE_FILE
229456fc
MT		 44#define CREATE_TRACE_POINTS
45#include "trace.h"
043405e1 46
24f1e32c 47#include <asm/debugreg.h>
043405e1 48#include <asm/uaccess.h>
d825ed0a 49#include <asm/msr.h>
a5f61300 50#include <asm/desc.h>
0bed3b56 51#include <asm/mtrr.h>
890ca9ae 52#include <asm/mce.h>
043405e1 53
313a3dc7 54#define MAX_IO_MSRS 256
a03490ed
CO		 55#define CR0_RESERVED_BITS \
56 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
57 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
58 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
59#define CR4_RESERVED_BITS \
60 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
61 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
62 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
63 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
64
65#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 66
67#define KVM_MAX_MCE_BANKS 32
68#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
69
50a37eb4
JR		 70/* EFER defaults:
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
73 */
74#ifdef CONFIG_X86_64
75static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
76#else
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
18863bdd
AK		 93#define KVM_NR_SHARED_MSRS 16
94
95struct kvm_shared_msrs_global {
96 int nr;
2bf78fa7 97 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 98};
99
100struct kvm_shared_msrs {
101 struct user_return_notifier urn;
102 bool registered;
2bf78fa7
SY		 103 struct kvm_shared_msr_values {
104 u64 host;
105 u64 curr;
106 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
110static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
111
417bc304 112struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 113 { "pf_fixed", VCPU_STAT(pf_fixed) },
114 { "pf_guest", VCPU_STAT(pf_guest) },
115 { "tlb_flush", VCPU_STAT(tlb_flush) },
116 { "invlpg", VCPU_STAT(invlpg) },
117 { "exits", VCPU_STAT(exits) },
118 { "io_exits", VCPU_STAT(io_exits) },
119 { "mmio_exits", VCPU_STAT(mmio_exits) },
120 { "signal_exits", VCPU_STAT(signal_exits) },
121 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 122 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 123 { "halt_exits", VCPU_STAT(halt_exits) },
124 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 125 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 126 { "request_irq", VCPU_STAT(request_irq_exits) },
127 { "irq_exits", VCPU_STAT(irq_exits) },
128 { "host_state_reload", VCPU_STAT(host_state_reload) },
129 { "efer_reload", VCPU_STAT(efer_reload) },
130 { "fpu_reload", VCPU_STAT(fpu_reload) },
131 { "insn_emulation", VCPU_STAT(insn_emulation) },
132 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 133 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 134 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 135 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
136 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
137 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
138 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
139 { "mmu_flooded", VM_STAT(mmu_flooded) },
140 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 141 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 142 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 143 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 144 { "largepages", VM_STAT(lpages) },
417bc304
HB		 145 { NULL }
146};
147
18863bdd
AK		 148static void kvm_on_user_return(struct user_return_notifier *urn)
149{
150 unsigned slot;
18863bdd
AK		 151 struct kvm_shared_msrs *locals
152 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 153 struct kvm_shared_msr_values *values;
18863bdd
AK		 154
155 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 156 values = &locals->values[slot];
157 if (values->host != values->curr) {
158 wrmsrl(shared_msrs_global.msrs[slot], values->host);
159 values->curr = values->host;
18863bdd
AK		 160 }
161 }
162 locals->registered = false;
163 user_return_notifier_unregister(urn);
164}
165
2bf78fa7 166static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 167{
2bf78fa7 168 struct kvm_shared_msrs *smsr;
18863bdd
AK		 169 u64 value;
170
2bf78fa7
SY		 171 smsr = &__get_cpu_var(shared_msrs);
172 /* only read, and nobody should modify it at this time,
173 * so don't need lock */
174 if (slot >= shared_msrs_global.nr) {
175 printk(KERN_ERR "kvm: invalid MSR slot!");
176 return;
177 }
178 rdmsrl_safe(msr, &value);
179 smsr->values[slot].host = value;
180 smsr->values[slot].curr = value;
181}
182
183void kvm_define_shared_msr(unsigned slot, u32 msr)
184{
18863bdd
AK		 185 if (slot >= shared_msrs_global.nr)
186 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 187 shared_msrs_global.msrs[slot] = msr;
188 /* we need ensured the shared_msr_global have been updated */
189 smp_wmb();
18863bdd
AK		 190}
191EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
192
193static void kvm_shared_msr_cpu_online(void)
194{
195 unsigned i;
18863bdd
AK		 196
197 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 198 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 199}
200
d5696725 201void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 202{
203 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
204
2bf78fa7 205 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 206 return;
2bf78fa7
SY		 207 smsr->values[slot].curr = value;
208 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 209 if (!smsr->registered) {
210 smsr->urn.on_user_return = kvm_on_user_return;
211 user_return_notifier_register(&smsr->urn);
212 smsr->registered = true;
213 }
214}
215EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
216
3548bab5
AK		 217static void drop_user_return_notifiers(void *ignore)
218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
221 if (smsr->registered)
222 kvm_on_user_return(&smsr->urn);
223}
224
5fb76f9b
CO		 225unsigned long segment_base(u16 selector)
226{
227 struct descriptor_table gdt;
a5f61300 228 struct desc_struct *d;
5fb76f9b
CO		 229 unsigned long table_base;
230 unsigned long v;
231
232 if (selector == 0)
233 return 0;
234
b792c344 235 kvm_get_gdt(&gdt);
5fb76f9b
CO		 236 table_base = gdt.base;
237
238 if (selector & 4) { /* from ldt */
b792c344 239 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 240
5fb76f9b
CO		 241 table_base = segment_base(ldt_selector);
242 }
a5f61300 243 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 244 v = get_desc_base(d);
5fb76f9b 245#ifdef CONFIG_X86_64
a5f61300
AK		 246 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
247 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 248#endif
249 return v;
250}
251EXPORT_SYMBOL_GPL(segment_base);
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
255 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 256 return vcpu->arch.apic_base;
6866b83e 257 else
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_get_apic_base);
261
262void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
263{
264 /* TODO: reserve bits check */
265 if (irqchip_in_kernel(vcpu->kvm))
266 kvm_lapic_set_base(vcpu, data);
267 else
ad312c7c 268 vcpu->arch.apic_base = data;
6866b83e
CO		 269}
270EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
3fd28fce
ED		 272#define EXCPT_BENIGN 0
273#define EXCPT_CONTRIBUTORY 1
274#define EXCPT_PF 2
275
276static int exception_class(int vector)
277{
278 switch (vector) {
279 case PF_VECTOR:
280 return EXCPT_PF;
281 case DE_VECTOR:
282 case TS_VECTOR:
283 case NP_VECTOR:
284 case SS_VECTOR:
285 case GP_VECTOR:
286 return EXCPT_CONTRIBUTORY;
287 default:
288 break;
289 }
290 return EXCPT_BENIGN;
291}
292
293static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
294 unsigned nr, bool has_error, u32 error_code)
295{
296 u32 prev_nr;
297 int class1, class2;
298
299 if (!vcpu->arch.exception.pending) {
300 queue:
301 vcpu->arch.exception.pending = true;
302 vcpu->arch.exception.has_error_code = has_error;
303 vcpu->arch.exception.nr = nr;
304 vcpu->arch.exception.error_code = error_code;
305 return;
306 }
307
308 /* to check exception */
309 prev_nr = vcpu->arch.exception.nr;
310 if (prev_nr == DF_VECTOR) {
311 /* triple fault -> shutdown */
312 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
313 return;
314 }
315 class1 = exception_class(prev_nr);
316 class2 = exception_class(nr);
317 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
318 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
319 /* generate double fault per SDM Table 5-5 */
320 vcpu->arch.exception.pending = true;
321 vcpu->arch.exception.has_error_code = true;
322 vcpu->arch.exception.nr = DF_VECTOR;
323 vcpu->arch.exception.error_code = 0;
324 } else
325 /* replace previous exception with a new one in a hope
326 that instruction re-execution will regenerate lost
327 exception */
328 goto queue;
329}
330
298101da
AK		 331void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
3fd28fce 333 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 334}
335EXPORT_SYMBOL_GPL(kvm_queue_exception);
336
c3c91fee
AK		 337void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
338 u32 error_code)
339{
340 ++vcpu->stat.pf_guest;
ad312c7c 341 vcpu->arch.cr2 = addr;
c3c91fee
AK		 342 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
343}
344
3419ffc8
SY		 345void kvm_inject_nmi(struct kvm_vcpu *vcpu)
346{
347 vcpu->arch.nmi_pending = 1;
348}
349EXPORT_SYMBOL_GPL(kvm_inject_nmi);
350
298101da
AK		 351void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
352{
3fd28fce 353 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 354}
355EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
356
0a79b009
AK		 357/*
358 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
359 * a #GP and return false.
360 */
361bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 362{
0a79b009
AK		 363 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
364 return true;
365 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
366 return false;
298101da 367}
0a79b009 368EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 369
a03490ed
CO		 370/*
371 * Load the pae pdptrs. Return true is they are all valid.
372 */
373int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
374{
375 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
376 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
377 int i;
378 int ret;
ad312c7c 379 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 380
a03490ed
CO		 381 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
382 offset * sizeof(u64), sizeof(pdpte));
383 if (ret < 0) {
384 ret = 0;
385 goto out;
386 }
387 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 388 if (is_present_gpte(pdpte[i]) &&
20c466b5 389 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 390 ret = 0;
391 goto out;
392 }
393 }
394 ret = 1;
395
ad312c7c 396 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 397 __set_bit(VCPU_EXREG_PDPTR,
398 (unsigned long *)&vcpu->arch.regs_avail);
399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 401out:
a03490ed
CO		 402
403 return ret;
404}
cc4b6871 405EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 406
d835dfec
AK		 407static bool pdptrs_changed(struct kvm_vcpu *vcpu)
408{
ad312c7c 409 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 410 bool changed = true;
411 int r;
412
413 if (is_long_mode(vcpu) || !is_pae(vcpu))
414 return false;
415
6de4f3ad
AK		 416 if (!test_bit(VCPU_EXREG_PDPTR,
417 (unsigned long *)&vcpu->arch.regs_avail))
418 return true;
419
ad312c7c 420 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 421 if (r < 0)
422 goto out;
ad312c7c 423 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 424out:
d835dfec
AK		 425
426 return changed;
427}
428
2d3ad1f4 429void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 430{
431 if (cr0 & CR0_RESERVED_BITS) {
432 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 433 cr0, vcpu->arch.cr0);
c1a5d4f9 434 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 435 return;
436 }
437
438 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
439 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 440 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 441 return;
442 }
443
444 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
445 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
446 "and a clear PE flag\n");
c1a5d4f9 447 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 448 return;
449 }
450
451 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
452#ifdef CONFIG_X86_64
ad312c7c 453 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 454 int cs_db, cs_l;
455
456 if (!is_pae(vcpu)) {
457 printk(KERN_DEBUG "set_cr0: #GP, start paging "
458 "in long mode while PAE is disabled\n");
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
464 printk(KERN_DEBUG "set_cr0: #GP, start paging "
465 "in long mode while CS.L == 1\n");
c1a5d4f9 466 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 467 return;
468
469 }
470 } else
471#endif
ad312c7c 472 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 473 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
474 "reserved bits\n");
c1a5d4f9 475 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 476 return;
477 }
478
479 }
480
481 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 482 vcpu->arch.cr0 = cr0;
a03490ed 483
a03490ed 484 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 485 return;
486}
2d3ad1f4 487EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 488
2d3ad1f4 489void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 490{
2d3ad1f4 491 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 494
2d3ad1f4 495void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 496{
fc78f519 497 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 498 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
499
a03490ed
CO		 500 if (cr4 & CR4_RESERVED_BITS) {
501 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 502 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 503 return;
504 }
505
506 if (is_long_mode(vcpu)) {
507 if (!(cr4 & X86_CR4_PAE)) {
508 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
509 "in long mode\n");
c1a5d4f9 510 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 511 return;
512 }
a2edf57f
AK		 513 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
514 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 515 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 516 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 517 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 518 return;
519 }
520
521 if (cr4 & X86_CR4_VMXE) {
522 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 523 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 524 return;
525 }
526 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 527 vcpu->arch.cr4 = cr4;
5a41accd 528 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 529 kvm_mmu_reset_context(vcpu);
a03490ed 530}
2d3ad1f4 531EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 532
2d3ad1f4 533void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 534{
ad312c7c 535 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 536 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 537 kvm_mmu_flush_tlb(vcpu);
538 return;
539 }
540
a03490ed
CO		 541 if (is_long_mode(vcpu)) {
542 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
543 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 } else {
548 if (is_pae(vcpu)) {
549 if (cr3 & CR3_PAE_RESERVED_BITS) {
550 printk(KERN_DEBUG
551 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 552 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 553 return;
554 }
555 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
556 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
557 "reserved bits\n");
c1a5d4f9 558 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 559 return;
560 }
561 }
562 /*
563 * We don't check reserved bits in nonpae mode, because
564 * this isn't enforced, and VMware depends on this.
565 */
566 }
567
a03490ed
CO		 568 /*
569 * Does the new cr3 value map to physical memory? (Note, we
570 * catch an invalid cr3 even in real-mode, because it would
571 * cause trouble later on when we turn on paging anyway.)
572 *
573 * A real CPU would silently accept an invalid cr3 and would
574 * attempt to use it - with largely undefined (and often hard
575 * to debug) behavior on the guest side.
576 */
577 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 578 kvm_inject_gp(vcpu, 0);
a03490ed 579 else {
ad312c7c
ZX		 580 vcpu->arch.cr3 = cr3;
581 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 582 }
a03490ed 583}
2d3ad1f4 584EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 585
2d3ad1f4 586void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 587{
588 if (cr8 & CR8_RESERVED_BITS) {
589 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 590 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 591 return;
592 }
593 if (irqchip_in_kernel(vcpu->kvm))
594 kvm_lapic_set_tpr(vcpu, cr8);
595 else
ad312c7c 596 vcpu->arch.cr8 = cr8;
a03490ed 597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 599
2d3ad1f4 600unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 601{
602 if (irqchip_in_kernel(vcpu->kvm))
603 return kvm_lapic_get_cr8(vcpu);
604 else
ad312c7c 605 return vcpu->arch.cr8;
a03490ed 606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 608
d8017474
AG		 609static inline u32 bit(int bitno)
610{
611 return 1 << (bitno & 31);
612}
613
043405e1
CO		 614/*
615 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
616 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
617 *
618 * This list is modified at module load time to reflect the
e3267cbb
GC		 619 * capabilities of the host cpu. This capabilities test skips MSRs that are
620 * kvm-specific. Those are put in the beginning of the list.
043405e1 621 */
e3267cbb
GC		 622
623#define KVM_SAVE_MSRS_BEGIN 2
043405e1 624static u32 msrs_to_save[] = {
e3267cbb 625 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 626 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
627 MSR_K6_STAR,
628#ifdef CONFIG_X86_64
629 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
630#endif
e3267cbb 631 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 632};
633
634static unsigned num_msrs_to_save;
635
636static u32 emulated_msrs[] = {
637 MSR_IA32_MISC_ENABLE,
638};
639
15c4a640
CO		 640static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
641{
f2b4b7dd 642 if (efer & efer_reserved_bits) {
15c4a640
CO		 643 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
644 efer);
c1a5d4f9 645 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 646 return;
647 }
648
649 if (is_paging(vcpu)
ad312c7c 650 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 651 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 652 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 653 return;
654 }
655
1b2fd70c
AG		 656 if (efer & EFER_FFXSR) {
657 struct kvm_cpuid_entry2 *feat;
658
659 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
660 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
661 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
662 kvm_inject_gp(vcpu, 0);
663 return;
664 }
665 }
666
d8017474
AG		 667 if (efer & EFER_SVME) {
668 struct kvm_cpuid_entry2 *feat;
669
670 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
671 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
672 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
673 kvm_inject_gp(vcpu, 0);
674 return;
675 }
676 }
677
15c4a640
CO		 678 kvm_x86_ops->set_efer(vcpu, efer);
679
680 efer &= ~EFER_LMA;
ad312c7c 681 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 682
ad312c7c 683 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 684
685 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
686 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 687}
688
f2b4b7dd
JR		 689void kvm_enable_efer_bits(u64 mask)
690{
691 efer_reserved_bits &= ~mask;
692}
693EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
694
695
15c4a640
CO		 696/*
697 * Writes msr value into into the appropriate "register".
698 * Returns 0 on success, non-0 otherwise.
699 * Assumes vcpu_load() was already called.
700 */
701int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
702{
703 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
704}
705
313a3dc7
CO		 706/*
707 * Adapt set_msr() to msr_io()'s calling convention
708 */
709static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
710{
711 return kvm_set_msr(vcpu, index, *data);
712}
713
18068523
GOC		 714static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
715{
716 static int version;
50d0a0f9 717 struct pvclock_wall_clock wc;
923de3cf 718 struct timespec boot;
18068523
GOC		 719
720 if (!wall_clock)
721 return;
722
723 version++;
724
18068523
GOC		 725 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
726
50d0a0f9
GH		 727 /*
728 * The guest calculates current wall clock time by adding
729 * system time (updated by kvm_write_guest_time below) to the
730 * wall clock specified here. guest system time equals host
731 * system time for us, thus we must fill in host boot time here.
732 */
923de3cf 733 getboottime(&boot);
50d0a0f9
GH		 734
735 wc.sec = boot.tv_sec;
736 wc.nsec = boot.tv_nsec;
737 wc.version = version;
18068523
GOC		 738
739 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
740
741 version++;
742 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 743}
744
50d0a0f9
GH		 745static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
746{
747 uint32_t quotient, remainder;
748
749 /* Don't try to replace with do_div(), this one calculates
750 * "(dividend << 32) / divisor" */
751 __asm__ ( "divl %4"
752 : "=a" (quotient), "=d" (remainder)
753 : "0" (0), "1" (dividend), "r" (divisor) );
754 return quotient;
755}
756
757static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
758{
759 uint64_t nsecs = 1000000000LL;
760 int32_t shift = 0;
761 uint64_t tps64;
762 uint32_t tps32;
763
764 tps64 = tsc_khz * 1000LL;
765 while (tps64 > nsecs*2) {
766 tps64 >>= 1;
767 shift--;
768 }
769
770 tps32 = (uint32_t)tps64;
771 while (tps32 <= (uint32_t)nsecs) {
772 tps32 <<= 1;
773 shift++;
774 }
775
776 hv_clock->tsc_shift = shift;
777 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
778
779 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 780 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 781 hv_clock->tsc_to_system_mul);
782}
783
c8076604
GH		 784static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
785
18068523
GOC		 786static void kvm_write_guest_time(struct kvm_vcpu *v)
787{
788 struct timespec ts;
789 unsigned long flags;
790 struct kvm_vcpu_arch *vcpu = &v->arch;
791 void *shared_kaddr;
463656c0 792 unsigned long this_tsc_khz;
18068523
GOC		 793
794 if ((!vcpu->time_page))
795 return;
796
463656c0
AK		 797 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
798 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
799 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
800 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 801 }
463656c0 802 put_cpu_var(cpu_tsc_khz);
50d0a0f9 803
18068523
GOC		 804 /* Keep irq disabled to prevent changes to the clock */
805 local_irq_save(flags);
af24a4e4 806 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 807 ktime_get_ts(&ts);
923de3cf 808 monotonic_to_bootbased(&ts);
18068523
GOC		 809 local_irq_restore(flags);
810
811 /* With all the info we got, fill in the values */
812
813 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 814 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
815
18068523
GOC		 816 /*
817 * The interface expects us to write an even number signaling that the
818 * update is finished. Since the guest won't see the intermediate
50d0a0f9 819 * state, we just increase by 2 at the end.
18068523 820 */
50d0a0f9 821 vcpu->hv_clock.version += 2;
18068523
GOC		 822
823 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
824
825 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 826 sizeof(vcpu->hv_clock));
18068523
GOC		 827
828 kunmap_atomic(shared_kaddr, KM_USER0);
829
830 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
831}
832
c8076604
GH		 833static int kvm_request_guest_time_update(struct kvm_vcpu *v)
834{
835 struct kvm_vcpu_arch *vcpu = &v->arch;
836
837 if (!vcpu->time_page)
838 return 0;
839 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
840 return 1;
841}
842
9ba075a6
AK		 843static bool msr_mtrr_valid(unsigned msr)
844{
845 switch (msr) {
846 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
847 case MSR_MTRRfix64K_00000:
848 case MSR_MTRRfix16K_80000:
849 case MSR_MTRRfix16K_A0000:
850 case MSR_MTRRfix4K_C0000:
851 case MSR_MTRRfix4K_C8000:
852 case MSR_MTRRfix4K_D0000:
853 case MSR_MTRRfix4K_D8000:
854 case MSR_MTRRfix4K_E0000:
855 case MSR_MTRRfix4K_E8000:
856 case MSR_MTRRfix4K_F0000:
857 case MSR_MTRRfix4K_F8000:
858 case MSR_MTRRdefType:
859 case MSR_IA32_CR_PAT:
860 return true;
861 case 0x2f8:
862 return true;
863 }
864 return false;
865}
866
d6289b93
MT		 867static bool valid_pat_type(unsigned t)
868{
869 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
870}
871
872static bool valid_mtrr_type(unsigned t)
873{
874 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
875}
876
877static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
878{
879 int i;
880
881 if (!msr_mtrr_valid(msr))
882 return false;
883
884 if (msr == MSR_IA32_CR_PAT) {
885 for (i = 0; i < 8; i++)
886 if (!valid_pat_type((data >> (i * 8)) & 0xff))
887 return false;
888 return true;
889 } else if (msr == MSR_MTRRdefType) {
890 if (data & ~0xcff)
891 return false;
892 return valid_mtrr_type(data & 0xff);
893 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
894 for (i = 0; i < 8 ; i++)
895 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
896 return false;
897 return true;
898 }
899
900 /* variable MTRRs */
901 return valid_mtrr_type(data & 0xff);
902}
903
9ba075a6
AK		 904static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
905{
0bed3b56
SY		 906 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
907
d6289b93 908 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 909 return 1;
910
0bed3b56
SY		 911 if (msr == MSR_MTRRdefType) {
912 vcpu->arch.mtrr_state.def_type = data;
913 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
914 } else if (msr == MSR_MTRRfix64K_00000)
915 p[0] = data;
916 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
917 p[1 + msr - MSR_MTRRfix16K_80000] = data;
918 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
919 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
920 else if (msr == MSR_IA32_CR_PAT)
921 vcpu->arch.pat = data;
922 else { /* Variable MTRRs */
923 int idx, is_mtrr_mask;
924 u64 *pt;
925
926 idx = (msr - 0x200) / 2;
927 is_mtrr_mask = msr - 0x200 - 2 * idx;
928 if (!is_mtrr_mask)
929 pt =
930 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
931 else
932 pt =
933 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
934 *pt = data;
935 }
936
937 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 938 return 0;
939}
15c4a640 940
890ca9ae 941static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 942{
890ca9ae
HY		 943 u64 mcg_cap = vcpu->arch.mcg_cap;
944 unsigned bank_num = mcg_cap & 0xff;
945
15c4a640 946 switch (msr) {
15c4a640 947 case MSR_IA32_MCG_STATUS:
890ca9ae 948 vcpu->arch.mcg_status = data;
15c4a640 949 break;
c7ac679c 950 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 951 if (!(mcg_cap & MCG_CTL_P))
952 return 1;
953 if (data != 0 && data != ~(u64)0)
954 return -1;
955 vcpu->arch.mcg_ctl = data;
956 break;
957 default:
958 if (msr >= MSR_IA32_MC0_CTL &&
959 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
960 u32 offset = msr - MSR_IA32_MC0_CTL;
961 /* only 0 or all 1s can be written to IA32_MCi_CTL */
962 if ((offset & 0x3) == 0 &&
963 data != 0 && data != ~(u64)0)
964 return -1;
965 vcpu->arch.mce_banks[offset] = data;
966 break;
967 }
968 return 1;
969 }
970 return 0;
971}
972
ffde22ac
ES		 973static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
974{
975 struct kvm *kvm = vcpu->kvm;
976 int lm = is_long_mode(vcpu);
977 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
978 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
979 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
980 : kvm->arch.xen_hvm_config.blob_size_32;
981 u32 page_num = data & ~PAGE_MASK;
982 u64 page_addr = data & PAGE_MASK;
983 u8 *page;
984 int r;
985
986 r = -E2BIG;
987 if (page_num >= blob_size)
988 goto out;
989 r = -ENOMEM;
990 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
991 if (!page)
992 goto out;
993 r = -EFAULT;
994 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
995 goto out_free;
996 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
997 goto out_free;
998 r = 0;
999out_free:
1000 kfree(page);
1001out:
1002 return r;
1003}
1004
15c4a640
CO		 1005int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1006{
1007 switch (msr) {
15c4a640
CO		 1008 case MSR_EFER:
1009 set_efer(vcpu, data);
1010 break;
8f1589d9
AP		 1011 case MSR_K7_HWCR:
1012 data &= ~(u64)0x40; /* ignore flush filter disable */
1013 if (data != 0) {
1014 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1015 data);
1016 return 1;
1017 }
15c4a640 1018 break;
f7c6d140
AP		 1019 case MSR_FAM10H_MMIO_CONF_BASE:
1020 if (data != 0) {
1021 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1022 "0x%llx\n", data);
1023 return 1;
1024 }
15c4a640 1025 break;
c323c0e5 1026 case MSR_AMD64_NB_CFG:
c7ac679c 1027 break;
b5e2fec0
AG		 1028 case MSR_IA32_DEBUGCTLMSR:
1029 if (!data) {
1030 /* We support the non-activated case already */
1031 break;
1032 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1033 /* Values other than LBR and BTF are vendor-specific,
1034 thus reserved and should throw a #GP */
1035 return 1;
1036 }
1037 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1038 __func__, data);
1039 break;
15c4a640
CO		 1040 case MSR_IA32_UCODE_REV:
1041 case MSR_IA32_UCODE_WRITE:
61a6bd67 1042 case MSR_VM_HSAVE_PA:
6098ca93 1043 case MSR_AMD64_PATCH_LOADER:
15c4a640 1044 break;
9ba075a6
AK		 1045 case 0x200 ... 0x2ff:
1046 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1047 case MSR_IA32_APICBASE:
1048 kvm_set_apic_base(vcpu, data);
1049 break;
0105d1a5
GN		 1050 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1051 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1052 case MSR_IA32_MISC_ENABLE:
ad312c7c 1053 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1054 break;
18068523
GOC		 1055 case MSR_KVM_WALL_CLOCK:
1056 vcpu->kvm->arch.wall_clock = data;
1057 kvm_write_wall_clock(vcpu->kvm, data);
1058 break;
1059 case MSR_KVM_SYSTEM_TIME: {
1060 if (vcpu->arch.time_page) {
1061 kvm_release_page_dirty(vcpu->arch.time_page);
1062 vcpu->arch.time_page = NULL;
1063 }
1064
1065 vcpu->arch.time = data;
1066
1067 /* we verify if the enable bit is set... */
1068 if (!(data & 1))
1069 break;
1070
1071 /* ...but clean it before doing the actual write */
1072 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1073
18068523
GOC		 1074 vcpu->arch.time_page =
1075 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1076
1077 if (is_error_page(vcpu->arch.time_page)) {
1078 kvm_release_page_clean(vcpu->arch.time_page);
1079 vcpu->arch.time_page = NULL;
1080 }
1081
c8076604 1082 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1083 break;
1084 }
890ca9ae
HY		 1085 case MSR_IA32_MCG_CTL:
1086 case MSR_IA32_MCG_STATUS:
1087 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1088 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1089
1090 /* Performance counters are not protected by a CPUID bit,
1091 * so we should check all of them in the generic path for the sake of
1092 * cross vendor migration.
1093 * Writing a zero into the event select MSRs disables them,
1094 * which we perfectly emulate ;-). Any other value should be at least
1095 * reported, some guests depend on them.
1096 */
1097 case MSR_P6_EVNTSEL0:
1098 case MSR_P6_EVNTSEL1:
1099 case MSR_K7_EVNTSEL0:
1100 case MSR_K7_EVNTSEL1:
1101 case MSR_K7_EVNTSEL2:
1102 case MSR_K7_EVNTSEL3:
1103 if (data != 0)
1104 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1105 "0x%x data 0x%llx\n", msr, data);
1106 break;
1107 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1108 * so we ignore writes to make it happy.
1109 */
1110 case MSR_P6_PERFCTR0:
1111 case MSR_P6_PERFCTR1:
1112 case MSR_K7_PERFCTR0:
1113 case MSR_K7_PERFCTR1:
1114 case MSR_K7_PERFCTR2:
1115 case MSR_K7_PERFCTR3:
1116 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1117 "0x%x data 0x%llx\n", msr, data);
1118 break;
15c4a640 1119 default:
ffde22ac
ES		 1120 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1121 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1122 if (!ignore_msrs) {
1123 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1124 msr, data);
1125 return 1;
1126 } else {
1127 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1128 msr, data);
1129 break;
1130 }
15c4a640
CO		 1131 }
1132 return 0;
1133}
1134EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1135
1136
1137/*
1138 * Reads an msr value (of 'msr_index') into 'pdata'.
1139 * Returns 0 on success, non-0 otherwise.
1140 * Assumes vcpu_load() was already called.
1141 */
1142int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1143{
1144 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1145}
1146
9ba075a6
AK		 1147static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1148{
0bed3b56
SY		 1149 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1150
9ba075a6
AK		 1151 if (!msr_mtrr_valid(msr))
1152 return 1;
1153
0bed3b56
SY		 1154 if (msr == MSR_MTRRdefType)
1155 *pdata = vcpu->arch.mtrr_state.def_type +
1156 (vcpu->arch.mtrr_state.enabled << 10);
1157 else if (msr == MSR_MTRRfix64K_00000)
1158 *pdata = p[0];
1159 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1160 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1161 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1162 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1163 else if (msr == MSR_IA32_CR_PAT)
1164 *pdata = vcpu->arch.pat;
1165 else { /* Variable MTRRs */
1166 int idx, is_mtrr_mask;
1167 u64 *pt;
1168
1169 idx = (msr - 0x200) / 2;
1170 is_mtrr_mask = msr - 0x200 - 2 * idx;
1171 if (!is_mtrr_mask)
1172 pt =
1173 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1174 else
1175 pt =
1176 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1177 *pdata = *pt;
1178 }
1179
9ba075a6
AK		 1180 return 0;
1181}
1182
890ca9ae 1183static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1184{
1185 u64 data;
890ca9ae
HY		 1186 u64 mcg_cap = vcpu->arch.mcg_cap;
1187 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1188
1189 switch (msr) {
15c4a640
CO		 1190 case MSR_IA32_P5_MC_ADDR:
1191 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1192 data = 0;
1193 break;
15c4a640 1194 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1195 data = vcpu->arch.mcg_cap;
1196 break;
c7ac679c 1197 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1198 if (!(mcg_cap & MCG_CTL_P))
1199 return 1;
1200 data = vcpu->arch.mcg_ctl;
1201 break;
1202 case MSR_IA32_MCG_STATUS:
1203 data = vcpu->arch.mcg_status;
1204 break;
1205 default:
1206 if (msr >= MSR_IA32_MC0_CTL &&
1207 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1208 u32 offset = msr - MSR_IA32_MC0_CTL;
1209 data = vcpu->arch.mce_banks[offset];
1210 break;
1211 }
1212 return 1;
1213 }
1214 *pdata = data;
1215 return 0;
1216}
1217
1218int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1219{
1220 u64 data;
1221
1222 switch (msr) {
890ca9ae 1223 case MSR_IA32_PLATFORM_ID:
15c4a640 1224 case MSR_IA32_UCODE_REV:
15c4a640 1225 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1226 case MSR_IA32_DEBUGCTLMSR:
1227 case MSR_IA32_LASTBRANCHFROMIP:
1228 case MSR_IA32_LASTBRANCHTOIP:
1229 case MSR_IA32_LASTINTFROMIP:
1230 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1231 case MSR_K8_SYSCFG:
1232 case MSR_K7_HWCR:
61a6bd67 1233 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1234 case MSR_P6_PERFCTR0:
1235 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1236 case MSR_P6_EVNTSEL0:
1237 case MSR_P6_EVNTSEL1:
9e699624 1238 case MSR_K7_EVNTSEL0:
1f3ee616 1239 case MSR_K7_PERFCTR0:
1fdbd48c 1240 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1241 case MSR_AMD64_NB_CFG:
f7c6d140 1242 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1243 data = 0;
1244 break;
9ba075a6
AK		 1245 case MSR_MTRRcap:
1246 data = 0x500 | KVM_NR_VAR_MTRR;
1247 break;
1248 case 0x200 ... 0x2ff:
1249 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1250 case 0xcd: /* fsb frequency */
1251 data = 3;
1252 break;
1253 case MSR_IA32_APICBASE:
1254 data = kvm_get_apic_base(vcpu);
1255 break;
0105d1a5
GN		 1256 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1257 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1258 break;
15c4a640 1259 case MSR_IA32_MISC_ENABLE:
ad312c7c 1260 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1261 break;
847f0ad8
AG		 1262 case MSR_IA32_PERF_STATUS:
1263 /* TSC increment by tick */
1264 data = 1000ULL;
1265 /* CPU multiplier */
1266 data |= (((uint64_t)4ULL) << 40);
1267 break;
15c4a640 1268 case MSR_EFER:
ad312c7c 1269 data = vcpu->arch.shadow_efer;
15c4a640 1270 break;
18068523
GOC		 1271 case MSR_KVM_WALL_CLOCK:
1272 data = vcpu->kvm->arch.wall_clock;
1273 break;
1274 case MSR_KVM_SYSTEM_TIME:
1275 data = vcpu->arch.time;
1276 break;
890ca9ae
HY		 1277 case MSR_IA32_P5_MC_ADDR:
1278 case MSR_IA32_P5_MC_TYPE:
1279 case MSR_IA32_MCG_CAP:
1280 case MSR_IA32_MCG_CTL:
1281 case MSR_IA32_MCG_STATUS:
1282 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1283 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1284 default:
ed85c068
AP		 1285 if (!ignore_msrs) {
1286 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1287 return 1;
1288 } else {
1289 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1290 data = 0;
1291 }
1292 break;
15c4a640
CO		 1293 }
1294 *pdata = data;
1295 return 0;
1296}
1297EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1298
313a3dc7
CO		 1299/*
1300 * Read or write a bunch of msrs. All parameters are kernel addresses.
1301 *
1302 * @return number of msrs set successfully.
1303 */
1304static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1305 struct kvm_msr_entry *entries,
1306 int (*do_msr)(struct kvm_vcpu *vcpu,
1307 unsigned index, u64 *data))
1308{
1309 int i;
1310
1311 vcpu_load(vcpu);
1312
3200f405 1313 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1314 for (i = 0; i < msrs->nmsrs; ++i)
1315 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1316 break;
3200f405 1317 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1318
1319 vcpu_put(vcpu);
1320
1321 return i;
1322}
1323
1324/*
1325 * Read or write a bunch of msrs. Parameters are user addresses.
1326 *
1327 * @return number of msrs set successfully.
1328 */
1329static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1330 int (*do_msr)(struct kvm_vcpu *vcpu,
1331 unsigned index, u64 *data),
1332 int writeback)
1333{
1334 struct kvm_msrs msrs;
1335 struct kvm_msr_entry *entries;
1336 int r, n;
1337 unsigned size;
1338
1339 r = -EFAULT;
1340 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1341 goto out;
1342
1343 r = -E2BIG;
1344 if (msrs.nmsrs >= MAX_IO_MSRS)
1345 goto out;
1346
1347 r = -ENOMEM;
1348 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1349 entries = vmalloc(size);
1350 if (!entries)
1351 goto out;
1352
1353 r = -EFAULT;
1354 if (copy_from_user(entries, user_msrs->entries, size))
1355 goto out_free;
1356
1357 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1358 if (r < 0)
1359 goto out_free;
1360
1361 r = -EFAULT;
1362 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1363 goto out_free;
1364
1365 r = n;
1366
1367out_free:
1368 vfree(entries);
1369out:
1370 return r;
1371}
1372
018d00d2
ZX		 1373int kvm_dev_ioctl_check_extension(long ext)
1374{
1375 int r;
1376
1377 switch (ext) {
1378 case KVM_CAP_IRQCHIP:
1379 case KVM_CAP_HLT:
1380 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1381 case KVM_CAP_SET_TSS_ADDR:
07716717 1382 case KVM_CAP_EXT_CPUID:
c8076604 1383 case KVM_CAP_CLOCKSOURCE:
7837699f 1384 case KVM_CAP_PIT:
a28e4f5a 1385 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1386 case KVM_CAP_MP_STATE:
ed848624 1387 case KVM_CAP_SYNC_MMU:
52d939a0 1388 case KVM_CAP_REINJECT_CONTROL:
4925663a 1389 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1390 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1391 case KVM_CAP_IRQFD:
d34e6b17 1392 case KVM_CAP_IOEVENTFD:
c5ff41ce 1393 case KVM_CAP_PIT2:
e9f42757 1394 case KVM_CAP_PIT_STATE2:
b927a3ce 1395 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1396 case KVM_CAP_XEN_HVM:
afbcf7ab 1397 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1398 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1399 r = 1;
1400 break;
542472b5
LV		 1401 case KVM_CAP_COALESCED_MMIO:
1402 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1403 break;
774ead3a
AK		 1404 case KVM_CAP_VAPIC:
1405 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1406 break;
f725230a
AK		 1407 case KVM_CAP_NR_VCPUS:
1408 r = KVM_MAX_VCPUS;
1409 break;
a988b910
AK		 1410 case KVM_CAP_NR_MEMSLOTS:
1411 r = KVM_MEMORY_SLOTS;
1412 break;
a68a6a72
MT		 1413 case KVM_CAP_PV_MMU: /* obsolete */
1414 r = 0;
2f333bcb 1415 break;
62c476c7 1416 case KVM_CAP_IOMMU:
19de40a8 1417 r = iommu_found();
62c476c7 1418 break;
890ca9ae
HY		 1419 case KVM_CAP_MCE:
1420 r = KVM_MAX_MCE_BANKS;
1421 break;
018d00d2
ZX		 1422 default:
1423 r = 0;
1424 break;
1425 }
1426 return r;
1427
1428}
1429
043405e1
CO		 1430long kvm_arch_dev_ioctl(struct file *filp,
1431 unsigned int ioctl, unsigned long arg)
1432{
1433 void __user *argp = (void __user *)arg;
1434 long r;
1435
1436 switch (ioctl) {
1437 case KVM_GET_MSR_INDEX_LIST: {
1438 struct kvm_msr_list __user *user_msr_list = argp;
1439 struct kvm_msr_list msr_list;
1440 unsigned n;
1441
1442 r = -EFAULT;
1443 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1444 goto out;
1445 n = msr_list.nmsrs;
1446 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1447 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1448 goto out;
1449 r = -E2BIG;
e125e7b6 1450 if (n < msr_list.nmsrs)
043405e1
CO		 1451 goto out;
1452 r = -EFAULT;
1453 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1454 num_msrs_to_save * sizeof(u32)))
1455 goto out;
e125e7b6 1456 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1457 &emulated_msrs,
1458 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1459 goto out;
1460 r = 0;
1461 break;
1462 }
674eea0f
AK		 1463 case KVM_GET_SUPPORTED_CPUID: {
1464 struct kvm_cpuid2 __user *cpuid_arg = argp;
1465 struct kvm_cpuid2 cpuid;
1466
1467 r = -EFAULT;
1468 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1469 goto out;
1470 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1471 cpuid_arg->entries);
674eea0f
AK		 1472 if (r)
1473 goto out;
1474
1475 r = -EFAULT;
1476 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1477 goto out;
1478 r = 0;
1479 break;
1480 }
890ca9ae
HY		 1481 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1482 u64 mce_cap;
1483
1484 mce_cap = KVM_MCE_CAP_SUPPORTED;
1485 r = -EFAULT;
1486 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1487 goto out;
1488 r = 0;
1489 break;
1490 }
043405e1
CO		 1491 default:
1492 r = -EINVAL;
1493 }
1494out:
1495 return r;
1496}
1497
313a3dc7
CO		 1498void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1499{
1500 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1501 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1502 unsigned long khz = cpufreq_quick_get(cpu);
1503 if (!khz)
1504 khz = tsc_khz;
1505 per_cpu(cpu_tsc_khz, cpu) = khz;
1506 }
c8076604 1507 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1508}
1509
1510void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1511{
1512 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1513 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1514}
1515
07716717 1516static int is_efer_nx(void)
313a3dc7 1517{
e286e86e 1518 unsigned long long efer = 0;
313a3dc7 1519
e286e86e 1520 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1521 return efer & EFER_NX;
1522}
1523
1524static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1525{
1526 int i;
1527 struct kvm_cpuid_entry2 *e, *entry;
1528
313a3dc7 1529 entry = NULL;
ad312c7c
ZX		 1530 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1531 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1532 if (e->function == 0x80000001) {
1533 entry = e;
1534 break;
1535 }
1536 }
07716717 1537 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1538 entry->edx &= ~(1 << 20);
1539 printk(KERN_INFO "kvm: guest NX capability removed\n");
1540 }
1541}
1542
07716717 1543/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1544static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1545 struct kvm_cpuid *cpuid,
1546 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1547{
1548 int r, i;
1549 struct kvm_cpuid_entry *cpuid_entries;
1550
1551 r = -E2BIG;
1552 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1553 goto out;
1554 r = -ENOMEM;
1555 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1556 if (!cpuid_entries)
1557 goto out;
1558 r = -EFAULT;
1559 if (copy_from_user(cpuid_entries, entries,
1560 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1561 goto out_free;
1562 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1563 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1564 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1565 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1566 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1567 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1568 vcpu->arch.cpuid_entries[i].index = 0;
1569 vcpu->arch.cpuid_entries[i].flags = 0;
1570 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1571 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1572 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1573 }
1574 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1575 cpuid_fix_nx_cap(vcpu);
1576 r = 0;
fc61b800 1577 kvm_apic_set_version(vcpu);
0e851880 1578 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1579
1580out_free:
1581 vfree(cpuid_entries);
1582out:
1583 return r;
1584}
1585
1586static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1587 struct kvm_cpuid2 *cpuid,
1588 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1589{
1590 int r;
1591
1592 r = -E2BIG;
1593 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1594 goto out;
1595 r = -EFAULT;
ad312c7c 1596 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1597 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1598 goto out;
ad312c7c 1599 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1600 kvm_apic_set_version(vcpu);
0e851880 1601 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1602 return 0;
1603
1604out:
1605 return r;
1606}
1607
07716717 1608static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1609 struct kvm_cpuid2 *cpuid,
1610 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1611{
1612 int r;
1613
1614 r = -E2BIG;
ad312c7c 1615 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1616 goto out;
1617 r = -EFAULT;
ad312c7c 1618 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1619 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1620 goto out;
1621 return 0;
1622
1623out:
ad312c7c 1624 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1625 return r;
1626}
1627
07716717 1628static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1629 u32 index)
07716717
DK		 1630{
1631 entry->function = function;
1632 entry->index = index;
1633 cpuid_count(entry->function, entry->index,
19355475 1634 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1635 entry->flags = 0;
1636}
1637
7faa4ee1
AK		 1638#define F(x) bit(X86_FEATURE_##x)
1639
07716717
DK		 1640static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1641 u32 index, int *nent, int maxnent)
1642{
7faa4ee1 1643 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1644 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1645#ifdef CONFIG_X86_64
7faa4ee1
AK		 1646 unsigned f_lm = F(LM);
1647#else
1648 unsigned f_lm = 0;
07716717 1649#endif
4e47c7a6 1650 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1651
1652 /* cpuid 1.edx */
1653 const u32 kvm_supported_word0_x86_features =
1654 F(FPU) | F(VME) | F(DE) | F(PSE) |
1655 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1656 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1657 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1658 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1659 0 /* Reserved, DS, ACPI */ | F(MMX) |
1660 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1661 0 /* HTT, TM, Reserved, PBE */;
1662 /* cpuid 0x80000001.edx */
1663 const u32 kvm_supported_word1_x86_features =
1664 F(FPU) | F(VME) | F(DE) | F(PSE) |
1665 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1666 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1667 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1668 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1669 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1670 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1671 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1672 /* cpuid 1.ecx */
1673 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1674 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1675 0 /* DS-CPL, VMX, SMX, EST */ |
1676 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1677 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1678 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1679 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1680 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1681 /* cpuid 0x80000001.ecx */
07716717 1682 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1683 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1684 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1685 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1686 0 /* SKINIT */ | 0 /* WDT */;
07716717 1687
19355475 1688 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1689 get_cpu();
1690 do_cpuid_1_ent(entry, function, index);
1691 ++*nent;
1692
1693 switch (function) {
1694 case 0:
1695 entry->eax = min(entry->eax, (u32)0xb);
1696 break;
1697 case 1:
1698 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1699 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1700 /* we support x2apic emulation even if host does not support
1701 * it since we emulate x2apic in software */
1702 entry->ecx |= F(X2APIC);
07716717
DK		 1703 break;
1704 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1705 * may return different values. This forces us to get_cpu() before
1706 * issuing the first command, and also to emulate this annoying behavior
1707 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1708 case 2: {
1709 int t, times = entry->eax & 0xff;
1710
1711 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1712 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1713 for (t = 1; t < times && *nent < maxnent; ++t) {
1714 do_cpuid_1_ent(&entry[t], function, 0);
1715 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1716 ++*nent;
1717 }
1718 break;
1719 }
1720 /* function 4 and 0xb have additional index. */
1721 case 4: {
14af3f3c 1722 int i, cache_type;
07716717
DK		 1723
1724 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1725 /* read more entries until cache_type is zero */
14af3f3c
HH		 1726 for (i = 1; *nent < maxnent; ++i) {
1727 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1728 if (!cache_type)
1729 break;
14af3f3c
HH		 1730 do_cpuid_1_ent(&entry[i], function, i);
1731 entry[i].flags |=
07716717
DK		 1732 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1733 ++*nent;
1734 }
1735 break;
1736 }
1737 case 0xb: {
14af3f3c 1738 int i, level_type;
07716717
DK		 1739
1740 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1741 /* read more entries until level_type is zero */
14af3f3c 1742 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1743 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1744 if (!level_type)
1745 break;
14af3f3c
HH		 1746 do_cpuid_1_ent(&entry[i], function, i);
1747 entry[i].flags |=
07716717
DK		 1748 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1749 ++*nent;
1750 }
1751 break;
1752 }
1753 case 0x80000000:
1754 entry->eax = min(entry->eax, 0x8000001a);
1755 break;
1756 case 0x80000001:
1757 entry->edx &= kvm_supported_word1_x86_features;
1758 entry->ecx &= kvm_supported_word6_x86_features;
1759 break;
1760 }
1761 put_cpu();
1762}
1763
7faa4ee1
AK		 1764#undef F
1765
674eea0f 1766static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1767 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1768{
1769 struct kvm_cpuid_entry2 *cpuid_entries;
1770 int limit, nent = 0, r = -E2BIG;
1771 u32 func;
1772
1773 if (cpuid->nent < 1)
1774 goto out;
6a544355
AK		 1775 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1776 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1777 r = -ENOMEM;
1778 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1779 if (!cpuid_entries)
1780 goto out;
1781
1782 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1783 limit = cpuid_entries[0].eax;
1784 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1785 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1786 &nent, cpuid->nent);
07716717
DK		 1787 r = -E2BIG;
1788 if (nent >= cpuid->nent)
1789 goto out_free;
1790
1791 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1792 limit = cpuid_entries[nent - 1].eax;
1793 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1794 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1795 &nent, cpuid->nent);
cb007648
MM		 1796 r = -E2BIG;
1797 if (nent >= cpuid->nent)
1798 goto out_free;
1799
07716717
DK		 1800 r = -EFAULT;
1801 if (copy_to_user(entries, cpuid_entries,
19355475 1802 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1803 goto out_free;
1804 cpuid->nent = nent;
1805 r = 0;
1806
1807out_free:
1808 vfree(cpuid_entries);
1809out:
1810 return r;
1811}
1812
313a3dc7
CO		 1813static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1814 struct kvm_lapic_state *s)
1815{
1816 vcpu_load(vcpu);
ad312c7c 1817 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1818 vcpu_put(vcpu);
1819
1820 return 0;
1821}
1822
1823static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1824 struct kvm_lapic_state *s)
1825{
1826 vcpu_load(vcpu);
ad312c7c 1827 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1828 kvm_apic_post_state_restore(vcpu);
cb142eb7 1829 update_cr8_intercept(vcpu);
313a3dc7
CO		 1830 vcpu_put(vcpu);
1831
1832 return 0;
1833}
1834
f77bc6a4
ZX		 1835static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1836 struct kvm_interrupt *irq)
1837{
1838 if (irq->irq < 0 || irq->irq >= 256)
1839 return -EINVAL;
1840 if (irqchip_in_kernel(vcpu->kvm))
1841 return -ENXIO;
1842 vcpu_load(vcpu);
1843
66fd3f7f 1844 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1845
1846 vcpu_put(vcpu);
1847
1848 return 0;
1849}
1850
c4abb7c9
JK		 1851static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1852{
1853 vcpu_load(vcpu);
1854 kvm_inject_nmi(vcpu);
1855 vcpu_put(vcpu);
1856
1857 return 0;
1858}
1859
b209749f
AK		 1860static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1861 struct kvm_tpr_access_ctl *tac)
1862{
1863 if (tac->flags)
1864 return -EINVAL;
1865 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1866 return 0;
1867}
1868
890ca9ae
HY		 1869static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1870 u64 mcg_cap)
1871{
1872 int r;
1873 unsigned bank_num = mcg_cap & 0xff, bank;
1874
1875 r = -EINVAL;
a9e38c3e 1876 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1877 goto out;
1878 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1879 goto out;
1880 r = 0;
1881 vcpu->arch.mcg_cap = mcg_cap;
1882 /* Init IA32_MCG_CTL to all 1s */
1883 if (mcg_cap & MCG_CTL_P)
1884 vcpu->arch.mcg_ctl = ~(u64)0;
1885 /* Init IA32_MCi_CTL to all 1s */
1886 for (bank = 0; bank < bank_num; bank++)
1887 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1888out:
1889 return r;
1890}
1891
1892static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1893 struct kvm_x86_mce *mce)
1894{
1895 u64 mcg_cap = vcpu->arch.mcg_cap;
1896 unsigned bank_num = mcg_cap & 0xff;
1897 u64 *banks = vcpu->arch.mce_banks;
1898
1899 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1900 return -EINVAL;
1901 /*
1902 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1903 * reporting is disabled
1904 */
1905 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1906 vcpu->arch.mcg_ctl != ~(u64)0)
1907 return 0;
1908 banks += 4 * mce->bank;
1909 /*
1910 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1911 * reporting is disabled for the bank
1912 */
1913 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1914 return 0;
1915 if (mce->status & MCI_STATUS_UC) {
1916 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 1917 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 1918 printk(KERN_DEBUG "kvm: set_mce: "
1919 "injects mce exception while "
1920 "previous one is in progress!\n");
1921 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1922 return 0;
1923 }
1924 if (banks[1] & MCI_STATUS_VAL)
1925 mce->status |= MCI_STATUS_OVER;
1926 banks[2] = mce->addr;
1927 banks[3] = mce->misc;
1928 vcpu->arch.mcg_status = mce->mcg_status;
1929 banks[1] = mce->status;
1930 kvm_queue_exception(vcpu, MC_VECTOR);
1931 } else if (!(banks[1] & MCI_STATUS_VAL)
1932 || !(banks[1] & MCI_STATUS_UC)) {
1933 if (banks[1] & MCI_STATUS_VAL)
1934 mce->status |= MCI_STATUS_OVER;
1935 banks[2] = mce->addr;
1936 banks[3] = mce->misc;
1937 banks[1] = mce->status;
1938 } else
1939 banks[1] |= MCI_STATUS_OVER;
1940 return 0;
1941}
1942
3cfc3092
JK		 1943static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1944 struct kvm_vcpu_events *events)
1945{
1946 vcpu_load(vcpu);
1947
1948 events->exception.injected = vcpu->arch.exception.pending;
1949 events->exception.nr = vcpu->arch.exception.nr;
1950 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1951 events->exception.error_code = vcpu->arch.exception.error_code;
1952
1953 events->interrupt.injected = vcpu->arch.interrupt.pending;
1954 events->interrupt.nr = vcpu->arch.interrupt.nr;
1955 events->interrupt.soft = vcpu->arch.interrupt.soft;
1956
1957 events->nmi.injected = vcpu->arch.nmi_injected;
1958 events->nmi.pending = vcpu->arch.nmi_pending;
1959 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1960
1961 events->sipi_vector = vcpu->arch.sipi_vector;
1962
dab4b911
JK		 1963 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1964 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 1965
1966 vcpu_put(vcpu);
1967}
1968
1969static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1970 struct kvm_vcpu_events *events)
1971{
dab4b911
JK		 1972 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1973 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 1974 return -EINVAL;
1975
1976 vcpu_load(vcpu);
1977
1978 vcpu->arch.exception.pending = events->exception.injected;
1979 vcpu->arch.exception.nr = events->exception.nr;
1980 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1981 vcpu->arch.exception.error_code = events->exception.error_code;
1982
1983 vcpu->arch.interrupt.pending = events->interrupt.injected;
1984 vcpu->arch.interrupt.nr = events->interrupt.nr;
1985 vcpu->arch.interrupt.soft = events->interrupt.soft;
1986 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1987 kvm_pic_clear_isr_ack(vcpu->kvm);
1988
1989 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 1990 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1991 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 1992 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1993
dab4b911
JK		 1994 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1995 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 1996
1997 vcpu_put(vcpu);
1998
1999 return 0;
2000}
2001
313a3dc7
CO		 2002long kvm_arch_vcpu_ioctl(struct file *filp,
2003 unsigned int ioctl, unsigned long arg)
2004{
2005 struct kvm_vcpu *vcpu = filp->private_data;
2006 void __user *argp = (void __user *)arg;
2007 int r;
b772ff36 2008 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2009
2010 switch (ioctl) {
2011 case KVM_GET_LAPIC: {
2204ae3c
MT		 2012 r = -EINVAL;
2013 if (!vcpu->arch.apic)
2014 goto out;
b772ff36 2015 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2016
b772ff36
DH		 2017 r = -ENOMEM;
2018 if (!lapic)
2019 goto out;
2020 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2021 if (r)
2022 goto out;
2023 r = -EFAULT;
b772ff36 2024 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2025 goto out;
2026 r = 0;
2027 break;
2028 }
2029 case KVM_SET_LAPIC: {
2204ae3c
MT		 2030 r = -EINVAL;
2031 if (!vcpu->arch.apic)
2032 goto out;
b772ff36
DH		 2033 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2034 r = -ENOMEM;
2035 if (!lapic)
2036 goto out;
313a3dc7 2037 r = -EFAULT;
b772ff36 2038 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2039 goto out;
b772ff36 2040 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2041 if (r)
2042 goto out;
2043 r = 0;
2044 break;
2045 }
f77bc6a4
ZX		 2046 case KVM_INTERRUPT: {
2047 struct kvm_interrupt irq;
2048
2049 r = -EFAULT;
2050 if (copy_from_user(&irq, argp, sizeof irq))
2051 goto out;
2052 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2053 if (r)
2054 goto out;
2055 r = 0;
2056 break;
2057 }
c4abb7c9
JK		 2058 case KVM_NMI: {
2059 r = kvm_vcpu_ioctl_nmi(vcpu);
2060 if (r)
2061 goto out;
2062 r = 0;
2063 break;
2064 }
313a3dc7
CO		 2065 case KVM_SET_CPUID: {
2066 struct kvm_cpuid __user *cpuid_arg = argp;
2067 struct kvm_cpuid cpuid;
2068
2069 r = -EFAULT;
2070 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2071 goto out;
2072 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2073 if (r)
2074 goto out;
2075 break;
2076 }
07716717
DK		 2077 case KVM_SET_CPUID2: {
2078 struct kvm_cpuid2 __user *cpuid_arg = argp;
2079 struct kvm_cpuid2 cpuid;
2080
2081 r = -EFAULT;
2082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2083 goto out;
2084 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2085 cpuid_arg->entries);
07716717
DK		 2086 if (r)
2087 goto out;
2088 break;
2089 }
2090 case KVM_GET_CPUID2: {
2091 struct kvm_cpuid2 __user *cpuid_arg = argp;
2092 struct kvm_cpuid2 cpuid;
2093
2094 r = -EFAULT;
2095 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2096 goto out;
2097 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2098 cpuid_arg->entries);
07716717
DK		 2099 if (r)
2100 goto out;
2101 r = -EFAULT;
2102 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2103 goto out;
2104 r = 0;
2105 break;
2106 }
313a3dc7
CO		 2107 case KVM_GET_MSRS:
2108 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2109 break;
2110 case KVM_SET_MSRS:
2111 r = msr_io(vcpu, argp, do_set_msr, 0);
2112 break;
b209749f
AK		 2113 case KVM_TPR_ACCESS_REPORTING: {
2114 struct kvm_tpr_access_ctl tac;
2115
2116 r = -EFAULT;
2117 if (copy_from_user(&tac, argp, sizeof tac))
2118 goto out;
2119 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2120 if (r)
2121 goto out;
2122 r = -EFAULT;
2123 if (copy_to_user(argp, &tac, sizeof tac))
2124 goto out;
2125 r = 0;
2126 break;
2127 };
b93463aa
AK		 2128 case KVM_SET_VAPIC_ADDR: {
2129 struct kvm_vapic_addr va;
2130
2131 r = -EINVAL;
2132 if (!irqchip_in_kernel(vcpu->kvm))
2133 goto out;
2134 r = -EFAULT;
2135 if (copy_from_user(&va, argp, sizeof va))
2136 goto out;
2137 r = 0;
2138 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2139 break;
2140 }
890ca9ae
HY		 2141 case KVM_X86_SETUP_MCE: {
2142 u64 mcg_cap;
2143
2144 r = -EFAULT;
2145 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2146 goto out;
2147 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2148 break;
2149 }
2150 case KVM_X86_SET_MCE: {
2151 struct kvm_x86_mce mce;
2152
2153 r = -EFAULT;
2154 if (copy_from_user(&mce, argp, sizeof mce))
2155 goto out;
2156 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2157 break;
2158 }
3cfc3092
JK		 2159 case KVM_GET_VCPU_EVENTS: {
2160 struct kvm_vcpu_events events;
2161
2162 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2163
2164 r = -EFAULT;
2165 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2166 break;
2167 r = 0;
2168 break;
2169 }
2170 case KVM_SET_VCPU_EVENTS: {
2171 struct kvm_vcpu_events events;
2172
2173 r = -EFAULT;
2174 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2175 break;
2176
2177 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2178 break;
2179 }
313a3dc7
CO		 2180 default:
2181 r = -EINVAL;
2182 }
2183out:
7a6ce84c 2184 kfree(lapic);
313a3dc7
CO		 2185 return r;
2186}
2187
1fe779f8
CO		 2188static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2189{
2190 int ret;
2191
2192 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2193 return -1;
2194 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2195 return ret;
2196}
2197
b927a3ce
SY		 2198static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2199 u64 ident_addr)
2200{
2201 kvm->arch.ept_identity_map_addr = ident_addr;
2202 return 0;
2203}
2204
1fe779f8
CO		 2205static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2206 u32 kvm_nr_mmu_pages)
2207{
2208 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2209 return -EINVAL;
2210
72dc67a6 2211 down_write(&kvm->slots_lock);
7c8a83b7 2212 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2213
2214 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2215 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2216
7c8a83b7 2217 spin_unlock(&kvm->mmu_lock);
72dc67a6 2218 up_write(&kvm->slots_lock);
1fe779f8
CO		 2219 return 0;
2220}
2221
2222static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2223{
f05e70ac 2224 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2225}
2226
a983fb23
MT		 2227gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2228{
2229 int i;
2230 struct kvm_mem_alias *alias;
2231 struct kvm_mem_aliases *aliases;
2232
2233 aliases = rcu_dereference(kvm->arch.aliases);
2234
2235 for (i = 0; i < aliases->naliases; ++i) {
2236 alias = &aliases->aliases[i];
2237 if (alias->flags & KVM_ALIAS_INVALID)
2238 continue;
2239 if (gfn >= alias->base_gfn
2240 && gfn < alias->base_gfn + alias->npages)
2241 return alias->target_gfn + gfn - alias->base_gfn;
2242 }
2243 return gfn;
2244}
2245
e9f85cde
ZX		 2246gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2247{
2248 int i;
2249 struct kvm_mem_alias *alias;
a983fb23
MT		 2250 struct kvm_mem_aliases *aliases;
2251
2252 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2253
fef9cce0
MT		 2254 for (i = 0; i < aliases->naliases; ++i) {
2255 alias = &aliases->aliases[i];
e9f85cde
ZX		 2256 if (gfn >= alias->base_gfn
2257 && gfn < alias->base_gfn + alias->npages)
2258 return alias->target_gfn + gfn - alias->base_gfn;
2259 }
2260 return gfn;
2261}
2262
1fe779f8
CO		 2263/*
2264 * Set a new alias region. Aliases map a portion of physical memory into
2265 * another portion. This is useful for memory windows, for example the PC
2266 * VGA region.
2267 */
2268static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2269 struct kvm_memory_alias *alias)
2270{
2271 int r, n;
2272 struct kvm_mem_alias *p;
a983fb23 2273 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2274
2275 r = -EINVAL;
2276 /* General sanity checks */
2277 if (alias->memory_size & (PAGE_SIZE - 1))
2278 goto out;
2279 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2280 goto out;
2281 if (alias->slot >= KVM_ALIAS_SLOTS)
2282 goto out;
2283 if (alias->guest_phys_addr + alias->memory_size
2284 < alias->guest_phys_addr)
2285 goto out;
2286 if (alias->target_phys_addr + alias->memory_size
2287 < alias->target_phys_addr)
2288 goto out;
2289
a983fb23
MT		 2290 r = -ENOMEM;
2291 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2292 if (!aliases)
2293 goto out;
2294
72dc67a6 2295 down_write(&kvm->slots_lock);
1fe779f8 2296
a983fb23
MT		 2297 /* invalidate any gfn reference in case of deletion/shrinking */
2298 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2299 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2300 old_aliases = kvm->arch.aliases;
2301 rcu_assign_pointer(kvm->arch.aliases, aliases);
2302 synchronize_srcu_expedited(&kvm->srcu);
2303 kvm_mmu_zap_all(kvm);
2304 kfree(old_aliases);
2305
2306 r = -ENOMEM;
2307 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2308 if (!aliases)
2309 goto out_unlock;
2310
2311 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2312
2313 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2314 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2315 p->npages = alias->memory_size >> PAGE_SHIFT;
2316 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2317 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2318
2319 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2320 if (aliases->aliases[n - 1].npages)
1fe779f8 2321 break;
fef9cce0 2322 aliases->naliases = n;
1fe779f8 2323
a983fb23
MT		 2324 old_aliases = kvm->arch.aliases;
2325 rcu_assign_pointer(kvm->arch.aliases, aliases);
2326 synchronize_srcu_expedited(&kvm->srcu);
2327 kfree(old_aliases);
2328 r = 0;
1fe779f8 2329
a983fb23 2330out_unlock:
72dc67a6 2331 up_write(&kvm->slots_lock);
1fe779f8
CO		 2332out:
2333 return r;
2334}
2335
2336static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2337{
2338 int r;
2339
2340 r = 0;
2341 switch (chip->chip_id) {
2342 case KVM_IRQCHIP_PIC_MASTER:
2343 memcpy(&chip->chip.pic,
2344 &pic_irqchip(kvm)->pics[0],
2345 sizeof(struct kvm_pic_state));
2346 break;
2347 case KVM_IRQCHIP_PIC_SLAVE:
2348 memcpy(&chip->chip.pic,
2349 &pic_irqchip(kvm)->pics[1],
2350 sizeof(struct kvm_pic_state));
2351 break;
2352 case KVM_IRQCHIP_IOAPIC:
eba0226b 2353 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2354 break;
2355 default:
2356 r = -EINVAL;
2357 break;
2358 }
2359 return r;
2360}
2361
2362static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2363{
2364 int r;
2365
2366 r = 0;
2367 switch (chip->chip_id) {
2368 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2369 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2370 memcpy(&pic_irqchip(kvm)->pics[0],
2371 &chip->chip.pic,
2372 sizeof(struct kvm_pic_state));
894a9c55 2373 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2374 break;
2375 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2376 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2377 memcpy(&pic_irqchip(kvm)->pics[1],
2378 &chip->chip.pic,
2379 sizeof(struct kvm_pic_state));
894a9c55 2380 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2381 break;
2382 case KVM_IRQCHIP_IOAPIC:
eba0226b 2383 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2384 break;
2385 default:
2386 r = -EINVAL;
2387 break;
2388 }
2389 kvm_pic_update_irq(pic_irqchip(kvm));
2390 return r;
2391}
2392
e0f63cb9
SY		 2393static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2394{
2395 int r = 0;
2396
894a9c55 2397 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2398 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2399 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2400 return r;
2401}
2402
2403static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2404{
2405 int r = 0;
2406
894a9c55 2407 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2408 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2409 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2410 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2411 return r;
2412}
2413
2414static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2415{
2416 int r = 0;
2417
2418 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2419 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2420 sizeof(ps->channels));
2421 ps->flags = kvm->arch.vpit->pit_state.flags;
2422 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2423 return r;
2424}
2425
2426static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2427{
2428 int r = 0, start = 0;
2429 u32 prev_legacy, cur_legacy;
2430 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2431 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2432 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2433 if (!prev_legacy && cur_legacy)
2434 start = 1;
2435 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2436 sizeof(kvm->arch.vpit->pit_state.channels));
2437 kvm->arch.vpit->pit_state.flags = ps->flags;
2438 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2439 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2440 return r;
2441}
2442
52d939a0
MT		 2443static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2444 struct kvm_reinject_control *control)
2445{
2446 if (!kvm->arch.vpit)
2447 return -ENXIO;
894a9c55 2448 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2449 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2450 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2451 return 0;
2452}
2453
5bb064dc
ZX		 2454/*
2455 * Get (and clear) the dirty memory log for a memory slot.
2456 */
2457int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2458 struct kvm_dirty_log *log)
2459{
b050b015 2460 int r, n, i;
5bb064dc 2461 struct kvm_memory_slot *memslot;
b050b015
MT		 2462 unsigned long is_dirty = 0;
2463 unsigned long *dirty_bitmap = NULL;
5bb064dc 2464
72dc67a6 2465 down_write(&kvm->slots_lock);
5bb064dc 2466
b050b015
MT		 2467 r = -EINVAL;
2468 if (log->slot >= KVM_MEMORY_SLOTS)
2469 goto out;
2470
2471 memslot = &kvm->memslots->memslots[log->slot];
2472 r = -ENOENT;
2473 if (!memslot->dirty_bitmap)
2474 goto out;
2475
2476 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2477
2478 r = -ENOMEM;
2479 dirty_bitmap = vmalloc(n);
2480 if (!dirty_bitmap)
5bb064dc 2481 goto out;
b050b015
MT		 2482 memset(dirty_bitmap, 0, n);
2483
2484 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2485 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2486
2487 /* If nothing is dirty, don't bother messing with page tables. */
2488 if (is_dirty) {
b050b015
MT		 2489 struct kvm_memslots *slots, *old_slots;
2490
7c8a83b7 2491 spin_lock(&kvm->mmu_lock);
5bb064dc 2492 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2493 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2494
2495 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2496 if (!slots)
2497 goto out_free;
2498
2499 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2500 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2501
2502 old_slots = kvm->memslots;
2503 rcu_assign_pointer(kvm->memslots, slots);
2504 synchronize_srcu_expedited(&kvm->srcu);
2505 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2506 kfree(old_slots);
5bb064dc 2507 }
b050b015 2508
5bb064dc 2509 r = 0;
b050b015
MT		 2510 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2511 r = -EFAULT;
2512out_free:
2513 vfree(dirty_bitmap);
5bb064dc 2514out:
72dc67a6 2515 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2516 return r;
2517}
2518
1fe779f8
CO		 2519long kvm_arch_vm_ioctl(struct file *filp,
2520 unsigned int ioctl, unsigned long arg)
2521{
2522 struct kvm *kvm = filp->private_data;
2523 void __user *argp = (void __user *)arg;
367e1319 2524 int r = -ENOTTY;
f0d66275
DH		 2525 /*
2526 * This union makes it completely explicit to gcc-3.x
2527 * that these two variables' stack usage should be
2528 * combined, not added together.
2529 */
2530 union {
2531 struct kvm_pit_state ps;
e9f42757 2532 struct kvm_pit_state2 ps2;
f0d66275 2533 struct kvm_memory_alias alias;
c5ff41ce 2534 struct kvm_pit_config pit_config;
f0d66275 2535 } u;
1fe779f8
CO		 2536
2537 switch (ioctl) {
2538 case KVM_SET_TSS_ADDR:
2539 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2540 if (r < 0)
2541 goto out;
2542 break;
b927a3ce
SY		 2543 case KVM_SET_IDENTITY_MAP_ADDR: {
2544 u64 ident_addr;
2545
2546 r = -EFAULT;
2547 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2548 goto out;
2549 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2550 if (r < 0)
2551 goto out;
2552 break;
2553 }
1fe779f8
CO		 2554 case KVM_SET_MEMORY_REGION: {
2555 struct kvm_memory_region kvm_mem;
2556 struct kvm_userspace_memory_region kvm_userspace_mem;
2557
2558 r = -EFAULT;
2559 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2560 goto out;
2561 kvm_userspace_mem.slot = kvm_mem.slot;
2562 kvm_userspace_mem.flags = kvm_mem.flags;
2563 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2564 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2565 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2566 if (r)
2567 goto out;
2568 break;
2569 }
2570 case KVM_SET_NR_MMU_PAGES:
2571 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2572 if (r)
2573 goto out;
2574 break;
2575 case KVM_GET_NR_MMU_PAGES:
2576 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2577 break;
f0d66275 2578 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2579 r = -EFAULT;
f0d66275 2580 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2581 goto out;
f0d66275 2582 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2583 if (r)
2584 goto out;
2585 break;
3ddea128
MT		 2586 case KVM_CREATE_IRQCHIP: {
2587 struct kvm_pic *vpic;
2588
2589 mutex_lock(&kvm->lock);
2590 r = -EEXIST;
2591 if (kvm->arch.vpic)
2592 goto create_irqchip_unlock;
1fe779f8 2593 r = -ENOMEM;
3ddea128
MT		 2594 vpic = kvm_create_pic(kvm);
2595 if (vpic) {
1fe779f8
CO		 2596 r = kvm_ioapic_init(kvm);
2597 if (r) {
3ddea128
MT		 2598 kfree(vpic);
2599 goto create_irqchip_unlock;
1fe779f8
CO		 2600 }
2601 } else
3ddea128
MT		 2602 goto create_irqchip_unlock;
2603 smp_wmb();
2604 kvm->arch.vpic = vpic;
2605 smp_wmb();
399ec807
AK		 2606 r = kvm_setup_default_irq_routing(kvm);
2607 if (r) {
3ddea128 2608 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2609 kfree(kvm->arch.vpic);
2610 kfree(kvm->arch.vioapic);
3ddea128
MT		 2611 kvm->arch.vpic = NULL;
2612 kvm->arch.vioapic = NULL;
2613 mutex_unlock(&kvm->irq_lock);
399ec807 2614 }
3ddea128
MT		 2615 create_irqchip_unlock:
2616 mutex_unlock(&kvm->lock);
1fe779f8 2617 break;
3ddea128 2618 }
7837699f 2619 case KVM_CREATE_PIT:
c5ff41ce
JK		 2620 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2621 goto create_pit;
2622 case KVM_CREATE_PIT2:
2623 r = -EFAULT;
2624 if (copy_from_user(&u.pit_config, argp,
2625 sizeof(struct kvm_pit_config)))
2626 goto out;
2627 create_pit:
108b5669 2628 down_write(&kvm->slots_lock);
269e05e4
AK		 2629 r = -EEXIST;
2630 if (kvm->arch.vpit)
2631 goto create_pit_unlock;
7837699f 2632 r = -ENOMEM;
c5ff41ce 2633 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2634 if (kvm->arch.vpit)
2635 r = 0;
269e05e4 2636 create_pit_unlock:
108b5669 2637 up_write(&kvm->slots_lock);
7837699f 2638 break;
4925663a 2639 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2640 case KVM_IRQ_LINE: {
2641 struct kvm_irq_level irq_event;
2642
2643 r = -EFAULT;
2644 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2645 goto out;
2646 if (irqchip_in_kernel(kvm)) {
4925663a 2647 __s32 status;
4925663a
GN		 2648 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2649 irq_event.irq, irq_event.level);
4925663a
GN		 2650 if (ioctl == KVM_IRQ_LINE_STATUS) {
2651 irq_event.status = status;
2652 if (copy_to_user(argp, &irq_event,
2653 sizeof irq_event))
2654 goto out;
2655 }
1fe779f8
CO		 2656 r = 0;
2657 }
2658 break;
2659 }
2660 case KVM_GET_IRQCHIP: {
2661 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2662 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2663
f0d66275
DH		 2664 r = -ENOMEM;
2665 if (!chip)
1fe779f8 2666 goto out;
f0d66275
DH		 2667 r = -EFAULT;
2668 if (copy_from_user(chip, argp, sizeof *chip))
2669 goto get_irqchip_out;
1fe779f8
CO		 2670 r = -ENXIO;
2671 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2672 goto get_irqchip_out;
2673 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2674 if (r)
f0d66275 2675 goto get_irqchip_out;
1fe779f8 2676 r = -EFAULT;
f0d66275
DH		 2677 if (copy_to_user(argp, chip, sizeof *chip))
2678 goto get_irqchip_out;
1fe779f8 2679 r = 0;
f0d66275
DH		 2680 get_irqchip_out:
2681 kfree(chip);
2682 if (r)
2683 goto out;
1fe779f8
CO		 2684 break;
2685 }
2686 case KVM_SET_IRQCHIP: {
2687 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2688 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2689
f0d66275
DH		 2690 r = -ENOMEM;
2691 if (!chip)
1fe779f8 2692 goto out;
f0d66275
DH		 2693 r = -EFAULT;
2694 if (copy_from_user(chip, argp, sizeof *chip))
2695 goto set_irqchip_out;
1fe779f8
CO		 2696 r = -ENXIO;
2697 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2698 goto set_irqchip_out;
2699 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2700 if (r)
f0d66275 2701 goto set_irqchip_out;
1fe779f8 2702 r = 0;
f0d66275
DH		 2703 set_irqchip_out:
2704 kfree(chip);
2705 if (r)
2706 goto out;
1fe779f8
CO		 2707 break;
2708 }
e0f63cb9 2709 case KVM_GET_PIT: {
e0f63cb9 2710 r = -EFAULT;
f0d66275 2711 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2712 goto out;
2713 r = -ENXIO;
2714 if (!kvm->arch.vpit)
2715 goto out;
f0d66275 2716 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2717 if (r)
2718 goto out;
2719 r = -EFAULT;
f0d66275 2720 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2721 goto out;
2722 r = 0;
2723 break;
2724 }
2725 case KVM_SET_PIT: {
e0f63cb9 2726 r = -EFAULT;
f0d66275 2727 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2728 goto out;
2729 r = -ENXIO;
2730 if (!kvm->arch.vpit)
2731 goto out;
f0d66275 2732 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2733 if (r)
2734 goto out;
2735 r = 0;
2736 break;
2737 }
e9f42757
BK		 2738 case KVM_GET_PIT2: {
2739 r = -ENXIO;
2740 if (!kvm->arch.vpit)
2741 goto out;
2742 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2743 if (r)
2744 goto out;
2745 r = -EFAULT;
2746 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2747 goto out;
2748 r = 0;
2749 break;
2750 }
2751 case KVM_SET_PIT2: {
2752 r = -EFAULT;
2753 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2754 goto out;
2755 r = -ENXIO;
2756 if (!kvm->arch.vpit)
2757 goto out;
2758 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2759 if (r)
2760 goto out;
2761 r = 0;
2762 break;
2763 }
52d939a0
MT		 2764 case KVM_REINJECT_CONTROL: {
2765 struct kvm_reinject_control control;
2766 r = -EFAULT;
2767 if (copy_from_user(&control, argp, sizeof(control)))
2768 goto out;
2769 r = kvm_vm_ioctl_reinject(kvm, &control);
2770 if (r)
2771 goto out;
2772 r = 0;
2773 break;
2774 }
ffde22ac
ES		 2775 case KVM_XEN_HVM_CONFIG: {
2776 r = -EFAULT;
2777 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2778 sizeof(struct kvm_xen_hvm_config)))
2779 goto out;
2780 r = -EINVAL;
2781 if (kvm->arch.xen_hvm_config.flags)
2782 goto out;
2783 r = 0;
2784 break;
2785 }
afbcf7ab
GC		 2786 case KVM_SET_CLOCK: {
2787 struct timespec now;
2788 struct kvm_clock_data user_ns;
2789 u64 now_ns;
2790 s64 delta;
2791
2792 r = -EFAULT;
2793 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2794 goto out;
2795
2796 r = -EINVAL;
2797 if (user_ns.flags)
2798 goto out;
2799
2800 r = 0;
2801 ktime_get_ts(&now);
2802 now_ns = timespec_to_ns(&now);
2803 delta = user_ns.clock - now_ns;
2804 kvm->arch.kvmclock_offset = delta;
2805 break;
2806 }
2807 case KVM_GET_CLOCK: {
2808 struct timespec now;
2809 struct kvm_clock_data user_ns;
2810 u64 now_ns;
2811
2812 ktime_get_ts(&now);
2813 now_ns = timespec_to_ns(&now);
2814 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2815 user_ns.flags = 0;
2816
2817 r = -EFAULT;
2818 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2819 goto out;
2820 r = 0;
2821 break;
2822 }
2823
1fe779f8
CO		 2824 default:
2825 ;
2826 }
2827out:
2828 return r;
2829}
2830
a16b043c 2831static void kvm_init_msr_list(void)
043405e1
CO		 2832{
2833 u32 dummy[2];
2834 unsigned i, j;
2835
e3267cbb
GC		 2836 /* skip the first msrs in the list. KVM-specific */
2837 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2838 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2839 continue;
2840 if (j < i)
2841 msrs_to_save[j] = msrs_to_save[i];
2842 j++;
2843 }
2844 num_msrs_to_save = j;
2845}
2846
bda9020e
MT		 2847static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2848 const void *v)
bbd9b64e 2849{
bda9020e
MT		 2850 if (vcpu->arch.apic &&
2851 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2852 return 0;
bbd9b64e 2853
e93f8a0f 2854 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2855}
2856
bda9020e 2857static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2858{
bda9020e
MT		 2859 if (vcpu->arch.apic &&
2860 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2861 return 0;
bbd9b64e 2862
e93f8a0f 2863 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 2864}
2865
cded19f3
HE		 2866static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2867 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2868{
2869 void *data = val;
10589a46 2870 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2871
2872 while (bytes) {
ad312c7c 2873 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2874 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2875 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2876 int ret;
2877
10589a46
MT		 2878 if (gpa == UNMAPPED_GVA) {
2879 r = X86EMUL_PROPAGATE_FAULT;
2880 goto out;
2881 }
77c2002e 2882 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2883 if (ret < 0) {
2884 r = X86EMUL_UNHANDLEABLE;
2885 goto out;
2886 }
bbd9b64e 2887
77c2002e
IE		 2888 bytes -= toread;
2889 data += toread;
2890 addr += toread;
bbd9b64e 2891 }
10589a46 2892out:
10589a46 2893 return r;
bbd9b64e 2894}
77c2002e 2895
cded19f3
HE		 2896static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2897 struct kvm_vcpu *vcpu)
77c2002e
IE		 2898{
2899 void *data = val;
2900 int r = X86EMUL_CONTINUE;
2901
2902 while (bytes) {
2903 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2904 unsigned offset = addr & (PAGE_SIZE-1);
2905 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2906 int ret;
2907
2908 if (gpa == UNMAPPED_GVA) {
2909 r = X86EMUL_PROPAGATE_FAULT;
2910 goto out;
2911 }
2912 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2913 if (ret < 0) {
2914 r = X86EMUL_UNHANDLEABLE;
2915 goto out;
2916 }
2917
2918 bytes -= towrite;
2919 data += towrite;
2920 addr += towrite;
2921 }
2922out:
2923 return r;
2924}
2925
bbd9b64e 2926
bbd9b64e
CO		 2927static int emulator_read_emulated(unsigned long addr,
2928 void *val,
2929 unsigned int bytes,
2930 struct kvm_vcpu *vcpu)
2931{
bbd9b64e
CO		 2932 gpa_t gpa;
2933
2934 if (vcpu->mmio_read_completed) {
2935 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2936 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2937 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2938 vcpu->mmio_read_completed = 0;
2939 return X86EMUL_CONTINUE;
2940 }
2941
ad312c7c 2942 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2943
2944 /* For APIC access vmexit */
2945 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2946 goto mmio;
2947
77c2002e
IE		 2948 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2949 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2950 return X86EMUL_CONTINUE;
2951 if (gpa == UNMAPPED_GVA)
2952 return X86EMUL_PROPAGATE_FAULT;
2953
2954mmio:
2955 /*
2956 * Is this MMIO handled locally?
2957 */
aec51dc4
AK		 2958 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2959 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2960 return X86EMUL_CONTINUE;
2961 }
aec51dc4
AK		 2962
2963 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2964
2965 vcpu->mmio_needed = 1;
2966 vcpu->mmio_phys_addr = gpa;
2967 vcpu->mmio_size = bytes;
2968 vcpu->mmio_is_write = 0;
2969
2970 return X86EMUL_UNHANDLEABLE;
2971}
2972
3200f405 2973int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2974 const void *val, int bytes)
bbd9b64e
CO		 2975{
2976 int ret;
2977
2978 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2979 if (ret < 0)
bbd9b64e 2980 return 0;
ad218f85 2981 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2982 return 1;
2983}
2984
2985static int emulator_write_emulated_onepage(unsigned long addr,
2986 const void *val,
2987 unsigned int bytes,
2988 struct kvm_vcpu *vcpu)
2989{
10589a46
MT		 2990 gpa_t gpa;
2991
10589a46 2992 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2993
2994 if (gpa == UNMAPPED_GVA) {
c3c91fee 2995 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2996 return X86EMUL_PROPAGATE_FAULT;
2997 }
2998
2999 /* For APIC access vmexit */
3000 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3001 goto mmio;
3002
3003 if (emulator_write_phys(vcpu, gpa, val, bytes))
3004 return X86EMUL_CONTINUE;
3005
3006mmio:
aec51dc4 3007 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3008 /*
3009 * Is this MMIO handled locally?
3010 */
bda9020e 3011 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3012 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3013
3014 vcpu->mmio_needed = 1;
3015 vcpu->mmio_phys_addr = gpa;
3016 vcpu->mmio_size = bytes;
3017 vcpu->mmio_is_write = 1;
3018 memcpy(vcpu->mmio_data, val, bytes);
3019
3020 return X86EMUL_CONTINUE;
3021}
3022
3023int emulator_write_emulated(unsigned long addr,
3024 const void *val,
3025 unsigned int bytes,
3026 struct kvm_vcpu *vcpu)
3027{
3028 /* Crossing a page boundary? */
3029 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3030 int rc, now;
3031
3032 now = -addr & ~PAGE_MASK;
3033 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3034 if (rc != X86EMUL_CONTINUE)
3035 return rc;
3036 addr += now;
3037 val += now;
3038 bytes -= now;
3039 }
3040 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3041}
3042EXPORT_SYMBOL_GPL(emulator_write_emulated);
3043
3044static int emulator_cmpxchg_emulated(unsigned long addr,
3045 const void *old,
3046 const void *new,
3047 unsigned int bytes,
3048 struct kvm_vcpu *vcpu)
3049{
9f51e24e 3050 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3051#ifndef CONFIG_X86_64
3052 /* guests cmpxchg8b have to be emulated atomically */
3053 if (bytes == 8) {
10589a46 3054 gpa_t gpa;
2bacc55c 3055 struct page *page;
c0b49b0d 3056 char *kaddr;
2bacc55c
MT		 3057 u64 val;
3058
10589a46
MT		 3059 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3060
2bacc55c
MT		 3061 if (gpa == UNMAPPED_GVA ||
3062 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3063 goto emul_write;
3064
3065 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3066 goto emul_write;
3067
3068 val = *(u64 *)new;
72dc67a6 3069
2bacc55c 3070 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3071
c0b49b0d
AM		 3072 kaddr = kmap_atomic(page, KM_USER0);
3073 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3074 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3075 kvm_release_page_dirty(page);
3076 }
3200f405 3077emul_write:
2bacc55c
MT		 3078#endif
3079
bbd9b64e
CO		 3080 return emulator_write_emulated(addr, new, bytes, vcpu);
3081}
3082
3083static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3084{
3085 return kvm_x86_ops->get_segment_base(vcpu, seg);
3086}
3087
3088int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3089{
a7052897 3090 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3091 return X86EMUL_CONTINUE;
3092}
3093
3094int emulate_clts(struct kvm_vcpu *vcpu)
3095{
ad312c7c 3096 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 3097 return X86EMUL_CONTINUE;
3098}
3099
3100int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3101{
3102 struct kvm_vcpu *vcpu = ctxt->vcpu;
3103
3104 switch (dr) {
3105 case 0 ... 3:
3106 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3107 return X86EMUL_CONTINUE;
3108 default:
b8688d51 3109 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3110 return X86EMUL_UNHANDLEABLE;
3111 }
3112}
3113
3114int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3115{
3116 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3117 int exception;
3118
3119 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3120 if (exception) {
3121 /* FIXME: better handling */
3122 return X86EMUL_UNHANDLEABLE;
3123 }
3124 return X86EMUL_CONTINUE;
3125}
3126
3127void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3128{
bbd9b64e 3129 u8 opcodes[4];
5fdbf976 3130 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3131 unsigned long rip_linear;
3132
f76c710d 3133 if (!printk_ratelimit())
bbd9b64e
CO		 3134 return;
3135
25be4608
GC		 3136 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3137
77c2002e 3138 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3139
3140 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3141 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3142}
3143EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3144
14af3f3c 3145static struct x86_emulate_ops emulate_ops = {
77c2002e 3146 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3147 .read_emulated = emulator_read_emulated,
3148 .write_emulated = emulator_write_emulated,
3149 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3150};
3151
5fdbf976
MT		 3152static void cache_all_regs(struct kvm_vcpu *vcpu)
3153{
3154 kvm_register_read(vcpu, VCPU_REGS_RAX);
3155 kvm_register_read(vcpu, VCPU_REGS_RSP);
3156 kvm_register_read(vcpu, VCPU_REGS_RIP);
3157 vcpu->arch.regs_dirty = ~0;
3158}
3159
bbd9b64e 3160int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3161 unsigned long cr2,
3162 u16 error_code,
571008da 3163 int emulation_type)
bbd9b64e 3164{
310b5d30 3165 int r, shadow_mask;
571008da 3166 struct decode_cache *c;
851ba692 3167 struct kvm_run *run = vcpu->run;
bbd9b64e 3168
26eef70c 3169 kvm_clear_exception_queue(vcpu);
ad312c7c 3170 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3171 /*
56e82318 3172 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3173 * instead of direct ->regs accesses, can save hundred cycles
3174 * on Intel for instructions that don't read/change RSP, for
3175 * for example.
3176 */
3177 cache_all_regs(vcpu);
bbd9b64e
CO		 3178
3179 vcpu->mmio_is_write = 0;
ad312c7c 3180 vcpu->arch.pio.string = 0;
bbd9b64e 3181
571008da 3182 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3183 int cs_db, cs_l;
3184 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3185
ad312c7c 3186 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3187 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3188 vcpu->arch.emulate_ctxt.mode =
3189 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3190 ? X86EMUL_MODE_REAL : cs_l
3191 ? X86EMUL_MODE_PROT64 : cs_db
3192 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3193
ad312c7c 3194 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3195
0cb5762e
AP		 3196 /* Only allow emulation of specific instructions on #UD
3197 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3198 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3199 if (emulation_type & EMULTYPE_TRAP_UD) {
3200 if (!c->twobyte)
3201 return EMULATE_FAIL;
3202 switch (c->b) {
3203 case 0x01: /* VMMCALL */
3204 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3205 return EMULATE_FAIL;
3206 break;
3207 case 0x34: /* sysenter */
3208 case 0x35: /* sysexit */
3209 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3210 return EMULATE_FAIL;
3211 break;
3212 case 0x05: /* syscall */
3213 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3214 return EMULATE_FAIL;
3215 break;
3216 default:
3217 return EMULATE_FAIL;
3218 }
3219
3220 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3221 return EMULATE_FAIL;
3222 }
571008da 3223
f2b5756b 3224 ++vcpu->stat.insn_emulation;
bbd9b64e 3225 if (r) {
f2b5756b 3226 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3227 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3228 return EMULATE_DONE;
3229 return EMULATE_FAIL;
3230 }
3231 }
3232
ba8afb6b
GN		 3233 if (emulation_type & EMULTYPE_SKIP) {
3234 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3235 return EMULATE_DONE;
3236 }
3237
ad312c7c 3238 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3239 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3240
3241 if (r == 0)
3242 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3243
ad312c7c 3244 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3245 return EMULATE_DO_MMIO;
3246
3247 if ((r || vcpu->mmio_is_write) && run) {
3248 run->exit_reason = KVM_EXIT_MMIO;
3249 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3250 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3251 run->mmio.len = vcpu->mmio_size;
3252 run->mmio.is_write = vcpu->mmio_is_write;
3253 }
3254
3255 if (r) {
3256 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3257 return EMULATE_DONE;
3258 if (!vcpu->mmio_needed) {
3259 kvm_report_emulation_failure(vcpu, "mmio");
3260 return EMULATE_FAIL;
3261 }
3262 return EMULATE_DO_MMIO;
3263 }
3264
91586a3b 3265 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3266
3267 if (vcpu->mmio_is_write) {
3268 vcpu->mmio_needed = 0;
3269 return EMULATE_DO_MMIO;
3270 }
3271
3272 return EMULATE_DONE;
3273}
3274EXPORT_SYMBOL_GPL(emulate_instruction);
3275
de7d789a
CO		 3276static int pio_copy_data(struct kvm_vcpu *vcpu)
3277{
ad312c7c 3278 void *p = vcpu->arch.pio_data;
0f346074 3279 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3280 unsigned bytes;
0f346074 3281 int ret;
de7d789a 3282
ad312c7c
ZX		 3283 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3284 if (vcpu->arch.pio.in)
0f346074 3285 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3286 else
0f346074
IE		 3287 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3288 return ret;
de7d789a
CO		 3289}
3290
3291int complete_pio(struct kvm_vcpu *vcpu)
3292{
ad312c7c 3293 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3294 long delta;
3295 int r;
5fdbf976 3296 unsigned long val;
de7d789a
CO		 3297
3298 if (!io->string) {
5fdbf976
MT		 3299 if (io->in) {
3300 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3301 memcpy(&val, vcpu->arch.pio_data, io->size);
3302 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3303 }
de7d789a
CO		 3304 } else {
3305 if (io->in) {
3306 r = pio_copy_data(vcpu);
5fdbf976 3307 if (r)
de7d789a 3308 return r;
de7d789a
CO		 3309 }
3310
3311 delta = 1;
3312 if (io->rep) {
3313 delta *= io->cur_count;
3314 /*
3315 * The size of the register should really depend on
3316 * current address size.
3317 */
5fdbf976
MT		 3318 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3319 val -= delta;
3320 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3321 }
3322 if (io->down)
3323 delta = -delta;
3324 delta *= io->size;
5fdbf976
MT		 3325 if (io->in) {
3326 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3327 val += delta;
3328 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3329 } else {
3330 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3331 val += delta;
3332 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3333 }
de7d789a
CO		 3334 }
3335
de7d789a
CO		 3336 io->count -= io->cur_count;
3337 io->cur_count = 0;
3338
3339 return 0;
3340}
3341
bda9020e 3342static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3343{
3344 /* TODO: String I/O for in kernel device */
bda9020e 3345 int r;
de7d789a 3346
ad312c7c 3347 if (vcpu->arch.pio.in)
e93f8a0f 3348 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3349 vcpu->arch.pio.size, pd);
de7d789a 3350 else
e93f8a0f
MT		 3351 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3352 vcpu->arch.pio.port, vcpu->arch.pio.size,
3353 pd);
bda9020e 3354 return r;
de7d789a
CO		 3355}
3356
bda9020e 3357static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3358{
ad312c7c
ZX		 3359 struct kvm_pio_request *io = &vcpu->arch.pio;
3360 void *pd = vcpu->arch.pio_data;
bda9020e 3361 int i, r = 0;
de7d789a 3362
de7d789a 3363 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3364 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3365 io->port, io->size, pd)) {
3366 r = -EOPNOTSUPP;
3367 break;
3368 }
de7d789a
CO		 3369 pd += io->size;
3370 }
bda9020e 3371 return r;
de7d789a
CO		 3372}
3373
851ba692 3374int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3375{
5fdbf976 3376 unsigned long val;
de7d789a
CO		 3377
3378 vcpu->run->exit_reason = KVM_EXIT_IO;
3379 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3380 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3381 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3382 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3383 vcpu->run->io.port = vcpu->arch.pio.port = port;
3384 vcpu->arch.pio.in = in;
3385 vcpu->arch.pio.string = 0;
3386 vcpu->arch.pio.down = 0;
ad312c7c 3387 vcpu->arch.pio.rep = 0;
de7d789a 3388
229456fc
MT		 3389 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3390 size, 1);
2714d1d3 3391
5fdbf976
MT		 3392 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3393 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3394
bda9020e 3395 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3396 complete_pio(vcpu);
3397 return 1;
3398 }
3399 return 0;
3400}
3401EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3402
851ba692 3403int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3404 int size, unsigned long count, int down,
3405 gva_t address, int rep, unsigned port)
3406{
3407 unsigned now, in_page;
0f346074 3408 int ret = 0;
de7d789a
CO		 3409
3410 vcpu->run->exit_reason = KVM_EXIT_IO;
3411 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3412 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3413 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3414 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3415 vcpu->run->io.port = vcpu->arch.pio.port = port;
3416 vcpu->arch.pio.in = in;
3417 vcpu->arch.pio.string = 1;
3418 vcpu->arch.pio.down = down;
ad312c7c 3419 vcpu->arch.pio.rep = rep;
de7d789a 3420
229456fc
MT		 3421 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3422 size, count);
2714d1d3 3423
de7d789a
CO		 3424 if (!count) {
3425 kvm_x86_ops->skip_emulated_instruction(vcpu);
3426 return 1;
3427 }
3428
3429 if (!down)
3430 in_page = PAGE_SIZE - offset_in_page(address);
3431 else
3432 in_page = offset_in_page(address) + size;
3433 now = min(count, (unsigned long)in_page / size);
0f346074 3434 if (!now)
de7d789a 3435 now = 1;
de7d789a
CO		 3436 if (down) {
3437 /*
3438 * String I/O in reverse. Yuck. Kill the guest, fix later.
3439 */
3440 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3441 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3442 return 1;
3443 }
3444 vcpu->run->io.count = now;
ad312c7c 3445 vcpu->arch.pio.cur_count = now;
de7d789a 3446
ad312c7c 3447 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3448 kvm_x86_ops->skip_emulated_instruction(vcpu);
3449
0f346074 3450 vcpu->arch.pio.guest_gva = address;
de7d789a 3451
ad312c7c 3452 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3453 /* string PIO write */
3454 ret = pio_copy_data(vcpu);
0f346074
IE		 3455 if (ret == X86EMUL_PROPAGATE_FAULT) {
3456 kvm_inject_gp(vcpu, 0);
3457 return 1;
3458 }
bda9020e 3459 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3460 complete_pio(vcpu);
ad312c7c 3461 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3462 ret = 1;
3463 }
bda9020e
MT		 3464 }
3465 /* no string PIO read support yet */
de7d789a
CO		 3466
3467 return ret;
3468}
3469EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3470
c8076604
GH		 3471static void bounce_off(void *info)
3472{
3473 /* nothing */
3474}
3475
c8076604
GH		 3476static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3477 void *data)
3478{
3479 struct cpufreq_freqs *freq = data;
3480 struct kvm *kvm;
3481 struct kvm_vcpu *vcpu;
3482 int i, send_ipi = 0;
3483
c8076604
GH		 3484 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3485 return 0;
3486 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3487 return 0;
0cca7907 3488 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3489
3490 spin_lock(&kvm_lock);
3491 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3492 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3493 if (vcpu->cpu != freq->cpu)
3494 continue;
3495 if (!kvm_request_guest_time_update(vcpu))
3496 continue;
3497 if (vcpu->cpu != smp_processor_id())
3498 send_ipi++;
3499 }
3500 }
3501 spin_unlock(&kvm_lock);
3502
3503 if (freq->old < freq->new && send_ipi) {
3504 /*
3505 * We upscale the frequency. Must make the guest
3506 * doesn't see old kvmclock values while running with
3507 * the new frequency, otherwise we risk the guest sees
3508 * time go backwards.
3509 *
3510 * In case we update the frequency for another cpu
3511 * (which might be in guest context) send an interrupt
3512 * to kick the cpu out of guest context. Next time
3513 * guest context is entered kvmclock will be updated,
3514 * so the guest will not see stale values.
3515 */
3516 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3517 }
3518 return 0;
3519}
3520
3521static struct notifier_block kvmclock_cpufreq_notifier_block = {
3522 .notifier_call = kvmclock_cpufreq_notifier
3523};
3524
b820cc0c
ZA		 3525static void kvm_timer_init(void)
3526{
3527 int cpu;
3528
b820cc0c 3529 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3530 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3531 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3532 for_each_online_cpu(cpu) {
3533 unsigned long khz = cpufreq_get(cpu);
3534 if (!khz)
3535 khz = tsc_khz;
3536 per_cpu(cpu_tsc_khz, cpu) = khz;
3537 }
0cca7907
ZA		 3538 } else {
3539 for_each_possible_cpu(cpu)
3540 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3541 }
3542}
3543
f8c16bba 3544int kvm_arch_init(void *opaque)
043405e1 3545{
b820cc0c 3546 int r;
f8c16bba
ZX		 3547 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3548
f8c16bba
ZX		 3549 if (kvm_x86_ops) {
3550 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3551 r = -EEXIST;
3552 goto out;
f8c16bba
ZX		 3553 }
3554
3555 if (!ops->cpu_has_kvm_support()) {
3556 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3557 r = -EOPNOTSUPP;
3558 goto out;
f8c16bba
ZX		 3559 }
3560 if (ops->disabled_by_bios()) {
3561 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3562 r = -EOPNOTSUPP;
3563 goto out;
f8c16bba
ZX		 3564 }
3565
97db56ce
AK		 3566 r = kvm_mmu_module_init();
3567 if (r)
3568 goto out;
3569
3570 kvm_init_msr_list();
3571
f8c16bba 3572 kvm_x86_ops = ops;
56c6d28a 3573 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3574 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3575 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3576 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3577
b820cc0c 3578 kvm_timer_init();
c8076604 3579
f8c16bba 3580 return 0;
56c6d28a
ZX		 3581
3582out:
56c6d28a 3583 return r;
043405e1 3584}
8776e519 3585
f8c16bba
ZX		 3586void kvm_arch_exit(void)
3587{
888d256e
JK		 3588 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3589 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3590 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3591 kvm_x86_ops = NULL;
56c6d28a
ZX		 3592 kvm_mmu_module_exit();
3593}
f8c16bba 3594
8776e519
HB		 3595int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3596{
3597 ++vcpu->stat.halt_exits;
3598 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3599 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3600 return 1;
3601 } else {
3602 vcpu->run->exit_reason = KVM_EXIT_HLT;
3603 return 0;
3604 }
3605}
3606EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3607
2f333bcb
MT		 3608static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3609 unsigned long a1)
3610{
3611 if (is_long_mode(vcpu))
3612 return a0;
3613 else
3614 return a0 | ((gpa_t)a1 << 32);
3615}
3616
8776e519
HB		 3617int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3618{
3619 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3620 int r = 1;
8776e519 3621
5fdbf976
MT		 3622 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3623 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3624 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3625 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3626 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3627
229456fc 3628 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3629
8776e519
HB		 3630 if (!is_long_mode(vcpu)) {
3631 nr &= 0xFFFFFFFF;
3632 a0 &= 0xFFFFFFFF;
3633 a1 &= 0xFFFFFFFF;
3634 a2 &= 0xFFFFFFFF;
3635 a3 &= 0xFFFFFFFF;
3636 }
3637
07708c4a
JK		 3638 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3639 ret = -KVM_EPERM;
3640 goto out;
3641 }
3642
8776e519 3643 switch (nr) {
b93463aa
AK		 3644 case KVM_HC_VAPIC_POLL_IRQ:
3645 ret = 0;
3646 break;
2f333bcb
MT		 3647 case KVM_HC_MMU_OP:
3648 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3649 break;
8776e519
HB		 3650 default:
3651 ret = -KVM_ENOSYS;
3652 break;
3653 }
07708c4a 3654out:
5fdbf976 3655 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3656 ++vcpu->stat.hypercalls;
2f333bcb 3657 return r;
8776e519
HB		 3658}
3659EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3660
3661int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3662{
3663 char instruction[3];
3664 int ret = 0;
5fdbf976 3665 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3666
8776e519
HB		 3667
3668 /*
3669 * Blow out the MMU to ensure that no other VCPU has an active mapping
3670 * to ensure that the updated hypercall appears atomically across all
3671 * VCPUs.
3672 */
3673 kvm_mmu_zap_all(vcpu->kvm);
3674
8776e519 3675 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3676 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3677 != X86EMUL_CONTINUE)
3678 ret = -EFAULT;
3679
8776e519
HB		 3680 return ret;
3681}
3682
3683static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3684{
3685 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3686}
3687
3688void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3689{
3690 struct descriptor_table dt = { limit, base };
3691
3692 kvm_x86_ops->set_gdt(vcpu, &dt);
3693}
3694
3695void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3696{
3697 struct descriptor_table dt = { limit, base };
3698
3699 kvm_x86_ops->set_idt(vcpu, &dt);
3700}
3701
3702void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3703 unsigned long *rflags)
3704{
2d3ad1f4 3705 kvm_lmsw(vcpu, msw);
91586a3b 3706 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3707}
3708
3709unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3710{
54e445ca
JR		 3711 unsigned long value;
3712
8776e519
HB		 3713 switch (cr) {
3714 case 0:
54e445ca
JR		 3715 value = vcpu->arch.cr0;
3716 break;
8776e519 3717 case 2:
54e445ca
JR		 3718 value = vcpu->arch.cr2;
3719 break;
8776e519 3720 case 3:
54e445ca
JR		 3721 value = vcpu->arch.cr3;
3722 break;
8776e519 3723 case 4:
fc78f519 3724 value = kvm_read_cr4(vcpu);
54e445ca 3725 break;
152ff9be 3726 case 8:
54e445ca
JR		 3727 value = kvm_get_cr8(vcpu);
3728 break;
8776e519 3729 default:
b8688d51 3730 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3731 return 0;
3732 }
54e445ca
JR		 3733
3734 return value;
8776e519
HB		 3735}
3736
3737void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3738 unsigned long *rflags)
3739{
3740 switch (cr) {
3741 case 0:
2d3ad1f4 3742 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3743 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3744 break;
3745 case 2:
ad312c7c 3746 vcpu->arch.cr2 = val;
8776e519
HB		 3747 break;
3748 case 3:
2d3ad1f4 3749 kvm_set_cr3(vcpu, val);
8776e519
HB		 3750 break;
3751 case 4:
fc78f519 3752 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3753 break;
152ff9be 3754 case 8:
2d3ad1f4 3755 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3756 break;
8776e519 3757 default:
b8688d51 3758 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3759 }
3760}
3761
07716717
DK		 3762static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3763{
ad312c7c
ZX		 3764 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3765 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3766
3767 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3768 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3769 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3770 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3771 if (ej->function == e->function) {
3772 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3773 return j;
3774 }
3775 }
3776 return 0; /* silence gcc, even though control never reaches here */
3777}
3778
3779/* find an entry with matching function, matching index (if needed), and that
3780 * should be read next (if it's stateful) */
3781static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3782 u32 function, u32 index)
3783{
3784 if (e->function != function)
3785 return 0;
3786 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3787 return 0;
3788 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3789 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3790 return 0;
3791 return 1;
3792}
3793
d8017474
AG		 3794struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3795 u32 function, u32 index)
8776e519
HB		 3796{
3797 int i;
d8017474 3798 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3799
ad312c7c 3800 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3801 struct kvm_cpuid_entry2 *e;
3802
ad312c7c 3803 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3804 if (is_matching_cpuid_entry(e, function, index)) {
3805 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3806 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3807 best = e;
3808 break;
3809 }
3810 /*
3811 * Both basic or both extended?
3812 */
3813 if (((e->function ^ function) & 0x80000000) == 0)
3814 if (!best || e->function > best->function)
3815 best = e;
3816 }
d8017474
AG		 3817 return best;
3818}
0e851880 3819EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 3820
82725b20
DE		 3821int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3822{
3823 struct kvm_cpuid_entry2 *best;
3824
3825 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3826 if (best)
3827 return best->eax & 0xff;
3828 return 36;
3829}
3830
d8017474
AG		 3831void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3832{
3833 u32 function, index;
3834 struct kvm_cpuid_entry2 *best;
3835
3836 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3837 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3838 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3839 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3840 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3841 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3842 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3843 if (best) {
5fdbf976
MT		 3844 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3845 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3846 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3847 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3848 }
8776e519 3849 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3850 trace_kvm_cpuid(function,
3851 kvm_register_read(vcpu, VCPU_REGS_RAX),
3852 kvm_register_read(vcpu, VCPU_REGS_RBX),
3853 kvm_register_read(vcpu, VCPU_REGS_RCX),
3854 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3855}
3856EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3857
b6c7a5dc
HB		 3858/*
3859 * Check if userspace requested an interrupt window, and that the
3860 * interrupt window is open.
3861 *
3862 * No need to exit to userspace if we already have an interrupt queued.
3863 */
851ba692 3864static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3865{
8061823a 3866 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3867 vcpu->run->request_interrupt_window &&
5df56646 3868 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3869}
3870
851ba692 3871static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3872{
851ba692
AK		 3873 struct kvm_run *kvm_run = vcpu->run;
3874
91586a3b 3875 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3876 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3877 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3878 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3879 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3880 else
b6c7a5dc 3881 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3882 kvm_arch_interrupt_allowed(vcpu) &&
3883 !kvm_cpu_has_interrupt(vcpu) &&
3884 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3885}
3886
b93463aa
AK		 3887static void vapic_enter(struct kvm_vcpu *vcpu)
3888{
3889 struct kvm_lapic *apic = vcpu->arch.apic;
3890 struct page *page;
3891
3892 if (!apic || !apic->vapic_addr)
3893 return;
3894
3895 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3896
3897 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3898}
3899
3900static void vapic_exit(struct kvm_vcpu *vcpu)
3901{
3902 struct kvm_lapic *apic = vcpu->arch.apic;
3903
3904 if (!apic || !apic->vapic_addr)
3905 return;
3906
f8b78fa3 3907 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3908 kvm_release_page_dirty(apic->vapic_page);
3909 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3910 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3911}
3912
95ba8273
GN		 3913static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3914{
3915 int max_irr, tpr;
3916
3917 if (!kvm_x86_ops->update_cr8_intercept)
3918 return;
3919
88c808fd
AK		 3920 if (!vcpu->arch.apic)
3921 return;
3922
8db3baa2
GN		 3923 if (!vcpu->arch.apic->vapic_addr)
3924 max_irr = kvm_lapic_find_highest_irr(vcpu);
3925 else
3926 max_irr = -1;
95ba8273
GN		 3927
3928 if (max_irr != -1)
3929 max_irr >>= 4;
3930
3931 tpr = kvm_lapic_get_cr8(vcpu);
3932
3933 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3934}
3935
851ba692 3936static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3937{
3938 /* try to reinject previous events if any */
b59bb7bd
GN		 3939 if (vcpu->arch.exception.pending) {
3940 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3941 vcpu->arch.exception.has_error_code,
3942 vcpu->arch.exception.error_code);
3943 return;
3944 }
3945
95ba8273
GN		 3946 if (vcpu->arch.nmi_injected) {
3947 kvm_x86_ops->set_nmi(vcpu);
3948 return;
3949 }
3950
3951 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3952 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3953 return;
3954 }
3955
3956 /* try to inject new event if pending */
3957 if (vcpu->arch.nmi_pending) {
3958 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3959 vcpu->arch.nmi_pending = false;
3960 vcpu->arch.nmi_injected = true;
3961 kvm_x86_ops->set_nmi(vcpu);
3962 }
3963 } else if (kvm_cpu_has_interrupt(vcpu)) {
3964 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3965 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3966 false);
3967 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3968 }
3969 }
3970}
3971
851ba692 3972static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3973{
3974 int r;
6a8b1d13 3975 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3976 vcpu->run->request_interrupt_window;
b6c7a5dc 3977
2e53d63a
MT		 3978 if (vcpu->requests)
3979 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3980 kvm_mmu_unload(vcpu);
3981
b6c7a5dc
HB		 3982 r = kvm_mmu_reload(vcpu);
3983 if (unlikely(r))
3984 goto out;
3985
2f52d58c
AK		 3986 if (vcpu->requests) {
3987 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3988 __kvm_migrate_timers(vcpu);
c8076604
GH		 3989 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3990 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3991 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3992 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3993 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3994 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3995 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3996 &vcpu->requests)) {
851ba692 3997 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 3998 r = 0;
3999 goto out;
4000 }
71c4dfaf 4001 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4002 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4003 r = 0;
4004 goto out;
4005 }
2f52d58c 4006 }
b93463aa 4007
b6c7a5dc
HB		 4008 preempt_disable();
4009
4010 kvm_x86_ops->prepare_guest_switch(vcpu);
4011 kvm_load_guest_fpu(vcpu);
4012
4013 local_irq_disable();
4014
32f88400
MT		 4015 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4016 smp_mb__after_clear_bit();
4017
d7690175 4018 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4019 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4020 local_irq_enable();
4021 preempt_enable();
4022 r = 1;
4023 goto out;
4024 }
4025
851ba692 4026 inject_pending_event(vcpu);
b6c7a5dc 4027
6a8b1d13
GN		 4028 /* enable NMI/IRQ window open exits if needed */
4029 if (vcpu->arch.nmi_pending)
4030 kvm_x86_ops->enable_nmi_window(vcpu);
4031 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4032 kvm_x86_ops->enable_irq_window(vcpu);
4033
95ba8273 4034 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4035 update_cr8_intercept(vcpu);
4036 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4037 }
b93463aa 4038
3200f405
MT		 4039 up_read(&vcpu->kvm->slots_lock);
4040
b6c7a5dc
HB		 4041 kvm_guest_enter();
4042
42dbaa5a 4043 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4044 set_debugreg(0, 7);
4045 set_debugreg(vcpu->arch.eff_db[0], 0);
4046 set_debugreg(vcpu->arch.eff_db[1], 1);
4047 set_debugreg(vcpu->arch.eff_db[2], 2);
4048 set_debugreg(vcpu->arch.eff_db[3], 3);
4049 }
b6c7a5dc 4050
229456fc 4051 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4052 kvm_x86_ops->run(vcpu);
b6c7a5dc 4053
24f1e32c
FW		 4054 /*
4055 * If the guest has used debug registers, at least dr7
4056 * will be disabled while returning to the host.
4057 * If we don't have active breakpoints in the host, we don't
4058 * care about the messed up debug address registers. But if
4059 * we have some of them active, restore the old state.
4060 */
59d8eb53 4061 if (hw_breakpoint_active())
24f1e32c 4062 hw_breakpoint_restore();
42dbaa5a 4063
32f88400 4064 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4065 local_irq_enable();
4066
4067 ++vcpu->stat.exits;
4068
4069 /*
4070 * We must have an instruction between local_irq_enable() and
4071 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4072 * the interrupt shadow. The stat.exits increment will do nicely.
4073 * But we need to prevent reordering, hence this barrier():
4074 */
4075 barrier();
4076
4077 kvm_guest_exit();
4078
4079 preempt_enable();
4080
3200f405
MT		 4081 down_read(&vcpu->kvm->slots_lock);
4082
b6c7a5dc
HB		 4083 /*
4084 * Profile KVM exit RIPs:
4085 */
4086 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4087 unsigned long rip = kvm_rip_read(vcpu);
4088 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4089 }
4090
298101da 4091
b93463aa
AK		 4092 kvm_lapic_sync_from_vapic(vcpu);
4093
851ba692 4094 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4095out:
4096 return r;
4097}
b6c7a5dc 4098
09cec754 4099
851ba692 4100static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4101{
4102 int r;
4103
4104 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4105 pr_debug("vcpu %d received sipi with vector # %x\n",
4106 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4107 kvm_lapic_reset(vcpu);
5f179287 4108 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4109 if (r)
4110 return r;
4111 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4112 }
4113
d7690175
MT		 4114 down_read(&vcpu->kvm->slots_lock);
4115 vapic_enter(vcpu);
4116
4117 r = 1;
4118 while (r > 0) {
af2152f5 4119 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4120 r = vcpu_enter_guest(vcpu);
d7690175
MT		 4121 else {
4122 up_read(&vcpu->kvm->slots_lock);
4123 kvm_vcpu_block(vcpu);
4124 down_read(&vcpu->kvm->slots_lock);
4125 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4126 {
4127 switch(vcpu->arch.mp_state) {
4128 case KVM_MP_STATE_HALTED:
d7690175 4129 vcpu->arch.mp_state =
09cec754
GN		 4130 KVM_MP_STATE_RUNNABLE;
4131 case KVM_MP_STATE_RUNNABLE:
4132 break;
4133 case KVM_MP_STATE_SIPI_RECEIVED:
4134 default:
4135 r = -EINTR;
4136 break;
4137 }
4138 }
d7690175
MT		 4139 }
4140
09cec754
GN		 4141 if (r <= 0)
4142 break;
4143
4144 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4145 if (kvm_cpu_has_pending_timer(vcpu))
4146 kvm_inject_pending_timer_irqs(vcpu);
4147
851ba692 4148 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4149 r = -EINTR;
851ba692 4150 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4151 ++vcpu->stat.request_irq_exits;
4152 }
4153 if (signal_pending(current)) {
4154 r = -EINTR;
851ba692 4155 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4156 ++vcpu->stat.signal_exits;
4157 }
4158 if (need_resched()) {
4159 up_read(&vcpu->kvm->slots_lock);
4160 kvm_resched(vcpu);
4161 down_read(&vcpu->kvm->slots_lock);
d7690175 4162 }
b6c7a5dc
HB		 4163 }
4164
d7690175 4165 up_read(&vcpu->kvm->slots_lock);
851ba692 4166 post_kvm_run_save(vcpu);
b6c7a5dc 4167
b93463aa
AK		 4168 vapic_exit(vcpu);
4169
b6c7a5dc
HB		 4170 return r;
4171}
4172
4173int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4174{
4175 int r;
4176 sigset_t sigsaved;
4177
4178 vcpu_load(vcpu);
4179
ac9f6dc0
AK		 4180 if (vcpu->sigset_active)
4181 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4182
a4535290 4183 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4184 kvm_vcpu_block(vcpu);
d7690175 4185 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4186 r = -EAGAIN;
4187 goto out;
b6c7a5dc
HB		 4188 }
4189
b6c7a5dc
HB		 4190 /* re-sync apic's tpr */
4191 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4192 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4193
ad312c7c 4194 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4195 r = complete_pio(vcpu);
4196 if (r)
4197 goto out;
4198 }
b6c7a5dc
HB		 4199 if (vcpu->mmio_needed) {
4200 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4201 vcpu->mmio_read_completed = 1;
4202 vcpu->mmio_needed = 0;
3200f405
MT		 4203
4204 down_read(&vcpu->kvm->slots_lock);
851ba692 4205 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4206 EMULTYPE_NO_DECODE);
3200f405 4207 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 4208 if (r == EMULATE_DO_MMIO) {
4209 /*
4210 * Read-modify-write. Back to userspace.
4211 */
4212 r = 0;
4213 goto out;
4214 }
4215 }
5fdbf976
MT		 4216 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4217 kvm_register_write(vcpu, VCPU_REGS_RAX,
4218 kvm_run->hypercall.ret);
b6c7a5dc 4219
851ba692 4220 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4221
4222out:
4223 if (vcpu->sigset_active)
4224 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4225
4226 vcpu_put(vcpu);
4227 return r;
4228}
4229
4230int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4231{
4232 vcpu_load(vcpu);
4233
5fdbf976
MT		 4234 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4235 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4236 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4237 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4238 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4239 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4240 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4241 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4242#ifdef CONFIG_X86_64
5fdbf976
MT		 4243 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4244 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4245 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4246 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4247 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4248 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4249 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4250 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4251#endif
4252
5fdbf976 4253 regs->rip = kvm_rip_read(vcpu);
91586a3b 4254 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4255
4256 vcpu_put(vcpu);
4257
4258 return 0;
4259}
4260
4261int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4262{
4263 vcpu_load(vcpu);
4264
5fdbf976
MT		 4265 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4266 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4267 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4268 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4269 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4270 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4271 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4272 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4273#ifdef CONFIG_X86_64
5fdbf976
MT		 4274 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4275 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4276 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4277 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4278 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4279 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4280 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4281 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4282#endif
4283
5fdbf976 4284 kvm_rip_write(vcpu, regs->rip);
91586a3b 4285 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4286
b4f14abd
JK		 4287 vcpu->arch.exception.pending = false;
4288
b6c7a5dc
HB		 4289 vcpu_put(vcpu);
4290
4291 return 0;
4292}
4293
3e6e0aab
GT		 4294void kvm_get_segment(struct kvm_vcpu *vcpu,
4295 struct kvm_segment *var, int seg)
b6c7a5dc 4296{
14af3f3c 4297 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4298}
4299
4300void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4301{
4302 struct kvm_segment cs;
4303
3e6e0aab 4304 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4305 *db = cs.db;
4306 *l = cs.l;
4307}
4308EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4309
4310int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4311 struct kvm_sregs *sregs)
4312{
4313 struct descriptor_table dt;
b6c7a5dc
HB		 4314
4315 vcpu_load(vcpu);
4316
3e6e0aab
GT		 4317 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4318 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4319 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4320 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4321 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4322 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4323
3e6e0aab
GT		 4324 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4325 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4326
4327 kvm_x86_ops->get_idt(vcpu, &dt);
4328 sregs->idt.limit = dt.limit;
4329 sregs->idt.base = dt.base;
4330 kvm_x86_ops->get_gdt(vcpu, &dt);
4331 sregs->gdt.limit = dt.limit;
4332 sregs->gdt.base = dt.base;
4333
ad312c7c
ZX		 4334 sregs->cr0 = vcpu->arch.cr0;
4335 sregs->cr2 = vcpu->arch.cr2;
4336 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4337 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4338 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4339 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4340 sregs->apic_base = kvm_get_apic_base(vcpu);
4341
923c61bb 4342 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4343
36752c9b 4344 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4345 set_bit(vcpu->arch.interrupt.nr,
4346 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4347
b6c7a5dc
HB		 4348 vcpu_put(vcpu);
4349
4350 return 0;
4351}
4352
62d9f0db
MT		 4353int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4354 struct kvm_mp_state *mp_state)
4355{
4356 vcpu_load(vcpu);
4357 mp_state->mp_state = vcpu->arch.mp_state;
4358 vcpu_put(vcpu);
4359 return 0;
4360}
4361
4362int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4363 struct kvm_mp_state *mp_state)
4364{
4365 vcpu_load(vcpu);
4366 vcpu->arch.mp_state = mp_state->mp_state;
4367 vcpu_put(vcpu);
4368 return 0;
4369}
4370
3e6e0aab 4371static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4372 struct kvm_segment *var, int seg)
4373{
14af3f3c 4374 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4375}
4376
37817f29
IE		 4377static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4378 struct kvm_segment *kvm_desct)
4379{
46a359e7
AM		 4380 kvm_desct->base = get_desc_base(seg_desc);
4381 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4382 if (seg_desc->g) {
4383 kvm_desct->limit <<= 12;
4384 kvm_desct->limit |= 0xfff;
4385 }
37817f29
IE		 4386 kvm_desct->selector = selector;
4387 kvm_desct->type = seg_desc->type;
4388 kvm_desct->present = seg_desc->p;
4389 kvm_desct->dpl = seg_desc->dpl;
4390 kvm_desct->db = seg_desc->d;
4391 kvm_desct->s = seg_desc->s;
4392 kvm_desct->l = seg_desc->l;
4393 kvm_desct->g = seg_desc->g;
4394 kvm_desct->avl = seg_desc->avl;
4395 if (!selector)
4396 kvm_desct->unusable = 1;
4397 else
4398 kvm_desct->unusable = 0;
4399 kvm_desct->padding = 0;
4400}
4401
b8222ad2
AS		 4402static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4403 u16 selector,
4404 struct descriptor_table *dtable)
37817f29
IE		 4405{
4406 if (selector & 1 << 2) {
4407 struct kvm_segment kvm_seg;
4408
3e6e0aab 4409 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4410
4411 if (kvm_seg.unusable)
4412 dtable->limit = 0;
4413 else
4414 dtable->limit = kvm_seg.limit;
4415 dtable->base = kvm_seg.base;
4416 }
4417 else
4418 kvm_x86_ops->get_gdt(vcpu, dtable);
4419}
4420
4421/* allowed just for 8 bytes segments */
4422static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4423 struct desc_struct *seg_desc)
4424{
4425 struct descriptor_table dtable;
4426 u16 index = selector >> 3;
4427
b8222ad2 4428 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4429
4430 if (dtable.limit < index * 8 + 7) {
4431 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4432 return 1;
4433 }
d9048d32 4434 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4435}
4436
4437/* allowed just for 8 bytes segments */
4438static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4439 struct desc_struct *seg_desc)
4440{
4441 struct descriptor_table dtable;
4442 u16 index = selector >> 3;
4443
b8222ad2 4444 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4445
4446 if (dtable.limit < index * 8 + 7)
4447 return 1;
d9048d32 4448 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4449}
4450
abb39119 4451static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4452 struct desc_struct *seg_desc)
4453{
46a359e7 4454 u32 base_addr = get_desc_base(seg_desc);
37817f29 4455
98899aa0 4456 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4457}
4458
37817f29
IE		 4459static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4460{
4461 struct kvm_segment kvm_seg;
4462
3e6e0aab 4463 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4464 return kvm_seg.selector;
4465}
4466
4467static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4468 u16 selector,
4469 struct kvm_segment *kvm_seg)
4470{
4471 struct desc_struct seg_desc;
4472
4473 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4474 return 1;
4475 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4476 return 0;
4477}
4478
2259e3a7 4479static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4480{
4481 struct kvm_segment segvar = {
4482 .base = selector << 4,
4483 .limit = 0xffff,
4484 .selector = selector,
4485 .type = 3,
4486 .present = 1,
4487 .dpl = 3,
4488 .db = 0,
4489 .s = 1,
4490 .l = 0,
4491 .g = 0,
4492 .avl = 0,
4493 .unusable = 0,
4494 };
4495 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4496 return 0;
4497}
4498
c0c7c04b
AL		 4499static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4500{
4501 return (seg != VCPU_SREG_LDTR) &&
4502 (seg != VCPU_SREG_TR) &&
91586a3b 4503 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4504}
4505
cb84b55f
MT		 4506static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4507 u16 selector)
4508{
4509 /* NULL selector is not valid for CS and SS */
4510 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4511 if (!selector)
4512 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4513}
4514
3e6e0aab
GT		 4515int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4516 int type_bits, int seg)
37817f29
IE		 4517{
4518 struct kvm_segment kvm_seg;
4519
c0c7c04b 4520 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4521 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4522 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4523 return 1;
cb84b55f
MT		 4524
4525 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4526 kvm_seg.type |= type_bits;
4527
4528 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4529 seg != VCPU_SREG_LDTR)
4530 if (!kvm_seg.s)
4531 kvm_seg.unusable = 1;
4532
3e6e0aab 4533 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4534 return 0;
4535}
4536
4537static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4538 struct tss_segment_32 *tss)
4539{
4540 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4541 tss->eip = kvm_rip_read(vcpu);
91586a3b 4542 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4543 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4544 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4545 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4546 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4547 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4548 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4549 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4550 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4551 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4552 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4553 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4554 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4555 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4556 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4557 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4558}
4559
4560static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4561 struct tss_segment_32 *tss)
4562{
4563 kvm_set_cr3(vcpu, tss->cr3);
4564
5fdbf976 4565 kvm_rip_write(vcpu, tss->eip);
91586a3b 4566 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4567
5fdbf976
MT		 4568 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4569 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4570 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4571 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4572 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4573 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4574 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4575 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4576
3e6e0aab 4577 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4578 return 1;
4579
3e6e0aab 4580 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4581 return 1;
4582
3e6e0aab 4583 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4584 return 1;
4585
3e6e0aab 4586 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4587 return 1;
4588
3e6e0aab 4589 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4590 return 1;
4591
3e6e0aab 4592 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4593 return 1;
4594
3e6e0aab 4595 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4596 return 1;
4597 return 0;
4598}
4599
4600static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4601 struct tss_segment_16 *tss)
4602{
5fdbf976 4603 tss->ip = kvm_rip_read(vcpu);
91586a3b 4604 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4605 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4606 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4607 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4608 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4609 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4610 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4611 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4612 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4613
4614 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4615 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4616 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4617 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4618 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4619}
4620
4621static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4622 struct tss_segment_16 *tss)
4623{
5fdbf976 4624 kvm_rip_write(vcpu, tss->ip);
91586a3b 4625 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4626 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4627 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4628 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4629 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4630 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4631 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4632 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4633 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4634
3e6e0aab 4635 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4636 return 1;
4637
3e6e0aab 4638 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4639 return 1;
4640
3e6e0aab 4641 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4642 return 1;
4643
3e6e0aab 4644 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4645 return 1;
4646
3e6e0aab 4647 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4648 return 1;
4649 return 0;
4650}
4651
8b2cf73c 4652static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4653 u16 old_tss_sel, u32 old_tss_base,
4654 struct desc_struct *nseg_desc)
37817f29
IE		 4655{
4656 struct tss_segment_16 tss_segment_16;
4657 int ret = 0;
4658
34198bf8
MT		 4659 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4660 sizeof tss_segment_16))
37817f29
IE		 4661 goto out;
4662
4663 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4664
34198bf8
MT		 4665 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4666 sizeof tss_segment_16))
37817f29 4667 goto out;
34198bf8
MT		 4668
4669 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4670 &tss_segment_16, sizeof tss_segment_16))
4671 goto out;
4672
b237ac37
GN		 4673 if (old_tss_sel != 0xffff) {
4674 tss_segment_16.prev_task_link = old_tss_sel;
4675
4676 if (kvm_write_guest(vcpu->kvm,
4677 get_tss_base_addr(vcpu, nseg_desc),
4678 &tss_segment_16.prev_task_link,
4679 sizeof tss_segment_16.prev_task_link))
4680 goto out;
4681 }
4682
37817f29
IE		 4683 if (load_state_from_tss16(vcpu, &tss_segment_16))
4684 goto out;
4685
4686 ret = 1;
4687out:
4688 return ret;
4689}
4690
8b2cf73c 4691static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4692 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4693 struct desc_struct *nseg_desc)
4694{
4695 struct tss_segment_32 tss_segment_32;
4696 int ret = 0;
4697
34198bf8
MT		 4698 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4699 sizeof tss_segment_32))
37817f29
IE		 4700 goto out;
4701
4702 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4703
34198bf8
MT		 4704 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4705 sizeof tss_segment_32))
4706 goto out;
4707
4708 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4709 &tss_segment_32, sizeof tss_segment_32))
37817f29 4710 goto out;
34198bf8 4711
b237ac37
GN		 4712 if (old_tss_sel != 0xffff) {
4713 tss_segment_32.prev_task_link = old_tss_sel;
4714
4715 if (kvm_write_guest(vcpu->kvm,
4716 get_tss_base_addr(vcpu, nseg_desc),
4717 &tss_segment_32.prev_task_link,
4718 sizeof tss_segment_32.prev_task_link))
4719 goto out;
4720 }
4721
37817f29
IE		 4722 if (load_state_from_tss32(vcpu, &tss_segment_32))
4723 goto out;
4724
4725 ret = 1;
4726out:
4727 return ret;
4728}
4729
4730int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4731{
4732 struct kvm_segment tr_seg;
4733 struct desc_struct cseg_desc;
4734 struct desc_struct nseg_desc;
4735 int ret = 0;
34198bf8
MT		 4736 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4737 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4738
34198bf8 4739 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4740
34198bf8
MT		 4741 /* FIXME: Handle errors. Failure to read either TSS or their
4742 * descriptors should generate a pagefault.
4743 */
37817f29
IE		 4744 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4745 goto out;
4746
34198bf8 4747 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4748 goto out;
4749
37817f29
IE		 4750 if (reason != TASK_SWITCH_IRET) {
4751 int cpl;
4752
4753 cpl = kvm_x86_ops->get_cpl(vcpu);
4754 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4755 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4756 return 1;
4757 }
4758 }
4759
46a359e7 4760 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4761 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4762 return 1;
4763 }
4764
4765 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4766 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4767 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4768 }
4769
4770 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4771 u32 eflags = kvm_get_rflags(vcpu);
4772 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4773 }
4774
b237ac37
GN		 4775 /* set back link to prev task only if NT bit is set in eflags
4776 note that old_tss_sel is not used afetr this point */
4777 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4778 old_tss_sel = 0xffff;
4779
37817f29 4780 if (nseg_desc.type & 8)
b237ac37
GN		 4781 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4782 old_tss_base, &nseg_desc);
37817f29 4783 else
b237ac37
GN		 4784 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4785 old_tss_base, &nseg_desc);
37817f29
IE		 4786
4787 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4788 u32 eflags = kvm_get_rflags(vcpu);
4789 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4790 }
4791
4792 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4793 nseg_desc.type |= (1 << 1);
37817f29
IE		 4794 save_guest_segment_descriptor(vcpu, tss_selector,
4795 &nseg_desc);
4796 }
4797
4798 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4799 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4800 tr_seg.type = 11;
3e6e0aab 4801 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4802out:
37817f29
IE		 4803 return ret;
4804}
4805EXPORT_SYMBOL_GPL(kvm_task_switch);
4806
b6c7a5dc
HB		 4807int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4808 struct kvm_sregs *sregs)
4809{
4810 int mmu_reset_needed = 0;
923c61bb 4811 int pending_vec, max_bits;
b6c7a5dc
HB		 4812 struct descriptor_table dt;
4813
4814 vcpu_load(vcpu);
4815
4816 dt.limit = sregs->idt.limit;
4817 dt.base = sregs->idt.base;
4818 kvm_x86_ops->set_idt(vcpu, &dt);
4819 dt.limit = sregs->gdt.limit;
4820 dt.base = sregs->gdt.base;
4821 kvm_x86_ops->set_gdt(vcpu, &dt);
4822
ad312c7c
ZX		 4823 vcpu->arch.cr2 = sregs->cr2;
4824 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4825 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4826
2d3ad1f4 4827 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4828
ad312c7c 4829 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4830 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4831 kvm_set_apic_base(vcpu, sregs->apic_base);
4832
ad312c7c 4833 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4834 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4835 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4836
fc78f519 4837 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4838 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4839 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4840 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4841 mmu_reset_needed = 1;
4842 }
b6c7a5dc
HB		 4843
4844 if (mmu_reset_needed)
4845 kvm_mmu_reset_context(vcpu);
4846
923c61bb
GN		 4847 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4848 pending_vec = find_first_bit(
4849 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4850 if (pending_vec < max_bits) {
66fd3f7f 4851 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4852 pr_debug("Set back pending irq %d\n", pending_vec);
4853 if (irqchip_in_kernel(vcpu->kvm))
4854 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4855 }
4856
3e6e0aab
GT		 4857 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4858 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4859 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4860 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4861 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4862 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4863
3e6e0aab
GT		 4864 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4865 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4866
5f0269f5
ME		 4867 update_cr8_intercept(vcpu);
4868
9c3e4aab 4869 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4870 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4871 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4872 !(vcpu->arch.cr0 & X86_CR0_PE))
4873 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4874
b6c7a5dc
HB		 4875 vcpu_put(vcpu);
4876
4877 return 0;
4878}
4879
d0bfb940
JK		 4880int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4881 struct kvm_guest_debug *dbg)
b6c7a5dc 4882{
355be0b9 4883 unsigned long rflags;
ae675ef0 4884 int i, r;
b6c7a5dc
HB		 4885
4886 vcpu_load(vcpu);
4887
4f926bf2
JK		 4888 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4889 r = -EBUSY;
4890 if (vcpu->arch.exception.pending)
4891 goto unlock_out;
4892 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4893 kvm_queue_exception(vcpu, DB_VECTOR);
4894 else
4895 kvm_queue_exception(vcpu, BP_VECTOR);
4896 }
4897
91586a3b
JK		 4898 /*
4899 * Read rflags as long as potentially injected trace flags are still
4900 * filtered out.
4901 */
4902 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4903
4904 vcpu->guest_debug = dbg->control;
4905 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4906 vcpu->guest_debug = 0;
4907
4908 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4909 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4910 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4911 vcpu->arch.switch_db_regs =
4912 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4913 } else {
4914 for (i = 0; i < KVM_NR_DB_REGS; i++)
4915 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4916 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4917 }
4918
94fe45da
JK		 4919 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4920 vcpu->arch.singlestep_cs =
4921 get_segment_selector(vcpu, VCPU_SREG_CS);
4922 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4923 }
4924
91586a3b
JK		 4925 /*
4926 * Trigger an rflags update that will inject or remove the trace
4927 * flags.
4928 */
4929 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4930
355be0b9 4931 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4932
4f926bf2 4933 r = 0;
d0bfb940 4934
4f926bf2 4935unlock_out:
b6c7a5dc
HB		 4936 vcpu_put(vcpu);
4937
4938 return r;
4939}
4940
d0752060
HB		 4941/*
4942 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4943 * we have asm/x86/processor.h
4944 */
4945struct fxsave {
4946 u16 cwd;
4947 u16 swd;
4948 u16 twd;
4949 u16 fop;
4950 u64 rip;
4951 u64 rdp;
4952 u32 mxcsr;
4953 u32 mxcsr_mask;
4954 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4955#ifdef CONFIG_X86_64
4956 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4957#else
4958 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4959#endif
4960};
4961
8b006791
ZX		 4962/*
4963 * Translate a guest virtual address to a guest physical address.
4964 */
4965int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4966 struct kvm_translation *tr)
4967{
4968 unsigned long vaddr = tr->linear_address;
4969 gpa_t gpa;
4970
4971 vcpu_load(vcpu);
72dc67a6 4972 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4973 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4974 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4975 tr->physical_address = gpa;
4976 tr->valid = gpa != UNMAPPED_GVA;
4977 tr->writeable = 1;
4978 tr->usermode = 0;
8b006791
ZX		 4979 vcpu_put(vcpu);
4980
4981 return 0;
4982}
4983
d0752060
HB		 4984int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4985{
ad312c7c 4986 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4987
4988 vcpu_load(vcpu);
4989
4990 memcpy(fpu->fpr, fxsave->st_space, 128);
4991 fpu->fcw = fxsave->cwd;
4992 fpu->fsw = fxsave->swd;
4993 fpu->ftwx = fxsave->twd;
4994 fpu->last_opcode = fxsave->fop;
4995 fpu->last_ip = fxsave->rip;
4996 fpu->last_dp = fxsave->rdp;
4997 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4998
4999 vcpu_put(vcpu);
5000
5001 return 0;
5002}
5003
5004int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5005{
ad312c7c 5006 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5007
5008 vcpu_load(vcpu);
5009
5010 memcpy(fxsave->st_space, fpu->fpr, 128);
5011 fxsave->cwd = fpu->fcw;
5012 fxsave->swd = fpu->fsw;
5013 fxsave->twd = fpu->ftwx;
5014 fxsave->fop = fpu->last_opcode;
5015 fxsave->rip = fpu->last_ip;
5016 fxsave->rdp = fpu->last_dp;
5017 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5018
5019 vcpu_put(vcpu);
5020
5021 return 0;
5022}
5023
5024void fx_init(struct kvm_vcpu *vcpu)
5025{
5026 unsigned after_mxcsr_mask;
5027
bc1a34f1
AA		 5028 /*
5029 * Touch the fpu the first time in non atomic context as if
5030 * this is the first fpu instruction the exception handler
5031 * will fire before the instruction returns and it'll have to
5032 * allocate ram with GFP_KERNEL.
5033 */
5034 if (!used_math())
d6e88aec 5035 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5036
d0752060
HB		 5037 /* Initialize guest FPU by resetting ours and saving into guest's */
5038 preempt_disable();
d6e88aec
AK		 5039 kvm_fx_save(&vcpu->arch.host_fx_image);
5040 kvm_fx_finit();
5041 kvm_fx_save(&vcpu->arch.guest_fx_image);
5042 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5043 preempt_enable();
5044
ad312c7c 5045 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5046 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5047 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5048 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5049 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5050}
5051EXPORT_SYMBOL_GPL(fx_init);
5052
5053void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5054{
5055 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
5056 return;
5057
5058 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5059 kvm_fx_save(&vcpu->arch.host_fx_image);
5060 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 5061}
5062EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
5063
5064void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5065{
5066 if (!vcpu->guest_fpu_loaded)
5067 return;
5068
5069 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5070 kvm_fx_save(&vcpu->arch.guest_fx_image);
5071 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5072 ++vcpu->stat.fpu_reload;
d0752060
HB		 5073}
5074EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 5075
5076void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5077{
7f1ea208
JR		 5078 if (vcpu->arch.time_page) {
5079 kvm_release_page_dirty(vcpu->arch.time_page);
5080 vcpu->arch.time_page = NULL;
5081 }
5082
e9b11c17
ZX		 5083 kvm_x86_ops->vcpu_free(vcpu);
5084}
5085
5086struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5087 unsigned int id)
5088{
26e5215f
AK		 5089 return kvm_x86_ops->vcpu_create(kvm, id);
5090}
e9b11c17 5091
26e5215f
AK		 5092int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5093{
5094 int r;
e9b11c17
ZX		 5095
5096 /* We do fxsave: this must be aligned. */
ad312c7c 5097 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5098
0bed3b56 5099 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5100 vcpu_load(vcpu);
5101 r = kvm_arch_vcpu_reset(vcpu);
5102 if (r == 0)
5103 r = kvm_mmu_setup(vcpu);
5104 vcpu_put(vcpu);
5105 if (r < 0)
5106 goto free_vcpu;
5107
26e5215f 5108 return 0;
e9b11c17
ZX		 5109free_vcpu:
5110 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5111 return r;
e9b11c17
ZX		 5112}
5113
d40ccc62 5114void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5115{
5116 vcpu_load(vcpu);
5117 kvm_mmu_unload(vcpu);
5118 vcpu_put(vcpu);
5119
5120 kvm_x86_ops->vcpu_free(vcpu);
5121}
5122
5123int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5124{
448fa4a9
JK		 5125 vcpu->arch.nmi_pending = false;
5126 vcpu->arch.nmi_injected = false;
5127
42dbaa5a
JK		 5128 vcpu->arch.switch_db_regs = 0;
5129 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5130 vcpu->arch.dr6 = DR6_FIXED_1;
5131 vcpu->arch.dr7 = DR7_FIXED_1;
5132
e9b11c17
ZX		 5133 return kvm_x86_ops->vcpu_reset(vcpu);
5134}
5135
10474ae8 5136int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5137{
0cca7907
ZA		 5138 /*
5139 * Since this may be called from a hotplug notifcation,
5140 * we can't get the CPU frequency directly.
5141 */
5142 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5143 int cpu = raw_smp_processor_id();
5144 per_cpu(cpu_tsc_khz, cpu) = 0;
5145 }
18863bdd
AK		 5146
5147 kvm_shared_msr_cpu_online();
5148
10474ae8 5149 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5150}
5151
5152void kvm_arch_hardware_disable(void *garbage)
5153{
5154 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5155 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5156}
5157
5158int kvm_arch_hardware_setup(void)
5159{
5160 return kvm_x86_ops->hardware_setup();
5161}
5162
5163void kvm_arch_hardware_unsetup(void)
5164{
5165 kvm_x86_ops->hardware_unsetup();
5166}
5167
5168void kvm_arch_check_processor_compat(void *rtn)
5169{
5170 kvm_x86_ops->check_processor_compatibility(rtn);
5171}
5172
5173int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5174{
5175 struct page *page;
5176 struct kvm *kvm;
5177 int r;
5178
5179 BUG_ON(vcpu->kvm == NULL);
5180 kvm = vcpu->kvm;
5181
ad312c7c 5182 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5183 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5184 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5185 else
a4535290 5186 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5187
5188 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5189 if (!page) {
5190 r = -ENOMEM;
5191 goto fail;
5192 }
ad312c7c 5193 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5194
5195 r = kvm_mmu_create(vcpu);
5196 if (r < 0)
5197 goto fail_free_pio_data;
5198
5199 if (irqchip_in_kernel(kvm)) {
5200 r = kvm_create_lapic(vcpu);
5201 if (r < 0)
5202 goto fail_mmu_destroy;
5203 }
5204
890ca9ae
HY		 5205 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5206 GFP_KERNEL);
5207 if (!vcpu->arch.mce_banks) {
5208 r = -ENOMEM;
443c39bc 5209 goto fail_free_lapic;
890ca9ae
HY		 5210 }
5211 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5212
e9b11c17 5213 return 0;
443c39bc
WY		 5214fail_free_lapic:
5215 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5216fail_mmu_destroy:
5217 kvm_mmu_destroy(vcpu);
5218fail_free_pio_data:
ad312c7c 5219 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5220fail:
5221 return r;
5222}
5223
5224void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5225{
36cb93fd 5226 kfree(vcpu->arch.mce_banks);
e9b11c17 5227 kvm_free_lapic(vcpu);
3200f405 5228 down_read(&vcpu->kvm->slots_lock);
e9b11c17 5229 kvm_mmu_destroy(vcpu);
3200f405 5230 up_read(&vcpu->kvm->slots_lock);
ad312c7c 5231 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5232}
d19a9cd2
ZX		 5233
5234struct kvm *kvm_arch_create_vm(void)
5235{
5236 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5237
5238 if (!kvm)
5239 return ERR_PTR(-ENOMEM);
5240
fef9cce0
MT		 5241 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5242 if (!kvm->arch.aliases) {
5243 kfree(kvm);
5244 return ERR_PTR(-ENOMEM);
5245 }
5246
f05e70ac 5247 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5248 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5249
5550af4d
SY		 5250 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5251 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5252
53f658b3
MT		 5253 rdtscll(kvm->arch.vm_init_tsc);
5254
d19a9cd2
ZX		 5255 return kvm;
5256}
5257
5258static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5259{
5260 vcpu_load(vcpu);
5261 kvm_mmu_unload(vcpu);
5262 vcpu_put(vcpu);
5263}
5264
5265static void kvm_free_vcpus(struct kvm *kvm)
5266{
5267 unsigned int i;
988a2cae 5268 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5269
5270 /*
5271 * Unpin any mmu pages first.
5272 */
988a2cae
GN		 5273 kvm_for_each_vcpu(i, vcpu, kvm)
5274 kvm_unload_vcpu_mmu(vcpu);
5275 kvm_for_each_vcpu(i, vcpu, kvm)
5276 kvm_arch_vcpu_free(vcpu);
5277
5278 mutex_lock(&kvm->lock);
5279 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5280 kvm->vcpus[i] = NULL;
d19a9cd2 5281
988a2cae
GN		 5282 atomic_set(&kvm->online_vcpus, 0);
5283 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5284}
5285
ad8ba2cd
SY		 5286void kvm_arch_sync_events(struct kvm *kvm)
5287{
ba4cef31 5288 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5289}
5290
d19a9cd2
ZX		 5291void kvm_arch_destroy_vm(struct kvm *kvm)
5292{
6eb55818 5293 kvm_iommu_unmap_guest(kvm);
7837699f 5294 kvm_free_pit(kvm);
d7deeeb0
ZX		 5295 kfree(kvm->arch.vpic);
5296 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5297 kvm_free_vcpus(kvm);
5298 kvm_free_physmem(kvm);
3d45830c
AK		 5299 if (kvm->arch.apic_access_page)
5300 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5301 if (kvm->arch.ept_identity_pagetable)
5302 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5303 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5304 kfree(kvm);
5305}
0de10343 5306
f7784b8e
MT		 5307int kvm_arch_prepare_memory_region(struct kvm *kvm,
5308 struct kvm_memory_slot *memslot,
0de10343 5309 struct kvm_memory_slot old,
f7784b8e 5310 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5311 int user_alloc)
5312{
f7784b8e 5313 int npages = memslot->npages;
0de10343
ZX		 5314
5315 /*To keep backward compatibility with older userspace,
5316 *x86 needs to hanlde !user_alloc case.
5317 */
5318 if (!user_alloc) {
5319 if (npages && !old.rmap) {
604b38ac
AA		 5320 unsigned long userspace_addr;
5321
72dc67a6 5322 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5323 userspace_addr = do_mmap(NULL, 0,
5324 npages * PAGE_SIZE,
5325 PROT_READ | PROT_WRITE,
acee3c04 5326 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5327 0);
72dc67a6 5328 up_write(&current->mm->mmap_sem);
0de10343 5329
604b38ac
AA		 5330 if (IS_ERR((void *)userspace_addr))
5331 return PTR_ERR((void *)userspace_addr);
5332
604b38ac 5333 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5334 }
5335 }
5336
f7784b8e
MT		 5337
5338 return 0;
5339}
5340
5341void kvm_arch_commit_memory_region(struct kvm *kvm,
5342 struct kvm_userspace_memory_region *mem,
5343 struct kvm_memory_slot old,
5344 int user_alloc)
5345{
5346
5347 int npages = mem->memory_size >> PAGE_SHIFT;
5348
5349 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5350 int ret;
5351
5352 down_write(&current->mm->mmap_sem);
5353 ret = do_munmap(current->mm, old.userspace_addr,
5354 old.npages * PAGE_SIZE);
5355 up_write(&current->mm->mmap_sem);
5356 if (ret < 0)
5357 printk(KERN_WARNING
5358 "kvm_vm_ioctl_set_memory_region: "
5359 "failed to munmap memory\n");
5360 }
5361
7c8a83b7 5362 spin_lock(&kvm->mmu_lock);
f05e70ac 5363 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5364 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5365 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5366 }
5367
5368 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5369 spin_unlock(&kvm->mmu_lock);
0de10343 5370}
1d737c8a 5371
34d4cb8f
MT		 5372void kvm_arch_flush_shadow(struct kvm *kvm)
5373{
5374 kvm_mmu_zap_all(kvm);
8986ecc0 5375 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5376}
5377
1d737c8a
ZX		 5378int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5379{
a4535290 5380 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5381 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5382 || vcpu->arch.nmi_pending ||
5383 (kvm_arch_interrupt_allowed(vcpu) &&
5384 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5385}
5736199a 5386
5736199a
ZX		 5387void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5388{
32f88400
MT		 5389 int me;
5390 int cpu = vcpu->cpu;
5736199a
ZX		 5391
5392 if (waitqueue_active(&vcpu->wq)) {
5393 wake_up_interruptible(&vcpu->wq);
5394 ++vcpu->stat.halt_wakeup;
5395 }
32f88400
MT		 5396
5397 me = get_cpu();
5398 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5399 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5400 smp_send_reschedule(cpu);
e9571ed5 5401 put_cpu();
5736199a 5402}
78646121
GN		 5403
5404int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5405{
5406 return kvm_x86_ops->interrupt_allowed(vcpu);
5407}
229456fc 5408
94fe45da
JK		 5409unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5410{
5411 unsigned long rflags;
5412
5413 rflags = kvm_x86_ops->get_rflags(vcpu);
5414 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5415 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5416 return rflags;
5417}
5418EXPORT_SYMBOL_GPL(kvm_get_rflags);
5419
5420void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5421{
5422 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5423 vcpu->arch.singlestep_cs ==
5424 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5425 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5426 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5427 kvm_x86_ops->set_rflags(vcpu, rflags);
5428}
5429EXPORT_SYMBOL_GPL(kvm_set_rflags);
5430
229456fc
MT		 5431EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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