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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
fe14d5f4 | 95 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
96 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
97 | .type = I915_GGTT_VIEW_ROTATED | |
98 | }; | |
fe14d5f4 | 99 | |
ee0ce478 VS |
100 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
101 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
6f65e29a BW |
149 | static void ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 flags); | |
152 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
153 | ||
07749ef3 MT |
154 | static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
155 | enum i915_cache_level level, | |
156 | bool valid) | |
94ec8f61 | 157 | { |
07749ef3 | 158 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 159 | pte |= addr; |
63c42e56 BW |
160 | |
161 | switch (level) { | |
162 | case I915_CACHE_NONE: | |
fbe5d36e | 163 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
164 | break; |
165 | case I915_CACHE_WT: | |
166 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
167 | break; | |
168 | default: | |
169 | pte |= PPAT_CACHED_INDEX; | |
170 | break; | |
171 | } | |
172 | ||
94ec8f61 BW |
173 | return pte; |
174 | } | |
175 | ||
07749ef3 MT |
176 | static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
177 | dma_addr_t addr, | |
178 | enum i915_cache_level level) | |
b1fe6673 | 179 | { |
07749ef3 | 180 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
181 | pde |= addr; |
182 | if (level != I915_CACHE_NONE) | |
183 | pde |= PPAT_CACHED_PDE_INDEX; | |
184 | else | |
185 | pde |= PPAT_UNCACHED_INDEX; | |
186 | return pde; | |
187 | } | |
188 | ||
07749ef3 MT |
189 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
190 | enum i915_cache_level level, | |
191 | bool valid, u32 unused) | |
54d12527 | 192 | { |
07749ef3 | 193 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 194 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
195 | |
196 | switch (level) { | |
350ec881 CW |
197 | case I915_CACHE_L3_LLC: |
198 | case I915_CACHE_LLC: | |
199 | pte |= GEN6_PTE_CACHE_LLC; | |
200 | break; | |
201 | case I915_CACHE_NONE: | |
202 | pte |= GEN6_PTE_UNCACHED; | |
203 | break; | |
204 | default: | |
5f77eeb0 | 205 | MISSING_CASE(level); |
350ec881 CW |
206 | } |
207 | ||
208 | return pte; | |
209 | } | |
210 | ||
07749ef3 MT |
211 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
212 | enum i915_cache_level level, | |
213 | bool valid, u32 unused) | |
350ec881 | 214 | { |
07749ef3 | 215 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
216 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
217 | ||
218 | switch (level) { | |
219 | case I915_CACHE_L3_LLC: | |
220 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
221 | break; |
222 | case I915_CACHE_LLC: | |
223 | pte |= GEN6_PTE_CACHE_LLC; | |
224 | break; | |
225 | case I915_CACHE_NONE: | |
9119708c | 226 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
227 | break; |
228 | default: | |
5f77eeb0 | 229 | MISSING_CASE(level); |
e7210c3c BW |
230 | } |
231 | ||
54d12527 BW |
232 | return pte; |
233 | } | |
234 | ||
07749ef3 MT |
235 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
236 | enum i915_cache_level level, | |
237 | bool valid, u32 flags) | |
93c34e70 | 238 | { |
07749ef3 | 239 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
240 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
241 | ||
24f3a8cf AG |
242 | if (!(flags & PTE_READ_ONLY)) |
243 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
244 | |
245 | if (level != I915_CACHE_NONE) | |
246 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
247 | ||
248 | return pte; | |
249 | } | |
250 | ||
07749ef3 MT |
251 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
252 | enum i915_cache_level level, | |
253 | bool valid, u32 unused) | |
9119708c | 254 | { |
07749ef3 | 255 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 256 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
257 | |
258 | if (level != I915_CACHE_NONE) | |
87a6b688 | 259 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
260 | |
261 | return pte; | |
262 | } | |
263 | ||
07749ef3 MT |
264 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
265 | enum i915_cache_level level, | |
266 | bool valid, u32 unused) | |
4d15c145 | 267 | { |
07749ef3 | 268 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
269 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
270 | ||
651d794f CW |
271 | switch (level) { |
272 | case I915_CACHE_NONE: | |
273 | break; | |
274 | case I915_CACHE_WT: | |
c51e9701 | 275 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
276 | break; |
277 | default: | |
c51e9701 | 278 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
279 | break; |
280 | } | |
4d15c145 BW |
281 | |
282 | return pte; | |
283 | } | |
284 | ||
678d96fb BW |
285 | #define i915_dma_unmap_single(px, dev) \ |
286 | __i915_dma_unmap_single((px)->daddr, dev) | |
287 | ||
288 | static inline void __i915_dma_unmap_single(dma_addr_t daddr, | |
289 | struct drm_device *dev) | |
290 | { | |
291 | struct device *device = &dev->pdev->dev; | |
292 | ||
293 | dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
294 | } | |
295 | ||
296 | /** | |
297 | * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. | |
298 | * @px: Page table/dir/etc to get a DMA map for | |
299 | * @dev: drm device | |
300 | * | |
301 | * Page table allocations are unified across all gens. They always require a | |
302 | * single 4k allocation, as well as a DMA mapping. If we keep the structs | |
303 | * symmetric here, the simple macro covers us for every page table type. | |
304 | * | |
305 | * Return: 0 if success. | |
306 | */ | |
307 | #define i915_dma_map_single(px, dev) \ | |
308 | i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) | |
309 | ||
310 | static inline int i915_dma_map_page_single(struct page *page, | |
311 | struct drm_device *dev, | |
312 | dma_addr_t *daddr) | |
313 | { | |
314 | struct device *device = &dev->pdev->dev; | |
315 | ||
316 | *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
1266cdb1 MT |
317 | if (dma_mapping_error(device, *daddr)) |
318 | return -ENOMEM; | |
319 | ||
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
ec565b3c | 323 | static void unmap_and_free_pt(struct i915_page_table *pt, |
678d96fb | 324 | struct drm_device *dev) |
06fda602 BW |
325 | { |
326 | if (WARN_ON(!pt->page)) | |
327 | return; | |
678d96fb BW |
328 | |
329 | i915_dma_unmap_single(pt, dev); | |
06fda602 | 330 | __free_page(pt->page); |
678d96fb | 331 | kfree(pt->used_ptes); |
06fda602 BW |
332 | kfree(pt); |
333 | } | |
334 | ||
5a8e9943 | 335 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 336 | struct i915_page_table *pt) |
5a8e9943 MT |
337 | { |
338 | gen8_pte_t *pt_vaddr, scratch_pte; | |
339 | int i; | |
340 | ||
341 | pt_vaddr = kmap_atomic(pt->page); | |
342 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
343 | I915_CACHE_LLC, true); | |
344 | ||
345 | for (i = 0; i < GEN8_PTES; i++) | |
346 | pt_vaddr[i] = scratch_pte; | |
347 | ||
348 | if (!HAS_LLC(vm->dev)) | |
349 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
350 | kunmap_atomic(pt_vaddr); | |
351 | } | |
352 | ||
ec565b3c | 353 | static struct i915_page_table *alloc_pt_single(struct drm_device *dev) |
06fda602 | 354 | { |
ec565b3c | 355 | struct i915_page_table *pt; |
678d96fb BW |
356 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
357 | GEN8_PTES : GEN6_PTES; | |
358 | int ret = -ENOMEM; | |
06fda602 BW |
359 | |
360 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
361 | if (!pt) | |
362 | return ERR_PTR(-ENOMEM); | |
363 | ||
678d96fb BW |
364 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
365 | GFP_KERNEL); | |
366 | ||
367 | if (!pt->used_ptes) | |
368 | goto fail_bitmap; | |
369 | ||
4933d519 | 370 | pt->page = alloc_page(GFP_KERNEL); |
678d96fb BW |
371 | if (!pt->page) |
372 | goto fail_page; | |
373 | ||
374 | ret = i915_dma_map_single(pt, dev); | |
375 | if (ret) | |
376 | goto fail_dma; | |
06fda602 BW |
377 | |
378 | return pt; | |
678d96fb BW |
379 | |
380 | fail_dma: | |
381 | __free_page(pt->page); | |
382 | fail_page: | |
383 | kfree(pt->used_ptes); | |
384 | fail_bitmap: | |
385 | kfree(pt); | |
386 | ||
387 | return ERR_PTR(ret); | |
06fda602 BW |
388 | } |
389 | ||
390 | /** | |
391 | * alloc_pt_range() - Allocate a multiple page tables | |
392 | * @pd: The page directory which will have at least @count entries | |
393 | * available to point to the allocated page tables. | |
394 | * @pde: First page directory entry for which we are allocating. | |
395 | * @count: Number of pages to allocate. | |
719cd21c | 396 | * @dev: DRM device. |
06fda602 BW |
397 | * |
398 | * Allocates multiple page table pages and sets the appropriate entries in the | |
399 | * page table structure within the page directory. Function cleans up after | |
400 | * itself on any failures. | |
401 | * | |
402 | * Return: 0 if allocation succeeded. | |
403 | */ | |
ec565b3c | 404 | static int alloc_pt_range(struct i915_page_directory *pd, uint16_t pde, size_t count, |
4933d519 | 405 | struct drm_device *dev) |
06fda602 BW |
406 | { |
407 | int i, ret; | |
408 | ||
409 | /* 512 is the max page tables per page_directory on any platform. */ | |
07749ef3 | 410 | if (WARN_ON(pde + count > I915_PDES)) |
06fda602 BW |
411 | return -EINVAL; |
412 | ||
413 | for (i = pde; i < pde + count; i++) { | |
ec565b3c | 414 | struct i915_page_table *pt = alloc_pt_single(dev); |
06fda602 BW |
415 | |
416 | if (IS_ERR(pt)) { | |
417 | ret = PTR_ERR(pt); | |
418 | goto err_out; | |
419 | } | |
420 | WARN(pd->page_table[i], | |
686135da | 421 | "Leaking page directory entry %d (%p)\n", |
06fda602 BW |
422 | i, pd->page_table[i]); |
423 | pd->page_table[i] = pt; | |
424 | } | |
425 | ||
426 | return 0; | |
427 | ||
428 | err_out: | |
429 | while (i-- > pde) | |
06dc68d6 | 430 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
431 | return ret; |
432 | } | |
433 | ||
e5815a2e MT |
434 | static void unmap_and_free_pd(struct i915_page_directory *pd, |
435 | struct drm_device *dev) | |
06fda602 BW |
436 | { |
437 | if (pd->page) { | |
e5815a2e | 438 | i915_dma_unmap_single(pd, dev); |
06fda602 BW |
439 | __free_page(pd->page); |
440 | kfree(pd); | |
441 | } | |
442 | } | |
443 | ||
e5815a2e | 444 | static struct i915_page_directory *alloc_pd_single(struct drm_device *dev) |
06fda602 | 445 | { |
ec565b3c | 446 | struct i915_page_directory *pd; |
e5815a2e | 447 | int ret; |
06fda602 BW |
448 | |
449 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
450 | if (!pd) | |
451 | return ERR_PTR(-ENOMEM); | |
452 | ||
5a8e9943 | 453 | pd->page = alloc_page(GFP_KERNEL); |
06fda602 BW |
454 | if (!pd->page) { |
455 | kfree(pd); | |
456 | return ERR_PTR(-ENOMEM); | |
457 | } | |
458 | ||
e5815a2e MT |
459 | ret = i915_dma_map_single(pd, dev); |
460 | if (ret) { | |
461 | __free_page(pd->page); | |
462 | kfree(pd); | |
463 | return ERR_PTR(ret); | |
464 | } | |
465 | ||
06fda602 BW |
466 | return pd; |
467 | } | |
468 | ||
94e409c1 | 469 | /* Broadwell Page Directory Pointer Descriptors */ |
7cb6d7ac MT |
470 | static int gen8_write_pdp(struct intel_engine_cs *ring, |
471 | unsigned entry, | |
472 | dma_addr_t addr) | |
94e409c1 BW |
473 | { |
474 | int ret; | |
475 | ||
476 | BUG_ON(entry >= 4); | |
477 | ||
478 | ret = intel_ring_begin(ring, 6); | |
479 | if (ret) | |
480 | return ret; | |
481 | ||
482 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
483 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 484 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
485 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
486 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 487 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
488 | intel_ring_advance(ring); |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
eeb9488e | 493 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 494 | struct intel_engine_cs *ring) |
94e409c1 | 495 | { |
eeb9488e | 496 | int i, ret; |
94e409c1 | 497 | |
7cb6d7ac MT |
498 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
499 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; | |
500 | dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr; | |
501 | /* The page directory might be NULL, but we need to clear out | |
502 | * whatever the previous context might have used. */ | |
503 | ret = gen8_write_pdp(ring, i, pd_daddr); | |
eeb9488e BW |
504 | if (ret) |
505 | return ret; | |
94e409c1 | 506 | } |
d595bd4b | 507 | |
eeb9488e | 508 | return 0; |
94e409c1 BW |
509 | } |
510 | ||
459108b8 | 511 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
512 | uint64_t start, |
513 | uint64_t length, | |
459108b8 BW |
514 | bool use_scratch) |
515 | { | |
516 | struct i915_hw_ppgtt *ppgtt = | |
517 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 518 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
519 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
520 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
521 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 522 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
523 | unsigned last_pte, i; |
524 | ||
525 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
526 | I915_CACHE_LLC, use_scratch); | |
527 | ||
528 | while (num_entries) { | |
ec565b3c MT |
529 | struct i915_page_directory *pd; |
530 | struct i915_page_table *pt; | |
06fda602 BW |
531 | struct page *page_table; |
532 | ||
533 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
534 | continue; | |
535 | ||
536 | pd = ppgtt->pdp.page_directory[pdpe]; | |
537 | ||
538 | if (WARN_ON(!pd->page_table[pde])) | |
539 | continue; | |
540 | ||
541 | pt = pd->page_table[pde]; | |
542 | ||
543 | if (WARN_ON(!pt->page)) | |
544 | continue; | |
545 | ||
546 | page_table = pt->page; | |
459108b8 | 547 | |
7ad47cf2 | 548 | last_pte = pte + num_entries; |
07749ef3 MT |
549 | if (last_pte > GEN8_PTES) |
550 | last_pte = GEN8_PTES; | |
459108b8 BW |
551 | |
552 | pt_vaddr = kmap_atomic(page_table); | |
553 | ||
7ad47cf2 | 554 | for (i = pte; i < last_pte; i++) { |
459108b8 | 555 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
556 | num_entries--; |
557 | } | |
459108b8 | 558 | |
fd1ab8f4 RB |
559 | if (!HAS_LLC(ppgtt->base.dev)) |
560 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
561 | kunmap_atomic(pt_vaddr); |
562 | ||
7ad47cf2 | 563 | pte = 0; |
07749ef3 | 564 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
565 | pdpe++; |
566 | pde = 0; | |
567 | } | |
459108b8 BW |
568 | } |
569 | } | |
570 | ||
9df15b49 BW |
571 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
572 | struct sg_table *pages, | |
782f1495 | 573 | uint64_t start, |
24f3a8cf | 574 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
575 | { |
576 | struct i915_hw_ppgtt *ppgtt = | |
577 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 578 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
579 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
580 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
581 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
582 | struct sg_page_iter sg_iter; |
583 | ||
6f1cc993 | 584 | pt_vaddr = NULL; |
7ad47cf2 | 585 | |
9df15b49 | 586 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 587 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
588 | break; |
589 | ||
d7b3de91 | 590 | if (pt_vaddr == NULL) { |
ec565b3c MT |
591 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
592 | struct i915_page_table *pt = pd->page_table[pde]; | |
06fda602 | 593 | struct page *page_table = pt->page; |
d7b3de91 BW |
594 | |
595 | pt_vaddr = kmap_atomic(page_table); | |
596 | } | |
9df15b49 | 597 | |
7ad47cf2 | 598 | pt_vaddr[pte] = |
6f1cc993 CW |
599 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
600 | cache_level, true); | |
07749ef3 | 601 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
602 | if (!HAS_LLC(ppgtt->base.dev)) |
603 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 604 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 605 | pt_vaddr = NULL; |
07749ef3 | 606 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
607 | pdpe++; |
608 | pde = 0; | |
609 | } | |
610 | pte = 0; | |
9df15b49 BW |
611 | } |
612 | } | |
fd1ab8f4 RB |
613 | if (pt_vaddr) { |
614 | if (!HAS_LLC(ppgtt->base.dev)) | |
615 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 616 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 617 | } |
9df15b49 BW |
618 | } |
619 | ||
69876bed MT |
620 | static void __gen8_do_map_pt(gen8_pde_t * const pde, |
621 | struct i915_page_table *pt, | |
622 | struct drm_device *dev) | |
623 | { | |
624 | gen8_pde_t entry = | |
625 | gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC); | |
626 | *pde = entry; | |
627 | } | |
628 | ||
629 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
630 | struct i915_page_directory *pd) | |
631 | { | |
632 | struct i915_hw_ppgtt *ppgtt = | |
633 | container_of(vm, struct i915_hw_ppgtt, base); | |
634 | gen8_pde_t *page_directory; | |
635 | struct i915_page_table *pt; | |
636 | int i; | |
637 | ||
638 | page_directory = kmap_atomic(pd->page); | |
639 | pt = ppgtt->scratch_pt; | |
640 | for (i = 0; i < I915_PDES; i++) | |
641 | /* Map the PDE to the page table */ | |
642 | __gen8_do_map_pt(page_directory + i, pt, vm->dev); | |
643 | ||
644 | if (!HAS_LLC(vm->dev)) | |
645 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
646 | ||
647 | kunmap_atomic(page_directory); | |
648 | } | |
649 | ||
e5815a2e MT |
650 | /* It's likely we'll map more than one pagetable at a time. This function will |
651 | * save us unnecessary kmap calls, but do no more functionally than multiple | |
652 | * calls to map_pt. */ | |
653 | static void gen8_map_pagetable_range(struct i915_page_directory *pd, | |
654 | uint64_t start, | |
655 | uint64_t length, | |
656 | struct drm_device *dev) | |
657 | { | |
658 | gen8_pde_t *page_directory = kmap_atomic(pd->page); | |
659 | struct i915_page_table *pt; | |
660 | uint64_t temp, pde; | |
661 | ||
662 | gen8_for_each_pde(pt, pd, start, length, temp, pde) | |
663 | __gen8_do_map_pt(page_directory + pde, pt, dev); | |
664 | ||
665 | if (!HAS_LLC(dev)) | |
666 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
667 | ||
668 | kunmap_atomic(page_directory); | |
669 | } | |
670 | ||
ec565b3c | 671 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
672 | { |
673 | int i; | |
674 | ||
06fda602 | 675 | if (!pd->page) |
7ad47cf2 BW |
676 | return; |
677 | ||
07749ef3 | 678 | for (i = 0; i < I915_PDES; i++) { |
06fda602 BW |
679 | if (WARN_ON(!pd->page_table[i])) |
680 | continue; | |
7ad47cf2 | 681 | |
06dc68d6 | 682 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
683 | pd->page_table[i] = NULL; |
684 | } | |
d7b3de91 BW |
685 | } |
686 | ||
687 | static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
688 | { |
689 | int i; | |
690 | ||
09942c65 | 691 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
06fda602 BW |
692 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
693 | continue; | |
694 | ||
06dc68d6 | 695 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
e5815a2e | 696 | unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 697 | } |
69876bed | 698 | |
e5815a2e | 699 | unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); |
69876bed | 700 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
b45a6715 BW |
701 | } |
702 | ||
37aca44a BW |
703 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
704 | { | |
705 | struct i915_hw_ppgtt *ppgtt = | |
706 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 707 | |
b45a6715 | 708 | gen8_ppgtt_free(ppgtt); |
37aca44a BW |
709 | } |
710 | ||
e5815a2e MT |
711 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
712 | struct i915_page_directory *pd, | |
5441f0cb | 713 | uint64_t start, |
e5815a2e | 714 | uint64_t length) |
bf2b4ed2 | 715 | { |
e5815a2e | 716 | struct drm_device *dev = ppgtt->base.dev; |
5441f0cb MT |
717 | struct i915_page_table *unused; |
718 | uint64_t temp; | |
719 | uint32_t pde; | |
bf2b4ed2 | 720 | |
5441f0cb MT |
721 | gen8_for_each_pde(unused, pd, start, length, temp, pde) { |
722 | WARN_ON(unused); | |
e5815a2e | 723 | pd->page_table[pde] = alloc_pt_single(dev); |
5441f0cb MT |
724 | if (IS_ERR(pd->page_table[pde])) |
725 | goto unwind_out; | |
726 | ||
e5815a2e | 727 | gen8_initialize_pt(&ppgtt->base, pd->page_table[pde]); |
7ad47cf2 BW |
728 | } |
729 | ||
bf2b4ed2 | 730 | return 0; |
7ad47cf2 BW |
731 | |
732 | unwind_out: | |
5441f0cb | 733 | while (pde--) |
e5815a2e | 734 | unmap_and_free_pt(pd->page_table[pde], dev); |
7ad47cf2 | 735 | |
d7b3de91 | 736 | return -ENOMEM; |
bf2b4ed2 BW |
737 | } |
738 | ||
c488dbba MT |
739 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
740 | struct i915_page_directory_pointer *pdp, | |
69876bed MT |
741 | uint64_t start, |
742 | uint64_t length) | |
bf2b4ed2 | 743 | { |
e5815a2e | 744 | struct drm_device *dev = ppgtt->base.dev; |
69876bed MT |
745 | struct i915_page_directory *unused; |
746 | uint64_t temp; | |
747 | uint32_t pdpe; | |
748 | ||
749 | /* FIXME: PPGTT container_of won't work for 64b */ | |
750 | WARN_ON((start + length) > 0x800000000ULL); | |
751 | ||
752 | gen8_for_each_pdpe(unused, pdp, start, length, temp, pdpe) { | |
753 | WARN_ON(unused); | |
e5815a2e | 754 | pdp->page_directory[pdpe] = alloc_pd_single(dev); |
c488dbba | 755 | if (IS_ERR(pdp->page_directory[pdpe])) |
d7b3de91 | 756 | goto unwind_out; |
69876bed MT |
757 | |
758 | gen8_initialize_pd(&ppgtt->base, | |
09942c65 | 759 | ppgtt->pdp.page_directory[pdpe]); |
d7b3de91 BW |
760 | } |
761 | ||
bf2b4ed2 | 762 | return 0; |
d7b3de91 BW |
763 | |
764 | unwind_out: | |
09942c65 | 765 | while (pdpe--) |
e5815a2e | 766 | unmap_and_free_pd(pdp->page_directory[pdpe], dev); |
d7b3de91 BW |
767 | |
768 | return -ENOMEM; | |
bf2b4ed2 BW |
769 | } |
770 | ||
e5815a2e MT |
771 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
772 | uint64_t start, | |
773 | uint64_t length) | |
bf2b4ed2 | 774 | { |
e5815a2e MT |
775 | struct i915_hw_ppgtt *ppgtt = |
776 | container_of(vm, struct i915_hw_ppgtt, base); | |
5441f0cb MT |
777 | struct i915_page_directory *pd; |
778 | uint64_t temp; | |
779 | uint32_t pdpe; | |
bf2b4ed2 BW |
780 | int ret; |
781 | ||
c488dbba | 782 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length); |
bf2b4ed2 BW |
783 | if (ret) |
784 | return ret; | |
785 | ||
5441f0cb | 786 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
e5815a2e | 787 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length); |
5441f0cb MT |
788 | if (ret) |
789 | goto err_out; | |
5441f0cb MT |
790 | } |
791 | ||
d7b3de91 | 792 | return 0; |
bf2b4ed2 | 793 | |
d7b3de91 BW |
794 | err_out: |
795 | gen8_ppgtt_free(ppgtt); | |
bf2b4ed2 BW |
796 | return ret; |
797 | } | |
798 | ||
eb0b44ad | 799 | /* |
f3a964b9 BW |
800 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
801 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
802 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
803 | * space. | |
37aca44a | 804 | * |
f3a964b9 | 805 | */ |
37aca44a BW |
806 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
807 | { | |
e5815a2e MT |
808 | struct i915_page_directory *pd; |
809 | uint64_t temp, start = 0; | |
810 | const uint64_t orig_length = size; | |
811 | uint32_t pdpe; | |
812 | int ret; | |
37aca44a | 813 | |
69876bed | 814 | ppgtt->base.start = 0; |
5441f0cb | 815 | ppgtt->base.total = size; |
e5815a2e MT |
816 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
817 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
818 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
819 | ppgtt->switch_mm = gen8_mm_switch; | |
69876bed MT |
820 | |
821 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); | |
822 | if (IS_ERR(ppgtt->scratch_pt)) | |
823 | return PTR_ERR(ppgtt->scratch_pt); | |
824 | ||
e5815a2e | 825 | ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev); |
7cb6d7ac MT |
826 | if (IS_ERR(ppgtt->scratch_pd)) |
827 | return PTR_ERR(ppgtt->scratch_pd); | |
828 | ||
69876bed | 829 | gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); |
7cb6d7ac | 830 | gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); |
69876bed | 831 | |
e5815a2e | 832 | ret = gen8_alloc_va_range(&ppgtt->base, start, size); |
7cb6d7ac | 833 | if (ret) { |
e5815a2e | 834 | unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); |
7cb6d7ac | 835 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
bf2b4ed2 | 836 | return ret; |
7cb6d7ac | 837 | } |
f3a964b9 | 838 | |
e5815a2e MT |
839 | start = 0; |
840 | size = orig_length; | |
37aca44a | 841 | |
e5815a2e MT |
842 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, size, temp, pdpe) |
843 | gen8_map_pagetable_range(pd, start, size, ppgtt->base.dev); | |
2934368e | 844 | |
09942c65 | 845 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
28cf5415 | 846 | return 0; |
37aca44a BW |
847 | } |
848 | ||
87d60b63 BW |
849 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
850 | { | |
87d60b63 | 851 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 852 | struct i915_page_table *unused; |
07749ef3 | 853 | gen6_pte_t scratch_pte; |
87d60b63 | 854 | uint32_t pd_entry; |
09942c65 MT |
855 | uint32_t pte, pde, temp; |
856 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 857 | |
24f3a8cf | 858 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 859 | |
09942c65 | 860 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 861 | u32 expected; |
07749ef3 | 862 | gen6_pte_t *pt_vaddr; |
06fda602 | 863 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; |
09942c65 | 864 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
865 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
866 | ||
867 | if (pd_entry != expected) | |
868 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
869 | pde, | |
870 | pd_entry, | |
871 | expected); | |
872 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
873 | ||
06fda602 | 874 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); |
07749ef3 | 875 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 876 | unsigned long va = |
07749ef3 | 877 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
878 | (pte * PAGE_SIZE); |
879 | int i; | |
880 | bool found = false; | |
881 | for (i = 0; i < 4; i++) | |
882 | if (pt_vaddr[pte + i] != scratch_pte) | |
883 | found = true; | |
884 | if (!found) | |
885 | continue; | |
886 | ||
887 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
888 | for (i = 0; i < 4; i++) { | |
889 | if (pt_vaddr[pte + i] != scratch_pte) | |
890 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
891 | else | |
892 | seq_puts(m, " SCRATCH "); | |
893 | } | |
894 | seq_puts(m, "\n"); | |
895 | } | |
896 | kunmap_atomic(pt_vaddr); | |
897 | } | |
898 | } | |
899 | ||
678d96fb | 900 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
901 | static void gen6_write_pde(struct i915_page_directory *pd, |
902 | const int pde, struct i915_page_table *pt) | |
6197349b | 903 | { |
678d96fb BW |
904 | /* Caller needs to make sure the write completes if necessary */ |
905 | struct i915_hw_ppgtt *ppgtt = | |
906 | container_of(pd, struct i915_hw_ppgtt, pd); | |
907 | u32 pd_entry; | |
6197349b | 908 | |
678d96fb BW |
909 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); |
910 | pd_entry |= GEN6_PDE_VALID; | |
6197349b | 911 | |
678d96fb BW |
912 | writel(pd_entry, ppgtt->pd_addr + pde); |
913 | } | |
6197349b | 914 | |
678d96fb BW |
915 | /* Write all the page tables found in the ppgtt structure to incrementing page |
916 | * directories. */ | |
917 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 918 | struct i915_page_directory *pd, |
678d96fb BW |
919 | uint32_t start, uint32_t length) |
920 | { | |
ec565b3c | 921 | struct i915_page_table *pt; |
678d96fb BW |
922 | uint32_t pde, temp; |
923 | ||
924 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
925 | gen6_write_pde(pd, pde, pt); | |
926 | ||
927 | /* Make sure write is complete before other code can use this page | |
928 | * table. Also require for WC mapped PTEs */ | |
929 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
930 | } |
931 | ||
b4a74e3a | 932 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 933 | { |
7324cc04 | 934 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 935 | |
7324cc04 | 936 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
937 | } |
938 | ||
90252e5c | 939 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 940 | struct intel_engine_cs *ring) |
90252e5c | 941 | { |
90252e5c BW |
942 | int ret; |
943 | ||
90252e5c BW |
944 | /* NB: TLBs must be flushed and invalidated before a switch */ |
945 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
946 | if (ret) | |
947 | return ret; | |
948 | ||
949 | ret = intel_ring_begin(ring, 6); | |
950 | if (ret) | |
951 | return ret; | |
952 | ||
953 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
954 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
955 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
956 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
957 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
958 | intel_ring_emit(ring, MI_NOOP); | |
959 | intel_ring_advance(ring); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
71ba2d64 YZ |
964 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
965 | struct intel_engine_cs *ring) | |
966 | { | |
967 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
968 | ||
969 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
970 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
971 | return 0; | |
972 | } | |
973 | ||
48a10389 | 974 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 975 | struct intel_engine_cs *ring) |
48a10389 | 976 | { |
48a10389 BW |
977 | int ret; |
978 | ||
48a10389 BW |
979 | /* NB: TLBs must be flushed and invalidated before a switch */ |
980 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
981 | if (ret) | |
982 | return ret; | |
983 | ||
984 | ret = intel_ring_begin(ring, 6); | |
985 | if (ret) | |
986 | return ret; | |
987 | ||
988 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
989 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
990 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
991 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
992 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
993 | intel_ring_emit(ring, MI_NOOP); | |
994 | intel_ring_advance(ring); | |
995 | ||
90252e5c BW |
996 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
997 | if (ring->id != RCS) { | |
998 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
999 | if (ret) | |
1000 | return ret; | |
1001 | } | |
1002 | ||
48a10389 BW |
1003 | return 0; |
1004 | } | |
1005 | ||
eeb9488e | 1006 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1007 | struct intel_engine_cs *ring) |
eeb9488e BW |
1008 | { |
1009 | struct drm_device *dev = ppgtt->base.dev; | |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011 | ||
48a10389 | 1012 | |
eeb9488e BW |
1013 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1014 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1015 | ||
1016 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
82460d97 | 1021 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1022 | { |
eeb9488e | 1023 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1024 | struct intel_engine_cs *ring; |
82460d97 | 1025 | int j; |
3e302542 | 1026 | |
eeb9488e BW |
1027 | for_each_ring(ring, dev_priv, j) { |
1028 | I915_WRITE(RING_MODE_GEN7(ring), | |
1029 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1030 | } |
eeb9488e | 1031 | } |
6197349b | 1032 | |
82460d97 | 1033 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1034 | { |
50227e1c | 1035 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1036 | struct intel_engine_cs *ring; |
b4a74e3a | 1037 | uint32_t ecochk, ecobits; |
3e302542 | 1038 | int i; |
6197349b | 1039 | |
b4a74e3a BW |
1040 | ecobits = I915_READ(GAC_ECO_BITS); |
1041 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1042 | |
b4a74e3a BW |
1043 | ecochk = I915_READ(GAM_ECOCHK); |
1044 | if (IS_HASWELL(dev)) { | |
1045 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1046 | } else { | |
1047 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1048 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1049 | } | |
1050 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1051 | |
b4a74e3a | 1052 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1053 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1054 | I915_WRITE(RING_MODE_GEN7(ring), |
1055 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1056 | } |
b4a74e3a | 1057 | } |
6197349b | 1058 | |
82460d97 | 1059 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1060 | { |
50227e1c | 1061 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1062 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1063 | |
b4a74e3a BW |
1064 | ecobits = I915_READ(GAC_ECO_BITS); |
1065 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1066 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1067 | |
b4a74e3a BW |
1068 | gab_ctl = I915_READ(GAB_CTL); |
1069 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1070 | ||
1071 | ecochk = I915_READ(GAM_ECOCHK); | |
1072 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1073 | ||
1074 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1075 | } |
1076 | ||
1d2a314c | 1077 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1078 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1079 | uint64_t start, |
1080 | uint64_t length, | |
828c7908 | 1081 | bool use_scratch) |
1d2a314c | 1082 | { |
853ba5d2 BW |
1083 | struct i915_hw_ppgtt *ppgtt = |
1084 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1085 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1086 | unsigned first_entry = start >> PAGE_SHIFT; |
1087 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1088 | unsigned act_pt = first_entry / GEN6_PTES; |
1089 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1090 | unsigned last_pte, i; |
1d2a314c | 1091 | |
24f3a8cf | 1092 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1093 | |
7bddb01f DV |
1094 | while (num_entries) { |
1095 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1096 | if (last_pte > GEN6_PTES) |
1097 | last_pte = GEN6_PTES; | |
7bddb01f | 1098 | |
06fda602 | 1099 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
1d2a314c | 1100 | |
7bddb01f DV |
1101 | for (i = first_pte; i < last_pte; i++) |
1102 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1103 | |
1104 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1105 | |
7bddb01f DV |
1106 | num_entries -= last_pte - first_pte; |
1107 | first_pte = 0; | |
a15326a5 | 1108 | act_pt++; |
7bddb01f | 1109 | } |
1d2a314c DV |
1110 | } |
1111 | ||
853ba5d2 | 1112 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1113 | struct sg_table *pages, |
782f1495 | 1114 | uint64_t start, |
24f3a8cf | 1115 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1116 | { |
853ba5d2 BW |
1117 | struct i915_hw_ppgtt *ppgtt = |
1118 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1119 | gen6_pte_t *pt_vaddr; |
782f1495 | 1120 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1121 | unsigned act_pt = first_entry / GEN6_PTES; |
1122 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1123 | struct sg_page_iter sg_iter; |
1124 | ||
cc79714f | 1125 | pt_vaddr = NULL; |
6e995e23 | 1126 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1127 | if (pt_vaddr == NULL) |
06fda602 | 1128 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
6e995e23 | 1129 | |
cc79714f CW |
1130 | pt_vaddr[act_pte] = |
1131 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1132 | cache_level, true, flags); |
1133 | ||
07749ef3 | 1134 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1135 | kunmap_atomic(pt_vaddr); |
cc79714f | 1136 | pt_vaddr = NULL; |
a15326a5 | 1137 | act_pt++; |
6e995e23 | 1138 | act_pte = 0; |
def886c3 | 1139 | } |
def886c3 | 1140 | } |
cc79714f CW |
1141 | if (pt_vaddr) |
1142 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1143 | } |
1144 | ||
563222a7 BW |
1145 | /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we |
1146 | * are switching between contexts with the same LRCA, we also must do a force | |
1147 | * restore. | |
1148 | */ | |
1149 | static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1150 | { | |
1151 | /* If current vm != vm, */ | |
1152 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1153 | } | |
1154 | ||
4933d519 | 1155 | static void gen6_initialize_pt(struct i915_address_space *vm, |
ec565b3c | 1156 | struct i915_page_table *pt) |
4933d519 MT |
1157 | { |
1158 | gen6_pte_t *pt_vaddr, scratch_pte; | |
1159 | int i; | |
1160 | ||
1161 | WARN_ON(vm->scratch.addr == 0); | |
1162 | ||
1163 | scratch_pte = vm->pte_encode(vm->scratch.addr, | |
1164 | I915_CACHE_LLC, true, 0); | |
1165 | ||
1166 | pt_vaddr = kmap_atomic(pt->page); | |
1167 | ||
1168 | for (i = 0; i < GEN6_PTES; i++) | |
1169 | pt_vaddr[i] = scratch_pte; | |
1170 | ||
1171 | kunmap_atomic(pt_vaddr); | |
1172 | } | |
1173 | ||
678d96fb BW |
1174 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
1175 | uint64_t start, uint64_t length) | |
1176 | { | |
4933d519 MT |
1177 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1178 | struct drm_device *dev = vm->dev; | |
1179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1180 | struct i915_hw_ppgtt *ppgtt = |
1181 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1182 | struct i915_page_table *pt; |
4933d519 | 1183 | const uint32_t start_save = start, length_save = length; |
678d96fb | 1184 | uint32_t pde, temp; |
4933d519 MT |
1185 | int ret; |
1186 | ||
1187 | WARN_ON(upper_32_bits(start)); | |
1188 | ||
1189 | bitmap_zero(new_page_tables, I915_PDES); | |
1190 | ||
1191 | /* The allocation is done in two stages so that we can bail out with | |
1192 | * minimal amount of pain. The first stage finds new page tables that | |
1193 | * need allocation. The second stage marks use ptes within the page | |
1194 | * tables. | |
1195 | */ | |
1196 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1197 | if (pt != ppgtt->scratch_pt) { | |
1198 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1199 | continue; | |
1200 | } | |
1201 | ||
1202 | /* We've already allocated a page table */ | |
1203 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1204 | ||
1205 | pt = alloc_pt_single(dev); | |
1206 | if (IS_ERR(pt)) { | |
1207 | ret = PTR_ERR(pt); | |
1208 | goto unwind_out; | |
1209 | } | |
1210 | ||
1211 | gen6_initialize_pt(vm, pt); | |
1212 | ||
1213 | ppgtt->pd.page_table[pde] = pt; | |
1214 | set_bit(pde, new_page_tables); | |
72744cb1 | 1215 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1216 | } |
1217 | ||
1218 | start = start_save; | |
1219 | length = length_save; | |
678d96fb BW |
1220 | |
1221 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1222 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1223 | ||
1224 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1225 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1226 | gen6_pte_count(start, length)); | |
1227 | ||
4933d519 MT |
1228 | if (test_and_clear_bit(pde, new_page_tables)) |
1229 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1230 | ||
72744cb1 MT |
1231 | trace_i915_page_table_entry_map(vm, pde, pt, |
1232 | gen6_pte_index(start), | |
1233 | gen6_pte_count(start, length), | |
1234 | GEN6_PTES); | |
4933d519 | 1235 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1236 | GEN6_PTES); |
1237 | } | |
1238 | ||
4933d519 MT |
1239 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1240 | ||
1241 | /* Make sure write is complete before other code can use this page | |
1242 | * table. Also require for WC mapped PTEs */ | |
1243 | readl(dev_priv->gtt.gsm); | |
1244 | ||
563222a7 | 1245 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1246 | return 0; |
4933d519 MT |
1247 | |
1248 | unwind_out: | |
1249 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1250 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 MT |
1251 | |
1252 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
1253 | unmap_and_free_pt(pt, vm->dev); | |
1254 | } | |
1255 | ||
1256 | mark_tlbs_dirty(ppgtt); | |
1257 | return ret; | |
678d96fb BW |
1258 | } |
1259 | ||
a00d825d BW |
1260 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
1261 | { | |
09942c65 MT |
1262 | struct i915_page_table *pt; |
1263 | uint32_t pde; | |
4933d519 | 1264 | |
09942c65 | 1265 | gen6_for_all_pdes(pt, ppgtt, pde) { |
4933d519 | 1266 | if (pt != ppgtt->scratch_pt) |
09942c65 | 1267 | unmap_and_free_pt(pt, ppgtt->base.dev); |
4933d519 | 1268 | } |
06fda602 | 1269 | |
4933d519 | 1270 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
e5815a2e | 1271 | unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); |
3440d265 DV |
1272 | } |
1273 | ||
a00d825d BW |
1274 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1275 | { | |
1276 | struct i915_hw_ppgtt *ppgtt = | |
1277 | container_of(vm, struct i915_hw_ppgtt, base); | |
1278 | ||
a00d825d BW |
1279 | drm_mm_remove_node(&ppgtt->node); |
1280 | ||
a00d825d BW |
1281 | gen6_ppgtt_free(ppgtt); |
1282 | } | |
1283 | ||
b146520f | 1284 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1285 | { |
853ba5d2 | 1286 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1287 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1288 | bool retried = false; |
b146520f | 1289 | int ret; |
1d2a314c | 1290 | |
c8d4c0d6 BW |
1291 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1292 | * allocator works in address space sizes, so it's multiplied by page | |
1293 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1294 | */ | |
1295 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 MT |
1296 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
1297 | if (IS_ERR(ppgtt->scratch_pt)) | |
1298 | return PTR_ERR(ppgtt->scratch_pt); | |
1299 | ||
1300 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1301 | ||
e3cc1995 | 1302 | alloc: |
c8d4c0d6 BW |
1303 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1304 | &ppgtt->node, GEN6_PD_SIZE, | |
1305 | GEN6_PD_ALIGN, 0, | |
1306 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1307 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1308 | if (ret == -ENOSPC && !retried) { |
1309 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1310 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1311 | I915_CACHE_NONE, |
1312 | 0, dev_priv->gtt.base.total, | |
1313 | 0); | |
e3cc1995 | 1314 | if (ret) |
678d96fb | 1315 | goto err_out; |
e3cc1995 BW |
1316 | |
1317 | retried = true; | |
1318 | goto alloc; | |
1319 | } | |
c8d4c0d6 | 1320 | |
c8c26622 | 1321 | if (ret) |
678d96fb BW |
1322 | goto err_out; |
1323 | ||
c8c26622 | 1324 | |
c8d4c0d6 BW |
1325 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1326 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1327 | |
c8c26622 | 1328 | return 0; |
678d96fb BW |
1329 | |
1330 | err_out: | |
4933d519 | 1331 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
678d96fb | 1332 | return ret; |
b146520f BW |
1333 | } |
1334 | ||
b146520f BW |
1335 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1336 | { | |
2f2cf682 | 1337 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1338 | } |
06dc68d6 | 1339 | |
4933d519 MT |
1340 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1341 | uint64_t start, uint64_t length) | |
1342 | { | |
ec565b3c | 1343 | struct i915_page_table *unused; |
4933d519 | 1344 | uint32_t pde, temp; |
1d2a314c | 1345 | |
4933d519 MT |
1346 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1347 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1348 | } |
1349 | ||
4933d519 | 1350 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) |
b146520f BW |
1351 | { |
1352 | struct drm_device *dev = ppgtt->base.dev; | |
1353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1354 | int ret; | |
1355 | ||
1356 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1357 | if (IS_GEN6(dev)) { | |
b146520f BW |
1358 | ppgtt->switch_mm = gen6_mm_switch; |
1359 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1360 | ppgtt->switch_mm = hsw_mm_switch; |
1361 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1362 | ppgtt->switch_mm = gen7_mm_switch; |
1363 | } else | |
1364 | BUG(); | |
1365 | ||
71ba2d64 YZ |
1366 | if (intel_vgpu_active(dev)) |
1367 | ppgtt->switch_mm = vgpu_mm_switch; | |
1368 | ||
b146520f BW |
1369 | ret = gen6_ppgtt_alloc(ppgtt); |
1370 | if (ret) | |
1371 | return ret; | |
1372 | ||
4933d519 MT |
1373 | if (aliasing) { |
1374 | /* preallocate all pts */ | |
09942c65 | 1375 | ret = alloc_pt_range(&ppgtt->pd, 0, I915_PDES, |
4933d519 MT |
1376 | ppgtt->base.dev); |
1377 | ||
1378 | if (ret) { | |
1379 | gen6_ppgtt_cleanup(&ppgtt->base); | |
1380 | return ret; | |
1381 | } | |
1382 | } | |
1383 | ||
678d96fb | 1384 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1385 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1386 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1387 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1388 | ppgtt->base.start = 0; |
09942c65 | 1389 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1390 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1391 | |
7324cc04 | 1392 | ppgtt->pd.pd_offset = |
07749ef3 | 1393 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1394 | |
678d96fb BW |
1395 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
1396 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
1397 | ||
4933d519 MT |
1398 | if (aliasing) |
1399 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); | |
1400 | else | |
1401 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); | |
1d2a314c | 1402 | |
678d96fb BW |
1403 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1404 | ||
440fd528 | 1405 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1406 | ppgtt->node.size >> 20, |
1407 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1408 | |
fa76da34 | 1409 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
7324cc04 | 1410 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1411 | |
b146520f | 1412 | return 0; |
3440d265 DV |
1413 | } |
1414 | ||
4933d519 MT |
1415 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, |
1416 | bool aliasing) | |
3440d265 DV |
1417 | { |
1418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1419 | |
853ba5d2 | 1420 | ppgtt->base.dev = dev; |
8407bb91 | 1421 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1422 | |
3ed124b2 | 1423 | if (INTEL_INFO(dev)->gen < 8) |
4933d519 | 1424 | return gen6_ppgtt_init(ppgtt, aliasing); |
3ed124b2 | 1425 | else |
1eb0f006 | 1426 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
fa76da34 DV |
1427 | } |
1428 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1429 | { | |
1430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1431 | int ret = 0; | |
3ed124b2 | 1432 | |
4933d519 | 1433 | ret = __hw_ppgtt_init(dev, ppgtt, false); |
fa76da34 | 1434 | if (ret == 0) { |
c7c48dfd | 1435 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1436 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1437 | ppgtt->base.total); | |
7e0d96bc | 1438 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1439 | } |
1d2a314c DV |
1440 | |
1441 | return ret; | |
1442 | } | |
1443 | ||
82460d97 DV |
1444 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1445 | { | |
1446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1447 | struct intel_engine_cs *ring; | |
1448 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1449 | int i, ret = 0; | |
1450 | ||
671b5013 TD |
1451 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1452 | * and the PDPs are contained within the context itself. We don't | |
1453 | * need to do anything here. */ | |
1454 | if (i915.enable_execlists) | |
1455 | return 0; | |
1456 | ||
82460d97 DV |
1457 | if (!USES_PPGTT(dev)) |
1458 | return 0; | |
1459 | ||
1460 | if (IS_GEN6(dev)) | |
1461 | gen6_ppgtt_enable(dev); | |
1462 | else if (IS_GEN7(dev)) | |
1463 | gen7_ppgtt_enable(dev); | |
1464 | else if (INTEL_INFO(dev)->gen >= 8) | |
1465 | gen8_ppgtt_enable(dev); | |
1466 | else | |
5f77eeb0 | 1467 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1468 | |
1469 | if (ppgtt) { | |
1470 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1471 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1472 | if (ret != 0) |
1473 | return ret; | |
7e0d96bc | 1474 | } |
93bd8649 | 1475 | } |
1d2a314c DV |
1476 | |
1477 | return ret; | |
1478 | } | |
4d884705 DV |
1479 | struct i915_hw_ppgtt * |
1480 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1481 | { | |
1482 | struct i915_hw_ppgtt *ppgtt; | |
1483 | int ret; | |
1484 | ||
1485 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1486 | if (!ppgtt) | |
1487 | return ERR_PTR(-ENOMEM); | |
1488 | ||
1489 | ret = i915_ppgtt_init(dev, ppgtt); | |
1490 | if (ret) { | |
1491 | kfree(ppgtt); | |
1492 | return ERR_PTR(ret); | |
1493 | } | |
1494 | ||
1495 | ppgtt->file_priv = fpriv; | |
1496 | ||
198c974d DCS |
1497 | trace_i915_ppgtt_create(&ppgtt->base); |
1498 | ||
4d884705 DV |
1499 | return ppgtt; |
1500 | } | |
1501 | ||
ee960be7 DV |
1502 | void i915_ppgtt_release(struct kref *kref) |
1503 | { | |
1504 | struct i915_hw_ppgtt *ppgtt = | |
1505 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1506 | ||
198c974d DCS |
1507 | trace_i915_ppgtt_release(&ppgtt->base); |
1508 | ||
ee960be7 DV |
1509 | /* vmas should already be unbound */ |
1510 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1511 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1512 | ||
19dd120c DV |
1513 | list_del(&ppgtt->base.global_link); |
1514 | drm_mm_takedown(&ppgtt->base.mm); | |
1515 | ||
ee960be7 DV |
1516 | ppgtt->base.cleanup(&ppgtt->base); |
1517 | kfree(ppgtt); | |
1518 | } | |
1d2a314c | 1519 | |
7e0d96bc | 1520 | static void |
6f65e29a BW |
1521 | ppgtt_bind_vma(struct i915_vma *vma, |
1522 | enum i915_cache_level cache_level, | |
1523 | u32 flags) | |
1d2a314c | 1524 | { |
24f3a8cf AG |
1525 | /* Currently applicable only to VLV */ |
1526 | if (vma->obj->gt_ro) | |
1527 | flags |= PTE_READ_ONLY; | |
1528 | ||
782f1495 | 1529 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1530 | cache_level, flags); |
1d2a314c DV |
1531 | } |
1532 | ||
7e0d96bc | 1533 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1534 | { |
6f65e29a | 1535 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1536 | vma->node.start, |
1537 | vma->obj->base.size, | |
6f65e29a | 1538 | true); |
7bddb01f DV |
1539 | } |
1540 | ||
a81cc00c BW |
1541 | extern int intel_iommu_gfx_mapped; |
1542 | /* Certain Gen5 chipsets require require idling the GPU before | |
1543 | * unmapping anything from the GTT when VT-d is enabled. | |
1544 | */ | |
1545 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1546 | { | |
1547 | #ifdef CONFIG_INTEL_IOMMU | |
1548 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1549 | * was loaded first. | |
1550 | */ | |
1551 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1552 | return true; | |
1553 | #endif | |
1554 | return false; | |
1555 | } | |
1556 | ||
5c042287 BW |
1557 | static bool do_idling(struct drm_i915_private *dev_priv) |
1558 | { | |
1559 | bool ret = dev_priv->mm.interruptible; | |
1560 | ||
a81cc00c | 1561 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1562 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1563 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1564 | DRM_ERROR("Couldn't idle GPU\n"); |
1565 | /* Wait a bit, in hopes it avoids the hang */ | |
1566 | udelay(10); | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | return ret; | |
1571 | } | |
1572 | ||
1573 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1574 | { | |
a81cc00c | 1575 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1576 | dev_priv->mm.interruptible = interruptible; |
1577 | } | |
1578 | ||
828c7908 BW |
1579 | void i915_check_and_clear_faults(struct drm_device *dev) |
1580 | { | |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1582 | struct intel_engine_cs *ring; |
828c7908 BW |
1583 | int i; |
1584 | ||
1585 | if (INTEL_INFO(dev)->gen < 6) | |
1586 | return; | |
1587 | ||
1588 | for_each_ring(ring, dev_priv, i) { | |
1589 | u32 fault_reg; | |
1590 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1591 | if (fault_reg & RING_FAULT_VALID) { | |
1592 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1593 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1594 | "\tAddress space: %s\n" |
1595 | "\tSource ID: %d\n" | |
1596 | "\tType: %d\n", | |
1597 | fault_reg & PAGE_MASK, | |
1598 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1599 | RING_FAULT_SRCID(fault_reg), | |
1600 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1601 | I915_WRITE(RING_FAULT_REG(ring), | |
1602 | fault_reg & ~RING_FAULT_VALID); | |
1603 | } | |
1604 | } | |
1605 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1606 | } | |
1607 | ||
91e56499 CW |
1608 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1609 | { | |
1610 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1611 | intel_gtt_chipset_flush(); | |
1612 | } else { | |
1613 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1614 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1615 | } | |
1616 | } | |
1617 | ||
828c7908 BW |
1618 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1619 | { | |
1620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1621 | ||
1622 | /* Don't bother messing with faults pre GEN6 as we have little | |
1623 | * documentation supporting that it's a good idea. | |
1624 | */ | |
1625 | if (INTEL_INFO(dev)->gen < 6) | |
1626 | return; | |
1627 | ||
1628 | i915_check_and_clear_faults(dev); | |
1629 | ||
1630 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1631 | dev_priv->gtt.base.start, |
1632 | dev_priv->gtt.base.total, | |
e568af1c | 1633 | true); |
91e56499 CW |
1634 | |
1635 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1636 | } |
1637 | ||
76aaf220 DV |
1638 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1639 | { | |
1640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1641 | struct drm_i915_gem_object *obj; |
80da2161 | 1642 | struct i915_address_space *vm; |
76aaf220 | 1643 | |
828c7908 BW |
1644 | i915_check_and_clear_faults(dev); |
1645 | ||
bee4a186 | 1646 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1647 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1648 | dev_priv->gtt.base.start, |
1649 | dev_priv->gtt.base.total, | |
828c7908 | 1650 | true); |
bee4a186 | 1651 | |
35c20a60 | 1652 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1653 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1654 | &dev_priv->gtt.base); | |
1655 | if (!vma) | |
1656 | continue; | |
1657 | ||
2c22569b | 1658 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1659 | /* The bind_vma code tries to be smart about tracking mappings. |
1660 | * Unfortunately above, we've just wiped out the mappings | |
1661 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1662 | * |
1663 | * Bind is not expected to fail since this is only called on | |
1664 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1665 | */ |
aff43766 | 1666 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1667 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1668 | } |
1669 | ||
80da2161 | 1670 | |
a2319c08 | 1671 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1672 | if (IS_CHERRYVIEW(dev)) |
1673 | chv_setup_private_ppat(dev_priv); | |
1674 | else | |
1675 | bdw_setup_private_ppat(dev_priv); | |
1676 | ||
80da2161 | 1677 | return; |
a2319c08 | 1678 | } |
80da2161 | 1679 | |
678d96fb BW |
1680 | if (USES_PPGTT(dev)) { |
1681 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1682 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1683 | ||
1684 | struct i915_hw_ppgtt *ppgtt = | |
1685 | container_of(vm, struct i915_hw_ppgtt, | |
1686 | base); | |
80da2161 | 1687 | |
678d96fb BW |
1688 | if (i915_is_ggtt(vm)) |
1689 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1690 | ||
1691 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
1692 | 0, ppgtt->base.total); | |
1693 | } | |
76aaf220 DV |
1694 | } |
1695 | ||
91e56499 | 1696 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1697 | } |
7c2e6fdf | 1698 | |
74163907 | 1699 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1700 | { |
9da3da66 | 1701 | if (obj->has_dma_mapping) |
74163907 | 1702 | return 0; |
9da3da66 CW |
1703 | |
1704 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1705 | obj->pages->sgl, obj->pages->nents, | |
1706 | PCI_DMA_BIDIRECTIONAL)) | |
1707 | return -ENOSPC; | |
1708 | ||
1709 | return 0; | |
7c2e6fdf DV |
1710 | } |
1711 | ||
07749ef3 | 1712 | static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1713 | { |
1714 | #ifdef writeq | |
1715 | writeq(pte, addr); | |
1716 | #else | |
1717 | iowrite32((u32)pte, addr); | |
1718 | iowrite32(pte >> 32, addr + 4); | |
1719 | #endif | |
1720 | } | |
1721 | ||
1722 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1723 | struct sg_table *st, | |
782f1495 | 1724 | uint64_t start, |
24f3a8cf | 1725 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1726 | { |
1727 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1728 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1729 | gen8_pte_t __iomem *gtt_entries = |
1730 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1731 | int i = 0; |
1732 | struct sg_page_iter sg_iter; | |
57007df7 | 1733 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1734 | |
1735 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1736 | addr = sg_dma_address(sg_iter.sg) + | |
1737 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1738 | gen8_set_pte(>t_entries[i], | |
1739 | gen8_pte_encode(addr, level, true)); | |
1740 | i++; | |
1741 | } | |
1742 | ||
1743 | /* | |
1744 | * XXX: This serves as a posting read to make sure that the PTE has | |
1745 | * actually been updated. There is some concern that even though | |
1746 | * registers and PTEs are within the same BAR that they are potentially | |
1747 | * of NUMA access patterns. Therefore, even with the way we assume | |
1748 | * hardware should work, we must keep this posting read for paranoia. | |
1749 | */ | |
1750 | if (i != 0) | |
1751 | WARN_ON(readq(>t_entries[i-1]) | |
1752 | != gen8_pte_encode(addr, level, true)); | |
1753 | ||
94ec8f61 BW |
1754 | /* This next bit makes the above posting read even more important. We |
1755 | * want to flush the TLBs only after we're certain all the PTE updates | |
1756 | * have finished. | |
1757 | */ | |
1758 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1759 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1760 | } |
1761 | ||
e76e9aeb BW |
1762 | /* |
1763 | * Binds an object into the global gtt with the specified cache level. The object | |
1764 | * will be accessible to the GPU via commands whose operands reference offsets | |
1765 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1766 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1767 | */ | |
853ba5d2 | 1768 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1769 | struct sg_table *st, |
782f1495 | 1770 | uint64_t start, |
24f3a8cf | 1771 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1772 | { |
853ba5d2 | 1773 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1774 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1775 | gen6_pte_t __iomem *gtt_entries = |
1776 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1777 | int i = 0; |
1778 | struct sg_page_iter sg_iter; | |
57007df7 | 1779 | dma_addr_t addr = 0; |
e76e9aeb | 1780 | |
6e995e23 | 1781 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1782 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1783 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1784 | i++; |
e76e9aeb BW |
1785 | } |
1786 | ||
e76e9aeb BW |
1787 | /* XXX: This serves as a posting read to make sure that the PTE has |
1788 | * actually been updated. There is some concern that even though | |
1789 | * registers and PTEs are within the same BAR that they are potentially | |
1790 | * of NUMA access patterns. Therefore, even with the way we assume | |
1791 | * hardware should work, we must keep this posting read for paranoia. | |
1792 | */ | |
57007df7 PM |
1793 | if (i != 0) { |
1794 | unsigned long gtt = readl(>t_entries[i-1]); | |
1795 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1796 | } | |
0f9b91c7 BW |
1797 | |
1798 | /* This next bit makes the above posting read even more important. We | |
1799 | * want to flush the TLBs only after we're certain all the PTE updates | |
1800 | * have finished. | |
1801 | */ | |
1802 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1803 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1804 | } |
1805 | ||
94ec8f61 | 1806 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1807 | uint64_t start, |
1808 | uint64_t length, | |
94ec8f61 BW |
1809 | bool use_scratch) |
1810 | { | |
1811 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1812 | unsigned first_entry = start >> PAGE_SHIFT; |
1813 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1814 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1815 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1816 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1817 | int i; | |
1818 | ||
1819 | if (WARN(num_entries > max_entries, | |
1820 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1821 | first_entry, num_entries, max_entries)) | |
1822 | num_entries = max_entries; | |
1823 | ||
1824 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1825 | I915_CACHE_LLC, | |
1826 | use_scratch); | |
1827 | for (i = 0; i < num_entries; i++) | |
1828 | gen8_set_pte(>t_base[i], scratch_pte); | |
1829 | readl(gtt_base); | |
1830 | } | |
1831 | ||
853ba5d2 | 1832 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1833 | uint64_t start, |
1834 | uint64_t length, | |
828c7908 | 1835 | bool use_scratch) |
7faf1ab2 | 1836 | { |
853ba5d2 | 1837 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1838 | unsigned first_entry = start >> PAGE_SHIFT; |
1839 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1840 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1841 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1842 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1843 | int i; |
1844 | ||
1845 | if (WARN(num_entries > max_entries, | |
1846 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1847 | first_entry, num_entries, max_entries)) | |
1848 | num_entries = max_entries; | |
1849 | ||
24f3a8cf | 1850 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1851 | |
7faf1ab2 DV |
1852 | for (i = 0; i < num_entries; i++) |
1853 | iowrite32(scratch_pte, >t_base[i]); | |
1854 | readl(gtt_base); | |
1855 | } | |
1856 | ||
6f65e29a BW |
1857 | |
1858 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1859 | enum i915_cache_level cache_level, | |
1860 | u32 unused) | |
7faf1ab2 | 1861 | { |
6f65e29a | 1862 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1863 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1864 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1865 | ||
6f65e29a | 1866 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1867 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1868 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1869 | } |
1870 | ||
853ba5d2 | 1871 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1872 | uint64_t start, |
1873 | uint64_t length, | |
828c7908 | 1874 | bool unused) |
7faf1ab2 | 1875 | { |
782f1495 BW |
1876 | unsigned first_entry = start >> PAGE_SHIFT; |
1877 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1878 | intel_gtt_clear_range(first_entry, num_entries); |
1879 | } | |
1880 | ||
6f65e29a BW |
1881 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1882 | { | |
1883 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1884 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1885 | |
6f65e29a | 1886 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1887 | vma->bound = 0; |
6f65e29a BW |
1888 | intel_gtt_clear_range(first, size); |
1889 | } | |
7faf1ab2 | 1890 | |
6f65e29a BW |
1891 | static void ggtt_bind_vma(struct i915_vma *vma, |
1892 | enum i915_cache_level cache_level, | |
1893 | u32 flags) | |
d5bd1449 | 1894 | { |
6f65e29a | 1895 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1896 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1897 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1898 | struct sg_table *pages = obj->pages; |
7faf1ab2 | 1899 | |
24f3a8cf AG |
1900 | /* Currently applicable only to VLV */ |
1901 | if (obj->gt_ro) | |
1902 | flags |= PTE_READ_ONLY; | |
1903 | ||
ec7adb6e JL |
1904 | if (i915_is_ggtt(vma->vm)) |
1905 | pages = vma->ggtt_view.pages; | |
1906 | ||
6f65e29a BW |
1907 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1908 | * or we have a global mapping already but the cacheability flags have | |
1909 | * changed, set the global PTEs. | |
1910 | * | |
1911 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1912 | * instead if none of the above hold true. | |
1913 | * | |
1914 | * NB: A global mapping should only be needed for special regions like | |
1915 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1916 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1917 | */ | |
1918 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1919 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1920 | (cache_level != obj->cache_level)) { |
ec7adb6e | 1921 | vma->vm->insert_entries(vma->vm, pages, |
782f1495 | 1922 | vma->node.start, |
24f3a8cf | 1923 | cache_level, flags); |
aff43766 | 1924 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1925 | } |
1926 | } | |
d5bd1449 | 1927 | |
6f65e29a | 1928 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1929 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1930 | (cache_level != obj->cache_level))) { |
1931 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
ec7adb6e | 1932 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1933 | vma->node.start, |
24f3a8cf | 1934 | cache_level, flags); |
aff43766 | 1935 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1936 | } |
d5bd1449 CW |
1937 | } |
1938 | ||
6f65e29a | 1939 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1940 | { |
6f65e29a | 1941 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1943 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1944 | |
aff43766 | 1945 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1946 | vma->vm->clear_range(vma->vm, |
1947 | vma->node.start, | |
1948 | obj->base.size, | |
6f65e29a | 1949 | true); |
aff43766 | 1950 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1951 | } |
74898d7e | 1952 | |
aff43766 | 1953 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1954 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1955 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1956 | vma->node.start, |
1957 | obj->base.size, | |
6f65e29a | 1958 | true); |
aff43766 | 1959 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1960 | } |
74163907 DV |
1961 | } |
1962 | ||
1963 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1964 | { |
5c042287 BW |
1965 | struct drm_device *dev = obj->base.dev; |
1966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1967 | bool interruptible; | |
1968 | ||
1969 | interruptible = do_idling(dev_priv); | |
1970 | ||
9da3da66 CW |
1971 | if (!obj->has_dma_mapping) |
1972 | dma_unmap_sg(&dev->pdev->dev, | |
1973 | obj->pages->sgl, obj->pages->nents, | |
1974 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1975 | |
1976 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1977 | } |
644ec02b | 1978 | |
42d6ab48 CW |
1979 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1980 | unsigned long color, | |
440fd528 TR |
1981 | u64 *start, |
1982 | u64 *end) | |
42d6ab48 CW |
1983 | { |
1984 | if (node->color != color) | |
1985 | *start += 4096; | |
1986 | ||
1987 | if (!list_empty(&node->node_list)) { | |
1988 | node = list_entry(node->node_list.next, | |
1989 | struct drm_mm_node, | |
1990 | node_list); | |
1991 | if (node->allocated && node->color != color) | |
1992 | *end -= 4096; | |
1993 | } | |
1994 | } | |
fbe5d36e | 1995 | |
f548c0e9 DV |
1996 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1997 | unsigned long start, | |
1998 | unsigned long mappable_end, | |
1999 | unsigned long end) | |
644ec02b | 2000 | { |
e78891ca BW |
2001 | /* Let GEM Manage all of the aperture. |
2002 | * | |
2003 | * However, leave one page at the end still bound to the scratch page. | |
2004 | * There are a number of places where the hardware apparently prefetches | |
2005 | * past the end of the object, and we've seen multiple hangs with the | |
2006 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2007 | * aperture. One page should be enough to keep any prefetching inside | |
2008 | * of the aperture. | |
2009 | */ | |
40d74980 BW |
2010 | struct drm_i915_private *dev_priv = dev->dev_private; |
2011 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2012 | struct drm_mm_node *entry; |
2013 | struct drm_i915_gem_object *obj; | |
2014 | unsigned long hole_start, hole_end; | |
fa76da34 | 2015 | int ret; |
644ec02b | 2016 | |
35451cb6 BW |
2017 | BUG_ON(mappable_end > end); |
2018 | ||
ed2f3452 | 2019 | /* Subtract the guard page ... */ |
40d74980 | 2020 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2021 | |
2022 | dev_priv->gtt.base.start = start; | |
2023 | dev_priv->gtt.base.total = end - start; | |
2024 | ||
2025 | if (intel_vgpu_active(dev)) { | |
2026 | ret = intel_vgt_balloon(dev); | |
2027 | if (ret) | |
2028 | return ret; | |
2029 | } | |
2030 | ||
42d6ab48 | 2031 | if (!HAS_LLC(dev)) |
93bd8649 | 2032 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2033 | |
ed2f3452 | 2034 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2035 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2036 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2037 | |
edd41a87 | 2038 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2039 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2040 | ||
2041 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2042 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2043 | if (ret) { |
2044 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2045 | return ret; | |
2046 | } | |
aff43766 | 2047 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2048 | } |
2049 | ||
ed2f3452 | 2050 | /* Clear any non-preallocated blocks */ |
40d74980 | 2051 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2052 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2053 | hole_start, hole_end); | |
782f1495 BW |
2054 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2055 | hole_end - hole_start, true); | |
ed2f3452 CW |
2056 | } |
2057 | ||
2058 | /* And finally clear the reserved guard page */ | |
782f1495 | 2059 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2060 | |
fa76da34 DV |
2061 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2062 | struct i915_hw_ppgtt *ppgtt; | |
2063 | ||
2064 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2065 | if (!ppgtt) | |
2066 | return -ENOMEM; | |
2067 | ||
4933d519 MT |
2068 | ret = __hw_ppgtt_init(dev, ppgtt, true); |
2069 | if (ret) { | |
2070 | kfree(ppgtt); | |
fa76da34 | 2071 | return ret; |
4933d519 | 2072 | } |
fa76da34 DV |
2073 | |
2074 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
2075 | } | |
2076 | ||
6c5566a8 | 2077 | return 0; |
e76e9aeb BW |
2078 | } |
2079 | ||
d7e5008f BW |
2080 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2081 | { | |
2082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2083 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 2084 | |
853ba5d2 | 2085 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2086 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2087 | |
e78891ca | 2088 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2089 | } |
2090 | ||
90d0a0e8 DV |
2091 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2092 | { | |
2093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2094 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2095 | ||
70e32544 DV |
2096 | if (dev_priv->mm.aliasing_ppgtt) { |
2097 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2098 | ||
2099 | ppgtt->base.cleanup(&ppgtt->base); | |
2100 | } | |
2101 | ||
90d0a0e8 | 2102 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2103 | if (intel_vgpu_active(dev)) |
2104 | intel_vgt_deballoon(); | |
2105 | ||
90d0a0e8 DV |
2106 | drm_mm_takedown(&vm->mm); |
2107 | list_del(&vm->global_link); | |
2108 | } | |
2109 | ||
2110 | vm->cleanup(vm); | |
2111 | } | |
70e32544 | 2112 | |
e76e9aeb BW |
2113 | static int setup_scratch_page(struct drm_device *dev) |
2114 | { | |
2115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2116 | struct page *page; | |
2117 | dma_addr_t dma_addr; | |
2118 | ||
2119 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2120 | if (page == NULL) | |
2121 | return -ENOMEM; | |
e76e9aeb BW |
2122 | set_pages_uc(page, 1); |
2123 | ||
2124 | #ifdef CONFIG_INTEL_IOMMU | |
2125 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2126 | PCI_DMA_BIDIRECTIONAL); | |
2127 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
2128 | return -EINVAL; | |
2129 | #else | |
2130 | dma_addr = page_to_phys(page); | |
2131 | #endif | |
853ba5d2 BW |
2132 | dev_priv->gtt.base.scratch.page = page; |
2133 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2134 | |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | static void teardown_scratch_page(struct drm_device *dev) | |
2139 | { | |
2140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2141 | struct page *page = dev_priv->gtt.base.scratch.page; |
2142 | ||
2143 | set_pages_wb(page, 1); | |
2144 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2145 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2146 | __free_page(page); |
e76e9aeb BW |
2147 | } |
2148 | ||
2149 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
2150 | { | |
2151 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2152 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2153 | return snb_gmch_ctl << 20; | |
2154 | } | |
2155 | ||
9459d252 BW |
2156 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
2157 | { | |
2158 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2159 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2160 | if (bdw_gmch_ctl) | |
2161 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2162 | |
2163 | #ifdef CONFIG_X86_32 | |
2164 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2165 | if (bdw_gmch_ctl > 4) | |
2166 | bdw_gmch_ctl = 4; | |
2167 | #endif | |
2168 | ||
9459d252 BW |
2169 | return bdw_gmch_ctl << 20; |
2170 | } | |
2171 | ||
d7f25f23 DL |
2172 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
2173 | { | |
2174 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2175 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2176 | ||
2177 | if (gmch_ctrl) | |
2178 | return 1 << (20 + gmch_ctrl); | |
2179 | ||
2180 | return 0; | |
2181 | } | |
2182 | ||
baa09f5f | 2183 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2184 | { |
2185 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2186 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2187 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2188 | } | |
2189 | ||
9459d252 BW |
2190 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
2191 | { | |
2192 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2193 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2194 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2195 | } | |
2196 | ||
d7f25f23 DL |
2197 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2198 | { | |
2199 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2200 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2201 | ||
2202 | /* | |
2203 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2204 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2205 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2206 | */ | |
2207 | if (gmch_ctrl < 0x11) | |
2208 | return gmch_ctrl << 25; | |
2209 | else if (gmch_ctrl < 0x17) | |
2210 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2211 | else | |
2212 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2213 | } | |
2214 | ||
66375014 DL |
2215 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2216 | { | |
2217 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2218 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2219 | ||
2220 | if (gen9_gmch_ctl < 0xf0) | |
2221 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2222 | else | |
2223 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2224 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2225 | } | |
2226 | ||
63340133 BW |
2227 | static int ggtt_probe_common(struct drm_device *dev, |
2228 | size_t gtt_size) | |
2229 | { | |
2230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2231 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2232 | int ret; |
2233 | ||
2234 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2235 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2236 | (pci_resource_len(dev->pdev, 0) / 2); |
2237 | ||
21c34607 | 2238 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
2239 | if (!dev_priv->gtt.gsm) { |
2240 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2241 | return -ENOMEM; | |
2242 | } | |
2243 | ||
2244 | ret = setup_scratch_page(dev); | |
2245 | if (ret) { | |
2246 | DRM_ERROR("Scratch setup failed\n"); | |
2247 | /* iounmap will also get called at remove, but meh */ | |
2248 | iounmap(dev_priv->gtt.gsm); | |
2249 | } | |
2250 | ||
2251 | return ret; | |
2252 | } | |
2253 | ||
fbe5d36e BW |
2254 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2255 | * bits. When using advanced contexts each context stores its own PAT, but | |
2256 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2257 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2258 | { |
fbe5d36e BW |
2259 | uint64_t pat; |
2260 | ||
2261 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2262 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2263 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2264 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2265 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2266 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2267 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2268 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2269 | ||
d6a8b72e RV |
2270 | if (!USES_PPGTT(dev_priv->dev)) |
2271 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2272 | * so RTL will always use the value corresponding to | |
2273 | * pat_sel = 000". | |
2274 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2275 | * MOCS still can be used though. | |
2276 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2277 | * before this patch, i.e. the same uncached + snooping access | |
2278 | * like on gen6/7 seems to be in effect. | |
2279 | * - So this just fixes blitter/render access. Again it looks | |
2280 | * like it's not just uncached access, but uncached + snooping. | |
2281 | * So we can still hold onto all our assumptions wrt cpu | |
2282 | * clflushing on LLC machines. | |
2283 | */ | |
2284 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2285 | ||
fbe5d36e BW |
2286 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2287 | * write would work. */ | |
2288 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2289 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2290 | } | |
2291 | ||
ee0ce478 VS |
2292 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2293 | { | |
2294 | uint64_t pat; | |
2295 | ||
2296 | /* | |
2297 | * Map WB on BDW to snooped on CHV. | |
2298 | * | |
2299 | * Only the snoop bit has meaning for CHV, the rest is | |
2300 | * ignored. | |
2301 | * | |
cf3d262e VS |
2302 | * The hardware will never snoop for certain types of accesses: |
2303 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2304 | * - PPGTT page tables | |
2305 | * - some other special cycles | |
2306 | * | |
2307 | * As with BDW, we also need to consider the following for GT accesses: | |
2308 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2309 | * so RTL will always use the value corresponding to | |
2310 | * pat_sel = 000". | |
2311 | * Which means we must set the snoop bit in PAT entry 0 | |
2312 | * in order to keep the global status page working. | |
ee0ce478 VS |
2313 | */ |
2314 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2315 | GEN8_PPAT(1, 0) | | |
2316 | GEN8_PPAT(2, 0) | | |
2317 | GEN8_PPAT(3, 0) | | |
2318 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2319 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2320 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2321 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2322 | ||
2323 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2324 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2325 | } | |
2326 | ||
63340133 BW |
2327 | static int gen8_gmch_probe(struct drm_device *dev, |
2328 | size_t *gtt_total, | |
2329 | size_t *stolen, | |
2330 | phys_addr_t *mappable_base, | |
2331 | unsigned long *mappable_end) | |
2332 | { | |
2333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2334 | unsigned int gtt_size; | |
2335 | u16 snb_gmch_ctl; | |
2336 | int ret; | |
2337 | ||
2338 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2339 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2340 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2341 | ||
2342 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2343 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2344 | ||
2345 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2346 | ||
66375014 DL |
2347 | if (INTEL_INFO(dev)->gen >= 9) { |
2348 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2349 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2350 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2351 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2352 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2353 | } else { | |
2354 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2355 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2356 | } | |
63340133 | 2357 | |
07749ef3 | 2358 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2359 | |
ee0ce478 VS |
2360 | if (IS_CHERRYVIEW(dev)) |
2361 | chv_setup_private_ppat(dev_priv); | |
2362 | else | |
2363 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2364 | |
63340133 BW |
2365 | ret = ggtt_probe_common(dev, gtt_size); |
2366 | ||
94ec8f61 BW |
2367 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2368 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2369 | |
2370 | return ret; | |
2371 | } | |
2372 | ||
baa09f5f BW |
2373 | static int gen6_gmch_probe(struct drm_device *dev, |
2374 | size_t *gtt_total, | |
41907ddc BW |
2375 | size_t *stolen, |
2376 | phys_addr_t *mappable_base, | |
2377 | unsigned long *mappable_end) | |
e76e9aeb BW |
2378 | { |
2379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2380 | unsigned int gtt_size; |
e76e9aeb | 2381 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2382 | int ret; |
2383 | ||
41907ddc BW |
2384 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2385 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2386 | ||
baa09f5f BW |
2387 | /* 64/512MB is the current min/max we actually know of, but this is just |
2388 | * a coarse sanity check. | |
e76e9aeb | 2389 | */ |
41907ddc | 2390 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2391 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2392 | dev_priv->gtt.mappable_end); | |
2393 | return -ENXIO; | |
e76e9aeb BW |
2394 | } |
2395 | ||
e76e9aeb BW |
2396 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2397 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2398 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2399 | |
c4ae25ec | 2400 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2401 | |
63340133 | 2402 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2403 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2404 | |
63340133 | 2405 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2406 | |
853ba5d2 BW |
2407 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2408 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2409 | |
e76e9aeb BW |
2410 | return ret; |
2411 | } | |
2412 | ||
853ba5d2 | 2413 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2414 | { |
853ba5d2 BW |
2415 | |
2416 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2417 | |
853ba5d2 BW |
2418 | iounmap(gtt->gsm); |
2419 | teardown_scratch_page(vm->dev); | |
644ec02b | 2420 | } |
baa09f5f BW |
2421 | |
2422 | static int i915_gmch_probe(struct drm_device *dev, | |
2423 | size_t *gtt_total, | |
41907ddc BW |
2424 | size_t *stolen, |
2425 | phys_addr_t *mappable_base, | |
2426 | unsigned long *mappable_end) | |
baa09f5f BW |
2427 | { |
2428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2429 | int ret; | |
2430 | ||
baa09f5f BW |
2431 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2432 | if (!ret) { | |
2433 | DRM_ERROR("failed to set up gmch\n"); | |
2434 | return -EIO; | |
2435 | } | |
2436 | ||
41907ddc | 2437 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2438 | |
2439 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2440 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2441 | |
c0a7f818 CW |
2442 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2443 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2444 | ||
baa09f5f BW |
2445 | return 0; |
2446 | } | |
2447 | ||
853ba5d2 | 2448 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2449 | { |
2450 | intel_gmch_remove(); | |
2451 | } | |
2452 | ||
2453 | int i915_gem_gtt_init(struct drm_device *dev) | |
2454 | { | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2457 | int ret; |
2458 | ||
baa09f5f | 2459 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2460 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2461 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2462 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2463 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2464 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2465 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2466 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2467 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2468 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2469 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2470 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2471 | else if (INTEL_INFO(dev)->gen >= 7) |
2472 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2473 | else |
350ec881 | 2474 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2475 | } else { |
2476 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2477 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2478 | } |
2479 | ||
853ba5d2 | 2480 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2481 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2482 | if (ret) |
baa09f5f | 2483 | return ret; |
baa09f5f | 2484 | |
853ba5d2 BW |
2485 | gtt->base.dev = dev; |
2486 | ||
baa09f5f | 2487 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2488 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2489 | gtt->base.total >> 20); | |
b2f21b4d BW |
2490 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2491 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2492 | #ifdef CONFIG_INTEL_IOMMU |
2493 | if (intel_iommu_gfx_mapped) | |
2494 | DRM_INFO("VT-d active for gfx access\n"); | |
2495 | #endif | |
cfa7c862 DV |
2496 | /* |
2497 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2498 | * user's requested state against the hardware/driver capabilities. We | |
2499 | * do this now so that we can print out any log messages once rather | |
2500 | * than every time we check intel_enable_ppgtt(). | |
2501 | */ | |
2502 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2503 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2504 | |
2505 | return 0; | |
2506 | } | |
6f65e29a | 2507 | |
ec7adb6e JL |
2508 | static struct i915_vma * |
2509 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2510 | struct i915_address_space *vm, | |
2511 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2512 | { |
dabde5c7 | 2513 | struct i915_vma *vma; |
6f65e29a | 2514 | |
ec7adb6e JL |
2515 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2516 | return ERR_PTR(-EINVAL); | |
dabde5c7 DC |
2517 | vma = kzalloc(sizeof(*vma), GFP_KERNEL); |
2518 | if (vma == NULL) | |
2519 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2520 | |
6f65e29a BW |
2521 | INIT_LIST_HEAD(&vma->vma_link); |
2522 | INIT_LIST_HEAD(&vma->mm_list); | |
2523 | INIT_LIST_HEAD(&vma->exec_list); | |
2524 | vma->vm = vm; | |
2525 | vma->obj = obj; | |
2526 | ||
b1252bcf | 2527 | if (INTEL_INFO(vm->dev)->gen >= 6) { |
7e0d96bc | 2528 | if (i915_is_ggtt(vm)) { |
ec7adb6e JL |
2529 | vma->ggtt_view = *ggtt_view; |
2530 | ||
7e0d96bc BW |
2531 | vma->unbind_vma = ggtt_unbind_vma; |
2532 | vma->bind_vma = ggtt_bind_vma; | |
2533 | } else { | |
2534 | vma->unbind_vma = ppgtt_unbind_vma; | |
2535 | vma->bind_vma = ppgtt_bind_vma; | |
2536 | } | |
b1252bcf | 2537 | } else { |
6f65e29a | 2538 | BUG_ON(!i915_is_ggtt(vm)); |
ec7adb6e | 2539 | vma->ggtt_view = *ggtt_view; |
6f65e29a BW |
2540 | vma->unbind_vma = i915_ggtt_unbind_vma; |
2541 | vma->bind_vma = i915_ggtt_bind_vma; | |
6f65e29a BW |
2542 | } |
2543 | ||
f7635669 TU |
2544 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2545 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2546 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2547 | |
2548 | return vma; | |
2549 | } | |
2550 | ||
2551 | struct i915_vma * | |
ec7adb6e JL |
2552 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2553 | struct i915_address_space *vm) | |
2554 | { | |
2555 | struct i915_vma *vma; | |
2556 | ||
2557 | vma = i915_gem_obj_to_vma(obj, vm); | |
2558 | if (!vma) | |
2559 | vma = __i915_gem_vma_create(obj, vm, | |
2560 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2561 | ||
2562 | return vma; | |
2563 | } | |
2564 | ||
2565 | struct i915_vma * | |
2566 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2567 | const struct i915_ggtt_view *view) |
6f65e29a | 2568 | { |
ec7adb6e | 2569 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2570 | struct i915_vma *vma; |
2571 | ||
ec7adb6e JL |
2572 | if (WARN_ON(!view)) |
2573 | return ERR_PTR(-EINVAL); | |
2574 | ||
2575 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2576 | ||
2577 | if (IS_ERR(vma)) | |
2578 | return vma; | |
2579 | ||
6f65e29a | 2580 | if (!vma) |
ec7adb6e | 2581 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2582 | |
2583 | return vma; | |
ec7adb6e | 2584 | |
6f65e29a | 2585 | } |
fe14d5f4 | 2586 | |
50470bb0 TU |
2587 | static void |
2588 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2589 | struct sg_table *st) | |
2590 | { | |
2591 | unsigned int column, row; | |
2592 | unsigned int src_idx; | |
2593 | struct scatterlist *sg = st->sgl; | |
2594 | ||
2595 | st->nents = 0; | |
2596 | ||
2597 | for (column = 0; column < width; column++) { | |
2598 | src_idx = width * (height - 1) + column; | |
2599 | for (row = 0; row < height; row++) { | |
2600 | st->nents++; | |
2601 | /* We don't need the pages, but need to initialize | |
2602 | * the entries so the sg list can be happily traversed. | |
2603 | * The only thing we need are DMA addresses. | |
2604 | */ | |
2605 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2606 | sg_dma_address(sg) = in[src_idx]; | |
2607 | sg_dma_len(sg) = PAGE_SIZE; | |
2608 | sg = sg_next(sg); | |
2609 | src_idx -= width; | |
2610 | } | |
2611 | } | |
2612 | } | |
2613 | ||
2614 | static struct sg_table * | |
2615 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2616 | struct drm_i915_gem_object *obj) | |
2617 | { | |
2618 | struct drm_device *dev = obj->base.dev; | |
2619 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; | |
2620 | unsigned long size, pages, rot_pages; | |
2621 | struct sg_page_iter sg_iter; | |
2622 | unsigned long i; | |
2623 | dma_addr_t *page_addr_list; | |
2624 | struct sg_table *st; | |
2625 | unsigned int tile_pitch, tile_height; | |
2626 | unsigned int width_pages, height_pages; | |
1d00dad5 | 2627 | int ret = -ENOMEM; |
50470bb0 TU |
2628 | |
2629 | pages = obj->base.size / PAGE_SIZE; | |
2630 | ||
2631 | /* Calculate tiling geometry. */ | |
2632 | tile_height = intel_tile_height(dev, rot_info->pixel_format, | |
2633 | rot_info->fb_modifier); | |
2634 | tile_pitch = PAGE_SIZE / tile_height; | |
2635 | width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); | |
2636 | height_pages = DIV_ROUND_UP(rot_info->height, tile_height); | |
2637 | rot_pages = width_pages * height_pages; | |
2638 | size = rot_pages * PAGE_SIZE; | |
2639 | ||
2640 | /* Allocate a temporary list of source pages for random access. */ | |
2641 | page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); | |
2642 | if (!page_addr_list) | |
2643 | return ERR_PTR(ret); | |
2644 | ||
2645 | /* Allocate target SG list. */ | |
2646 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2647 | if (!st) | |
2648 | goto err_st_alloc; | |
2649 | ||
2650 | ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); | |
2651 | if (ret) | |
2652 | goto err_sg_alloc; | |
2653 | ||
2654 | /* Populate source page list from the object. */ | |
2655 | i = 0; | |
2656 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2657 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2658 | i++; | |
2659 | } | |
2660 | ||
2661 | /* Rotate the pages. */ | |
2662 | rotate_pages(page_addr_list, width_pages, height_pages, st); | |
2663 | ||
2664 | DRM_DEBUG_KMS( | |
2665 | "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", | |
2666 | size, rot_info->pitch, rot_info->height, | |
2667 | rot_info->pixel_format, width_pages, height_pages, | |
2668 | rot_pages); | |
2669 | ||
2670 | drm_free_large(page_addr_list); | |
2671 | ||
2672 | return st; | |
2673 | ||
2674 | err_sg_alloc: | |
2675 | kfree(st); | |
2676 | err_st_alloc: | |
2677 | drm_free_large(page_addr_list); | |
2678 | ||
2679 | DRM_DEBUG_KMS( | |
2680 | "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", | |
2681 | size, ret, rot_info->pitch, rot_info->height, | |
2682 | rot_info->pixel_format, width_pages, height_pages, | |
2683 | rot_pages); | |
2684 | return ERR_PTR(ret); | |
2685 | } | |
ec7adb6e | 2686 | |
50470bb0 TU |
2687 | static inline int |
2688 | i915_get_ggtt_vma_pages(struct i915_vma *vma) | |
fe14d5f4 | 2689 | { |
50470bb0 TU |
2690 | int ret = 0; |
2691 | ||
fe14d5f4 TU |
2692 | if (vma->ggtt_view.pages) |
2693 | return 0; | |
2694 | ||
2695 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2696 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2697 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2698 | vma->ggtt_view.pages = | |
2699 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2700 | else |
2701 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2702 | vma->ggtt_view.type); | |
2703 | ||
2704 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2705 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2706 | vma->ggtt_view.type); |
50470bb0 TU |
2707 | ret = -EINVAL; |
2708 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2709 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2710 | vma->ggtt_view.pages = NULL; | |
2711 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2712 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2713 | } |
2714 | ||
50470bb0 | 2715 | return ret; |
fe14d5f4 TU |
2716 | } |
2717 | ||
2718 | /** | |
2719 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2720 | * @vma: VMA to map | |
2721 | * @cache_level: mapping cache level | |
2722 | * @flags: flags like global or local mapping | |
2723 | * | |
2724 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2725 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2726 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2727 | */ | |
2728 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2729 | u32 flags) | |
2730 | { | |
ec7adb6e JL |
2731 | if (i915_is_ggtt(vma->vm)) { |
2732 | int ret = i915_get_ggtt_vma_pages(vma); | |
fe14d5f4 | 2733 | |
ec7adb6e JL |
2734 | if (ret) |
2735 | return ret; | |
2736 | } | |
fe14d5f4 TU |
2737 | |
2738 | vma->bind_vma(vma, cache_level, flags); | |
2739 | ||
2740 | return 0; | |
2741 | } |