]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
106 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
107 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
108 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
109 | int num_connectors); | |
e7457a9a | 110 | |
0e32b39c DA |
111 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
112 | { | |
113 | if (!connector->mst_port) | |
114 | return connector->encoder; | |
115 | else | |
116 | return &connector->mst_port->mst_encoders[pipe]->base; | |
117 | } | |
118 | ||
79e53945 | 119 | typedef struct { |
0206e353 | 120 | int min, max; |
79e53945 JB |
121 | } intel_range_t; |
122 | ||
123 | typedef struct { | |
0206e353 AJ |
124 | int dot_limit; |
125 | int p2_slow, p2_fast; | |
79e53945 JB |
126 | } intel_p2_t; |
127 | ||
d4906093 ML |
128 | typedef struct intel_limit intel_limit_t; |
129 | struct intel_limit { | |
0206e353 AJ |
130 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
131 | intel_p2_t p2; | |
d4906093 | 132 | }; |
79e53945 | 133 | |
d2acd215 DV |
134 | int |
135 | intel_pch_rawclk(struct drm_device *dev) | |
136 | { | |
137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
138 | ||
139 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
140 | ||
141 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
142 | } | |
143 | ||
021357ac CW |
144 | static inline u32 /* units of 100MHz */ |
145 | intel_fdi_link_freq(struct drm_device *dev) | |
146 | { | |
8b99e68c CW |
147 | if (IS_GEN5(dev)) { |
148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
149 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
150 | } else | |
151 | return 27; | |
021357ac CW |
152 | } |
153 | ||
5d536e28 | 154 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 155 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 156 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 157 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
158 | .m = { .min = 96, .max = 140 }, |
159 | .m1 = { .min = 18, .max = 26 }, | |
160 | .m2 = { .min = 6, .max = 16 }, | |
161 | .p = { .min = 4, .max = 128 }, | |
162 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 165000, |
164 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
165 | }; |
166 | ||
5d536e28 DV |
167 | static const intel_limit_t intel_limits_i8xx_dvo = { |
168 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 169 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 170 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
171 | .m = { .min = 96, .max = 140 }, |
172 | .m1 = { .min = 18, .max = 26 }, | |
173 | .m2 = { .min = 6, .max = 16 }, | |
174 | .p = { .min = 4, .max = 128 }, | |
175 | .p1 = { .min = 2, .max = 33 }, | |
176 | .p2 = { .dot_limit = 165000, | |
177 | .p2_slow = 4, .p2_fast = 4 }, | |
178 | }; | |
179 | ||
e4b36699 | 180 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 181 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 182 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 183 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
184 | .m = { .min = 96, .max = 140 }, |
185 | .m1 = { .min = 18, .max = 26 }, | |
186 | .m2 = { .min = 6, .max = 16 }, | |
187 | .p = { .min = 4, .max = 128 }, | |
188 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
189 | .p2 = { .dot_limit = 165000, |
190 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 191 | }; |
273e27ca | 192 | |
e4b36699 | 193 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
194 | .dot = { .min = 20000, .max = 400000 }, |
195 | .vco = { .min = 1400000, .max = 2800000 }, | |
196 | .n = { .min = 1, .max = 6 }, | |
197 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
198 | .m1 = { .min = 8, .max = 18 }, |
199 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
200 | .p = { .min = 5, .max = 80 }, |
201 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
202 | .p2 = { .dot_limit = 200000, |
203 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
204 | }; |
205 | ||
206 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
207 | .dot = { .min = 20000, .max = 400000 }, |
208 | .vco = { .min = 1400000, .max = 2800000 }, | |
209 | .n = { .min = 1, .max = 6 }, | |
210 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
211 | .m1 = { .min = 8, .max = 18 }, |
212 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
213 | .p = { .min = 7, .max = 98 }, |
214 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
215 | .p2 = { .dot_limit = 112000, |
216 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
217 | }; |
218 | ||
273e27ca | 219 | |
e4b36699 | 220 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
221 | .dot = { .min = 25000, .max = 270000 }, |
222 | .vco = { .min = 1750000, .max = 3500000}, | |
223 | .n = { .min = 1, .max = 4 }, | |
224 | .m = { .min = 104, .max = 138 }, | |
225 | .m1 = { .min = 17, .max = 23 }, | |
226 | .m2 = { .min = 5, .max = 11 }, | |
227 | .p = { .min = 10, .max = 30 }, | |
228 | .p1 = { .min = 1, .max = 3}, | |
229 | .p2 = { .dot_limit = 270000, | |
230 | .p2_slow = 10, | |
231 | .p2_fast = 10 | |
044c7c41 | 232 | }, |
e4b36699 KP |
233 | }; |
234 | ||
235 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
236 | .dot = { .min = 22000, .max = 400000 }, |
237 | .vco = { .min = 1750000, .max = 3500000}, | |
238 | .n = { .min = 1, .max = 4 }, | |
239 | .m = { .min = 104, .max = 138 }, | |
240 | .m1 = { .min = 16, .max = 23 }, | |
241 | .m2 = { .min = 5, .max = 11 }, | |
242 | .p = { .min = 5, .max = 80 }, | |
243 | .p1 = { .min = 1, .max = 8}, | |
244 | .p2 = { .dot_limit = 165000, | |
245 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
246 | }; |
247 | ||
248 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
249 | .dot = { .min = 20000, .max = 115000 }, |
250 | .vco = { .min = 1750000, .max = 3500000 }, | |
251 | .n = { .min = 1, .max = 3 }, | |
252 | .m = { .min = 104, .max = 138 }, | |
253 | .m1 = { .min = 17, .max = 23 }, | |
254 | .m2 = { .min = 5, .max = 11 }, | |
255 | .p = { .min = 28, .max = 112 }, | |
256 | .p1 = { .min = 2, .max = 8 }, | |
257 | .p2 = { .dot_limit = 0, | |
258 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 259 | }, |
e4b36699 KP |
260 | }; |
261 | ||
262 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
263 | .dot = { .min = 80000, .max = 224000 }, |
264 | .vco = { .min = 1750000, .max = 3500000 }, | |
265 | .n = { .min = 1, .max = 3 }, | |
266 | .m = { .min = 104, .max = 138 }, | |
267 | .m1 = { .min = 17, .max = 23 }, | |
268 | .m2 = { .min = 5, .max = 11 }, | |
269 | .p = { .min = 14, .max = 42 }, | |
270 | .p1 = { .min = 2, .max = 6 }, | |
271 | .p2 = { .dot_limit = 0, | |
272 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 273 | }, |
e4b36699 KP |
274 | }; |
275 | ||
f2b115e6 | 276 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
277 | .dot = { .min = 20000, .max = 400000}, |
278 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 279 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
280 | .n = { .min = 3, .max = 6 }, |
281 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 282 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
283 | .m1 = { .min = 0, .max = 0 }, |
284 | .m2 = { .min = 0, .max = 254 }, | |
285 | .p = { .min = 5, .max = 80 }, | |
286 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
287 | .p2 = { .dot_limit = 200000, |
288 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
289 | }; |
290 | ||
f2b115e6 | 291 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
292 | .dot = { .min = 20000, .max = 400000 }, |
293 | .vco = { .min = 1700000, .max = 3500000 }, | |
294 | .n = { .min = 3, .max = 6 }, | |
295 | .m = { .min = 2, .max = 256 }, | |
296 | .m1 = { .min = 0, .max = 0 }, | |
297 | .m2 = { .min = 0, .max = 254 }, | |
298 | .p = { .min = 7, .max = 112 }, | |
299 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
300 | .p2 = { .dot_limit = 112000, |
301 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
302 | }; |
303 | ||
273e27ca EA |
304 | /* Ironlake / Sandybridge |
305 | * | |
306 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
307 | * the range value for them is (actual_value - 2). | |
308 | */ | |
b91ad0ec | 309 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
310 | .dot = { .min = 25000, .max = 350000 }, |
311 | .vco = { .min = 1760000, .max = 3510000 }, | |
312 | .n = { .min = 1, .max = 5 }, | |
313 | .m = { .min = 79, .max = 127 }, | |
314 | .m1 = { .min = 12, .max = 22 }, | |
315 | .m2 = { .min = 5, .max = 9 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8 }, | |
318 | .p2 = { .dot_limit = 225000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
b91ad0ec | 322 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
323 | .dot = { .min = 25000, .max = 350000 }, |
324 | .vco = { .min = 1760000, .max = 3510000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 79, .max = 118 }, | |
327 | .m1 = { .min = 12, .max = 22 }, | |
328 | .m2 = { .min = 5, .max = 9 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 225000, | |
332 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
333 | }; |
334 | ||
335 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
336 | .dot = { .min = 25000, .max = 350000 }, |
337 | .vco = { .min = 1760000, .max = 3510000 }, | |
338 | .n = { .min = 1, .max = 3 }, | |
339 | .m = { .min = 79, .max = 127 }, | |
340 | .m1 = { .min = 12, .max = 22 }, | |
341 | .m2 = { .min = 5, .max = 9 }, | |
342 | .p = { .min = 14, .max = 56 }, | |
343 | .p1 = { .min = 2, .max = 8 }, | |
344 | .p2 = { .dot_limit = 225000, | |
345 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
346 | }; |
347 | ||
273e27ca | 348 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 349 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000 }, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 79, .max = 126 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 357 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
358 | .p2 = { .dot_limit = 225000, |
359 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
360 | }; |
361 | ||
362 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
363 | .dot = { .min = 25000, .max = 350000 }, |
364 | .vco = { .min = 1760000, .max = 3510000 }, | |
365 | .n = { .min = 1, .max = 3 }, | |
366 | .m = { .min = 79, .max = 126 }, | |
367 | .m1 = { .min = 12, .max = 22 }, | |
368 | .m2 = { .min = 5, .max = 9 }, | |
369 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 370 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
371 | .p2 = { .dot_limit = 225000, |
372 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
373 | }; |
374 | ||
dc730512 | 375 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
376 | /* |
377 | * These are the data rate limits (measured in fast clocks) | |
378 | * since those are the strictest limits we have. The fast | |
379 | * clock and actual rate limits are more relaxed, so checking | |
380 | * them would make no difference. | |
381 | */ | |
382 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 383 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 384 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
385 | .m1 = { .min = 2, .max = 3 }, |
386 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 387 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 388 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
389 | }; |
390 | ||
ef9348c8 CML |
391 | static const intel_limit_t intel_limits_chv = { |
392 | /* | |
393 | * These are the data rate limits (measured in fast clocks) | |
394 | * since those are the strictest limits we have. The fast | |
395 | * clock and actual rate limits are more relaxed, so checking | |
396 | * them would make no difference. | |
397 | */ | |
398 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 399 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
400 | .n = { .min = 1, .max = 1 }, |
401 | .m1 = { .min = 2, .max = 2 }, | |
402 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
403 | .p1 = { .min = 2, .max = 4 }, | |
404 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
405 | }; | |
406 | ||
5ab7b0b7 ID |
407 | static const intel_limit_t intel_limits_bxt = { |
408 | /* FIXME: find real dot limits */ | |
409 | .dot = { .min = 0, .max = INT_MAX }, | |
410 | .vco = { .min = 4800000, .max = 6480000 }, | |
411 | .n = { .min = 1, .max = 1 }, | |
412 | .m1 = { .min = 2, .max = 2 }, | |
413 | /* FIXME: find real m2 limits */ | |
414 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
415 | .p1 = { .min = 2, .max = 4 }, | |
416 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
417 | }; | |
418 | ||
6b4bf1c4 VS |
419 | static void vlv_clock(int refclk, intel_clock_t *clock) |
420 | { | |
421 | clock->m = clock->m1 * clock->m2; | |
422 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
423 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
424 | return; | |
fb03ac01 VS |
425 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
426 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
427 | } |
428 | ||
e0638cdf PZ |
429 | /** |
430 | * Returns whether any output on the specified pipe is of the specified type | |
431 | */ | |
4093561b | 432 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 433 | { |
409ee761 | 434 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
435 | struct intel_encoder *encoder; |
436 | ||
409ee761 | 437 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
438 | if (encoder->type == type) |
439 | return true; | |
440 | ||
441 | return false; | |
442 | } | |
443 | ||
d0737e1d ACO |
444 | /** |
445 | * Returns whether any output on the specified pipe will have the specified | |
446 | * type after a staged modeset is complete, i.e., the same as | |
447 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
448 | * encoder->crtc. | |
449 | */ | |
a93e255f ACO |
450 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
451 | int type) | |
d0737e1d | 452 | { |
a93e255f ACO |
453 | struct drm_atomic_state *state = crtc_state->base.state; |
454 | struct drm_connector_state *connector_state; | |
d0737e1d | 455 | struct intel_encoder *encoder; |
a93e255f ACO |
456 | int i, num_connectors = 0; |
457 | ||
458 | for (i = 0; i < state->num_connector; i++) { | |
459 | if (!state->connectors[i]) | |
460 | continue; | |
461 | ||
462 | connector_state = state->connector_states[i]; | |
463 | if (connector_state->crtc != crtc_state->base.crtc) | |
464 | continue; | |
465 | ||
466 | num_connectors++; | |
d0737e1d | 467 | |
a93e255f ACO |
468 | encoder = to_intel_encoder(connector_state->best_encoder); |
469 | if (encoder->type == type) | |
d0737e1d | 470 | return true; |
a93e255f ACO |
471 | } |
472 | ||
473 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
474 | |
475 | return false; | |
476 | } | |
477 | ||
a93e255f ACO |
478 | static const intel_limit_t * |
479 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 480 | { |
a93e255f | 481 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 482 | const intel_limit_t *limit; |
b91ad0ec | 483 | |
a93e255f | 484 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 485 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 486 | if (refclk == 100000) |
b91ad0ec ZW |
487 | limit = &intel_limits_ironlake_dual_lvds_100m; |
488 | else | |
489 | limit = &intel_limits_ironlake_dual_lvds; | |
490 | } else { | |
1b894b59 | 491 | if (refclk == 100000) |
b91ad0ec ZW |
492 | limit = &intel_limits_ironlake_single_lvds_100m; |
493 | else | |
494 | limit = &intel_limits_ironlake_single_lvds; | |
495 | } | |
c6bb3538 | 496 | } else |
b91ad0ec | 497 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
498 | |
499 | return limit; | |
500 | } | |
501 | ||
a93e255f ACO |
502 | static const intel_limit_t * |
503 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 504 | { |
a93e255f | 505 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
506 | const intel_limit_t *limit; |
507 | ||
a93e255f | 508 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 509 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 510 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 511 | else |
e4b36699 | 512 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
513 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
514 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 515 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 516 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 517 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 518 | } else /* The option is for other outputs */ |
e4b36699 | 519 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
520 | |
521 | return limit; | |
522 | } | |
523 | ||
a93e255f ACO |
524 | static const intel_limit_t * |
525 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 526 | { |
a93e255f | 527 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
528 | const intel_limit_t *limit; |
529 | ||
5ab7b0b7 ID |
530 | if (IS_BROXTON(dev)) |
531 | limit = &intel_limits_bxt; | |
532 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 533 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 534 | else if (IS_G4X(dev)) { |
a93e255f | 535 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 536 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 537 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 538 | limit = &intel_limits_pineview_lvds; |
2177832f | 539 | else |
f2b115e6 | 540 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
541 | } else if (IS_CHERRYVIEW(dev)) { |
542 | limit = &intel_limits_chv; | |
a0c4da24 | 543 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 544 | limit = &intel_limits_vlv; |
a6c45cf0 | 545 | } else if (!IS_GEN2(dev)) { |
a93e255f | 546 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
547 | limit = &intel_limits_i9xx_lvds; |
548 | else | |
549 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 550 | } else { |
a93e255f | 551 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 552 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 553 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 554 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
555 | else |
556 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
557 | } |
558 | return limit; | |
559 | } | |
560 | ||
f2b115e6 AJ |
561 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
562 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 563 | { |
2177832f SL |
564 | clock->m = clock->m2 + 2; |
565 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
566 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
567 | return; | |
fb03ac01 VS |
568 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
569 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
570 | } |
571 | ||
7429e9d4 DV |
572 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
573 | { | |
574 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
575 | } | |
576 | ||
ac58c3f0 | 577 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 578 | { |
7429e9d4 | 579 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 580 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
581 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
582 | return; | |
fb03ac01 VS |
583 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
584 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
585 | } |
586 | ||
ef9348c8 CML |
587 | static void chv_clock(int refclk, intel_clock_t *clock) |
588 | { | |
589 | clock->m = clock->m1 * clock->m2; | |
590 | clock->p = clock->p1 * clock->p2; | |
591 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
592 | return; | |
593 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
594 | clock->n << 22); | |
595 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
596 | } | |
597 | ||
7c04d1d9 | 598 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
599 | /** |
600 | * Returns whether the given set of divisors are valid for a given refclk with | |
601 | * the given connectors. | |
602 | */ | |
603 | ||
1b894b59 CW |
604 | static bool intel_PLL_is_valid(struct drm_device *dev, |
605 | const intel_limit_t *limit, | |
606 | const intel_clock_t *clock) | |
79e53945 | 607 | { |
f01b7962 VS |
608 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
609 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 610 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 611 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 612 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 613 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 614 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 615 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 616 | |
5ab7b0b7 | 617 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
5ab7b0b7 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
d4906093 | 639 | static bool |
a93e255f ACO |
640 | i9xx_find_best_dpll(const intel_limit_t *limit, |
641 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
642 | int target, int refclk, intel_clock_t *match_clock, |
643 | intel_clock_t *best_clock) | |
79e53945 | 644 | { |
a93e255f | 645 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 646 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 647 | intel_clock_t clock; |
79e53945 JB |
648 | int err = target; |
649 | ||
a93e255f | 650 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 651 | /* |
a210b028 DV |
652 | * For LVDS just rely on its current settings for dual-channel. |
653 | * We haven't figured out how to reliably set up different | |
654 | * single/dual channel state, if we even can. | |
79e53945 | 655 | */ |
1974cad0 | 656 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
657 | clock.p2 = limit->p2.p2_fast; |
658 | else | |
659 | clock.p2 = limit->p2.p2_slow; | |
660 | } else { | |
661 | if (target < limit->p2.dot_limit) | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | else | |
664 | clock.p2 = limit->p2.p2_fast; | |
665 | } | |
666 | ||
0206e353 | 667 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 668 | |
42158660 ZY |
669 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
670 | clock.m1++) { | |
671 | for (clock.m2 = limit->m2.min; | |
672 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 673 | if (clock.m2 >= clock.m1) |
42158660 ZY |
674 | break; |
675 | for (clock.n = limit->n.min; | |
676 | clock.n <= limit->n.max; clock.n++) { | |
677 | for (clock.p1 = limit->p1.min; | |
678 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
679 | int this_err; |
680 | ||
ac58c3f0 DV |
681 | i9xx_clock(refclk, &clock); |
682 | if (!intel_PLL_is_valid(dev, limit, | |
683 | &clock)) | |
684 | continue; | |
685 | if (match_clock && | |
686 | clock.p != match_clock->p) | |
687 | continue; | |
688 | ||
689 | this_err = abs(clock.dot - target); | |
690 | if (this_err < err) { | |
691 | *best_clock = clock; | |
692 | err = this_err; | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | ||
699 | return (err != target); | |
700 | } | |
701 | ||
702 | static bool | |
a93e255f ACO |
703 | pnv_find_best_dpll(const intel_limit_t *limit, |
704 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
705 | int target, int refclk, intel_clock_t *match_clock, |
706 | intel_clock_t *best_clock) | |
79e53945 | 707 | { |
a93e255f | 708 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 709 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 710 | intel_clock_t clock; |
79e53945 JB |
711 | int err = target; |
712 | ||
a93e255f | 713 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 714 | /* |
a210b028 DV |
715 | * For LVDS just rely on its current settings for dual-channel. |
716 | * We haven't figured out how to reliably set up different | |
717 | * single/dual channel state, if we even can. | |
79e53945 | 718 | */ |
1974cad0 | 719 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
720 | clock.p2 = limit->p2.p2_fast; |
721 | else | |
722 | clock.p2 = limit->p2.p2_slow; | |
723 | } else { | |
724 | if (target < limit->p2.dot_limit) | |
725 | clock.p2 = limit->p2.p2_slow; | |
726 | else | |
727 | clock.p2 = limit->p2.p2_fast; | |
728 | } | |
729 | ||
0206e353 | 730 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 731 | |
42158660 ZY |
732 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
733 | clock.m1++) { | |
734 | for (clock.m2 = limit->m2.min; | |
735 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
736 | for (clock.n = limit->n.min; |
737 | clock.n <= limit->n.max; clock.n++) { | |
738 | for (clock.p1 = limit->p1.min; | |
739 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
740 | int this_err; |
741 | ||
ac58c3f0 | 742 | pineview_clock(refclk, &clock); |
1b894b59 CW |
743 | if (!intel_PLL_is_valid(dev, limit, |
744 | &clock)) | |
79e53945 | 745 | continue; |
cec2f356 SP |
746 | if (match_clock && |
747 | clock.p != match_clock->p) | |
748 | continue; | |
79e53945 JB |
749 | |
750 | this_err = abs(clock.dot - target); | |
751 | if (this_err < err) { | |
752 | *best_clock = clock; | |
753 | err = this_err; | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | return (err != target); | |
761 | } | |
762 | ||
d4906093 | 763 | static bool |
a93e255f ACO |
764 | g4x_find_best_dpll(const intel_limit_t *limit, |
765 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
766 | int target, int refclk, intel_clock_t *match_clock, |
767 | intel_clock_t *best_clock) | |
d4906093 | 768 | { |
a93e255f | 769 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 770 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
771 | intel_clock_t clock; |
772 | int max_n; | |
773 | bool found; | |
6ba770dc AJ |
774 | /* approximately equals target * 0.00585 */ |
775 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
776 | found = false; |
777 | ||
a93e255f | 778 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 779 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
780 | clock.p2 = limit->p2.p2_fast; |
781 | else | |
782 | clock.p2 = limit->p2.p2_slow; | |
783 | } else { | |
784 | if (target < limit->p2.dot_limit) | |
785 | clock.p2 = limit->p2.p2_slow; | |
786 | else | |
787 | clock.p2 = limit->p2.p2_fast; | |
788 | } | |
789 | ||
790 | memset(best_clock, 0, sizeof(*best_clock)); | |
791 | max_n = limit->n.max; | |
f77f13e2 | 792 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 793 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 794 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
795 | for (clock.m1 = limit->m1.max; |
796 | clock.m1 >= limit->m1.min; clock.m1--) { | |
797 | for (clock.m2 = limit->m2.max; | |
798 | clock.m2 >= limit->m2.min; clock.m2--) { | |
799 | for (clock.p1 = limit->p1.max; | |
800 | clock.p1 >= limit->p1.min; clock.p1--) { | |
801 | int this_err; | |
802 | ||
ac58c3f0 | 803 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
804 | if (!intel_PLL_is_valid(dev, limit, |
805 | &clock)) | |
d4906093 | 806 | continue; |
1b894b59 CW |
807 | |
808 | this_err = abs(clock.dot - target); | |
d4906093 ML |
809 | if (this_err < err_most) { |
810 | *best_clock = clock; | |
811 | err_most = this_err; | |
812 | max_n = clock.n; | |
813 | found = true; | |
814 | } | |
815 | } | |
816 | } | |
817 | } | |
818 | } | |
2c07245f ZW |
819 | return found; |
820 | } | |
821 | ||
d5dd62bd ID |
822 | /* |
823 | * Check if the calculated PLL configuration is more optimal compared to the | |
824 | * best configuration and error found so far. Return the calculated error. | |
825 | */ | |
826 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
827 | const intel_clock_t *calculated_clock, | |
828 | const intel_clock_t *best_clock, | |
829 | unsigned int best_error_ppm, | |
830 | unsigned int *error_ppm) | |
831 | { | |
9ca3ba01 ID |
832 | /* |
833 | * For CHV ignore the error and consider only the P value. | |
834 | * Prefer a bigger P value based on HW requirements. | |
835 | */ | |
836 | if (IS_CHERRYVIEW(dev)) { | |
837 | *error_ppm = 0; | |
838 | ||
839 | return calculated_clock->p > best_clock->p; | |
840 | } | |
841 | ||
24be4e46 ID |
842 | if (WARN_ON_ONCE(!target_freq)) |
843 | return false; | |
844 | ||
d5dd62bd ID |
845 | *error_ppm = div_u64(1000000ULL * |
846 | abs(target_freq - calculated_clock->dot), | |
847 | target_freq); | |
848 | /* | |
849 | * Prefer a better P value over a better (smaller) error if the error | |
850 | * is small. Ensure this preference for future configurations too by | |
851 | * setting the error to 0. | |
852 | */ | |
853 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
854 | *error_ppm = 0; | |
855 | ||
856 | return true; | |
857 | } | |
858 | ||
859 | return *error_ppm + 10 < best_error_ppm; | |
860 | } | |
861 | ||
a0c4da24 | 862 | static bool |
a93e255f ACO |
863 | vlv_find_best_dpll(const intel_limit_t *limit, |
864 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
865 | int target, int refclk, intel_clock_t *match_clock, |
866 | intel_clock_t *best_clock) | |
a0c4da24 | 867 | { |
a93e255f | 868 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 869 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 870 | intel_clock_t clock; |
69e4f900 | 871 | unsigned int bestppm = 1000000; |
27e639bf VS |
872 | /* min update 19.2 MHz */ |
873 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 874 | bool found = false; |
a0c4da24 | 875 | |
6b4bf1c4 VS |
876 | target *= 5; /* fast clock */ |
877 | ||
878 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
879 | |
880 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 881 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 882 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 883 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 884 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 885 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 886 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 887 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 888 | unsigned int ppm; |
69e4f900 | 889 | |
6b4bf1c4 VS |
890 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
891 | refclk * clock.m1); | |
892 | ||
893 | vlv_clock(refclk, &clock); | |
43b0ac53 | 894 | |
f01b7962 VS |
895 | if (!intel_PLL_is_valid(dev, limit, |
896 | &clock)) | |
43b0ac53 VS |
897 | continue; |
898 | ||
d5dd62bd ID |
899 | if (!vlv_PLL_is_optimal(dev, target, |
900 | &clock, | |
901 | best_clock, | |
902 | bestppm, &ppm)) | |
903 | continue; | |
6b4bf1c4 | 904 | |
d5dd62bd ID |
905 | *best_clock = clock; |
906 | bestppm = ppm; | |
907 | found = true; | |
a0c4da24 JB |
908 | } |
909 | } | |
910 | } | |
911 | } | |
a0c4da24 | 912 | |
49e497ef | 913 | return found; |
a0c4da24 | 914 | } |
a4fc5ed6 | 915 | |
ef9348c8 | 916 | static bool |
a93e255f ACO |
917 | chv_find_best_dpll(const intel_limit_t *limit, |
918 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
919 | int target, int refclk, intel_clock_t *match_clock, |
920 | intel_clock_t *best_clock) | |
921 | { | |
a93e255f | 922 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 923 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 924 | unsigned int best_error_ppm; |
ef9348c8 CML |
925 | intel_clock_t clock; |
926 | uint64_t m2; | |
927 | int found = false; | |
928 | ||
929 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 930 | best_error_ppm = 1000000; |
ef9348c8 CML |
931 | |
932 | /* | |
933 | * Based on hardware doc, the n always set to 1, and m1 always | |
934 | * set to 2. If requires to support 200Mhz refclk, we need to | |
935 | * revisit this because n may not 1 anymore. | |
936 | */ | |
937 | clock.n = 1, clock.m1 = 2; | |
938 | target *= 5; /* fast clock */ | |
939 | ||
940 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
941 | for (clock.p2 = limit->p2.p2_fast; | |
942 | clock.p2 >= limit->p2.p2_slow; | |
943 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 944 | unsigned int error_ppm; |
ef9348c8 CML |
945 | |
946 | clock.p = clock.p1 * clock.p2; | |
947 | ||
948 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
949 | clock.n) << 22, refclk * clock.m1); | |
950 | ||
951 | if (m2 > INT_MAX/clock.m1) | |
952 | continue; | |
953 | ||
954 | clock.m2 = m2; | |
955 | ||
956 | chv_clock(refclk, &clock); | |
957 | ||
958 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
959 | continue; | |
960 | ||
9ca3ba01 ID |
961 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
962 | best_error_ppm, &error_ppm)) | |
963 | continue; | |
964 | ||
965 | *best_clock = clock; | |
966 | best_error_ppm = error_ppm; | |
967 | found = true; | |
ef9348c8 CML |
968 | } |
969 | } | |
970 | ||
971 | return found; | |
972 | } | |
973 | ||
5ab7b0b7 ID |
974 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
975 | intel_clock_t *best_clock) | |
976 | { | |
977 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
978 | ||
979 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
980 | target_clock, refclk, NULL, best_clock); | |
981 | } | |
982 | ||
20ddf665 VS |
983 | bool intel_crtc_active(struct drm_crtc *crtc) |
984 | { | |
985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
986 | ||
987 | /* Be paranoid as we can arrive here with only partial | |
988 | * state retrieved from the hardware during setup. | |
989 | * | |
241bfc38 | 990 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
991 | * as Haswell has gained clock readout/fastboot support. |
992 | * | |
66e514c1 | 993 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 994 | * properly reconstruct framebuffers. |
c3d1f436 MR |
995 | * |
996 | * FIXME: The intel_crtc->active here should be switched to | |
997 | * crtc->state->active once we have proper CRTC states wired up | |
998 | * for atomic. | |
20ddf665 | 999 | */ |
c3d1f436 | 1000 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1001 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1002 | } |
1003 | ||
a5c961d1 PZ |
1004 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1005 | enum pipe pipe) | |
1006 | { | |
1007 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
6e3c9717 | 1010 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1011 | } |
1012 | ||
fbf49ea2 VS |
1013 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1014 | { | |
1015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1016 | u32 reg = PIPEDSL(pipe); | |
1017 | u32 line1, line2; | |
1018 | u32 line_mask; | |
1019 | ||
1020 | if (IS_GEN2(dev)) | |
1021 | line_mask = DSL_LINEMASK_GEN2; | |
1022 | else | |
1023 | line_mask = DSL_LINEMASK_GEN3; | |
1024 | ||
1025 | line1 = I915_READ(reg) & line_mask; | |
1026 | mdelay(5); | |
1027 | line2 = I915_READ(reg) & line_mask; | |
1028 | ||
1029 | return line1 == line2; | |
1030 | } | |
1031 | ||
ab7ad7f6 KP |
1032 | /* |
1033 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1034 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1035 | * |
1036 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1037 | * spinning on the vblank interrupt status bit, since we won't actually | |
1038 | * see an interrupt when the pipe is disabled. | |
1039 | * | |
ab7ad7f6 KP |
1040 | * On Gen4 and above: |
1041 | * wait for the pipe register state bit to turn off | |
1042 | * | |
1043 | * Otherwise: | |
1044 | * wait for the display line value to settle (it usually | |
1045 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1046 | * |
9d0498a2 | 1047 | */ |
575f7ab7 | 1048 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1049 | { |
575f7ab7 | 1050 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1051 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1052 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1053 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1054 | |
1055 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1056 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1057 | |
1058 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1059 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1060 | 100)) | |
284637d9 | 1061 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1062 | } else { |
ab7ad7f6 | 1063 | /* Wait for the display line to settle */ |
fbf49ea2 | 1064 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1065 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1066 | } |
79e53945 JB |
1067 | } |
1068 | ||
b0ea7d37 DL |
1069 | /* |
1070 | * ibx_digital_port_connected - is the specified port connected? | |
1071 | * @dev_priv: i915 private structure | |
1072 | * @port: the port to test | |
1073 | * | |
1074 | * Returns true if @port is connected, false otherwise. | |
1075 | */ | |
1076 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1077 | struct intel_digital_port *port) | |
1078 | { | |
1079 | u32 bit; | |
1080 | ||
c36346e3 | 1081 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1082 | switch (port->port) { |
c36346e3 DL |
1083 | case PORT_B: |
1084 | bit = SDE_PORTB_HOTPLUG; | |
1085 | break; | |
1086 | case PORT_C: | |
1087 | bit = SDE_PORTC_HOTPLUG; | |
1088 | break; | |
1089 | case PORT_D: | |
1090 | bit = SDE_PORTD_HOTPLUG; | |
1091 | break; | |
1092 | default: | |
1093 | return true; | |
1094 | } | |
1095 | } else { | |
eba905b2 | 1096 | switch (port->port) { |
c36346e3 DL |
1097 | case PORT_B: |
1098 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1099 | break; | |
1100 | case PORT_C: | |
1101 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1102 | break; | |
1103 | case PORT_D: | |
1104 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1105 | break; | |
1106 | default: | |
1107 | return true; | |
1108 | } | |
b0ea7d37 DL |
1109 | } |
1110 | ||
1111 | return I915_READ(SDEISR) & bit; | |
1112 | } | |
1113 | ||
b24e7179 JB |
1114 | static const char *state_string(bool enabled) |
1115 | { | |
1116 | return enabled ? "on" : "off"; | |
1117 | } | |
1118 | ||
1119 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1120 | void assert_pll(struct drm_i915_private *dev_priv, |
1121 | enum pipe pipe, bool state) | |
b24e7179 JB |
1122 | { |
1123 | int reg; | |
1124 | u32 val; | |
1125 | bool cur_state; | |
1126 | ||
1127 | reg = DPLL(pipe); | |
1128 | val = I915_READ(reg); | |
1129 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1130 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1131 | "PLL state assertion failure (expected %s, current %s)\n", |
1132 | state_string(state), state_string(cur_state)); | |
1133 | } | |
b24e7179 | 1134 | |
23538ef1 JN |
1135 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1136 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1137 | { | |
1138 | u32 val; | |
1139 | bool cur_state; | |
1140 | ||
1141 | mutex_lock(&dev_priv->dpio_lock); | |
1142 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1143 | mutex_unlock(&dev_priv->dpio_lock); | |
1144 | ||
1145 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1146 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1147 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1148 | state_string(state), state_string(cur_state)); | |
1149 | } | |
1150 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1151 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1152 | ||
55607e8a | 1153 | struct intel_shared_dpll * |
e2b78267 DV |
1154 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1155 | { | |
1156 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1157 | ||
6e3c9717 | 1158 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1159 | return NULL; |
1160 | ||
6e3c9717 | 1161 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1162 | } |
1163 | ||
040484af | 1164 | /* For ILK+ */ |
55607e8a DV |
1165 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1166 | struct intel_shared_dpll *pll, | |
1167 | bool state) | |
040484af | 1168 | { |
040484af | 1169 | bool cur_state; |
5358901f | 1170 | struct intel_dpll_hw_state hw_state; |
040484af | 1171 | |
92b27b08 | 1172 | if (WARN (!pll, |
46edb027 | 1173 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1174 | return; |
ee7b9f93 | 1175 | |
5358901f | 1176 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1177 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1178 | "%s assertion failure (expected %s, current %s)\n", |
1179 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1180 | } |
040484af JB |
1181 | |
1182 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1183 | enum pipe pipe, bool state) | |
1184 | { | |
1185 | int reg; | |
1186 | u32 val; | |
1187 | bool cur_state; | |
ad80a810 PZ |
1188 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1189 | pipe); | |
040484af | 1190 | |
affa9354 PZ |
1191 | if (HAS_DDI(dev_priv->dev)) { |
1192 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1193 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1194 | val = I915_READ(reg); |
ad80a810 | 1195 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1196 | } else { |
1197 | reg = FDI_TX_CTL(pipe); | |
1198 | val = I915_READ(reg); | |
1199 | cur_state = !!(val & FDI_TX_ENABLE); | |
1200 | } | |
e2c719b7 | 1201 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1202 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1203 | state_string(state), state_string(cur_state)); | |
1204 | } | |
1205 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1206 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1207 | ||
1208 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1209 | enum pipe pipe, bool state) | |
1210 | { | |
1211 | int reg; | |
1212 | u32 val; | |
1213 | bool cur_state; | |
1214 | ||
d63fa0dc PZ |
1215 | reg = FDI_RX_CTL(pipe); |
1216 | val = I915_READ(reg); | |
1217 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1218 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1219 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1220 | state_string(state), state_string(cur_state)); | |
1221 | } | |
1222 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1223 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1224 | ||
1225 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1226 | enum pipe pipe) | |
1227 | { | |
1228 | int reg; | |
1229 | u32 val; | |
1230 | ||
1231 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1232 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1233 | return; |
1234 | ||
bf507ef7 | 1235 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1236 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1237 | return; |
1238 | ||
040484af JB |
1239 | reg = FDI_TX_CTL(pipe); |
1240 | val = I915_READ(reg); | |
e2c719b7 | 1241 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1242 | } |
1243 | ||
55607e8a DV |
1244 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1245 | enum pipe pipe, bool state) | |
040484af JB |
1246 | { |
1247 | int reg; | |
1248 | u32 val; | |
55607e8a | 1249 | bool cur_state; |
040484af JB |
1250 | |
1251 | reg = FDI_RX_CTL(pipe); | |
1252 | val = I915_READ(reg); | |
55607e8a | 1253 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1254 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1255 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1256 | state_string(state), state_string(cur_state)); | |
040484af JB |
1257 | } |
1258 | ||
b680c37a DV |
1259 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1260 | enum pipe pipe) | |
ea0760cf | 1261 | { |
bedd4dba JN |
1262 | struct drm_device *dev = dev_priv->dev; |
1263 | int pp_reg; | |
ea0760cf JB |
1264 | u32 val; |
1265 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1266 | bool locked = true; |
ea0760cf | 1267 | |
bedd4dba JN |
1268 | if (WARN_ON(HAS_DDI(dev))) |
1269 | return; | |
1270 | ||
1271 | if (HAS_PCH_SPLIT(dev)) { | |
1272 | u32 port_sel; | |
1273 | ||
ea0760cf | 1274 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1275 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1276 | ||
1277 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1278 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1279 | panel_pipe = PIPE_B; | |
1280 | /* XXX: else fix for eDP */ | |
1281 | } else if (IS_VALLEYVIEW(dev)) { | |
1282 | /* presumably write lock depends on pipe, not port select */ | |
1283 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1284 | panel_pipe = pipe; | |
ea0760cf JB |
1285 | } else { |
1286 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1287 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1288 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1289 | } |
1290 | ||
1291 | val = I915_READ(pp_reg); | |
1292 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1293 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1294 | locked = false; |
1295 | ||
e2c719b7 | 1296 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1297 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1298 | pipe_name(pipe)); |
ea0760cf JB |
1299 | } |
1300 | ||
93ce0ba6 JN |
1301 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1302 | enum pipe pipe, bool state) | |
1303 | { | |
1304 | struct drm_device *dev = dev_priv->dev; | |
1305 | bool cur_state; | |
1306 | ||
d9d82081 | 1307 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1308 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1309 | else |
5efb3e28 | 1310 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1311 | |
e2c719b7 | 1312 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1313 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1314 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1315 | } | |
1316 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1317 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1318 | ||
b840d907 JB |
1319 | void assert_pipe(struct drm_i915_private *dev_priv, |
1320 | enum pipe pipe, bool state) | |
b24e7179 JB |
1321 | { |
1322 | int reg; | |
1323 | u32 val; | |
63d7bbe9 | 1324 | bool cur_state; |
702e7a56 PZ |
1325 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1326 | pipe); | |
b24e7179 | 1327 | |
b6b5d049 VS |
1328 | /* if we need the pipe quirk it must be always on */ |
1329 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1330 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1331 | state = true; |
1332 | ||
f458ebbc | 1333 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1334 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1335 | cur_state = false; |
1336 | } else { | |
1337 | reg = PIPECONF(cpu_transcoder); | |
1338 | val = I915_READ(reg); | |
1339 | cur_state = !!(val & PIPECONF_ENABLE); | |
1340 | } | |
1341 | ||
e2c719b7 | 1342 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1343 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1344 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1345 | } |
1346 | ||
931872fc CW |
1347 | static void assert_plane(struct drm_i915_private *dev_priv, |
1348 | enum plane plane, bool state) | |
b24e7179 JB |
1349 | { |
1350 | int reg; | |
1351 | u32 val; | |
931872fc | 1352 | bool cur_state; |
b24e7179 JB |
1353 | |
1354 | reg = DSPCNTR(plane); | |
1355 | val = I915_READ(reg); | |
931872fc | 1356 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1357 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1358 | "plane %c assertion failure (expected %s, current %s)\n", |
1359 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1360 | } |
1361 | ||
931872fc CW |
1362 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1363 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1364 | ||
b24e7179 JB |
1365 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1366 | enum pipe pipe) | |
1367 | { | |
653e1026 | 1368 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1369 | int reg, i; |
1370 | u32 val; | |
1371 | int cur_pipe; | |
1372 | ||
653e1026 VS |
1373 | /* Primary planes are fixed to pipes on gen4+ */ |
1374 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1375 | reg = DSPCNTR(pipe); |
1376 | val = I915_READ(reg); | |
e2c719b7 | 1377 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1378 | "plane %c assertion failure, should be disabled but not\n", |
1379 | plane_name(pipe)); | |
19ec1358 | 1380 | return; |
28c05794 | 1381 | } |
19ec1358 | 1382 | |
b24e7179 | 1383 | /* Need to check both planes against the pipe */ |
055e393f | 1384 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1385 | reg = DSPCNTR(i); |
1386 | val = I915_READ(reg); | |
1387 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1388 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1389 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1390 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1391 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1392 | } |
1393 | } | |
1394 | ||
19332d7a JB |
1395 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1396 | enum pipe pipe) | |
1397 | { | |
20674eef | 1398 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1399 | int reg, sprite; |
19332d7a JB |
1400 | u32 val; |
1401 | ||
7feb8b88 | 1402 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1403 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1404 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1405 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1406 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1407 | sprite, pipe_name(pipe)); | |
1408 | } | |
1409 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1410 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1411 | reg = SPCNTR(pipe, sprite); |
20674eef | 1412 | val = I915_READ(reg); |
e2c719b7 | 1413 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1414 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1415 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1416 | } |
1417 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1418 | reg = SPRCTL(pipe); | |
19332d7a | 1419 | val = I915_READ(reg); |
e2c719b7 | 1420 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1421 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1422 | plane_name(pipe), pipe_name(pipe)); |
1423 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1424 | reg = DVSCNTR(pipe); | |
19332d7a | 1425 | val = I915_READ(reg); |
e2c719b7 | 1426 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1427 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1428 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1429 | } |
1430 | } | |
1431 | ||
08c71e5e VS |
1432 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1433 | { | |
e2c719b7 | 1434 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1435 | drm_crtc_vblank_put(crtc); |
1436 | } | |
1437 | ||
89eff4be | 1438 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1439 | { |
1440 | u32 val; | |
1441 | bool enabled; | |
1442 | ||
e2c719b7 | 1443 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1444 | |
92f2584a JB |
1445 | val = I915_READ(PCH_DREF_CONTROL); |
1446 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1447 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1448 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1449 | } |
1450 | ||
ab9412ba DV |
1451 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1452 | enum pipe pipe) | |
92f2584a JB |
1453 | { |
1454 | int reg; | |
1455 | u32 val; | |
1456 | bool enabled; | |
1457 | ||
ab9412ba | 1458 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1459 | val = I915_READ(reg); |
1460 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1461 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1462 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1463 | pipe_name(pipe)); | |
92f2584a JB |
1464 | } |
1465 | ||
4e634389 KP |
1466 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1467 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1468 | { |
1469 | if ((val & DP_PORT_EN) == 0) | |
1470 | return false; | |
1471 | ||
1472 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1473 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1474 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1475 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1476 | return false; | |
44f37d1f CML |
1477 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1478 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1479 | return false; | |
f0575e92 KP |
1480 | } else { |
1481 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1482 | return false; | |
1483 | } | |
1484 | return true; | |
1485 | } | |
1486 | ||
1519b995 KP |
1487 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1488 | enum pipe pipe, u32 val) | |
1489 | { | |
dc0fa718 | 1490 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1491 | return false; |
1492 | ||
1493 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1494 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1495 | return false; |
44f37d1f CML |
1496 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1497 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1498 | return false; | |
1519b995 | 1499 | } else { |
dc0fa718 | 1500 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1501 | return false; |
1502 | } | |
1503 | return true; | |
1504 | } | |
1505 | ||
1506 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1507 | enum pipe pipe, u32 val) | |
1508 | { | |
1509 | if ((val & LVDS_PORT_EN) == 0) | |
1510 | return false; | |
1511 | ||
1512 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1513 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1514 | return false; | |
1515 | } else { | |
1516 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1517 | return false; | |
1518 | } | |
1519 | return true; | |
1520 | } | |
1521 | ||
1522 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1523 | enum pipe pipe, u32 val) | |
1524 | { | |
1525 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1526 | return false; | |
1527 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1528 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1529 | return false; | |
1530 | } else { | |
1531 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1532 | return false; | |
1533 | } | |
1534 | return true; | |
1535 | } | |
1536 | ||
291906f1 | 1537 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1538 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1539 | { |
47a05eca | 1540 | u32 val = I915_READ(reg); |
e2c719b7 | 1541 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1542 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1543 | reg, pipe_name(pipe)); |
de9a35ab | 1544 | |
e2c719b7 | 1545 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1546 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1547 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1548 | } |
1549 | ||
1550 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1551 | enum pipe pipe, int reg) | |
1552 | { | |
47a05eca | 1553 | u32 val = I915_READ(reg); |
e2c719b7 | 1554 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1555 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1556 | reg, pipe_name(pipe)); |
de9a35ab | 1557 | |
e2c719b7 | 1558 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1559 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1560 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1561 | } |
1562 | ||
1563 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1564 | enum pipe pipe) | |
1565 | { | |
1566 | int reg; | |
1567 | u32 val; | |
291906f1 | 1568 | |
f0575e92 KP |
1569 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1570 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1571 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1572 | |
1573 | reg = PCH_ADPA; | |
1574 | val = I915_READ(reg); | |
e2c719b7 | 1575 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1576 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1577 | pipe_name(pipe)); |
291906f1 JB |
1578 | |
1579 | reg = PCH_LVDS; | |
1580 | val = I915_READ(reg); | |
e2c719b7 | 1581 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1582 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1583 | pipe_name(pipe)); |
291906f1 | 1584 | |
e2debe91 PZ |
1585 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1586 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1587 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1588 | } |
1589 | ||
40e9cf64 JB |
1590 | static void intel_init_dpio(struct drm_device *dev) |
1591 | { | |
1592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1593 | ||
1594 | if (!IS_VALLEYVIEW(dev)) | |
1595 | return; | |
1596 | ||
a09caddd CML |
1597 | /* |
1598 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1599 | * CHV x1 PHY (DP/HDMI D) | |
1600 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1601 | */ | |
1602 | if (IS_CHERRYVIEW(dev)) { | |
1603 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1604 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1605 | } else { | |
1606 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1607 | } | |
5382f5f3 JB |
1608 | } |
1609 | ||
d288f65f | 1610 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1611 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1612 | { |
426115cf DV |
1613 | struct drm_device *dev = crtc->base.dev; |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1615 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1616 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1617 | |
426115cf | 1618 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1619 | |
1620 | /* No really, not for ILK+ */ | |
1621 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1622 | ||
1623 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1624 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1625 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1626 | |
426115cf DV |
1627 | I915_WRITE(reg, dpll); |
1628 | POSTING_READ(reg); | |
1629 | udelay(150); | |
1630 | ||
1631 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1632 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1633 | ||
d288f65f | 1634 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1635 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1636 | |
1637 | /* We do this three times for luck */ | |
426115cf | 1638 | I915_WRITE(reg, dpll); |
87442f73 DV |
1639 | POSTING_READ(reg); |
1640 | udelay(150); /* wait for warmup */ | |
426115cf | 1641 | I915_WRITE(reg, dpll); |
87442f73 DV |
1642 | POSTING_READ(reg); |
1643 | udelay(150); /* wait for warmup */ | |
426115cf | 1644 | I915_WRITE(reg, dpll); |
87442f73 DV |
1645 | POSTING_READ(reg); |
1646 | udelay(150); /* wait for warmup */ | |
1647 | } | |
1648 | ||
d288f65f | 1649 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1650 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1651 | { |
1652 | struct drm_device *dev = crtc->base.dev; | |
1653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1654 | int pipe = crtc->pipe; | |
1655 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1656 | u32 tmp; |
1657 | ||
1658 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1659 | ||
1660 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1661 | ||
1662 | mutex_lock(&dev_priv->dpio_lock); | |
1663 | ||
1664 | /* Enable back the 10bit clock to display controller */ | |
1665 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1666 | tmp |= DPIO_DCLKP_EN; | |
1667 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1668 | ||
1669 | /* | |
1670 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1671 | */ | |
1672 | udelay(1); | |
1673 | ||
1674 | /* Enable PLL */ | |
d288f65f | 1675 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1676 | |
1677 | /* Check PLL is locked */ | |
a11b0703 | 1678 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1679 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1680 | ||
a11b0703 | 1681 | /* not sure when this should be written */ |
d288f65f | 1682 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1683 | POSTING_READ(DPLL_MD(pipe)); |
1684 | ||
9d556c99 CML |
1685 | mutex_unlock(&dev_priv->dpio_lock); |
1686 | } | |
1687 | ||
1c4e0274 VS |
1688 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1689 | { | |
1690 | struct intel_crtc *crtc; | |
1691 | int count = 0; | |
1692 | ||
1693 | for_each_intel_crtc(dev, crtc) | |
1694 | count += crtc->active && | |
409ee761 | 1695 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1696 | |
1697 | return count; | |
1698 | } | |
1699 | ||
66e3d5c0 | 1700 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1701 | { |
66e3d5c0 DV |
1702 | struct drm_device *dev = crtc->base.dev; |
1703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1704 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1705 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1706 | |
66e3d5c0 | 1707 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1708 | |
63d7bbe9 | 1709 | /* No really, not for ILK+ */ |
3d13ef2e | 1710 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1711 | |
1712 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1713 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1714 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1715 | |
1c4e0274 VS |
1716 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1717 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1718 | /* | |
1719 | * It appears to be important that we don't enable this | |
1720 | * for the current pipe before otherwise configuring the | |
1721 | * PLL. No idea how this should be handled if multiple | |
1722 | * DVO outputs are enabled simultaneosly. | |
1723 | */ | |
1724 | dpll |= DPLL_DVO_2X_MODE; | |
1725 | I915_WRITE(DPLL(!crtc->pipe), | |
1726 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1727 | } | |
66e3d5c0 DV |
1728 | |
1729 | /* Wait for the clocks to stabilize. */ | |
1730 | POSTING_READ(reg); | |
1731 | udelay(150); | |
1732 | ||
1733 | if (INTEL_INFO(dev)->gen >= 4) { | |
1734 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1735 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1736 | } else { |
1737 | /* The pixel multiplier can only be updated once the | |
1738 | * DPLL is enabled and the clocks are stable. | |
1739 | * | |
1740 | * So write it again. | |
1741 | */ | |
1742 | I915_WRITE(reg, dpll); | |
1743 | } | |
63d7bbe9 JB |
1744 | |
1745 | /* We do this three times for luck */ | |
66e3d5c0 | 1746 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1747 | POSTING_READ(reg); |
1748 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1749 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1750 | POSTING_READ(reg); |
1751 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1752 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1753 | POSTING_READ(reg); |
1754 | udelay(150); /* wait for warmup */ | |
1755 | } | |
1756 | ||
1757 | /** | |
50b44a44 | 1758 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1759 | * @dev_priv: i915 private structure |
1760 | * @pipe: pipe PLL to disable | |
1761 | * | |
1762 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1763 | * | |
1764 | * Note! This is for pre-ILK only. | |
1765 | */ | |
1c4e0274 | 1766 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1767 | { |
1c4e0274 VS |
1768 | struct drm_device *dev = crtc->base.dev; |
1769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1770 | enum pipe pipe = crtc->pipe; | |
1771 | ||
1772 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1773 | if (IS_I830(dev) && | |
409ee761 | 1774 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1775 | intel_num_dvo_pipes(dev) == 1) { |
1776 | I915_WRITE(DPLL(PIPE_B), | |
1777 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1778 | I915_WRITE(DPLL(PIPE_A), | |
1779 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1780 | } | |
1781 | ||
b6b5d049 VS |
1782 | /* Don't disable pipe or pipe PLLs if needed */ |
1783 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1784 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1785 | return; |
1786 | ||
1787 | /* Make sure the pipe isn't still relying on us */ | |
1788 | assert_pipe_disabled(dev_priv, pipe); | |
1789 | ||
50b44a44 DV |
1790 | I915_WRITE(DPLL(pipe), 0); |
1791 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1792 | } |
1793 | ||
f6071166 JB |
1794 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1795 | { | |
1796 | u32 val = 0; | |
1797 | ||
1798 | /* Make sure the pipe isn't still relying on us */ | |
1799 | assert_pipe_disabled(dev_priv, pipe); | |
1800 | ||
e5cbfbfb ID |
1801 | /* |
1802 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1803 | * The latter is needed for VGA hotplug / manual detection. | |
1804 | */ | |
f6071166 | 1805 | if (pipe == PIPE_B) |
e5cbfbfb | 1806 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1807 | I915_WRITE(DPLL(pipe), val); |
1808 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1809 | |
1810 | } | |
1811 | ||
1812 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1813 | { | |
d752048d | 1814 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1815 | u32 val; |
1816 | ||
a11b0703 VS |
1817 | /* Make sure the pipe isn't still relying on us */ |
1818 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1819 | |
a11b0703 | 1820 | /* Set PLL en = 0 */ |
d17ec4ce | 1821 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1822 | if (pipe != PIPE_A) |
1823 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1824 | I915_WRITE(DPLL(pipe), val); | |
1825 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1826 | |
1827 | mutex_lock(&dev_priv->dpio_lock); | |
1828 | ||
1829 | /* Disable 10bit clock to display controller */ | |
1830 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1831 | val &= ~DPIO_DCLKP_EN; | |
1832 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1833 | ||
61407f6d VS |
1834 | /* disable left/right clock distribution */ |
1835 | if (pipe != PIPE_B) { | |
1836 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1837 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1838 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1839 | } else { | |
1840 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1841 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1842 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1843 | } | |
1844 | ||
d752048d | 1845 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1846 | } |
1847 | ||
e4607fcf CML |
1848 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1849 | struct intel_digital_port *dport) | |
89b667f8 JB |
1850 | { |
1851 | u32 port_mask; | |
00fc31b7 | 1852 | int dpll_reg; |
89b667f8 | 1853 | |
e4607fcf CML |
1854 | switch (dport->port) { |
1855 | case PORT_B: | |
89b667f8 | 1856 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1857 | dpll_reg = DPLL(0); |
e4607fcf CML |
1858 | break; |
1859 | case PORT_C: | |
89b667f8 | 1860 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1861 | dpll_reg = DPLL(0); |
1862 | break; | |
1863 | case PORT_D: | |
1864 | port_mask = DPLL_PORTD_READY_MASK; | |
1865 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1866 | break; |
1867 | default: | |
1868 | BUG(); | |
1869 | } | |
89b667f8 | 1870 | |
00fc31b7 | 1871 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1872 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1873 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1874 | } |
1875 | ||
b14b1055 DV |
1876 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1877 | { | |
1878 | struct drm_device *dev = crtc->base.dev; | |
1879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1880 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1881 | ||
be19f0ff CW |
1882 | if (WARN_ON(pll == NULL)) |
1883 | return; | |
1884 | ||
3e369b76 | 1885 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1886 | if (pll->active == 0) { |
1887 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1888 | WARN_ON(pll->on); | |
1889 | assert_shared_dpll_disabled(dev_priv, pll); | |
1890 | ||
1891 | pll->mode_set(dev_priv, pll); | |
1892 | } | |
1893 | } | |
1894 | ||
92f2584a | 1895 | /** |
85b3894f | 1896 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1897 | * @dev_priv: i915 private structure |
1898 | * @pipe: pipe PLL to enable | |
1899 | * | |
1900 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1901 | * drives the transcoder clock. | |
1902 | */ | |
85b3894f | 1903 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1904 | { |
3d13ef2e DL |
1905 | struct drm_device *dev = crtc->base.dev; |
1906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1907 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1908 | |
87a875bb | 1909 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1910 | return; |
1911 | ||
3e369b76 | 1912 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1913 | return; |
ee7b9f93 | 1914 | |
74dd6928 | 1915 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1916 | pll->name, pll->active, pll->on, |
e2b78267 | 1917 | crtc->base.base.id); |
92f2584a | 1918 | |
cdbd2316 DV |
1919 | if (pll->active++) { |
1920 | WARN_ON(!pll->on); | |
e9d6944e | 1921 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1922 | return; |
1923 | } | |
f4a091c7 | 1924 | WARN_ON(pll->on); |
ee7b9f93 | 1925 | |
bd2bb1b9 PZ |
1926 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1927 | ||
46edb027 | 1928 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1929 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1930 | pll->on = true; |
92f2584a JB |
1931 | } |
1932 | ||
f6daaec2 | 1933 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1934 | { |
3d13ef2e DL |
1935 | struct drm_device *dev = crtc->base.dev; |
1936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1937 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1938 | |
92f2584a | 1939 | /* PCH only available on ILK+ */ |
3d13ef2e | 1940 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1941 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1942 | return; |
92f2584a | 1943 | |
3e369b76 | 1944 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1945 | return; |
7a419866 | 1946 | |
46edb027 DV |
1947 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1948 | pll->name, pll->active, pll->on, | |
e2b78267 | 1949 | crtc->base.base.id); |
7a419866 | 1950 | |
48da64a8 | 1951 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1952 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1953 | return; |
1954 | } | |
1955 | ||
e9d6944e | 1956 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1957 | WARN_ON(!pll->on); |
cdbd2316 | 1958 | if (--pll->active) |
7a419866 | 1959 | return; |
ee7b9f93 | 1960 | |
46edb027 | 1961 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1962 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1963 | pll->on = false; |
bd2bb1b9 PZ |
1964 | |
1965 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1966 | } |
1967 | ||
b8a4f404 PZ |
1968 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1969 | enum pipe pipe) | |
040484af | 1970 | { |
23670b32 | 1971 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1972 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1974 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1975 | |
1976 | /* PCH only available on ILK+ */ | |
55522f37 | 1977 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1978 | |
1979 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1980 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1981 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1982 | |
1983 | /* FDI must be feeding us bits for PCH ports */ | |
1984 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1985 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1986 | ||
23670b32 DV |
1987 | if (HAS_PCH_CPT(dev)) { |
1988 | /* Workaround: Set the timing override bit before enabling the | |
1989 | * pch transcoder. */ | |
1990 | reg = TRANS_CHICKEN2(pipe); | |
1991 | val = I915_READ(reg); | |
1992 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1993 | I915_WRITE(reg, val); | |
59c859d6 | 1994 | } |
23670b32 | 1995 | |
ab9412ba | 1996 | reg = PCH_TRANSCONF(pipe); |
040484af | 1997 | val = I915_READ(reg); |
5f7f726d | 1998 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1999 | |
2000 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2001 | /* | |
2002 | * make the BPC in transcoder be consistent with | |
2003 | * that in pipeconf reg. | |
2004 | */ | |
dfd07d72 DV |
2005 | val &= ~PIPECONF_BPC_MASK; |
2006 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2007 | } |
5f7f726d PZ |
2008 | |
2009 | val &= ~TRANS_INTERLACE_MASK; | |
2010 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2011 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2012 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2013 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2014 | else | |
2015 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2016 | else |
2017 | val |= TRANS_PROGRESSIVE; | |
2018 | ||
040484af JB |
2019 | I915_WRITE(reg, val | TRANS_ENABLE); |
2020 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2021 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2022 | } |
2023 | ||
8fb033d7 | 2024 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2025 | enum transcoder cpu_transcoder) |
040484af | 2026 | { |
8fb033d7 | 2027 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2028 | |
2029 | /* PCH only available on ILK+ */ | |
55522f37 | 2030 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2031 | |
8fb033d7 | 2032 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2033 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2034 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2035 | |
223a6fdf PZ |
2036 | /* Workaround: set timing override bit. */ |
2037 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2038 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2039 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2040 | ||
25f3ef11 | 2041 | val = TRANS_ENABLE; |
937bb610 | 2042 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2043 | |
9a76b1c6 PZ |
2044 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2045 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2046 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2047 | else |
2048 | val |= TRANS_PROGRESSIVE; | |
2049 | ||
ab9412ba DV |
2050 | I915_WRITE(LPT_TRANSCONF, val); |
2051 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2052 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2053 | } |
2054 | ||
b8a4f404 PZ |
2055 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2056 | enum pipe pipe) | |
040484af | 2057 | { |
23670b32 DV |
2058 | struct drm_device *dev = dev_priv->dev; |
2059 | uint32_t reg, val; | |
040484af JB |
2060 | |
2061 | /* FDI relies on the transcoder */ | |
2062 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2063 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2064 | ||
291906f1 JB |
2065 | /* Ports must be off as well */ |
2066 | assert_pch_ports_disabled(dev_priv, pipe); | |
2067 | ||
ab9412ba | 2068 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2069 | val = I915_READ(reg); |
2070 | val &= ~TRANS_ENABLE; | |
2071 | I915_WRITE(reg, val); | |
2072 | /* wait for PCH transcoder off, transcoder state */ | |
2073 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2074 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2075 | |
2076 | if (!HAS_PCH_IBX(dev)) { | |
2077 | /* Workaround: Clear the timing override chicken bit again. */ | |
2078 | reg = TRANS_CHICKEN2(pipe); | |
2079 | val = I915_READ(reg); | |
2080 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2081 | I915_WRITE(reg, val); | |
2082 | } | |
040484af JB |
2083 | } |
2084 | ||
ab4d966c | 2085 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2086 | { |
8fb033d7 PZ |
2087 | u32 val; |
2088 | ||
ab9412ba | 2089 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2090 | val &= ~TRANS_ENABLE; |
ab9412ba | 2091 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2092 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2093 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2094 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2095 | |
2096 | /* Workaround: clear timing override bit. */ | |
2097 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2098 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2099 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2100 | } |
2101 | ||
b24e7179 | 2102 | /** |
309cfea8 | 2103 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2104 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2105 | * |
0372264a | 2106 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2107 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2108 | */ |
e1fdc473 | 2109 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2110 | { |
0372264a PZ |
2111 | struct drm_device *dev = crtc->base.dev; |
2112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2113 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2114 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2115 | pipe); | |
1a240d4d | 2116 | enum pipe pch_transcoder; |
b24e7179 JB |
2117 | int reg; |
2118 | u32 val; | |
2119 | ||
58c6eaa2 | 2120 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2121 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2122 | assert_sprites_disabled(dev_priv, pipe); |
2123 | ||
681e5811 | 2124 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2125 | pch_transcoder = TRANSCODER_A; |
2126 | else | |
2127 | pch_transcoder = pipe; | |
2128 | ||
b24e7179 JB |
2129 | /* |
2130 | * A pipe without a PLL won't actually be able to drive bits from | |
2131 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2132 | * need the check. | |
2133 | */ | |
50360403 | 2134 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2135 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2136 | assert_dsi_pll_enabled(dev_priv); |
2137 | else | |
2138 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2139 | else { |
6e3c9717 | 2140 | if (crtc->config->has_pch_encoder) { |
040484af | 2141 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2142 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2143 | assert_fdi_tx_pll_enabled(dev_priv, |
2144 | (enum pipe) cpu_transcoder); | |
040484af JB |
2145 | } |
2146 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2147 | } | |
b24e7179 | 2148 | |
702e7a56 | 2149 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2150 | val = I915_READ(reg); |
7ad25d48 | 2151 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2152 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2153 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2154 | return; |
7ad25d48 | 2155 | } |
00d70b15 CW |
2156 | |
2157 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2158 | POSTING_READ(reg); |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2176 | int reg; |
2177 | u32 val; | |
2178 | ||
2179 | /* | |
2180 | * Make sure planes won't keep trying to pump pixels to us, | |
2181 | * or we might hang the display. | |
2182 | */ | |
2183 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2184 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2185 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2186 | |
702e7a56 | 2187 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2188 | val = I915_READ(reg); |
00d70b15 CW |
2189 | if ((val & PIPECONF_ENABLE) == 0) |
2190 | return; | |
2191 | ||
67adc644 VS |
2192 | /* |
2193 | * Double wide has implications for planes | |
2194 | * so best keep it disabled when not needed. | |
2195 | */ | |
6e3c9717 | 2196 | if (crtc->config->double_wide) |
67adc644 VS |
2197 | val &= ~PIPECONF_DOUBLE_WIDE; |
2198 | ||
2199 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2200 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2201 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2202 | val &= ~PIPECONF_ENABLE; |
2203 | ||
2204 | I915_WRITE(reg, val); | |
2205 | if ((val & PIPECONF_ENABLE) == 0) | |
2206 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2207 | } |
2208 | ||
d74362c9 KP |
2209 | /* |
2210 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2211 | * trigger in order to latch. The display address reg provides this. | |
2212 | */ | |
1dba99f4 VS |
2213 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2214 | enum plane plane) | |
d74362c9 | 2215 | { |
3d13ef2e DL |
2216 | struct drm_device *dev = dev_priv->dev; |
2217 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2218 | |
2219 | I915_WRITE(reg, I915_READ(reg)); | |
2220 | POSTING_READ(reg); | |
d74362c9 KP |
2221 | } |
2222 | ||
b24e7179 | 2223 | /** |
262ca2b0 | 2224 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2225 | * @plane: plane to be enabled |
2226 | * @crtc: crtc for the plane | |
b24e7179 | 2227 | * |
fdd508a6 | 2228 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2229 | */ |
fdd508a6 VS |
2230 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2231 | struct drm_crtc *crtc) | |
b24e7179 | 2232 | { |
fdd508a6 VS |
2233 | struct drm_device *dev = plane->dev; |
2234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2236 | |
2237 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2238 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2239 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2240 | |
fdd508a6 VS |
2241 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2242 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2243 | |
2244 | /* | |
2245 | * BDW signals flip done immediately if the plane | |
2246 | * is disabled, even if the plane enable is already | |
2247 | * armed to occur at the next vblank :( | |
2248 | */ | |
2249 | if (IS_BROADWELL(dev)) | |
2250 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2251 | } |
2252 | ||
693db184 CW |
2253 | static bool need_vtd_wa(struct drm_device *dev) |
2254 | { | |
2255 | #ifdef CONFIG_INTEL_IOMMU | |
2256 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2257 | return true; | |
2258 | #endif | |
2259 | return false; | |
2260 | } | |
2261 | ||
50470bb0 | 2262 | unsigned int |
6761dd31 TU |
2263 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2264 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2265 | { |
6761dd31 TU |
2266 | unsigned int tile_height; |
2267 | uint32_t pixel_bytes; | |
a57ce0b2 | 2268 | |
b5d0e9bf DL |
2269 | switch (fb_format_modifier) { |
2270 | case DRM_FORMAT_MOD_NONE: | |
2271 | tile_height = 1; | |
2272 | break; | |
2273 | case I915_FORMAT_MOD_X_TILED: | |
2274 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2275 | break; | |
2276 | case I915_FORMAT_MOD_Y_TILED: | |
2277 | tile_height = 32; | |
2278 | break; | |
2279 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2280 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2281 | switch (pixel_bytes) { | |
b5d0e9bf | 2282 | default: |
6761dd31 | 2283 | case 1: |
b5d0e9bf DL |
2284 | tile_height = 64; |
2285 | break; | |
6761dd31 TU |
2286 | case 2: |
2287 | case 4: | |
b5d0e9bf DL |
2288 | tile_height = 32; |
2289 | break; | |
6761dd31 | 2290 | case 8: |
b5d0e9bf DL |
2291 | tile_height = 16; |
2292 | break; | |
6761dd31 | 2293 | case 16: |
b5d0e9bf DL |
2294 | WARN_ONCE(1, |
2295 | "128-bit pixels are not supported for display!"); | |
2296 | tile_height = 16; | |
2297 | break; | |
2298 | } | |
2299 | break; | |
2300 | default: | |
2301 | MISSING_CASE(fb_format_modifier); | |
2302 | tile_height = 1; | |
2303 | break; | |
2304 | } | |
091df6cb | 2305 | |
6761dd31 TU |
2306 | return tile_height; |
2307 | } | |
2308 | ||
2309 | unsigned int | |
2310 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2311 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2312 | { | |
2313 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2314 | fb_format_modifier)); | |
a57ce0b2 JB |
2315 | } |
2316 | ||
f64b98cd TU |
2317 | static int |
2318 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2319 | const struct drm_plane_state *plane_state) | |
2320 | { | |
50470bb0 | 2321 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2322 | |
f64b98cd TU |
2323 | *view = i915_ggtt_view_normal; |
2324 | ||
50470bb0 TU |
2325 | if (!plane_state) |
2326 | return 0; | |
2327 | ||
121920fa | 2328 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2329 | return 0; |
2330 | ||
9abc4648 | 2331 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2332 | |
2333 | info->height = fb->height; | |
2334 | info->pixel_format = fb->pixel_format; | |
2335 | info->pitch = fb->pitches[0]; | |
2336 | info->fb_modifier = fb->modifier[0]; | |
2337 | ||
f64b98cd TU |
2338 | return 0; |
2339 | } | |
2340 | ||
127bd2ac | 2341 | int |
850c4cdc TU |
2342 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2343 | struct drm_framebuffer *fb, | |
82bc3b2d | 2344 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2345 | struct intel_engine_cs *pipelined) |
6b95a207 | 2346 | { |
850c4cdc | 2347 | struct drm_device *dev = fb->dev; |
ce453d81 | 2348 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2349 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2350 | struct i915_ggtt_view view; |
6b95a207 KH |
2351 | u32 alignment; |
2352 | int ret; | |
2353 | ||
ebcdd39e MR |
2354 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2355 | ||
7b911adc TU |
2356 | switch (fb->modifier[0]) { |
2357 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2358 | if (INTEL_INFO(dev)->gen >= 9) |
2359 | alignment = 256 * 1024; | |
2360 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2361 | alignment = 128 * 1024; |
a6c45cf0 | 2362 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2363 | alignment = 4 * 1024; |
2364 | else | |
2365 | alignment = 64 * 1024; | |
6b95a207 | 2366 | break; |
7b911adc | 2367 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2368 | if (INTEL_INFO(dev)->gen >= 9) |
2369 | alignment = 256 * 1024; | |
2370 | else { | |
2371 | /* pin() will align the object as required by fence */ | |
2372 | alignment = 0; | |
2373 | } | |
6b95a207 | 2374 | break; |
7b911adc | 2375 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2376 | case I915_FORMAT_MOD_Yf_TILED: |
2377 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2378 | "Y tiling bo slipped through, driver bug!\n")) | |
2379 | return -EINVAL; | |
2380 | alignment = 1 * 1024 * 1024; | |
2381 | break; | |
6b95a207 | 2382 | default: |
7b911adc TU |
2383 | MISSING_CASE(fb->modifier[0]); |
2384 | return -EINVAL; | |
6b95a207 KH |
2385 | } |
2386 | ||
f64b98cd TU |
2387 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2388 | if (ret) | |
2389 | return ret; | |
2390 | ||
693db184 CW |
2391 | /* Note that the w/a also requires 64 PTE of padding following the |
2392 | * bo. We currently fill all unused PTE with the shadow page and so | |
2393 | * we should always have valid PTE following the scanout preventing | |
2394 | * the VT-d warning. | |
2395 | */ | |
2396 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2397 | alignment = 256 * 1024; | |
2398 | ||
d6dd6843 PZ |
2399 | /* |
2400 | * Global gtt pte registers are special registers which actually forward | |
2401 | * writes to a chunk of system memory. Which means that there is no risk | |
2402 | * that the register values disappear as soon as we call | |
2403 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2404 | * pin/unpin/fence and not more. | |
2405 | */ | |
2406 | intel_runtime_pm_get(dev_priv); | |
2407 | ||
ce453d81 | 2408 | dev_priv->mm.interruptible = false; |
e6617330 | 2409 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2410 | &view); |
48b956c5 | 2411 | if (ret) |
ce453d81 | 2412 | goto err_interruptible; |
6b95a207 KH |
2413 | |
2414 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2415 | * fence, whereas 965+ only requires a fence if using | |
2416 | * framebuffer compression. For simplicity, we always install | |
2417 | * a fence as the cost is not that onerous. | |
2418 | */ | |
06d98131 | 2419 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2420 | if (ret) |
2421 | goto err_unpin; | |
1690e1eb | 2422 | |
9a5a53b3 | 2423 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2424 | |
ce453d81 | 2425 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2426 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2427 | return 0; |
48b956c5 CW |
2428 | |
2429 | err_unpin: | |
f64b98cd | 2430 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2431 | err_interruptible: |
2432 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2433 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2434 | return ret; |
6b95a207 KH |
2435 | } |
2436 | ||
82bc3b2d TU |
2437 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2438 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2439 | { |
82bc3b2d | 2440 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2441 | struct i915_ggtt_view view; |
2442 | int ret; | |
82bc3b2d | 2443 | |
ebcdd39e MR |
2444 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2445 | ||
f64b98cd TU |
2446 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2447 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2448 | ||
1690e1eb | 2449 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2450 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2451 | } |
2452 | ||
c2c75131 DV |
2453 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2454 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2455 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2456 | unsigned int tiling_mode, | |
2457 | unsigned int cpp, | |
2458 | unsigned int pitch) | |
c2c75131 | 2459 | { |
bc752862 CW |
2460 | if (tiling_mode != I915_TILING_NONE) { |
2461 | unsigned int tile_rows, tiles; | |
c2c75131 | 2462 | |
bc752862 CW |
2463 | tile_rows = *y / 8; |
2464 | *y %= 8; | |
c2c75131 | 2465 | |
bc752862 CW |
2466 | tiles = *x / (512/cpp); |
2467 | *x %= 512/cpp; | |
2468 | ||
2469 | return tile_rows * pitch * 8 + tiles * 4096; | |
2470 | } else { | |
2471 | unsigned int offset; | |
2472 | ||
2473 | offset = *y * pitch + *x * cpp; | |
2474 | *y = 0; | |
2475 | *x = (offset & 4095) / cpp; | |
2476 | return offset & -4096; | |
2477 | } | |
c2c75131 DV |
2478 | } |
2479 | ||
b35d63fa | 2480 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2481 | { |
2482 | switch (format) { | |
2483 | case DISPPLANE_8BPP: | |
2484 | return DRM_FORMAT_C8; | |
2485 | case DISPPLANE_BGRX555: | |
2486 | return DRM_FORMAT_XRGB1555; | |
2487 | case DISPPLANE_BGRX565: | |
2488 | return DRM_FORMAT_RGB565; | |
2489 | default: | |
2490 | case DISPPLANE_BGRX888: | |
2491 | return DRM_FORMAT_XRGB8888; | |
2492 | case DISPPLANE_RGBX888: | |
2493 | return DRM_FORMAT_XBGR8888; | |
2494 | case DISPPLANE_BGRX101010: | |
2495 | return DRM_FORMAT_XRGB2101010; | |
2496 | case DISPPLANE_RGBX101010: | |
2497 | return DRM_FORMAT_XBGR2101010; | |
2498 | } | |
2499 | } | |
2500 | ||
bc8d7dff DL |
2501 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2502 | { | |
2503 | switch (format) { | |
2504 | case PLANE_CTL_FORMAT_RGB_565: | |
2505 | return DRM_FORMAT_RGB565; | |
2506 | default: | |
2507 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2508 | if (rgb_order) { | |
2509 | if (alpha) | |
2510 | return DRM_FORMAT_ABGR8888; | |
2511 | else | |
2512 | return DRM_FORMAT_XBGR8888; | |
2513 | } else { | |
2514 | if (alpha) | |
2515 | return DRM_FORMAT_ARGB8888; | |
2516 | else | |
2517 | return DRM_FORMAT_XRGB8888; | |
2518 | } | |
2519 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2520 | if (rgb_order) | |
2521 | return DRM_FORMAT_XBGR2101010; | |
2522 | else | |
2523 | return DRM_FORMAT_XRGB2101010; | |
2524 | } | |
2525 | } | |
2526 | ||
5724dbd1 | 2527 | static bool |
f6936e29 DV |
2528 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2529 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2530 | { |
2531 | struct drm_device *dev = crtc->base.dev; | |
2532 | struct drm_i915_gem_object *obj = NULL; | |
2533 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2534 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2535 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2536 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2537 | PAGE_SIZE); | |
2538 | ||
2539 | size_aligned -= base_aligned; | |
46f297fb | 2540 | |
ff2652ea CW |
2541 | if (plane_config->size == 0) |
2542 | return false; | |
2543 | ||
f37b5c2b DV |
2544 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2545 | base_aligned, | |
2546 | base_aligned, | |
2547 | size_aligned); | |
46f297fb | 2548 | if (!obj) |
484b41dd | 2549 | return false; |
46f297fb | 2550 | |
49af449b DL |
2551 | obj->tiling_mode = plane_config->tiling; |
2552 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2553 | obj->stride = fb->pitches[0]; |
46f297fb | 2554 | |
6bf129df DL |
2555 | mode_cmd.pixel_format = fb->pixel_format; |
2556 | mode_cmd.width = fb->width; | |
2557 | mode_cmd.height = fb->height; | |
2558 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2559 | mode_cmd.modifier[0] = fb->modifier[0]; |
2560 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2561 | |
2562 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2563 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2564 | &mode_cmd, obj)) { |
46f297fb JB |
2565 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2566 | goto out_unref_obj; | |
2567 | } | |
46f297fb | 2568 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2569 | |
f6936e29 | 2570 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2571 | return true; |
46f297fb JB |
2572 | |
2573 | out_unref_obj: | |
2574 | drm_gem_object_unreference(&obj->base); | |
2575 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2576 | return false; |
2577 | } | |
2578 | ||
afd65eb4 MR |
2579 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2580 | static void | |
2581 | update_state_fb(struct drm_plane *plane) | |
2582 | { | |
2583 | if (plane->fb == plane->state->fb) | |
2584 | return; | |
2585 | ||
2586 | if (plane->state->fb) | |
2587 | drm_framebuffer_unreference(plane->state->fb); | |
2588 | plane->state->fb = plane->fb; | |
2589 | if (plane->state->fb) | |
2590 | drm_framebuffer_reference(plane->state->fb); | |
2591 | } | |
2592 | ||
5724dbd1 | 2593 | static void |
f6936e29 DV |
2594 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2595 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2596 | { |
2597 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2598 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2599 | struct drm_crtc *c; |
2600 | struct intel_crtc *i; | |
2ff8fde1 | 2601 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2602 | struct drm_plane *primary = intel_crtc->base.primary; |
2603 | struct drm_framebuffer *fb; | |
484b41dd | 2604 | |
2d14030b | 2605 | if (!plane_config->fb) |
484b41dd JB |
2606 | return; |
2607 | ||
f6936e29 | 2608 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2609 | fb = &plane_config->fb->base; |
2610 | goto valid_fb; | |
f55548b5 | 2611 | } |
484b41dd | 2612 | |
2d14030b | 2613 | kfree(plane_config->fb); |
484b41dd JB |
2614 | |
2615 | /* | |
2616 | * Failed to alloc the obj, check to see if we should share | |
2617 | * an fb with another CRTC instead | |
2618 | */ | |
70e1e0ec | 2619 | for_each_crtc(dev, c) { |
484b41dd JB |
2620 | i = to_intel_crtc(c); |
2621 | ||
2622 | if (c == &intel_crtc->base) | |
2623 | continue; | |
2624 | ||
2ff8fde1 MR |
2625 | if (!i->active) |
2626 | continue; | |
2627 | ||
88595ac9 DV |
2628 | fb = c->primary->fb; |
2629 | if (!fb) | |
484b41dd JB |
2630 | continue; |
2631 | ||
88595ac9 | 2632 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2633 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2634 | drm_framebuffer_reference(fb); |
2635 | goto valid_fb; | |
484b41dd JB |
2636 | } |
2637 | } | |
88595ac9 DV |
2638 | |
2639 | return; | |
2640 | ||
2641 | valid_fb: | |
2642 | obj = intel_fb_obj(fb); | |
2643 | if (obj->tiling_mode != I915_TILING_NONE) | |
2644 | dev_priv->preserve_bios_swizzle = true; | |
2645 | ||
2646 | primary->fb = fb; | |
2647 | primary->state->crtc = &intel_crtc->base; | |
2648 | primary->crtc = &intel_crtc->base; | |
2649 | update_state_fb(primary); | |
2650 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2651 | } |
2652 | ||
29b9bde6 DV |
2653 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2654 | struct drm_framebuffer *fb, | |
2655 | int x, int y) | |
81255565 JB |
2656 | { |
2657 | struct drm_device *dev = crtc->dev; | |
2658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2659 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2660 | struct drm_plane *primary = crtc->primary; |
2661 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2662 | struct drm_i915_gem_object *obj; |
81255565 | 2663 | int plane = intel_crtc->plane; |
e506a0c6 | 2664 | unsigned long linear_offset; |
81255565 | 2665 | u32 dspcntr; |
f45651ba | 2666 | u32 reg = DSPCNTR(plane); |
48404c1e | 2667 | int pixel_size; |
f45651ba | 2668 | |
b70709a6 | 2669 | if (!visible || !fb) { |
fdd508a6 VS |
2670 | I915_WRITE(reg, 0); |
2671 | if (INTEL_INFO(dev)->gen >= 4) | |
2672 | I915_WRITE(DSPSURF(plane), 0); | |
2673 | else | |
2674 | I915_WRITE(DSPADDR(plane), 0); | |
2675 | POSTING_READ(reg); | |
2676 | return; | |
2677 | } | |
2678 | ||
c9ba6fad VS |
2679 | obj = intel_fb_obj(fb); |
2680 | if (WARN_ON(obj == NULL)) | |
2681 | return; | |
2682 | ||
2683 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2684 | ||
f45651ba VS |
2685 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2686 | ||
fdd508a6 | 2687 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2688 | |
2689 | if (INTEL_INFO(dev)->gen < 4) { | |
2690 | if (intel_crtc->pipe == PIPE_B) | |
2691 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2692 | ||
2693 | /* pipesrc and dspsize control the size that is scaled from, | |
2694 | * which should always be the user's requested size. | |
2695 | */ | |
2696 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2697 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2698 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2699 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2700 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2701 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2702 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2703 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2704 | I915_WRITE(PRIMPOS(plane), 0); |
2705 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2706 | } |
81255565 | 2707 | |
57779d06 VS |
2708 | switch (fb->pixel_format) { |
2709 | case DRM_FORMAT_C8: | |
81255565 JB |
2710 | dspcntr |= DISPPLANE_8BPP; |
2711 | break; | |
57779d06 VS |
2712 | case DRM_FORMAT_XRGB1555: |
2713 | case DRM_FORMAT_ARGB1555: | |
2714 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2715 | break; |
57779d06 VS |
2716 | case DRM_FORMAT_RGB565: |
2717 | dspcntr |= DISPPLANE_BGRX565; | |
2718 | break; | |
2719 | case DRM_FORMAT_XRGB8888: | |
2720 | case DRM_FORMAT_ARGB8888: | |
2721 | dspcntr |= DISPPLANE_BGRX888; | |
2722 | break; | |
2723 | case DRM_FORMAT_XBGR8888: | |
2724 | case DRM_FORMAT_ABGR8888: | |
2725 | dspcntr |= DISPPLANE_RGBX888; | |
2726 | break; | |
2727 | case DRM_FORMAT_XRGB2101010: | |
2728 | case DRM_FORMAT_ARGB2101010: | |
2729 | dspcntr |= DISPPLANE_BGRX101010; | |
2730 | break; | |
2731 | case DRM_FORMAT_XBGR2101010: | |
2732 | case DRM_FORMAT_ABGR2101010: | |
2733 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2734 | break; |
2735 | default: | |
baba133a | 2736 | BUG(); |
81255565 | 2737 | } |
57779d06 | 2738 | |
f45651ba VS |
2739 | if (INTEL_INFO(dev)->gen >= 4 && |
2740 | obj->tiling_mode != I915_TILING_NONE) | |
2741 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2742 | |
de1aa629 VS |
2743 | if (IS_G4X(dev)) |
2744 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2745 | ||
b9897127 | 2746 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2747 | |
c2c75131 DV |
2748 | if (INTEL_INFO(dev)->gen >= 4) { |
2749 | intel_crtc->dspaddr_offset = | |
bc752862 | 2750 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2751 | pixel_size, |
bc752862 | 2752 | fb->pitches[0]); |
c2c75131 DV |
2753 | linear_offset -= intel_crtc->dspaddr_offset; |
2754 | } else { | |
e506a0c6 | 2755 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2756 | } |
e506a0c6 | 2757 | |
8e7d688b | 2758 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2759 | dspcntr |= DISPPLANE_ROTATE_180; |
2760 | ||
6e3c9717 ACO |
2761 | x += (intel_crtc->config->pipe_src_w - 1); |
2762 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2763 | |
2764 | /* Finding the last pixel of the last line of the display | |
2765 | data and adding to linear_offset*/ | |
2766 | linear_offset += | |
6e3c9717 ACO |
2767 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2768 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2769 | } |
2770 | ||
2771 | I915_WRITE(reg, dspcntr); | |
2772 | ||
01f2c773 | 2773 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2774 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2775 | I915_WRITE(DSPSURF(plane), |
2776 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2777 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2778 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2779 | } else |
f343c5f6 | 2780 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2781 | POSTING_READ(reg); |
17638cd6 JB |
2782 | } |
2783 | ||
29b9bde6 DV |
2784 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2785 | struct drm_framebuffer *fb, | |
2786 | int x, int y) | |
17638cd6 JB |
2787 | { |
2788 | struct drm_device *dev = crtc->dev; | |
2789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2791 | struct drm_plane *primary = crtc->primary; |
2792 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2793 | struct drm_i915_gem_object *obj; |
17638cd6 | 2794 | int plane = intel_crtc->plane; |
e506a0c6 | 2795 | unsigned long linear_offset; |
17638cd6 | 2796 | u32 dspcntr; |
f45651ba | 2797 | u32 reg = DSPCNTR(plane); |
48404c1e | 2798 | int pixel_size; |
f45651ba | 2799 | |
b70709a6 | 2800 | if (!visible || !fb) { |
fdd508a6 VS |
2801 | I915_WRITE(reg, 0); |
2802 | I915_WRITE(DSPSURF(plane), 0); | |
2803 | POSTING_READ(reg); | |
2804 | return; | |
2805 | } | |
2806 | ||
c9ba6fad VS |
2807 | obj = intel_fb_obj(fb); |
2808 | if (WARN_ON(obj == NULL)) | |
2809 | return; | |
2810 | ||
2811 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2812 | ||
f45651ba VS |
2813 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2814 | ||
fdd508a6 | 2815 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2816 | |
2817 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2818 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2819 | |
57779d06 VS |
2820 | switch (fb->pixel_format) { |
2821 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2822 | dspcntr |= DISPPLANE_8BPP; |
2823 | break; | |
57779d06 VS |
2824 | case DRM_FORMAT_RGB565: |
2825 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2826 | break; |
57779d06 VS |
2827 | case DRM_FORMAT_XRGB8888: |
2828 | case DRM_FORMAT_ARGB8888: | |
2829 | dspcntr |= DISPPLANE_BGRX888; | |
2830 | break; | |
2831 | case DRM_FORMAT_XBGR8888: | |
2832 | case DRM_FORMAT_ABGR8888: | |
2833 | dspcntr |= DISPPLANE_RGBX888; | |
2834 | break; | |
2835 | case DRM_FORMAT_XRGB2101010: | |
2836 | case DRM_FORMAT_ARGB2101010: | |
2837 | dspcntr |= DISPPLANE_BGRX101010; | |
2838 | break; | |
2839 | case DRM_FORMAT_XBGR2101010: | |
2840 | case DRM_FORMAT_ABGR2101010: | |
2841 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2842 | break; |
2843 | default: | |
baba133a | 2844 | BUG(); |
17638cd6 JB |
2845 | } |
2846 | ||
2847 | if (obj->tiling_mode != I915_TILING_NONE) | |
2848 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2849 | |
f45651ba | 2850 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2851 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2852 | |
b9897127 | 2853 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2854 | intel_crtc->dspaddr_offset = |
bc752862 | 2855 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2856 | pixel_size, |
bc752862 | 2857 | fb->pitches[0]); |
c2c75131 | 2858 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2859 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2860 | dspcntr |= DISPPLANE_ROTATE_180; |
2861 | ||
2862 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2863 | x += (intel_crtc->config->pipe_src_w - 1); |
2864 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2865 | |
2866 | /* Finding the last pixel of the last line of the display | |
2867 | data and adding to linear_offset*/ | |
2868 | linear_offset += | |
6e3c9717 ACO |
2869 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2870 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2871 | } |
2872 | } | |
2873 | ||
2874 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2875 | |
01f2c773 | 2876 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2877 | I915_WRITE(DSPSURF(plane), |
2878 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2879 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2880 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2881 | } else { | |
2882 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2883 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2884 | } | |
17638cd6 | 2885 | POSTING_READ(reg); |
17638cd6 JB |
2886 | } |
2887 | ||
b321803d DL |
2888 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2889 | uint32_t pixel_format) | |
2890 | { | |
2891 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2892 | ||
2893 | /* | |
2894 | * The stride is either expressed as a multiple of 64 bytes | |
2895 | * chunks for linear buffers or in number of tiles for tiled | |
2896 | * buffers. | |
2897 | */ | |
2898 | switch (fb_modifier) { | |
2899 | case DRM_FORMAT_MOD_NONE: | |
2900 | return 64; | |
2901 | case I915_FORMAT_MOD_X_TILED: | |
2902 | if (INTEL_INFO(dev)->gen == 2) | |
2903 | return 128; | |
2904 | return 512; | |
2905 | case I915_FORMAT_MOD_Y_TILED: | |
2906 | /* No need to check for old gens and Y tiling since this is | |
2907 | * about the display engine and those will be blocked before | |
2908 | * we get here. | |
2909 | */ | |
2910 | return 128; | |
2911 | case I915_FORMAT_MOD_Yf_TILED: | |
2912 | if (bits_per_pixel == 8) | |
2913 | return 64; | |
2914 | else | |
2915 | return 128; | |
2916 | default: | |
2917 | MISSING_CASE(fb_modifier); | |
2918 | return 64; | |
2919 | } | |
2920 | } | |
2921 | ||
121920fa TU |
2922 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2923 | struct drm_i915_gem_object *obj) | |
2924 | { | |
9abc4648 | 2925 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2926 | |
2927 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2928 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2929 | |
2930 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2931 | } | |
2932 | ||
a1b2278e CK |
2933 | /* |
2934 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2935 | */ | |
2936 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2937 | { | |
2938 | struct drm_device *dev; | |
2939 | struct drm_i915_private *dev_priv; | |
2940 | struct intel_crtc_scaler_state *scaler_state; | |
2941 | int i; | |
2942 | ||
2943 | if (!intel_crtc || !intel_crtc->config) | |
2944 | return; | |
2945 | ||
2946 | dev = intel_crtc->base.dev; | |
2947 | dev_priv = dev->dev_private; | |
2948 | scaler_state = &intel_crtc->config->scaler_state; | |
2949 | ||
2950 | /* loop through and disable scalers that aren't in use */ | |
2951 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2952 | if (!scaler_state->scalers[i].in_use) { | |
2953 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2954 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2955 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2956 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2957 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2958 | } | |
2959 | } | |
2960 | } | |
2961 | ||
6156a456 | 2962 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2963 | { |
6156a456 CK |
2964 | u32 plane_ctl_format = 0; |
2965 | switch (pixel_format) { | |
70d21f0e | 2966 | case DRM_FORMAT_RGB565: |
6156a456 | 2967 | plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; |
f75fb42a | 2968 | break; |
70d21f0e | 2969 | case DRM_FORMAT_XBGR8888: |
6156a456 CK |
2970 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
2971 | break; | |
2972 | case DRM_FORMAT_XRGB8888: | |
2973 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888; | |
70d21f0e | 2974 | break; |
6156a456 CK |
2975 | /* |
2976 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2977 | * to be already pre-multiplied. We need to add a knob (or a different | |
2978 | * DRM_FORMAT) for user-space to configure that. | |
2979 | */ | |
f75fb42a | 2980 | case DRM_FORMAT_ABGR8888: |
6156a456 CK |
2981 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
2982 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2983 | break; | |
2984 | case DRM_FORMAT_ARGB8888: | |
2985 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | | |
2986 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
f75fb42a | 2987 | break; |
70d21f0e | 2988 | case DRM_FORMAT_XRGB2101010: |
6156a456 | 2989 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e DL |
2990 | break; |
2991 | case DRM_FORMAT_XBGR2101010: | |
6156a456 CK |
2992 | plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
2993 | break; | |
2994 | case DRM_FORMAT_YUYV: | |
2995 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
2996 | break; | |
2997 | case DRM_FORMAT_YVYU: | |
2998 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
2999 | break; | |
3000 | case DRM_FORMAT_UYVY: | |
3001 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
3002 | break; | |
3003 | case DRM_FORMAT_VYUY: | |
3004 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
70d21f0e DL |
3005 | break; |
3006 | default: | |
3007 | BUG(); | |
3008 | } | |
6156a456 CK |
3009 | return plane_ctl_format; |
3010 | } | |
70d21f0e | 3011 | |
6156a456 CK |
3012 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3013 | { | |
3014 | u32 plane_ctl_tiling = 0; | |
3015 | switch (fb_modifier) { | |
30af77c4 | 3016 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3017 | break; |
30af77c4 | 3018 | case I915_FORMAT_MOD_X_TILED: |
6156a456 | 3019 | plane_ctl_tiling = PLANE_CTL_TILED_X; |
b321803d DL |
3020 | break; |
3021 | case I915_FORMAT_MOD_Y_TILED: | |
6156a456 | 3022 | plane_ctl_tiling = PLANE_CTL_TILED_Y; |
b321803d DL |
3023 | break; |
3024 | case I915_FORMAT_MOD_Yf_TILED: | |
6156a456 | 3025 | plane_ctl_tiling = PLANE_CTL_TILED_YF; |
70d21f0e DL |
3026 | break; |
3027 | default: | |
6156a456 | 3028 | MISSING_CASE(fb_modifier); |
70d21f0e | 3029 | } |
6156a456 CK |
3030 | return plane_ctl_tiling; |
3031 | } | |
70d21f0e | 3032 | |
6156a456 CK |
3033 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3034 | { | |
3035 | u32 plane_ctl_rotation = 0; | |
3b7a5119 | 3036 | switch (rotation) { |
6156a456 CK |
3037 | case BIT(DRM_ROTATE_0): |
3038 | break; | |
3b7a5119 | 3039 | case BIT(DRM_ROTATE_90): |
6156a456 | 3040 | plane_ctl_rotation = PLANE_CTL_ROTATE_90; |
3b7a5119 | 3041 | break; |
3b7a5119 | 3042 | case BIT(DRM_ROTATE_180): |
6156a456 | 3043 | plane_ctl_rotation = PLANE_CTL_ROTATE_180; |
3b7a5119 | 3044 | break; |
3b7a5119 | 3045 | case BIT(DRM_ROTATE_270): |
6156a456 | 3046 | plane_ctl_rotation = PLANE_CTL_ROTATE_270; |
3b7a5119 | 3047 | break; |
6156a456 CK |
3048 | default: |
3049 | MISSING_CASE(rotation); | |
3050 | } | |
3051 | ||
3052 | return plane_ctl_rotation; | |
3053 | } | |
3054 | ||
3055 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3056 | struct drm_framebuffer *fb, | |
3057 | int x, int y) | |
3058 | { | |
3059 | struct drm_device *dev = crtc->dev; | |
3060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3062 | struct drm_plane *plane = crtc->primary; |
3063 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3064 | struct drm_i915_gem_object *obj; |
3065 | int pipe = intel_crtc->pipe; | |
3066 | u32 plane_ctl, stride_div, stride; | |
3067 | u32 tile_height, plane_offset, plane_size; | |
3068 | unsigned int rotation; | |
3069 | int x_offset, y_offset; | |
3070 | unsigned long surf_addr; | |
6156a456 CK |
3071 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3072 | struct intel_plane_state *plane_state; | |
3073 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3074 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3075 | int scaler_id = -1; | |
3076 | ||
6156a456 CK |
3077 | plane_state = to_intel_plane_state(plane->state); |
3078 | ||
b70709a6 | 3079 | if (!visible || !fb) { |
6156a456 CK |
3080 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3081 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3082 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3083 | return; | |
3b7a5119 | 3084 | } |
70d21f0e | 3085 | |
6156a456 CK |
3086 | plane_ctl = PLANE_CTL_ENABLE | |
3087 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3088 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3089 | ||
3090 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3091 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3092 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3093 | ||
3094 | rotation = plane->state->rotation; | |
3095 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3096 | ||
b321803d DL |
3097 | obj = intel_fb_obj(fb); |
3098 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3099 | fb->pixel_format); | |
3b7a5119 SJ |
3100 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3101 | ||
6156a456 CK |
3102 | /* |
3103 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3104 | * update_plane helpers are called from legacy paths. | |
3105 | * Once full atomic crtc is available, below check can be avoided. | |
3106 | */ | |
3107 | if (drm_rect_width(&plane_state->src)) { | |
3108 | scaler_id = plane_state->scaler_id; | |
3109 | src_x = plane_state->src.x1 >> 16; | |
3110 | src_y = plane_state->src.y1 >> 16; | |
3111 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3112 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3113 | dst_x = plane_state->dst.x1; | |
3114 | dst_y = plane_state->dst.y1; | |
3115 | dst_w = drm_rect_width(&plane_state->dst); | |
3116 | dst_h = drm_rect_height(&plane_state->dst); | |
3117 | ||
3118 | WARN_ON(x != src_x || y != src_y); | |
3119 | } else { | |
3120 | src_w = intel_crtc->config->pipe_src_w; | |
3121 | src_h = intel_crtc->config->pipe_src_h; | |
3122 | } | |
3123 | ||
3b7a5119 SJ |
3124 | if (intel_rotation_90_or_270(rotation)) { |
3125 | /* stride = Surface height in tiles */ | |
3126 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3127 | fb->modifier[0]); | |
3128 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3129 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3130 | y_offset = x; |
6156a456 | 3131 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3132 | } else { |
3133 | stride = fb->pitches[0] / stride_div; | |
3134 | x_offset = x; | |
3135 | y_offset = y; | |
6156a456 | 3136 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3137 | } |
3138 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3139 | |
70d21f0e | 3140 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3141 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3142 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3143 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3144 | |
3145 | if (scaler_id >= 0) { | |
3146 | uint32_t ps_ctrl = 0; | |
3147 | ||
3148 | WARN_ON(!dst_w || !dst_h); | |
3149 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3150 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3151 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3152 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3153 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3154 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3155 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3156 | } else { | |
3157 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3158 | } | |
3159 | ||
121920fa | 3160 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3161 | |
3162 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3163 | } | |
3164 | ||
17638cd6 JB |
3165 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3166 | static int | |
3167 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3168 | int x, int y, enum mode_set_atomic state) | |
3169 | { | |
3170 | struct drm_device *dev = crtc->dev; | |
3171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3172 | |
6b8e6ed0 CW |
3173 | if (dev_priv->display.disable_fbc) |
3174 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3175 | |
29b9bde6 DV |
3176 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3177 | ||
3178 | return 0; | |
81255565 JB |
3179 | } |
3180 | ||
7514747d | 3181 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3182 | { |
96a02917 VS |
3183 | struct drm_crtc *crtc; |
3184 | ||
70e1e0ec | 3185 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3187 | enum plane plane = intel_crtc->plane; | |
3188 | ||
3189 | intel_prepare_page_flip(dev, plane); | |
3190 | intel_finish_page_flip_plane(dev, plane); | |
3191 | } | |
7514747d VS |
3192 | } |
3193 | ||
3194 | static void intel_update_primary_planes(struct drm_device *dev) | |
3195 | { | |
3196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3197 | struct drm_crtc *crtc; | |
96a02917 | 3198 | |
70e1e0ec | 3199 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3201 | ||
51fd371b | 3202 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3203 | /* |
3204 | * FIXME: Once we have proper support for primary planes (and | |
3205 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3206 | * a NULL crtc->primary->fb. |
947fdaad | 3207 | */ |
f4510a27 | 3208 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3209 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3210 | crtc->primary->fb, |
262ca2b0 MR |
3211 | crtc->x, |
3212 | crtc->y); | |
51fd371b | 3213 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3214 | } |
3215 | } | |
3216 | ||
7514747d VS |
3217 | void intel_prepare_reset(struct drm_device *dev) |
3218 | { | |
f98ce92f VS |
3219 | struct drm_i915_private *dev_priv = to_i915(dev); |
3220 | struct intel_crtc *crtc; | |
3221 | ||
7514747d VS |
3222 | /* no reset support for gen2 */ |
3223 | if (IS_GEN2(dev)) | |
3224 | return; | |
3225 | ||
3226 | /* reset doesn't touch the display */ | |
3227 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3228 | return; | |
3229 | ||
3230 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3231 | |
3232 | /* | |
3233 | * Disabling the crtcs gracefully seems nicer. Also the | |
3234 | * g33 docs say we should at least disable all the planes. | |
3235 | */ | |
3236 | for_each_intel_crtc(dev, crtc) { | |
3237 | if (crtc->active) | |
3238 | dev_priv->display.crtc_disable(&crtc->base); | |
3239 | } | |
7514747d VS |
3240 | } |
3241 | ||
3242 | void intel_finish_reset(struct drm_device *dev) | |
3243 | { | |
3244 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3245 | ||
3246 | /* | |
3247 | * Flips in the rings will be nuked by the reset, | |
3248 | * so complete all pending flips so that user space | |
3249 | * will get its events and not get stuck. | |
3250 | */ | |
3251 | intel_complete_page_flips(dev); | |
3252 | ||
3253 | /* no reset support for gen2 */ | |
3254 | if (IS_GEN2(dev)) | |
3255 | return; | |
3256 | ||
3257 | /* reset doesn't touch the display */ | |
3258 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3259 | /* | |
3260 | * Flips in the rings have been nuked by the reset, | |
3261 | * so update the base address of all primary | |
3262 | * planes to the the last fb to make sure we're | |
3263 | * showing the correct fb after a reset. | |
3264 | */ | |
3265 | intel_update_primary_planes(dev); | |
3266 | return; | |
3267 | } | |
3268 | ||
3269 | /* | |
3270 | * The display has been reset as well, | |
3271 | * so need a full re-initialization. | |
3272 | */ | |
3273 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3274 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3275 | ||
3276 | intel_modeset_init_hw(dev); | |
3277 | ||
3278 | spin_lock_irq(&dev_priv->irq_lock); | |
3279 | if (dev_priv->display.hpd_irq_setup) | |
3280 | dev_priv->display.hpd_irq_setup(dev); | |
3281 | spin_unlock_irq(&dev_priv->irq_lock); | |
3282 | ||
3283 | intel_modeset_setup_hw_state(dev, true); | |
3284 | ||
3285 | intel_hpd_init(dev_priv); | |
3286 | ||
3287 | drm_modeset_unlock_all(dev); | |
3288 | } | |
3289 | ||
14667a4b CW |
3290 | static int |
3291 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3292 | { | |
2ff8fde1 | 3293 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3294 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3295 | bool was_interruptible = dev_priv->mm.interruptible; | |
3296 | int ret; | |
3297 | ||
14667a4b CW |
3298 | /* Big Hammer, we also need to ensure that any pending |
3299 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3300 | * current scanout is retired before unpinning the old | |
3301 | * framebuffer. | |
3302 | * | |
3303 | * This should only fail upon a hung GPU, in which case we | |
3304 | * can safely continue. | |
3305 | */ | |
3306 | dev_priv->mm.interruptible = false; | |
3307 | ret = i915_gem_object_finish_gpu(obj); | |
3308 | dev_priv->mm.interruptible = was_interruptible; | |
3309 | ||
3310 | return ret; | |
3311 | } | |
3312 | ||
7d5e3799 CW |
3313 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3314 | { | |
3315 | struct drm_device *dev = crtc->dev; | |
3316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3318 | bool pending; |
3319 | ||
3320 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3321 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3322 | return false; | |
3323 | ||
5e2d7afc | 3324 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3325 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3326 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3327 | |
3328 | return pending; | |
3329 | } | |
3330 | ||
e30e8f75 GP |
3331 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3332 | { | |
3333 | struct drm_device *dev = crtc->base.dev; | |
3334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3335 | const struct drm_display_mode *adjusted_mode; | |
3336 | ||
3337 | if (!i915.fastboot) | |
3338 | return; | |
3339 | ||
3340 | /* | |
3341 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3342 | * that in compute_mode_changes we check the native mode (not the pfit | |
3343 | * mode) to see if we can flip rather than do a full mode set. In the | |
3344 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3345 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3346 | * sized surface. | |
3347 | * | |
3348 | * To fix this properly, we need to hoist the checks up into | |
3349 | * compute_mode_changes (or above), check the actual pfit state and | |
3350 | * whether the platform allows pfit disable with pipe active, and only | |
3351 | * then update the pipesrc and pfit state, even on the flip path. | |
3352 | */ | |
3353 | ||
6e3c9717 | 3354 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3355 | |
3356 | I915_WRITE(PIPESRC(crtc->pipe), | |
3357 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3358 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3359 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3360 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3361 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3362 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3363 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3364 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3365 | } | |
6e3c9717 ACO |
3366 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3367 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3368 | } |
3369 | ||
5e84e1a4 ZW |
3370 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3371 | { | |
3372 | struct drm_device *dev = crtc->dev; | |
3373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3375 | int pipe = intel_crtc->pipe; | |
3376 | u32 reg, temp; | |
3377 | ||
3378 | /* enable normal train */ | |
3379 | reg = FDI_TX_CTL(pipe); | |
3380 | temp = I915_READ(reg); | |
61e499bf | 3381 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3382 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3383 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3384 | } else { |
3385 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3386 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3387 | } |
5e84e1a4 ZW |
3388 | I915_WRITE(reg, temp); |
3389 | ||
3390 | reg = FDI_RX_CTL(pipe); | |
3391 | temp = I915_READ(reg); | |
3392 | if (HAS_PCH_CPT(dev)) { | |
3393 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3394 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3395 | } else { | |
3396 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3397 | temp |= FDI_LINK_TRAIN_NONE; | |
3398 | } | |
3399 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3400 | ||
3401 | /* wait one idle pattern time */ | |
3402 | POSTING_READ(reg); | |
3403 | udelay(1000); | |
357555c0 JB |
3404 | |
3405 | /* IVB wants error correction enabled */ | |
3406 | if (IS_IVYBRIDGE(dev)) | |
3407 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3408 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3409 | } |
3410 | ||
8db9d77b ZW |
3411 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3412 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3413 | { | |
3414 | struct drm_device *dev = crtc->dev; | |
3415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3416 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3417 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3418 | u32 reg, temp, tries; |
8db9d77b | 3419 | |
1c8562f6 | 3420 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3421 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3422 | |
e1a44743 AJ |
3423 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3424 | for train result */ | |
5eddb70b CW |
3425 | reg = FDI_RX_IMR(pipe); |
3426 | temp = I915_READ(reg); | |
e1a44743 AJ |
3427 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3428 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3429 | I915_WRITE(reg, temp); |
3430 | I915_READ(reg); | |
e1a44743 AJ |
3431 | udelay(150); |
3432 | ||
8db9d77b | 3433 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3434 | reg = FDI_TX_CTL(pipe); |
3435 | temp = I915_READ(reg); | |
627eb5a3 | 3436 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3437 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3438 | temp &= ~FDI_LINK_TRAIN_NONE; |
3439 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3440 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3441 | |
5eddb70b CW |
3442 | reg = FDI_RX_CTL(pipe); |
3443 | temp = I915_READ(reg); | |
8db9d77b ZW |
3444 | temp &= ~FDI_LINK_TRAIN_NONE; |
3445 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3446 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3447 | ||
3448 | POSTING_READ(reg); | |
8db9d77b ZW |
3449 | udelay(150); |
3450 | ||
5b2adf89 | 3451 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3452 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3453 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3454 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3455 | |
5eddb70b | 3456 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3457 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3458 | temp = I915_READ(reg); |
8db9d77b ZW |
3459 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3460 | ||
3461 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3462 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3463 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3464 | break; |
3465 | } | |
8db9d77b | 3466 | } |
e1a44743 | 3467 | if (tries == 5) |
5eddb70b | 3468 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3469 | |
3470 | /* Train 2 */ | |
5eddb70b CW |
3471 | reg = FDI_TX_CTL(pipe); |
3472 | temp = I915_READ(reg); | |
8db9d77b ZW |
3473 | temp &= ~FDI_LINK_TRAIN_NONE; |
3474 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3475 | I915_WRITE(reg, temp); |
8db9d77b | 3476 | |
5eddb70b CW |
3477 | reg = FDI_RX_CTL(pipe); |
3478 | temp = I915_READ(reg); | |
8db9d77b ZW |
3479 | temp &= ~FDI_LINK_TRAIN_NONE; |
3480 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3481 | I915_WRITE(reg, temp); |
8db9d77b | 3482 | |
5eddb70b CW |
3483 | POSTING_READ(reg); |
3484 | udelay(150); | |
8db9d77b | 3485 | |
5eddb70b | 3486 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3487 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3488 | temp = I915_READ(reg); |
8db9d77b ZW |
3489 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3490 | ||
3491 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3492 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3493 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3494 | break; | |
3495 | } | |
8db9d77b | 3496 | } |
e1a44743 | 3497 | if (tries == 5) |
5eddb70b | 3498 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3499 | |
3500 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3501 | |
8db9d77b ZW |
3502 | } |
3503 | ||
0206e353 | 3504 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3505 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3506 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3507 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3508 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3509 | }; | |
3510 | ||
3511 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3512 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3513 | { | |
3514 | struct drm_device *dev = crtc->dev; | |
3515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3516 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3517 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3518 | u32 reg, temp, i, retry; |
8db9d77b | 3519 | |
e1a44743 AJ |
3520 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3521 | for train result */ | |
5eddb70b CW |
3522 | reg = FDI_RX_IMR(pipe); |
3523 | temp = I915_READ(reg); | |
e1a44743 AJ |
3524 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3525 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3526 | I915_WRITE(reg, temp); |
3527 | ||
3528 | POSTING_READ(reg); | |
e1a44743 AJ |
3529 | udelay(150); |
3530 | ||
8db9d77b | 3531 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3532 | reg = FDI_TX_CTL(pipe); |
3533 | temp = I915_READ(reg); | |
627eb5a3 | 3534 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3535 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3536 | temp &= ~FDI_LINK_TRAIN_NONE; |
3537 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3538 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3539 | /* SNB-B */ | |
3540 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3541 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3542 | |
d74cf324 DV |
3543 | I915_WRITE(FDI_RX_MISC(pipe), |
3544 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3545 | ||
5eddb70b CW |
3546 | reg = FDI_RX_CTL(pipe); |
3547 | temp = I915_READ(reg); | |
8db9d77b ZW |
3548 | if (HAS_PCH_CPT(dev)) { |
3549 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3550 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3551 | } else { | |
3552 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3553 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3554 | } | |
5eddb70b CW |
3555 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3556 | ||
3557 | POSTING_READ(reg); | |
8db9d77b ZW |
3558 | udelay(150); |
3559 | ||
0206e353 | 3560 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3561 | reg = FDI_TX_CTL(pipe); |
3562 | temp = I915_READ(reg); | |
8db9d77b ZW |
3563 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3564 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3565 | I915_WRITE(reg, temp); |
3566 | ||
3567 | POSTING_READ(reg); | |
8db9d77b ZW |
3568 | udelay(500); |
3569 | ||
fa37d39e SP |
3570 | for (retry = 0; retry < 5; retry++) { |
3571 | reg = FDI_RX_IIR(pipe); | |
3572 | temp = I915_READ(reg); | |
3573 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3574 | if (temp & FDI_RX_BIT_LOCK) { | |
3575 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3576 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3577 | break; | |
3578 | } | |
3579 | udelay(50); | |
8db9d77b | 3580 | } |
fa37d39e SP |
3581 | if (retry < 5) |
3582 | break; | |
8db9d77b ZW |
3583 | } |
3584 | if (i == 4) | |
5eddb70b | 3585 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3586 | |
3587 | /* Train 2 */ | |
5eddb70b CW |
3588 | reg = FDI_TX_CTL(pipe); |
3589 | temp = I915_READ(reg); | |
8db9d77b ZW |
3590 | temp &= ~FDI_LINK_TRAIN_NONE; |
3591 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3592 | if (IS_GEN6(dev)) { | |
3593 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3594 | /* SNB-B */ | |
3595 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3596 | } | |
5eddb70b | 3597 | I915_WRITE(reg, temp); |
8db9d77b | 3598 | |
5eddb70b CW |
3599 | reg = FDI_RX_CTL(pipe); |
3600 | temp = I915_READ(reg); | |
8db9d77b ZW |
3601 | if (HAS_PCH_CPT(dev)) { |
3602 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3603 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3604 | } else { | |
3605 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3606 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3607 | } | |
5eddb70b CW |
3608 | I915_WRITE(reg, temp); |
3609 | ||
3610 | POSTING_READ(reg); | |
8db9d77b ZW |
3611 | udelay(150); |
3612 | ||
0206e353 | 3613 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3614 | reg = FDI_TX_CTL(pipe); |
3615 | temp = I915_READ(reg); | |
8db9d77b ZW |
3616 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3617 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3618 | I915_WRITE(reg, temp); |
3619 | ||
3620 | POSTING_READ(reg); | |
8db9d77b ZW |
3621 | udelay(500); |
3622 | ||
fa37d39e SP |
3623 | for (retry = 0; retry < 5; retry++) { |
3624 | reg = FDI_RX_IIR(pipe); | |
3625 | temp = I915_READ(reg); | |
3626 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3627 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3628 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3629 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3630 | break; | |
3631 | } | |
3632 | udelay(50); | |
8db9d77b | 3633 | } |
fa37d39e SP |
3634 | if (retry < 5) |
3635 | break; | |
8db9d77b ZW |
3636 | } |
3637 | if (i == 4) | |
5eddb70b | 3638 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3639 | |
3640 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3641 | } | |
3642 | ||
357555c0 JB |
3643 | /* Manual link training for Ivy Bridge A0 parts */ |
3644 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3645 | { | |
3646 | struct drm_device *dev = crtc->dev; | |
3647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3649 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3650 | u32 reg, temp, i, j; |
357555c0 JB |
3651 | |
3652 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3653 | for train result */ | |
3654 | reg = FDI_RX_IMR(pipe); | |
3655 | temp = I915_READ(reg); | |
3656 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3657 | temp &= ~FDI_RX_BIT_LOCK; | |
3658 | I915_WRITE(reg, temp); | |
3659 | ||
3660 | POSTING_READ(reg); | |
3661 | udelay(150); | |
3662 | ||
01a415fd DV |
3663 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3664 | I915_READ(FDI_RX_IIR(pipe))); | |
3665 | ||
139ccd3f JB |
3666 | /* Try each vswing and preemphasis setting twice before moving on */ |
3667 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3668 | /* disable first in case we need to retry */ | |
3669 | reg = FDI_TX_CTL(pipe); | |
3670 | temp = I915_READ(reg); | |
3671 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3672 | temp &= ~FDI_TX_ENABLE; | |
3673 | I915_WRITE(reg, temp); | |
357555c0 | 3674 | |
139ccd3f JB |
3675 | reg = FDI_RX_CTL(pipe); |
3676 | temp = I915_READ(reg); | |
3677 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3678 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3679 | temp &= ~FDI_RX_ENABLE; | |
3680 | I915_WRITE(reg, temp); | |
357555c0 | 3681 | |
139ccd3f | 3682 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3683 | reg = FDI_TX_CTL(pipe); |
3684 | temp = I915_READ(reg); | |
139ccd3f | 3685 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3686 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3687 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3688 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3689 | temp |= snb_b_fdi_train_param[j/2]; |
3690 | temp |= FDI_COMPOSITE_SYNC; | |
3691 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3692 | |
139ccd3f JB |
3693 | I915_WRITE(FDI_RX_MISC(pipe), |
3694 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3695 | |
139ccd3f | 3696 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3697 | temp = I915_READ(reg); |
139ccd3f JB |
3698 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3699 | temp |= FDI_COMPOSITE_SYNC; | |
3700 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3701 | |
139ccd3f JB |
3702 | POSTING_READ(reg); |
3703 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3704 | |
139ccd3f JB |
3705 | for (i = 0; i < 4; i++) { |
3706 | reg = FDI_RX_IIR(pipe); | |
3707 | temp = I915_READ(reg); | |
3708 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3709 | |
139ccd3f JB |
3710 | if (temp & FDI_RX_BIT_LOCK || |
3711 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3712 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3713 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3714 | i); | |
3715 | break; | |
3716 | } | |
3717 | udelay(1); /* should be 0.5us */ | |
3718 | } | |
3719 | if (i == 4) { | |
3720 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3721 | continue; | |
3722 | } | |
357555c0 | 3723 | |
139ccd3f | 3724 | /* Train 2 */ |
357555c0 JB |
3725 | reg = FDI_TX_CTL(pipe); |
3726 | temp = I915_READ(reg); | |
139ccd3f JB |
3727 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3728 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3729 | I915_WRITE(reg, temp); | |
3730 | ||
3731 | reg = FDI_RX_CTL(pipe); | |
3732 | temp = I915_READ(reg); | |
3733 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3734 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3735 | I915_WRITE(reg, temp); |
3736 | ||
3737 | POSTING_READ(reg); | |
139ccd3f | 3738 | udelay(2); /* should be 1.5us */ |
357555c0 | 3739 | |
139ccd3f JB |
3740 | for (i = 0; i < 4; i++) { |
3741 | reg = FDI_RX_IIR(pipe); | |
3742 | temp = I915_READ(reg); | |
3743 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3744 | |
139ccd3f JB |
3745 | if (temp & FDI_RX_SYMBOL_LOCK || |
3746 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3747 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3748 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3749 | i); | |
3750 | goto train_done; | |
3751 | } | |
3752 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3753 | } |
139ccd3f JB |
3754 | if (i == 4) |
3755 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3756 | } |
357555c0 | 3757 | |
139ccd3f | 3758 | train_done: |
357555c0 JB |
3759 | DRM_DEBUG_KMS("FDI train done.\n"); |
3760 | } | |
3761 | ||
88cefb6c | 3762 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3763 | { |
88cefb6c | 3764 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3765 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3766 | int pipe = intel_crtc->pipe; |
5eddb70b | 3767 | u32 reg, temp; |
79e53945 | 3768 | |
c64e311e | 3769 | |
c98e9dcf | 3770 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3771 | reg = FDI_RX_CTL(pipe); |
3772 | temp = I915_READ(reg); | |
627eb5a3 | 3773 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3774 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3775 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3776 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3777 | ||
3778 | POSTING_READ(reg); | |
c98e9dcf JB |
3779 | udelay(200); |
3780 | ||
3781 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3782 | temp = I915_READ(reg); |
3783 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3784 | ||
3785 | POSTING_READ(reg); | |
c98e9dcf JB |
3786 | udelay(200); |
3787 | ||
20749730 PZ |
3788 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3789 | reg = FDI_TX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3792 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3793 | |
20749730 PZ |
3794 | POSTING_READ(reg); |
3795 | udelay(100); | |
6be4a607 | 3796 | } |
0e23b99d JB |
3797 | } |
3798 | ||
88cefb6c DV |
3799 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3800 | { | |
3801 | struct drm_device *dev = intel_crtc->base.dev; | |
3802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3803 | int pipe = intel_crtc->pipe; | |
3804 | u32 reg, temp; | |
3805 | ||
3806 | /* Switch from PCDclk to Rawclk */ | |
3807 | reg = FDI_RX_CTL(pipe); | |
3808 | temp = I915_READ(reg); | |
3809 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3810 | ||
3811 | /* Disable CPU FDI TX PLL */ | |
3812 | reg = FDI_TX_CTL(pipe); | |
3813 | temp = I915_READ(reg); | |
3814 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3815 | ||
3816 | POSTING_READ(reg); | |
3817 | udelay(100); | |
3818 | ||
3819 | reg = FDI_RX_CTL(pipe); | |
3820 | temp = I915_READ(reg); | |
3821 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3822 | ||
3823 | /* Wait for the clocks to turn off. */ | |
3824 | POSTING_READ(reg); | |
3825 | udelay(100); | |
3826 | } | |
3827 | ||
0fc932b8 JB |
3828 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3829 | { | |
3830 | struct drm_device *dev = crtc->dev; | |
3831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3832 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3833 | int pipe = intel_crtc->pipe; | |
3834 | u32 reg, temp; | |
3835 | ||
3836 | /* disable CPU FDI tx and PCH FDI rx */ | |
3837 | reg = FDI_TX_CTL(pipe); | |
3838 | temp = I915_READ(reg); | |
3839 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3840 | POSTING_READ(reg); | |
3841 | ||
3842 | reg = FDI_RX_CTL(pipe); | |
3843 | temp = I915_READ(reg); | |
3844 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3845 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3846 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3847 | ||
3848 | POSTING_READ(reg); | |
3849 | udelay(100); | |
3850 | ||
3851 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3852 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3853 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3854 | |
3855 | /* still set train pattern 1 */ | |
3856 | reg = FDI_TX_CTL(pipe); | |
3857 | temp = I915_READ(reg); | |
3858 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3859 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3860 | I915_WRITE(reg, temp); | |
3861 | ||
3862 | reg = FDI_RX_CTL(pipe); | |
3863 | temp = I915_READ(reg); | |
3864 | if (HAS_PCH_CPT(dev)) { | |
3865 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3866 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3867 | } else { | |
3868 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3869 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3870 | } | |
3871 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3872 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3873 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3874 | I915_WRITE(reg, temp); |
3875 | ||
3876 | POSTING_READ(reg); | |
3877 | udelay(100); | |
3878 | } | |
3879 | ||
5dce5b93 CW |
3880 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3881 | { | |
3882 | struct intel_crtc *crtc; | |
3883 | ||
3884 | /* Note that we don't need to be called with mode_config.lock here | |
3885 | * as our list of CRTC objects is static for the lifetime of the | |
3886 | * device and so cannot disappear as we iterate. Similarly, we can | |
3887 | * happily treat the predicates as racy, atomic checks as userspace | |
3888 | * cannot claim and pin a new fb without at least acquring the | |
3889 | * struct_mutex and so serialising with us. | |
3890 | */ | |
d3fcc808 | 3891 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3892 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3893 | continue; | |
3894 | ||
3895 | if (crtc->unpin_work) | |
3896 | intel_wait_for_vblank(dev, crtc->pipe); | |
3897 | ||
3898 | return true; | |
3899 | } | |
3900 | ||
3901 | return false; | |
3902 | } | |
3903 | ||
d6bbafa1 CW |
3904 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3905 | { | |
3906 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3907 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3908 | ||
3909 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3910 | smp_rmb(); | |
3911 | intel_crtc->unpin_work = NULL; | |
3912 | ||
3913 | if (work->event) | |
3914 | drm_send_vblank_event(intel_crtc->base.dev, | |
3915 | intel_crtc->pipe, | |
3916 | work->event); | |
3917 | ||
3918 | drm_crtc_vblank_put(&intel_crtc->base); | |
3919 | ||
3920 | wake_up_all(&dev_priv->pending_flip_queue); | |
3921 | queue_work(dev_priv->wq, &work->work); | |
3922 | ||
3923 | trace_i915_flip_complete(intel_crtc->plane, | |
3924 | work->pending_flip_obj); | |
3925 | } | |
3926 | ||
46a55d30 | 3927 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3928 | { |
0f91128d | 3929 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3930 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3931 | |
2c10d571 | 3932 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3933 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3934 | !intel_crtc_has_pending_flip(crtc), | |
3935 | 60*HZ) == 0)) { | |
3936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3937 | |
5e2d7afc | 3938 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3939 | if (intel_crtc->unpin_work) { |
3940 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3941 | page_flip_completed(intel_crtc); | |
3942 | } | |
5e2d7afc | 3943 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3944 | } |
5bb61643 | 3945 | |
975d568a CW |
3946 | if (crtc->primary->fb) { |
3947 | mutex_lock(&dev->struct_mutex); | |
3948 | intel_finish_fb(crtc->primary->fb); | |
3949 | mutex_unlock(&dev->struct_mutex); | |
3950 | } | |
e6c3a2a6 CW |
3951 | } |
3952 | ||
e615efe4 ED |
3953 | /* Program iCLKIP clock to the desired frequency */ |
3954 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3955 | { | |
3956 | struct drm_device *dev = crtc->dev; | |
3957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3958 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3959 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3960 | u32 temp; | |
3961 | ||
09153000 DV |
3962 | mutex_lock(&dev_priv->dpio_lock); |
3963 | ||
e615efe4 ED |
3964 | /* It is necessary to ungate the pixclk gate prior to programming |
3965 | * the divisors, and gate it back when it is done. | |
3966 | */ | |
3967 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3968 | ||
3969 | /* Disable SSCCTL */ | |
3970 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3971 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3972 | SBI_SSCCTL_DISABLE, | |
3973 | SBI_ICLK); | |
e615efe4 ED |
3974 | |
3975 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3976 | if (clock == 20000) { |
e615efe4 ED |
3977 | auxdiv = 1; |
3978 | divsel = 0x41; | |
3979 | phaseinc = 0x20; | |
3980 | } else { | |
3981 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3982 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3983 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3984 | * convert the virtual clock precision to KHz here for higher |
3985 | * precision. | |
3986 | */ | |
3987 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3988 | u32 iclk_pi_range = 64; | |
3989 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3990 | ||
12d7ceed | 3991 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3992 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3993 | pi_value = desired_divisor % iclk_pi_range; | |
3994 | ||
3995 | auxdiv = 0; | |
3996 | divsel = msb_divisor_value - 2; | |
3997 | phaseinc = pi_value; | |
3998 | } | |
3999 | ||
4000 | /* This should not happen with any sane values */ | |
4001 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4002 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4003 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4004 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4005 | ||
4006 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4007 | clock, |
e615efe4 ED |
4008 | auxdiv, |
4009 | divsel, | |
4010 | phasedir, | |
4011 | phaseinc); | |
4012 | ||
4013 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4014 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4015 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4016 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4017 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4018 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4019 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4020 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4021 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4022 | |
4023 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4024 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4025 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4026 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4027 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4028 | |
4029 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4030 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4031 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4032 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4033 | |
4034 | /* Wait for initialization time */ | |
4035 | udelay(24); | |
4036 | ||
4037 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
4038 | |
4039 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
4040 | } |
4041 | ||
275f01b2 DV |
4042 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4043 | enum pipe pch_transcoder) | |
4044 | { | |
4045 | struct drm_device *dev = crtc->base.dev; | |
4046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4047 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4048 | |
4049 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4050 | I915_READ(HTOTAL(cpu_transcoder))); | |
4051 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4052 | I915_READ(HBLANK(cpu_transcoder))); | |
4053 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4054 | I915_READ(HSYNC(cpu_transcoder))); | |
4055 | ||
4056 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4057 | I915_READ(VTOTAL(cpu_transcoder))); | |
4058 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4059 | I915_READ(VBLANK(cpu_transcoder))); | |
4060 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4061 | I915_READ(VSYNC(cpu_transcoder))); | |
4062 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4063 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4064 | } | |
4065 | ||
003632d9 | 4066 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4067 | { |
4068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4069 | uint32_t temp; | |
4070 | ||
4071 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4072 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4073 | return; |
4074 | ||
4075 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4076 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4077 | ||
003632d9 ACO |
4078 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4079 | if (enable) | |
4080 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4081 | ||
4082 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4083 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4084 | POSTING_READ(SOUTH_CHICKEN1); | |
4085 | } | |
4086 | ||
4087 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4088 | { | |
4089 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4090 | |
4091 | switch (intel_crtc->pipe) { | |
4092 | case PIPE_A: | |
4093 | break; | |
4094 | case PIPE_B: | |
6e3c9717 | 4095 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4096 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4097 | else |
003632d9 | 4098 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4099 | |
4100 | break; | |
4101 | case PIPE_C: | |
003632d9 | 4102 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4103 | |
4104 | break; | |
4105 | default: | |
4106 | BUG(); | |
4107 | } | |
4108 | } | |
4109 | ||
f67a559d JB |
4110 | /* |
4111 | * Enable PCH resources required for PCH ports: | |
4112 | * - PCH PLLs | |
4113 | * - FDI training & RX/TX | |
4114 | * - update transcoder timings | |
4115 | * - DP transcoding bits | |
4116 | * - transcoder | |
4117 | */ | |
4118 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4119 | { |
4120 | struct drm_device *dev = crtc->dev; | |
4121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4123 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4124 | u32 reg, temp; |
2c07245f | 4125 | |
ab9412ba | 4126 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4127 | |
1fbc0d78 DV |
4128 | if (IS_IVYBRIDGE(dev)) |
4129 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4130 | ||
cd986abb DV |
4131 | /* Write the TU size bits before fdi link training, so that error |
4132 | * detection works. */ | |
4133 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4134 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4135 | ||
c98e9dcf | 4136 | /* For PCH output, training FDI link */ |
674cf967 | 4137 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4138 | |
3ad8a208 DV |
4139 | /* We need to program the right clock selection before writing the pixel |
4140 | * mutliplier into the DPLL. */ | |
303b81e0 | 4141 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4142 | u32 sel; |
4b645f14 | 4143 | |
c98e9dcf | 4144 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4145 | temp |= TRANS_DPLL_ENABLE(pipe); |
4146 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4147 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4148 | temp |= sel; |
4149 | else | |
4150 | temp &= ~sel; | |
c98e9dcf | 4151 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4152 | } |
5eddb70b | 4153 | |
3ad8a208 DV |
4154 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4155 | * transcoder, and we actually should do this to not upset any PCH | |
4156 | * transcoder that already use the clock when we share it. | |
4157 | * | |
4158 | * Note that enable_shared_dpll tries to do the right thing, but | |
4159 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4160 | * the right LVDS enable sequence. */ | |
85b3894f | 4161 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4162 | |
d9b6cb56 JB |
4163 | /* set transcoder timing, panel must allow it */ |
4164 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4165 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4166 | |
303b81e0 | 4167 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4168 | |
c98e9dcf | 4169 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4170 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4171 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4172 | reg = TRANS_DP_CTL(pipe); |
4173 | temp = I915_READ(reg); | |
4174 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4175 | TRANS_DP_SYNC_MASK | |
4176 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4177 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4178 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4179 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4180 | |
4181 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4182 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4183 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4184 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4185 | |
4186 | switch (intel_trans_dp_port_sel(crtc)) { | |
4187 | case PCH_DP_B: | |
5eddb70b | 4188 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4189 | break; |
4190 | case PCH_DP_C: | |
5eddb70b | 4191 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4192 | break; |
4193 | case PCH_DP_D: | |
5eddb70b | 4194 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4195 | break; |
4196 | default: | |
e95d41e1 | 4197 | BUG(); |
32f9d658 | 4198 | } |
2c07245f | 4199 | |
5eddb70b | 4200 | I915_WRITE(reg, temp); |
6be4a607 | 4201 | } |
b52eb4dc | 4202 | |
b8a4f404 | 4203 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4204 | } |
4205 | ||
1507e5bd PZ |
4206 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4207 | { | |
4208 | struct drm_device *dev = crtc->dev; | |
4209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4211 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4212 | |
ab9412ba | 4213 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4214 | |
8c52b5e8 | 4215 | lpt_program_iclkip(crtc); |
1507e5bd | 4216 | |
0540e488 | 4217 | /* Set transcoder timing. */ |
275f01b2 | 4218 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4219 | |
937bb610 | 4220 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4221 | } |
4222 | ||
716c2e55 | 4223 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4224 | { |
e2b78267 | 4225 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4226 | |
4227 | if (pll == NULL) | |
4228 | return; | |
4229 | ||
3e369b76 | 4230 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4231 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4232 | return; |
4233 | } | |
4234 | ||
3e369b76 ACO |
4235 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4236 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4237 | WARN_ON(pll->on); |
4238 | WARN_ON(pll->active); | |
4239 | } | |
4240 | ||
6e3c9717 | 4241 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4242 | } |
4243 | ||
190f68c5 ACO |
4244 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4245 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4246 | { |
e2b78267 | 4247 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4248 | struct intel_shared_dpll *pll; |
e2b78267 | 4249 | enum intel_dpll_id i; |
ee7b9f93 | 4250 | |
98b6bd99 DV |
4251 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4252 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4253 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4254 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4255 | |
46edb027 DV |
4256 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4257 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4258 | |
8bd31e67 | 4259 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4260 | |
98b6bd99 DV |
4261 | goto found; |
4262 | } | |
4263 | ||
bcddf610 S |
4264 | if (IS_BROXTON(dev_priv->dev)) { |
4265 | /* PLL is attached to port in bxt */ | |
4266 | struct intel_encoder *encoder; | |
4267 | struct intel_digital_port *intel_dig_port; | |
4268 | ||
4269 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4270 | if (WARN_ON(!encoder)) | |
4271 | return NULL; | |
4272 | ||
4273 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4274 | /* 1:1 mapping between ports and PLLs */ | |
4275 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4276 | pll = &dev_priv->shared_dplls[i]; | |
4277 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4278 | crtc->base.base.id, pll->name); | |
4279 | WARN_ON(pll->new_config->crtc_mask); | |
4280 | ||
4281 | goto found; | |
4282 | } | |
4283 | ||
e72f9fbf DV |
4284 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4285 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4286 | |
4287 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4288 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4289 | continue; |
4290 | ||
190f68c5 | 4291 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4292 | &pll->new_config->hw_state, |
4293 | sizeof(pll->new_config->hw_state)) == 0) { | |
4294 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4295 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4296 | pll->new_config->crtc_mask, |
4297 | pll->active); | |
ee7b9f93 JB |
4298 | goto found; |
4299 | } | |
4300 | } | |
4301 | ||
4302 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4303 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4304 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4305 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4306 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4307 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4308 | goto found; |
4309 | } | |
4310 | } | |
4311 | ||
4312 | return NULL; | |
4313 | ||
4314 | found: | |
8bd31e67 | 4315 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4316 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4317 | |
190f68c5 | 4318 | crtc_state->shared_dpll = i; |
46edb027 DV |
4319 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4320 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4321 | |
8bd31e67 | 4322 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4323 | |
ee7b9f93 JB |
4324 | return pll; |
4325 | } | |
4326 | ||
8bd31e67 ACO |
4327 | /** |
4328 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4329 | * @dev_priv: DRM device | |
4330 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4331 | * | |
4332 | * Starts a new PLL staged config, copying the current config but | |
4333 | * releasing the references of pipes specified in clear_pipes. | |
4334 | */ | |
4335 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4336 | unsigned clear_pipes) | |
4337 | { | |
4338 | struct intel_shared_dpll *pll; | |
4339 | enum intel_dpll_id i; | |
4340 | ||
4341 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4342 | pll = &dev_priv->shared_dplls[i]; | |
4343 | ||
4344 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4345 | GFP_KERNEL); | |
4346 | if (!pll->new_config) | |
4347 | goto cleanup; | |
4348 | ||
4349 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4350 | } | |
4351 | ||
4352 | return 0; | |
4353 | ||
4354 | cleanup: | |
4355 | while (--i >= 0) { | |
4356 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4357 | kfree(pll->new_config); |
8bd31e67 ACO |
4358 | pll->new_config = NULL; |
4359 | } | |
4360 | ||
4361 | return -ENOMEM; | |
4362 | } | |
4363 | ||
4364 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4365 | { | |
4366 | struct intel_shared_dpll *pll; | |
4367 | enum intel_dpll_id i; | |
4368 | ||
4369 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4370 | pll = &dev_priv->shared_dplls[i]; | |
4371 | ||
4372 | WARN_ON(pll->new_config == &pll->config); | |
4373 | ||
4374 | pll->config = *pll->new_config; | |
4375 | kfree(pll->new_config); | |
4376 | pll->new_config = NULL; | |
4377 | } | |
4378 | } | |
4379 | ||
4380 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4381 | { | |
4382 | struct intel_shared_dpll *pll; | |
4383 | enum intel_dpll_id i; | |
4384 | ||
4385 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4386 | pll = &dev_priv->shared_dplls[i]; | |
4387 | ||
4388 | WARN_ON(pll->new_config == &pll->config); | |
4389 | ||
4390 | kfree(pll->new_config); | |
4391 | pll->new_config = NULL; | |
4392 | } | |
4393 | } | |
4394 | ||
a1520318 | 4395 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4396 | { |
4397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4398 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4399 | u32 temp; |
4400 | ||
4401 | temp = I915_READ(dslreg); | |
4402 | udelay(500); | |
4403 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4404 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4405 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4406 | } |
4407 | } | |
4408 | ||
a1b2278e CK |
4409 | /** |
4410 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4411 | * @intel_crtc: crtc | |
4412 | * @crtc_state: crtc_state | |
4413 | * @plane: plane (NULL indicates crtc is requesting update) | |
4414 | * @plane_state: plane's state | |
4415 | * @force_detach: request unconditional detachment of scaler | |
4416 | * | |
4417 | * This function updates scaler state for requested plane or crtc. | |
4418 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4419 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4420 | * as NULL. | |
4421 | * | |
4422 | * Return | |
4423 | * 0 - scaler_usage updated successfully | |
4424 | * error - requested scaling cannot be supported or other error condition | |
4425 | */ | |
4426 | int | |
4427 | skl_update_scaler_users( | |
4428 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4429 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4430 | int force_detach) | |
4431 | { | |
4432 | int need_scaling; | |
4433 | int idx; | |
4434 | int src_w, src_h, dst_w, dst_h; | |
4435 | int *scaler_id; | |
4436 | struct drm_framebuffer *fb; | |
4437 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4438 | unsigned int rotation; |
a1b2278e CK |
4439 | |
4440 | if (!intel_crtc || !crtc_state) | |
4441 | return 0; | |
4442 | ||
4443 | scaler_state = &crtc_state->scaler_state; | |
4444 | ||
4445 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4446 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4447 | ||
4448 | if (intel_plane) { | |
4449 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4450 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4451 | dst_w = drm_rect_width(&plane_state->dst); | |
4452 | dst_h = drm_rect_height(&plane_state->dst); | |
4453 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4454 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4455 | } else { |
4456 | struct drm_display_mode *adjusted_mode = | |
4457 | &crtc_state->base.adjusted_mode; | |
4458 | src_w = crtc_state->pipe_src_w; | |
4459 | src_h = crtc_state->pipe_src_h; | |
4460 | dst_w = adjusted_mode->hdisplay; | |
4461 | dst_h = adjusted_mode->vdisplay; | |
4462 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4463 | rotation = DRM_ROTATE_0; |
a1b2278e | 4464 | } |
6156a456 CK |
4465 | |
4466 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4467 | (src_h != dst_w || src_w != dst_h): | |
4468 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4469 | |
4470 | /* | |
4471 | * if plane is being disabled or scaler is no more required or force detach | |
4472 | * - free scaler binded to this plane/crtc | |
4473 | * - in order to do this, update crtc->scaler_usage | |
4474 | * | |
4475 | * Here scaler state in crtc_state is set free so that | |
4476 | * scaler can be assigned to other user. Actual register | |
4477 | * update to free the scaler is done in plane/panel-fit programming. | |
4478 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4479 | */ | |
4480 | if (force_detach || !need_scaling || (intel_plane && | |
4481 | (!fb || !plane_state->visible))) { | |
4482 | if (*scaler_id >= 0) { | |
4483 | scaler_state->scaler_users &= ~(1 << idx); | |
4484 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4485 | ||
4486 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4487 | "crtc_state = %p scaler_users = 0x%x\n", | |
4488 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4489 | intel_plane ? intel_plane->base.base.id : | |
4490 | intel_crtc->base.base.id, crtc_state, | |
4491 | scaler_state->scaler_users); | |
4492 | *scaler_id = -1; | |
4493 | } | |
4494 | return 0; | |
4495 | } | |
4496 | ||
4497 | /* range checks */ | |
4498 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4499 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4500 | ||
4501 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4502 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4503 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4504 | "size is out of scaler range\n", | |
4505 | intel_plane ? "PLANE" : "CRTC", | |
4506 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4507 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4508 | return -EINVAL; | |
4509 | } | |
4510 | ||
4511 | /* check colorkey */ | |
4512 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4513 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4514 | intel_plane->base.base.id); | |
4515 | return -EINVAL; | |
4516 | } | |
4517 | ||
4518 | /* Check src format */ | |
4519 | if (intel_plane) { | |
4520 | switch (fb->pixel_format) { | |
4521 | case DRM_FORMAT_RGB565: | |
4522 | case DRM_FORMAT_XBGR8888: | |
4523 | case DRM_FORMAT_XRGB8888: | |
4524 | case DRM_FORMAT_ABGR8888: | |
4525 | case DRM_FORMAT_ARGB8888: | |
4526 | case DRM_FORMAT_XRGB2101010: | |
4527 | case DRM_FORMAT_ARGB2101010: | |
4528 | case DRM_FORMAT_XBGR2101010: | |
4529 | case DRM_FORMAT_ABGR2101010: | |
4530 | case DRM_FORMAT_YUYV: | |
4531 | case DRM_FORMAT_YVYU: | |
4532 | case DRM_FORMAT_UYVY: | |
4533 | case DRM_FORMAT_VYUY: | |
4534 | break; | |
4535 | default: | |
4536 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4537 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4538 | return -EINVAL; | |
4539 | } | |
4540 | } | |
4541 | ||
4542 | /* mark this plane as a scaler user in crtc_state */ | |
4543 | scaler_state->scaler_users |= (1 << idx); | |
4544 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4545 | "crtc_state = %p scaler_users = 0x%x\n", | |
4546 | intel_plane ? "PLANE" : "CRTC", | |
4547 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4548 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4549 | return 0; | |
4550 | } | |
4551 | ||
4552 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4553 | { |
4554 | struct drm_device *dev = crtc->base.dev; | |
4555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4556 | int pipe = crtc->pipe; | |
a1b2278e CK |
4557 | struct intel_crtc_scaler_state *scaler_state = |
4558 | &crtc->config->scaler_state; | |
4559 | ||
4560 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4561 | ||
4562 | /* To update pfit, first update scaler state */ | |
4563 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4564 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4565 | skl_detach_scalers(crtc); | |
4566 | if (!enable) | |
4567 | return; | |
bd2e244f | 4568 | |
6e3c9717 | 4569 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4570 | int id; |
4571 | ||
4572 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4573 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4574 | return; | |
4575 | } | |
4576 | ||
4577 | id = scaler_state->scaler_id; | |
4578 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4579 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4580 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4581 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4582 | ||
4583 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4584 | } |
4585 | } | |
4586 | ||
b074cec8 JB |
4587 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4588 | { | |
4589 | struct drm_device *dev = crtc->base.dev; | |
4590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4591 | int pipe = crtc->pipe; | |
4592 | ||
6e3c9717 | 4593 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4594 | /* Force use of hard-coded filter coefficients |
4595 | * as some pre-programmed values are broken, | |
4596 | * e.g. x201. | |
4597 | */ | |
4598 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4599 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4600 | PF_PIPE_SEL_IVB(pipe)); | |
4601 | else | |
4602 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4603 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4604 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4605 | } |
4606 | } | |
4607 | ||
4a3b8769 | 4608 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4609 | { |
4610 | struct drm_device *dev = crtc->dev; | |
4611 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4612 | struct drm_plane *plane; |
bb53d4ae VS |
4613 | struct intel_plane *intel_plane; |
4614 | ||
af2b653b MR |
4615 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4616 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4617 | if (intel_plane->pipe == pipe) |
4618 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4619 | } |
bb53d4ae VS |
4620 | } |
4621 | ||
20bc8673 | 4622 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4623 | { |
cea165c3 VS |
4624 | struct drm_device *dev = crtc->base.dev; |
4625 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4626 | |
6e3c9717 | 4627 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4628 | return; |
4629 | ||
cea165c3 VS |
4630 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4631 | intel_wait_for_vblank(dev, crtc->pipe); | |
4632 | ||
d77e4531 | 4633 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4634 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4635 | mutex_lock(&dev_priv->rps.hw_lock); |
4636 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4637 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4638 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4639 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4640 | * mailbox." Moreover, the mailbox may return a bogus state, |
4641 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4642 | */ |
4643 | } else { | |
4644 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4645 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4646 | * is essentially intel_wait_for_vblank. If we don't have this | |
4647 | * and don't wait for vblanks until the end of crtc_enable, then | |
4648 | * the HW state readout code will complain that the expected | |
4649 | * IPS_CTL value is not the one we read. */ | |
4650 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4651 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4652 | } | |
d77e4531 PZ |
4653 | } |
4654 | ||
20bc8673 | 4655 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4656 | { |
4657 | struct drm_device *dev = crtc->base.dev; | |
4658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4659 | ||
6e3c9717 | 4660 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4661 | return; |
4662 | ||
4663 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4664 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4665 | mutex_lock(&dev_priv->rps.hw_lock); |
4666 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4667 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4668 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4669 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4670 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4671 | } else { |
2a114cc1 | 4672 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4673 | POSTING_READ(IPS_CTL); |
4674 | } | |
d77e4531 PZ |
4675 | |
4676 | /* We need to wait for a vblank before we can disable the plane. */ | |
4677 | intel_wait_for_vblank(dev, crtc->pipe); | |
4678 | } | |
4679 | ||
4680 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4681 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4682 | { | |
4683 | struct drm_device *dev = crtc->dev; | |
4684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4686 | enum pipe pipe = intel_crtc->pipe; | |
4687 | int palreg = PALETTE(pipe); | |
4688 | int i; | |
4689 | bool reenable_ips = false; | |
4690 | ||
4691 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4692 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4693 | return; |
4694 | ||
50360403 | 4695 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4696 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4697 | assert_dsi_pll_enabled(dev_priv); |
4698 | else | |
4699 | assert_pll_enabled(dev_priv, pipe); | |
4700 | } | |
4701 | ||
4702 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4703 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4704 | palreg = LGC_PALETTE(pipe); |
4705 | ||
4706 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4707 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4708 | */ | |
6e3c9717 | 4709 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4710 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4711 | GAMMA_MODE_MODE_SPLIT)) { | |
4712 | hsw_disable_ips(intel_crtc); | |
4713 | reenable_ips = true; | |
4714 | } | |
4715 | ||
4716 | for (i = 0; i < 256; i++) { | |
4717 | I915_WRITE(palreg + 4 * i, | |
4718 | (intel_crtc->lut_r[i] << 16) | | |
4719 | (intel_crtc->lut_g[i] << 8) | | |
4720 | intel_crtc->lut_b[i]); | |
4721 | } | |
4722 | ||
4723 | if (reenable_ips) | |
4724 | hsw_enable_ips(intel_crtc); | |
4725 | } | |
4726 | ||
d3eedb1a VS |
4727 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4728 | { | |
4729 | if (!enable && intel_crtc->overlay) { | |
4730 | struct drm_device *dev = intel_crtc->base.dev; | |
4731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4732 | ||
4733 | mutex_lock(&dev->struct_mutex); | |
4734 | dev_priv->mm.interruptible = false; | |
4735 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4736 | dev_priv->mm.interruptible = true; | |
4737 | mutex_unlock(&dev->struct_mutex); | |
4738 | } | |
4739 | ||
4740 | /* Let userspace switch the overlay on again. In most cases userspace | |
4741 | * has to recompute where to put it anyway. | |
4742 | */ | |
4743 | } | |
4744 | ||
d3eedb1a | 4745 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4746 | { |
4747 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4749 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4750 | |
fdd508a6 | 4751 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4752 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4753 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4754 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4755 | |
4756 | hsw_enable_ips(intel_crtc); | |
4757 | ||
4758 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4759 | intel_fbc_update(dev); |
a5c4d7bc | 4760 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4761 | |
4762 | /* | |
4763 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4764 | * to compute the mask of flip planes precisely. For the time being | |
4765 | * consider this a flip from a NULL plane. | |
4766 | */ | |
4767 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4768 | } |
4769 | ||
d3eedb1a | 4770 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4771 | { |
4772 | struct drm_device *dev = crtc->dev; | |
4773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
27321ae8 | 4775 | struct intel_plane *intel_plane; |
a5c4d7bc | 4776 | int pipe = intel_crtc->pipe; |
a5c4d7bc VS |
4777 | |
4778 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4779 | |
e35fef21 | 4780 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4781 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4782 | |
4783 | hsw_disable_ips(intel_crtc); | |
4784 | ||
d3eedb1a | 4785 | intel_crtc_dpms_overlay(intel_crtc, false); |
27321ae8 ML |
4786 | for_each_intel_plane(dev, intel_plane) { |
4787 | if (intel_plane->pipe == pipe) { | |
4788 | struct drm_crtc *from = intel_plane->base.crtc; | |
4789 | ||
4790 | intel_plane->disable_plane(&intel_plane->base, | |
4791 | from ?: crtc, true); | |
4792 | } | |
4793 | } | |
f98551ae | 4794 | |
f99d7069 DV |
4795 | /* |
4796 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4797 | * to compute the mask of flip planes precisely. For the time being | |
4798 | * consider this a flip to a NULL plane. | |
4799 | */ | |
4800 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4801 | } |
4802 | ||
f67a559d JB |
4803 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4804 | { | |
4805 | struct drm_device *dev = crtc->dev; | |
4806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4808 | struct intel_encoder *encoder; |
f67a559d | 4809 | int pipe = intel_crtc->pipe; |
f67a559d | 4810 | |
83d65738 | 4811 | WARN_ON(!crtc->state->enable); |
08a48469 | 4812 | |
f67a559d JB |
4813 | if (intel_crtc->active) |
4814 | return; | |
4815 | ||
6e3c9717 | 4816 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4817 | intel_prepare_shared_dpll(intel_crtc); |
4818 | ||
6e3c9717 | 4819 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4820 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4821 | |
4822 | intel_set_pipe_timings(intel_crtc); | |
4823 | ||
6e3c9717 | 4824 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4825 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4826 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4827 | } |
4828 | ||
4829 | ironlake_set_pipeconf(crtc); | |
4830 | ||
f67a559d | 4831 | intel_crtc->active = true; |
8664281b | 4832 | |
a72e4c9f DV |
4833 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4834 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4835 | |
f6736a1a | 4836 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4837 | if (encoder->pre_enable) |
4838 | encoder->pre_enable(encoder); | |
f67a559d | 4839 | |
6e3c9717 | 4840 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4841 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4842 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4843 | * enabling. */ | |
88cefb6c | 4844 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4845 | } else { |
4846 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4847 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4848 | } | |
f67a559d | 4849 | |
b074cec8 | 4850 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4851 | |
9c54c0dd JB |
4852 | /* |
4853 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4854 | * clocks enabled | |
4855 | */ | |
4856 | intel_crtc_load_lut(crtc); | |
4857 | ||
f37fcc2a | 4858 | intel_update_watermarks(crtc); |
e1fdc473 | 4859 | intel_enable_pipe(intel_crtc); |
f67a559d | 4860 | |
6e3c9717 | 4861 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4862 | ironlake_pch_enable(crtc); |
c98e9dcf | 4863 | |
f9b61ff6 DV |
4864 | assert_vblank_disabled(crtc); |
4865 | drm_crtc_vblank_on(crtc); | |
4866 | ||
fa5c73b1 DV |
4867 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4868 | encoder->enable(encoder); | |
61b77ddd DV |
4869 | |
4870 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4871 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4872 | |
d3eedb1a | 4873 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4874 | } |
4875 | ||
42db64ef PZ |
4876 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4877 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4878 | { | |
f5adf94e | 4879 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4880 | } |
4881 | ||
e4916946 PZ |
4882 | /* |
4883 | * This implements the workaround described in the "notes" section of the mode | |
4884 | * set sequence documentation. When going from no pipes or single pipe to | |
4885 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4886 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4887 | */ | |
4888 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4889 | { | |
4890 | struct drm_device *dev = crtc->base.dev; | |
4891 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4892 | ||
4893 | /* We want to get the other_active_crtc only if there's only 1 other | |
4894 | * active crtc. */ | |
d3fcc808 | 4895 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4896 | if (!crtc_it->active || crtc_it == crtc) |
4897 | continue; | |
4898 | ||
4899 | if (other_active_crtc) | |
4900 | return; | |
4901 | ||
4902 | other_active_crtc = crtc_it; | |
4903 | } | |
4904 | if (!other_active_crtc) | |
4905 | return; | |
4906 | ||
4907 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4908 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4909 | } | |
4910 | ||
4f771f10 PZ |
4911 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4912 | { | |
4913 | struct drm_device *dev = crtc->dev; | |
4914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4916 | struct intel_encoder *encoder; | |
4917 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4918 | |
83d65738 | 4919 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4920 | |
4921 | if (intel_crtc->active) | |
4922 | return; | |
4923 | ||
df8ad70c DV |
4924 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4925 | intel_enable_shared_dpll(intel_crtc); | |
4926 | ||
6e3c9717 | 4927 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4928 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4929 | |
4930 | intel_set_pipe_timings(intel_crtc); | |
4931 | ||
6e3c9717 ACO |
4932 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4933 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4934 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4935 | } |
4936 | ||
6e3c9717 | 4937 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4938 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4939 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4940 | } |
4941 | ||
4942 | haswell_set_pipeconf(crtc); | |
4943 | ||
4944 | intel_set_pipe_csc(crtc); | |
4945 | ||
4f771f10 | 4946 | intel_crtc->active = true; |
8664281b | 4947 | |
a72e4c9f | 4948 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4949 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4950 | if (encoder->pre_enable) | |
4951 | encoder->pre_enable(encoder); | |
4952 | ||
6e3c9717 | 4953 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4954 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4955 | true); | |
4fe9467d ID |
4956 | dev_priv->display.fdi_link_train(crtc); |
4957 | } | |
4958 | ||
1f544388 | 4959 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4960 | |
ff6d9f55 | 4961 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 4962 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 4963 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 4964 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
4965 | else |
4966 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
4967 | |
4968 | /* | |
4969 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4970 | * clocks enabled | |
4971 | */ | |
4972 | intel_crtc_load_lut(crtc); | |
4973 | ||
1f544388 | 4974 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4975 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4976 | |
f37fcc2a | 4977 | intel_update_watermarks(crtc); |
e1fdc473 | 4978 | intel_enable_pipe(intel_crtc); |
42db64ef | 4979 | |
6e3c9717 | 4980 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4981 | lpt_pch_enable(crtc); |
4f771f10 | 4982 | |
6e3c9717 | 4983 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4984 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4985 | ||
f9b61ff6 DV |
4986 | assert_vblank_disabled(crtc); |
4987 | drm_crtc_vblank_on(crtc); | |
4988 | ||
8807e55b | 4989 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4990 | encoder->enable(encoder); |
8807e55b JN |
4991 | intel_opregion_notify_encoder(encoder, true); |
4992 | } | |
4f771f10 | 4993 | |
e4916946 PZ |
4994 | /* If we change the relative order between pipe/planes enabling, we need |
4995 | * to change the workaround. */ | |
4996 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4997 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4998 | } |
4999 | ||
3f8dce3a DV |
5000 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5001 | { | |
5002 | struct drm_device *dev = crtc->base.dev; | |
5003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5004 | int pipe = crtc->pipe; | |
5005 | ||
5006 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5007 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5008 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5009 | I915_WRITE(PF_CTL(pipe), 0); |
5010 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5011 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5012 | } | |
5013 | } | |
5014 | ||
6be4a607 JB |
5015 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5016 | { | |
5017 | struct drm_device *dev = crtc->dev; | |
5018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5020 | struct intel_encoder *encoder; |
6be4a607 | 5021 | int pipe = intel_crtc->pipe; |
5eddb70b | 5022 | u32 reg, temp; |
b52eb4dc | 5023 | |
f7abfe8b CW |
5024 | if (!intel_crtc->active) |
5025 | return; | |
5026 | ||
d3eedb1a | 5027 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 5028 | |
ea9d758d DV |
5029 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5030 | encoder->disable(encoder); | |
5031 | ||
f9b61ff6 DV |
5032 | drm_crtc_vblank_off(crtc); |
5033 | assert_vblank_disabled(crtc); | |
5034 | ||
6e3c9717 | 5035 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5036 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5037 | |
575f7ab7 | 5038 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5039 | |
3f8dce3a | 5040 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5041 | |
bf49ec8c DV |
5042 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5043 | if (encoder->post_disable) | |
5044 | encoder->post_disable(encoder); | |
2c07245f | 5045 | |
6e3c9717 | 5046 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5047 | ironlake_fdi_disable(crtc); |
913d8d11 | 5048 | |
d925c59a | 5049 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5050 | |
d925c59a DV |
5051 | if (HAS_PCH_CPT(dev)) { |
5052 | /* disable TRANS_DP_CTL */ | |
5053 | reg = TRANS_DP_CTL(pipe); | |
5054 | temp = I915_READ(reg); | |
5055 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5056 | TRANS_DP_PORT_SEL_MASK); | |
5057 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5058 | I915_WRITE(reg, temp); | |
5059 | ||
5060 | /* disable DPLL_SEL */ | |
5061 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5062 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5063 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5064 | } |
e3421a18 | 5065 | |
d925c59a | 5066 | /* disable PCH DPLL */ |
e72f9fbf | 5067 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5068 | |
d925c59a DV |
5069 | ironlake_fdi_pll_disable(intel_crtc); |
5070 | } | |
6b383a7f | 5071 | |
f7abfe8b | 5072 | intel_crtc->active = false; |
46ba614c | 5073 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5074 | |
5075 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5076 | intel_fbc_update(dev); |
d1ebd816 | 5077 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5078 | } |
1b3c7a47 | 5079 | |
4f771f10 | 5080 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5081 | { |
4f771f10 PZ |
5082 | struct drm_device *dev = crtc->dev; |
5083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5085 | struct intel_encoder *encoder; |
6e3c9717 | 5086 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5087 | |
4f771f10 PZ |
5088 | if (!intel_crtc->active) |
5089 | return; | |
5090 | ||
d3eedb1a | 5091 | intel_crtc_disable_planes(crtc); |
dda9a66a | 5092 | |
8807e55b JN |
5093 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5094 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5095 | encoder->disable(encoder); |
8807e55b | 5096 | } |
4f771f10 | 5097 | |
f9b61ff6 DV |
5098 | drm_crtc_vblank_off(crtc); |
5099 | assert_vblank_disabled(crtc); | |
5100 | ||
6e3c9717 | 5101 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5102 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5103 | false); | |
575f7ab7 | 5104 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5105 | |
6e3c9717 | 5106 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5107 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5108 | ||
ad80a810 | 5109 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5110 | |
ff6d9f55 | 5111 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5112 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5113 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5114 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5115 | else |
5116 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5117 | |
1f544388 | 5118 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5119 | |
6e3c9717 | 5120 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5121 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5122 | intel_ddi_fdi_disable(crtc); |
83616634 | 5123 | } |
4f771f10 | 5124 | |
97b040aa ID |
5125 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5126 | if (encoder->post_disable) | |
5127 | encoder->post_disable(encoder); | |
5128 | ||
4f771f10 | 5129 | intel_crtc->active = false; |
46ba614c | 5130 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5131 | |
5132 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5133 | intel_fbc_update(dev); |
4f771f10 | 5134 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5135 | |
5136 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5137 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5138 | } |
5139 | ||
ee7b9f93 JB |
5140 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5141 | { | |
5142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5143 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5144 | } |
5145 | ||
6441ab5f | 5146 | |
2dd24552 JB |
5147 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5148 | { | |
5149 | struct drm_device *dev = crtc->base.dev; | |
5150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5151 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5152 | |
681a8504 | 5153 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5154 | return; |
5155 | ||
2dd24552 | 5156 | /* |
c0b03411 DV |
5157 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5158 | * according to register description and PRM. | |
2dd24552 | 5159 | */ |
c0b03411 DV |
5160 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5161 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5162 | |
b074cec8 JB |
5163 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5164 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5165 | |
5166 | /* Border color in case we don't scale up to the full screen. Black by | |
5167 | * default, change to something else for debugging. */ | |
5168 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5169 | } |
5170 | ||
d05410f9 DA |
5171 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5172 | { | |
5173 | switch (port) { | |
5174 | case PORT_A: | |
5175 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5176 | case PORT_B: | |
5177 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5178 | case PORT_C: | |
5179 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5180 | case PORT_D: | |
5181 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5182 | default: | |
5183 | WARN_ON_ONCE(1); | |
5184 | return POWER_DOMAIN_PORT_OTHER; | |
5185 | } | |
5186 | } | |
5187 | ||
77d22dca ID |
5188 | #define for_each_power_domain(domain, mask) \ |
5189 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5190 | if ((1 << (domain)) & (mask)) | |
5191 | ||
319be8ae ID |
5192 | enum intel_display_power_domain |
5193 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5194 | { | |
5195 | struct drm_device *dev = intel_encoder->base.dev; | |
5196 | struct intel_digital_port *intel_dig_port; | |
5197 | ||
5198 | switch (intel_encoder->type) { | |
5199 | case INTEL_OUTPUT_UNKNOWN: | |
5200 | /* Only DDI platforms should ever use this output type */ | |
5201 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5202 | case INTEL_OUTPUT_DISPLAYPORT: | |
5203 | case INTEL_OUTPUT_HDMI: | |
5204 | case INTEL_OUTPUT_EDP: | |
5205 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5206 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5207 | case INTEL_OUTPUT_DP_MST: |
5208 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5209 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5210 | case INTEL_OUTPUT_ANALOG: |
5211 | return POWER_DOMAIN_PORT_CRT; | |
5212 | case INTEL_OUTPUT_DSI: | |
5213 | return POWER_DOMAIN_PORT_DSI; | |
5214 | default: | |
5215 | return POWER_DOMAIN_PORT_OTHER; | |
5216 | } | |
5217 | } | |
5218 | ||
5219 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5220 | { |
319be8ae ID |
5221 | struct drm_device *dev = crtc->dev; |
5222 | struct intel_encoder *intel_encoder; | |
5223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5224 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5225 | unsigned long mask; |
5226 | enum transcoder transcoder; | |
5227 | ||
5228 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5229 | ||
5230 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5231 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5232 | if (intel_crtc->config->pch_pfit.enabled || |
5233 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5234 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5235 | ||
319be8ae ID |
5236 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5237 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5238 | ||
77d22dca ID |
5239 | return mask; |
5240 | } | |
5241 | ||
679dacd4 | 5242 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5243 | { |
679dacd4 | 5244 | struct drm_device *dev = state->dev; |
77d22dca ID |
5245 | struct drm_i915_private *dev_priv = dev->dev_private; |
5246 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5247 | struct intel_crtc *crtc; | |
5248 | ||
5249 | /* | |
5250 | * First get all needed power domains, then put all unneeded, to avoid | |
5251 | * any unnecessary toggling of the power wells. | |
5252 | */ | |
d3fcc808 | 5253 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5254 | enum intel_display_power_domain domain; |
5255 | ||
83d65738 | 5256 | if (!crtc->base.state->enable) |
77d22dca ID |
5257 | continue; |
5258 | ||
319be8ae | 5259 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5260 | |
5261 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5262 | intel_display_power_get(dev_priv, domain); | |
5263 | } | |
5264 | ||
50f6e502 | 5265 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5266 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5267 | |
d3fcc808 | 5268 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5269 | enum intel_display_power_domain domain; |
5270 | ||
5271 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5272 | intel_display_power_put(dev_priv, domain); | |
5273 | ||
5274 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5275 | } | |
5276 | ||
5277 | intel_display_set_init_power(dev_priv, false); | |
5278 | } | |
5279 | ||
f8437dd1 VK |
5280 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5281 | { | |
5282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5283 | uint32_t divider; | |
5284 | uint32_t ratio; | |
5285 | uint32_t current_freq; | |
5286 | int ret; | |
5287 | ||
5288 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5289 | switch (frequency) { | |
5290 | case 144000: | |
5291 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5292 | ratio = BXT_DE_PLL_RATIO(60); | |
5293 | break; | |
5294 | case 288000: | |
5295 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5296 | ratio = BXT_DE_PLL_RATIO(60); | |
5297 | break; | |
5298 | case 384000: | |
5299 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5300 | ratio = BXT_DE_PLL_RATIO(60); | |
5301 | break; | |
5302 | case 576000: | |
5303 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5304 | ratio = BXT_DE_PLL_RATIO(60); | |
5305 | break; | |
5306 | case 624000: | |
5307 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5308 | ratio = BXT_DE_PLL_RATIO(65); | |
5309 | break; | |
5310 | case 19200: | |
5311 | /* | |
5312 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5313 | * to suppress GCC warning. | |
5314 | */ | |
5315 | ratio = 0; | |
5316 | divider = 0; | |
5317 | break; | |
5318 | default: | |
5319 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5320 | ||
5321 | return; | |
5322 | } | |
5323 | ||
5324 | mutex_lock(&dev_priv->rps.hw_lock); | |
5325 | /* Inform power controller of upcoming frequency change */ | |
5326 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5327 | 0x80000000); | |
5328 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5329 | ||
5330 | if (ret) { | |
5331 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5332 | ret, frequency); | |
5333 | return; | |
5334 | } | |
5335 | ||
5336 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5337 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5338 | current_freq = current_freq * 500 + 1000; | |
5339 | ||
5340 | /* | |
5341 | * DE PLL has to be disabled when | |
5342 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5343 | * - before setting to 624MHz (PLL needs toggling) | |
5344 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5345 | */ | |
5346 | if (frequency == 19200 || frequency == 624000 || | |
5347 | current_freq == 624000) { | |
5348 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5349 | /* Timeout 200us */ | |
5350 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5351 | 1)) | |
5352 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5353 | } | |
5354 | ||
5355 | if (frequency != 19200) { | |
5356 | uint32_t val; | |
5357 | ||
5358 | val = I915_READ(BXT_DE_PLL_CTL); | |
5359 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5360 | val |= ratio; | |
5361 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5362 | ||
5363 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5364 | /* Timeout 200us */ | |
5365 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5366 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5367 | ||
5368 | val = I915_READ(CDCLK_CTL); | |
5369 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5370 | val |= divider; | |
5371 | /* | |
5372 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5373 | * enable otherwise. | |
5374 | */ | |
5375 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5376 | if (frequency >= 500000) | |
5377 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5378 | ||
5379 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5380 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5381 | val |= (frequency - 1000) / 500; | |
5382 | I915_WRITE(CDCLK_CTL, val); | |
5383 | } | |
5384 | ||
5385 | mutex_lock(&dev_priv->rps.hw_lock); | |
5386 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5387 | DIV_ROUND_UP(frequency, 25000)); | |
5388 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5389 | ||
5390 | if (ret) { | |
5391 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5392 | ret, frequency); | |
5393 | return; | |
5394 | } | |
5395 | ||
5396 | dev_priv->cdclk_freq = frequency; | |
5397 | } | |
5398 | ||
5399 | void broxton_init_cdclk(struct drm_device *dev) | |
5400 | { | |
5401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5402 | uint32_t val; | |
5403 | ||
5404 | /* | |
5405 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5406 | * or else the reset will hang because there is no PCH to respond. | |
5407 | * Move the handshake programming to initialization sequence. | |
5408 | * Previously was left up to BIOS. | |
5409 | */ | |
5410 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5411 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5412 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5413 | ||
5414 | /* Enable PG1 for cdclk */ | |
5415 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5416 | ||
5417 | /* check if cd clock is enabled */ | |
5418 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5419 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5420 | return; | |
5421 | } | |
5422 | ||
5423 | /* | |
5424 | * FIXME: | |
5425 | * - The initial CDCLK needs to be read from VBT. | |
5426 | * Need to make this change after VBT has changes for BXT. | |
5427 | * - check if setting the max (or any) cdclk freq is really necessary | |
5428 | * here, it belongs to modeset time | |
5429 | */ | |
5430 | broxton_set_cdclk(dev, 624000); | |
5431 | ||
5432 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5433 | POSTING_READ(DBUF_CTL); |
5434 | ||
f8437dd1 VK |
5435 | udelay(10); |
5436 | ||
5437 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5438 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5439 | } | |
5440 | ||
5441 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5442 | { | |
5443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5444 | ||
5445 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5446 | POSTING_READ(DBUF_CTL); |
5447 | ||
f8437dd1 VK |
5448 | udelay(10); |
5449 | ||
5450 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5451 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5452 | ||
5453 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5454 | broxton_set_cdclk(dev, 19200); | |
5455 | ||
5456 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5457 | } | |
5458 | ||
dfcab17e | 5459 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5460 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5461 | { |
586f49dc | 5462 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5463 | |
586f49dc JB |
5464 | /* Obtain SKU information */ |
5465 | mutex_lock(&dev_priv->dpio_lock); | |
5466 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5467 | CCK_FUSE_HPLL_FREQ_MASK; | |
5468 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5469 | |
dfcab17e | 5470 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5471 | } |
5472 | ||
f8bf63fd VS |
5473 | static void vlv_update_cdclk(struct drm_device *dev) |
5474 | { | |
5475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5476 | ||
164dfd28 | 5477 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5478 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5479 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5480 | |
5481 | /* | |
5482 | * Program the gmbus_freq based on the cdclk frequency. | |
5483 | * BSpec erroneously claims we should aim for 4MHz, but | |
5484 | * in fact 1MHz is the correct frequency. | |
5485 | */ | |
164dfd28 | 5486 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5487 | } |
5488 | ||
30a970c6 JB |
5489 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5490 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5491 | { | |
5492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5493 | u32 val, cmd; | |
5494 | ||
164dfd28 VK |
5495 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5496 | != dev_priv->cdclk_freq); | |
d60c4473 | 5497 | |
dfcab17e | 5498 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5499 | cmd = 2; |
dfcab17e | 5500 | else if (cdclk == 266667) |
30a970c6 JB |
5501 | cmd = 1; |
5502 | else | |
5503 | cmd = 0; | |
5504 | ||
5505 | mutex_lock(&dev_priv->rps.hw_lock); | |
5506 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5507 | val &= ~DSPFREQGUAR_MASK; | |
5508 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5509 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5510 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5511 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5512 | 50)) { | |
5513 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5514 | } | |
5515 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5516 | ||
dfcab17e | 5517 | if (cdclk == 400000) { |
6bcda4f0 | 5518 | u32 divider; |
30a970c6 | 5519 | |
6bcda4f0 | 5520 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5521 | |
5522 | mutex_lock(&dev_priv->dpio_lock); | |
5523 | /* adjust cdclk divider */ | |
5524 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5525 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5526 | val |= divider; |
5527 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5528 | |
5529 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5530 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5531 | 50)) | |
5532 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5533 | mutex_unlock(&dev_priv->dpio_lock); |
5534 | } | |
5535 | ||
5536 | mutex_lock(&dev_priv->dpio_lock); | |
5537 | /* adjust self-refresh exit latency value */ | |
5538 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5539 | val &= ~0x7f; | |
5540 | ||
5541 | /* | |
5542 | * For high bandwidth configs, we set a higher latency in the bunit | |
5543 | * so that the core display fetch happens in time to avoid underruns. | |
5544 | */ | |
dfcab17e | 5545 | if (cdclk == 400000) |
30a970c6 JB |
5546 | val |= 4500 / 250; /* 4.5 usec */ |
5547 | else | |
5548 | val |= 3000 / 250; /* 3.0 usec */ | |
5549 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5550 | mutex_unlock(&dev_priv->dpio_lock); | |
5551 | ||
f8bf63fd | 5552 | vlv_update_cdclk(dev); |
30a970c6 JB |
5553 | } |
5554 | ||
383c5a6a VS |
5555 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5556 | { | |
5557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5558 | u32 val, cmd; | |
5559 | ||
164dfd28 VK |
5560 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5561 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5562 | |
5563 | switch (cdclk) { | |
383c5a6a VS |
5564 | case 333333: |
5565 | case 320000: | |
383c5a6a | 5566 | case 266667: |
383c5a6a | 5567 | case 200000: |
383c5a6a VS |
5568 | break; |
5569 | default: | |
5f77eeb0 | 5570 | MISSING_CASE(cdclk); |
383c5a6a VS |
5571 | return; |
5572 | } | |
5573 | ||
9d0d3fda VS |
5574 | /* |
5575 | * Specs are full of misinformation, but testing on actual | |
5576 | * hardware has shown that we just need to write the desired | |
5577 | * CCK divider into the Punit register. | |
5578 | */ | |
5579 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5580 | ||
383c5a6a VS |
5581 | mutex_lock(&dev_priv->rps.hw_lock); |
5582 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5583 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5584 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5585 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5586 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5587 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5588 | 50)) { | |
5589 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5590 | } | |
5591 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5592 | ||
5593 | vlv_update_cdclk(dev); | |
5594 | } | |
5595 | ||
30a970c6 JB |
5596 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5597 | int max_pixclk) | |
5598 | { | |
6bcda4f0 | 5599 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5600 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5601 | |
30a970c6 JB |
5602 | /* |
5603 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5604 | * 200MHz | |
5605 | * 267MHz | |
29dc7ef3 | 5606 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5607 | * 400MHz (VLV only) |
5608 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5609 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5610 | * |
5611 | * We seem to get an unstable or solid color picture at 200MHz. | |
5612 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5613 | * are off. | |
30a970c6 | 5614 | */ |
6cca3195 VS |
5615 | if (!IS_CHERRYVIEW(dev_priv) && |
5616 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5617 | return 400000; |
6cca3195 | 5618 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5619 | return freq_320; |
e37c67a1 | 5620 | else if (max_pixclk > 0) |
dfcab17e | 5621 | return 266667; |
e37c67a1 VS |
5622 | else |
5623 | return 200000; | |
30a970c6 JB |
5624 | } |
5625 | ||
f8437dd1 VK |
5626 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5627 | int max_pixclk) | |
5628 | { | |
5629 | /* | |
5630 | * FIXME: | |
5631 | * - remove the guardband, it's not needed on BXT | |
5632 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5633 | */ | |
5634 | if (max_pixclk > 576000*9/10) | |
5635 | return 624000; | |
5636 | else if (max_pixclk > 384000*9/10) | |
5637 | return 576000; | |
5638 | else if (max_pixclk > 288000*9/10) | |
5639 | return 384000; | |
5640 | else if (max_pixclk > 144000*9/10) | |
5641 | return 288000; | |
5642 | else | |
5643 | return 144000; | |
5644 | } | |
5645 | ||
2f2d7aa1 | 5646 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5647 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5648 | { |
304603f4 | 5649 | struct drm_device *dev = state->dev; |
30a970c6 | 5650 | struct intel_crtc *intel_crtc; |
304603f4 | 5651 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5652 | int max_pixclk = 0; |
5653 | ||
d3fcc808 | 5654 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5655 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5656 | if (IS_ERR(crtc_state)) | |
5657 | return PTR_ERR(crtc_state); | |
5658 | ||
5659 | if (!crtc_state->base.enable) | |
5660 | continue; | |
5661 | ||
5662 | max_pixclk = max(max_pixclk, | |
5663 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5664 | } |
5665 | ||
5666 | return max_pixclk; | |
5667 | } | |
5668 | ||
304603f4 | 5669 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5670 | unsigned *prepare_pipes) |
30a970c6 | 5671 | { |
304603f4 | 5672 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5673 | struct intel_crtc *intel_crtc; |
304603f4 | 5674 | int max_pixclk = intel_mode_max_pixclk(state); |
f8437dd1 | 5675 | int cdclk; |
30a970c6 | 5676 | |
304603f4 ACO |
5677 | if (max_pixclk < 0) |
5678 | return max_pixclk; | |
30a970c6 | 5679 | |
f8437dd1 VK |
5680 | if (IS_VALLEYVIEW(dev_priv)) |
5681 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5682 | else | |
5683 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5684 | ||
5685 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5686 | return 0; |
30a970c6 | 5687 | |
2f2d7aa1 | 5688 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5689 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5690 | if (intel_crtc->base.state->enable) |
30a970c6 | 5691 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5692 | |
5693 | return 0; | |
30a970c6 JB |
5694 | } |
5695 | ||
1e69cd74 VS |
5696 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5697 | { | |
5698 | unsigned int credits, default_credits; | |
5699 | ||
5700 | if (IS_CHERRYVIEW(dev_priv)) | |
5701 | default_credits = PFI_CREDIT(12); | |
5702 | else | |
5703 | default_credits = PFI_CREDIT(8); | |
5704 | ||
164dfd28 | 5705 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5706 | /* CHV suggested value is 31 or 63 */ |
5707 | if (IS_CHERRYVIEW(dev_priv)) | |
5708 | credits = PFI_CREDIT_31; | |
5709 | else | |
5710 | credits = PFI_CREDIT(15); | |
5711 | } else { | |
5712 | credits = default_credits; | |
5713 | } | |
5714 | ||
5715 | /* | |
5716 | * WA - write default credits before re-programming | |
5717 | * FIXME: should we also set the resend bit here? | |
5718 | */ | |
5719 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5720 | default_credits); | |
5721 | ||
5722 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5723 | credits | PFI_CREDIT_RESEND); | |
5724 | ||
5725 | /* | |
5726 | * FIXME is this guaranteed to clear | |
5727 | * immediately or should we poll for it? | |
5728 | */ | |
5729 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5730 | } | |
5731 | ||
679dacd4 | 5732 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5733 | { |
679dacd4 | 5734 | struct drm_device *dev = state->dev; |
30a970c6 | 5735 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5736 | int max_pixclk = intel_mode_max_pixclk(state); |
5737 | int req_cdclk; | |
5738 | ||
5739 | /* The only reason this can fail is if we fail to add the crtc_state | |
5740 | * to the atomic state. But that can't happen since the call to | |
5741 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5742 | * can't have failed otherwise the mode set would be aborted) added all | |
5743 | * the states already. */ | |
5744 | if (WARN_ON(max_pixclk < 0)) | |
5745 | return; | |
30a970c6 | 5746 | |
304603f4 | 5747 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 5748 | |
164dfd28 | 5749 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5750 | /* |
5751 | * FIXME: We can end up here with all power domains off, yet | |
5752 | * with a CDCLK frequency other than the minimum. To account | |
5753 | * for this take the PIPE-A power domain, which covers the HW | |
5754 | * blocks needed for the following programming. This can be | |
5755 | * removed once it's guaranteed that we get here either with | |
5756 | * the minimum CDCLK set, or the required power domains | |
5757 | * enabled. | |
5758 | */ | |
5759 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5760 | ||
383c5a6a VS |
5761 | if (IS_CHERRYVIEW(dev)) |
5762 | cherryview_set_cdclk(dev, req_cdclk); | |
5763 | else | |
5764 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5765 | |
1e69cd74 VS |
5766 | vlv_program_pfi_credits(dev_priv); |
5767 | ||
738c05c0 | 5768 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5769 | } |
30a970c6 JB |
5770 | } |
5771 | ||
89b667f8 JB |
5772 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5773 | { | |
5774 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5775 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5777 | struct intel_encoder *encoder; | |
5778 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5779 | bool is_dsi; |
89b667f8 | 5780 | |
83d65738 | 5781 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5782 | |
5783 | if (intel_crtc->active) | |
5784 | return; | |
5785 | ||
409ee761 | 5786 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5787 | |
1ae0d137 VS |
5788 | if (!is_dsi) { |
5789 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5790 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5791 | else |
6e3c9717 | 5792 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5793 | } |
5b18e57c | 5794 | |
6e3c9717 | 5795 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5796 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5797 | |
5798 | intel_set_pipe_timings(intel_crtc); | |
5799 | ||
c14b0485 VS |
5800 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5802 | ||
5803 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5804 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5805 | } | |
5806 | ||
5b18e57c DV |
5807 | i9xx_set_pipeconf(intel_crtc); |
5808 | ||
89b667f8 | 5809 | intel_crtc->active = true; |
89b667f8 | 5810 | |
a72e4c9f | 5811 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5812 | |
89b667f8 JB |
5813 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5814 | if (encoder->pre_pll_enable) | |
5815 | encoder->pre_pll_enable(encoder); | |
5816 | ||
9d556c99 CML |
5817 | if (!is_dsi) { |
5818 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5819 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5820 | else |
6e3c9717 | 5821 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5822 | } |
89b667f8 JB |
5823 | |
5824 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5825 | if (encoder->pre_enable) | |
5826 | encoder->pre_enable(encoder); | |
5827 | ||
2dd24552 JB |
5828 | i9xx_pfit_enable(intel_crtc); |
5829 | ||
63cbb074 VS |
5830 | intel_crtc_load_lut(crtc); |
5831 | ||
f37fcc2a | 5832 | intel_update_watermarks(crtc); |
e1fdc473 | 5833 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5834 | |
4b3a9526 VS |
5835 | assert_vblank_disabled(crtc); |
5836 | drm_crtc_vblank_on(crtc); | |
5837 | ||
f9b61ff6 DV |
5838 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5839 | encoder->enable(encoder); | |
5840 | ||
9ab0460b | 5841 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5842 | |
56b80e1f | 5843 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5844 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5845 | } |
5846 | ||
f13c2ef3 DV |
5847 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5848 | { | |
5849 | struct drm_device *dev = crtc->base.dev; | |
5850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5851 | ||
6e3c9717 ACO |
5852 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5853 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5854 | } |
5855 | ||
0b8765c6 | 5856 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5857 | { |
5858 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5859 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5861 | struct intel_encoder *encoder; |
79e53945 | 5862 | int pipe = intel_crtc->pipe; |
79e53945 | 5863 | |
83d65738 | 5864 | WARN_ON(!crtc->state->enable); |
08a48469 | 5865 | |
f7abfe8b CW |
5866 | if (intel_crtc->active) |
5867 | return; | |
5868 | ||
f13c2ef3 DV |
5869 | i9xx_set_pll_dividers(intel_crtc); |
5870 | ||
6e3c9717 | 5871 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5872 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5873 | |
5874 | intel_set_pipe_timings(intel_crtc); | |
5875 | ||
5b18e57c DV |
5876 | i9xx_set_pipeconf(intel_crtc); |
5877 | ||
f7abfe8b | 5878 | intel_crtc->active = true; |
6b383a7f | 5879 | |
4a3436e8 | 5880 | if (!IS_GEN2(dev)) |
a72e4c9f | 5881 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5882 | |
9d6d9f19 MK |
5883 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5884 | if (encoder->pre_enable) | |
5885 | encoder->pre_enable(encoder); | |
5886 | ||
f6736a1a DV |
5887 | i9xx_enable_pll(intel_crtc); |
5888 | ||
2dd24552 JB |
5889 | i9xx_pfit_enable(intel_crtc); |
5890 | ||
63cbb074 VS |
5891 | intel_crtc_load_lut(crtc); |
5892 | ||
f37fcc2a | 5893 | intel_update_watermarks(crtc); |
e1fdc473 | 5894 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5895 | |
4b3a9526 VS |
5896 | assert_vblank_disabled(crtc); |
5897 | drm_crtc_vblank_on(crtc); | |
5898 | ||
f9b61ff6 DV |
5899 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5900 | encoder->enable(encoder); | |
5901 | ||
9ab0460b | 5902 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5903 | |
4a3436e8 VS |
5904 | /* |
5905 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5906 | * So don't enable underrun reporting before at least some planes | |
5907 | * are enabled. | |
5908 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5909 | * but leave the pipe running. | |
5910 | */ | |
5911 | if (IS_GEN2(dev)) | |
a72e4c9f | 5912 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5913 | |
56b80e1f | 5914 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5915 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5916 | } |
79e53945 | 5917 | |
87476d63 DV |
5918 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5919 | { | |
5920 | struct drm_device *dev = crtc->base.dev; | |
5921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5922 | |
6e3c9717 | 5923 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5924 | return; |
87476d63 | 5925 | |
328d8e82 | 5926 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5927 | |
328d8e82 DV |
5928 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5929 | I915_READ(PFIT_CONTROL)); | |
5930 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5931 | } |
5932 | ||
0b8765c6 JB |
5933 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5934 | { | |
5935 | struct drm_device *dev = crtc->dev; | |
5936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5937 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5938 | struct intel_encoder *encoder; |
0b8765c6 | 5939 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5940 | |
f7abfe8b CW |
5941 | if (!intel_crtc->active) |
5942 | return; | |
5943 | ||
4a3436e8 VS |
5944 | /* |
5945 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5946 | * So diasble underrun reporting before all the planes get disabled. | |
5947 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5948 | * but leave the pipe running. | |
5949 | */ | |
5950 | if (IS_GEN2(dev)) | |
a72e4c9f | 5951 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5952 | |
564ed191 ID |
5953 | /* |
5954 | * Vblank time updates from the shadow to live plane control register | |
5955 | * are blocked if the memory self-refresh mode is active at that | |
5956 | * moment. So to make sure the plane gets truly disabled, disable | |
5957 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5958 | * will be checked/applied by the HW only at the next frame start | |
5959 | * event which is after the vblank start event, so we need to have a | |
5960 | * wait-for-vblank between disabling the plane and the pipe. | |
5961 | */ | |
5962 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5963 | intel_crtc_disable_planes(crtc); |
5964 | ||
6304cd91 VS |
5965 | /* |
5966 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5967 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5968 | * We also need to wait on all gmch platforms because of the |
5969 | * self-refresh mode constraint explained above. | |
6304cd91 | 5970 | */ |
564ed191 | 5971 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5972 | |
4b3a9526 VS |
5973 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5974 | encoder->disable(encoder); | |
5975 | ||
f9b61ff6 DV |
5976 | drm_crtc_vblank_off(crtc); |
5977 | assert_vblank_disabled(crtc); | |
5978 | ||
575f7ab7 | 5979 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5980 | |
87476d63 | 5981 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5982 | |
89b667f8 JB |
5983 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5984 | if (encoder->post_disable) | |
5985 | encoder->post_disable(encoder); | |
5986 | ||
409ee761 | 5987 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5988 | if (IS_CHERRYVIEW(dev)) |
5989 | chv_disable_pll(dev_priv, pipe); | |
5990 | else if (IS_VALLEYVIEW(dev)) | |
5991 | vlv_disable_pll(dev_priv, pipe); | |
5992 | else | |
1c4e0274 | 5993 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5994 | } |
0b8765c6 | 5995 | |
4a3436e8 | 5996 | if (!IS_GEN2(dev)) |
a72e4c9f | 5997 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5998 | |
f7abfe8b | 5999 | intel_crtc->active = false; |
46ba614c | 6000 | intel_update_watermarks(crtc); |
f37fcc2a | 6001 | |
efa9624e | 6002 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6003 | intel_fbc_update(dev); |
efa9624e | 6004 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6005 | } |
6006 | ||
ee7b9f93 JB |
6007 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6008 | { | |
6009 | } | |
6010 | ||
b04c5bd6 BF |
6011 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6012 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6013 | { |
6014 | struct drm_device *dev = crtc->dev; | |
6015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6016 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6017 | enum intel_display_power_domain domain; |
6018 | unsigned long domains; | |
976f8a20 | 6019 | |
0e572fe7 DV |
6020 | if (enable) { |
6021 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6022 | domains = get_crtc_power_domains(crtc); |
6023 | for_each_power_domain(domain, domains) | |
6024 | intel_display_power_get(dev_priv, domain); | |
6025 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6026 | |
6027 | dev_priv->display.crtc_enable(crtc); | |
6028 | } | |
6029 | } else { | |
6030 | if (intel_crtc->active) { | |
6031 | dev_priv->display.crtc_disable(crtc); | |
6032 | ||
e1e9fb84 DV |
6033 | domains = intel_crtc->enabled_power_domains; |
6034 | for_each_power_domain(domain, domains) | |
6035 | intel_display_power_put(dev_priv, domain); | |
6036 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6037 | } |
6038 | } | |
b04c5bd6 BF |
6039 | } |
6040 | ||
6041 | /** | |
6042 | * Sets the power management mode of the pipe and plane. | |
6043 | */ | |
6044 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6045 | { | |
6046 | struct drm_device *dev = crtc->dev; | |
6047 | struct intel_encoder *intel_encoder; | |
6048 | bool enable = false; | |
6049 | ||
6050 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6051 | enable |= intel_encoder->connectors_active; | |
6052 | ||
6053 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
6054 | } |
6055 | ||
cdd59983 CW |
6056 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6057 | { | |
cdd59983 | 6058 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6059 | struct drm_connector *connector; |
ee7b9f93 | 6060 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6061 | |
976f8a20 | 6062 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6063 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
6064 | |
6065 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
6066 | dev_priv->display.off(crtc); |
6067 | ||
70a101f8 | 6068 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6069 | |
6070 | /* Update computed state. */ | |
6071 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6072 | if (!connector->encoder || !connector->encoder->crtc) | |
6073 | continue; | |
6074 | ||
6075 | if (connector->encoder->crtc != crtc) | |
6076 | continue; | |
6077 | ||
6078 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6079 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6080 | } |
6081 | } | |
6082 | ||
ea5b213a | 6083 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6084 | { |
4ef69c7a | 6085 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6086 | |
ea5b213a CW |
6087 | drm_encoder_cleanup(encoder); |
6088 | kfree(intel_encoder); | |
7e7d76c3 JB |
6089 | } |
6090 | ||
9237329d | 6091 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6092 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6093 | * state of the entire output pipe. */ | |
9237329d | 6094 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6095 | { |
5ab432ef DV |
6096 | if (mode == DRM_MODE_DPMS_ON) { |
6097 | encoder->connectors_active = true; | |
6098 | ||
b2cabb0e | 6099 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6100 | } else { |
6101 | encoder->connectors_active = false; | |
6102 | ||
b2cabb0e | 6103 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6104 | } |
79e53945 JB |
6105 | } |
6106 | ||
0a91ca29 DV |
6107 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6108 | * internal consistency). */ | |
b980514c | 6109 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6110 | { |
0a91ca29 DV |
6111 | if (connector->get_hw_state(connector)) { |
6112 | struct intel_encoder *encoder = connector->encoder; | |
6113 | struct drm_crtc *crtc; | |
6114 | bool encoder_enabled; | |
6115 | enum pipe pipe; | |
6116 | ||
6117 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6118 | connector->base.base.id, | |
c23cc417 | 6119 | connector->base.name); |
0a91ca29 | 6120 | |
0e32b39c DA |
6121 | /* there is no real hw state for MST connectors */ |
6122 | if (connector->mst_port) | |
6123 | return; | |
6124 | ||
e2c719b7 | 6125 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6126 | "wrong connector dpms state\n"); |
e2c719b7 | 6127 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6128 | "active connector not linked to encoder\n"); |
0a91ca29 | 6129 | |
36cd7444 | 6130 | if (encoder) { |
e2c719b7 | 6131 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6132 | "encoder->connectors_active not set\n"); |
6133 | ||
6134 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6135 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6136 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6137 | return; |
0a91ca29 | 6138 | |
36cd7444 | 6139 | crtc = encoder->base.crtc; |
0a91ca29 | 6140 | |
83d65738 MR |
6141 | I915_STATE_WARN(!crtc->state->enable, |
6142 | "crtc not enabled\n"); | |
e2c719b7 RC |
6143 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6144 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6145 | "encoder active on the wrong pipe\n"); |
6146 | } | |
0a91ca29 | 6147 | } |
79e53945 JB |
6148 | } |
6149 | ||
08d9bc92 ACO |
6150 | int intel_connector_init(struct intel_connector *connector) |
6151 | { | |
6152 | struct drm_connector_state *connector_state; | |
6153 | ||
6154 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6155 | if (!connector_state) | |
6156 | return -ENOMEM; | |
6157 | ||
6158 | connector->base.state = connector_state; | |
6159 | return 0; | |
6160 | } | |
6161 | ||
6162 | struct intel_connector *intel_connector_alloc(void) | |
6163 | { | |
6164 | struct intel_connector *connector; | |
6165 | ||
6166 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6167 | if (!connector) | |
6168 | return NULL; | |
6169 | ||
6170 | if (intel_connector_init(connector) < 0) { | |
6171 | kfree(connector); | |
6172 | return NULL; | |
6173 | } | |
6174 | ||
6175 | return connector; | |
6176 | } | |
6177 | ||
5ab432ef DV |
6178 | /* Even simpler default implementation, if there's really no special case to |
6179 | * consider. */ | |
6180 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6181 | { |
5ab432ef DV |
6182 | /* All the simple cases only support two dpms states. */ |
6183 | if (mode != DRM_MODE_DPMS_ON) | |
6184 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6185 | |
5ab432ef DV |
6186 | if (mode == connector->dpms) |
6187 | return; | |
6188 | ||
6189 | connector->dpms = mode; | |
6190 | ||
6191 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6192 | if (connector->encoder) |
6193 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6194 | |
b980514c | 6195 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6196 | } |
6197 | ||
f0947c37 DV |
6198 | /* Simple connector->get_hw_state implementation for encoders that support only |
6199 | * one connector and no cloning and hence the encoder state determines the state | |
6200 | * of the connector. */ | |
6201 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6202 | { |
24929352 | 6203 | enum pipe pipe = 0; |
f0947c37 | 6204 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6205 | |
f0947c37 | 6206 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6207 | } |
6208 | ||
6d293983 | 6209 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6210 | { |
6d293983 ACO |
6211 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6212 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6213 | |
6214 | return 0; | |
6215 | } | |
6216 | ||
6d293983 | 6217 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6218 | struct intel_crtc_state *pipe_config) |
1857e1da | 6219 | { |
6d293983 ACO |
6220 | struct drm_atomic_state *state = pipe_config->base.state; |
6221 | struct intel_crtc *other_crtc; | |
6222 | struct intel_crtc_state *other_crtc_state; | |
6223 | ||
1857e1da DV |
6224 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6225 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6226 | if (pipe_config->fdi_lanes > 4) { | |
6227 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6228 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6229 | return -EINVAL; |
1857e1da DV |
6230 | } |
6231 | ||
bafb6553 | 6232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6233 | if (pipe_config->fdi_lanes > 2) { |
6234 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6235 | pipe_config->fdi_lanes); | |
6d293983 | 6236 | return -EINVAL; |
1857e1da | 6237 | } else { |
6d293983 | 6238 | return 0; |
1857e1da DV |
6239 | } |
6240 | } | |
6241 | ||
6242 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6243 | return 0; |
1857e1da DV |
6244 | |
6245 | /* Ivybridge 3 pipe is really complicated */ | |
6246 | switch (pipe) { | |
6247 | case PIPE_A: | |
6d293983 | 6248 | return 0; |
1857e1da | 6249 | case PIPE_B: |
6d293983 ACO |
6250 | if (pipe_config->fdi_lanes <= 2) |
6251 | return 0; | |
6252 | ||
6253 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6254 | other_crtc_state = | |
6255 | intel_atomic_get_crtc_state(state, other_crtc); | |
6256 | if (IS_ERR(other_crtc_state)) | |
6257 | return PTR_ERR(other_crtc_state); | |
6258 | ||
6259 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6260 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6261 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6262 | return -EINVAL; |
1857e1da | 6263 | } |
6d293983 | 6264 | return 0; |
1857e1da | 6265 | case PIPE_C: |
251cc67c VS |
6266 | if (pipe_config->fdi_lanes > 2) { |
6267 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6268 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6269 | return -EINVAL; |
251cc67c | 6270 | } |
6d293983 ACO |
6271 | |
6272 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6273 | other_crtc_state = | |
6274 | intel_atomic_get_crtc_state(state, other_crtc); | |
6275 | if (IS_ERR(other_crtc_state)) | |
6276 | return PTR_ERR(other_crtc_state); | |
6277 | ||
6278 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6279 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6280 | return -EINVAL; |
1857e1da | 6281 | } |
6d293983 | 6282 | return 0; |
1857e1da DV |
6283 | default: |
6284 | BUG(); | |
6285 | } | |
6286 | } | |
6287 | ||
e29c22c0 DV |
6288 | #define RETRY 1 |
6289 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6290 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6291 | { |
1857e1da | 6292 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6293 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6294 | int lane, link_bw, fdi_dotclock, ret; |
6295 | bool needs_recompute = false; | |
877d48d5 | 6296 | |
e29c22c0 | 6297 | retry: |
877d48d5 DV |
6298 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6299 | * each output octet as 10 bits. The actual frequency | |
6300 | * is stored as a divider into a 100MHz clock, and the | |
6301 | * mode pixel clock is stored in units of 1KHz. | |
6302 | * Hence the bw of each lane in terms of the mode signal | |
6303 | * is: | |
6304 | */ | |
6305 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6306 | ||
241bfc38 | 6307 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6308 | |
2bd89a07 | 6309 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6310 | pipe_config->pipe_bpp); |
6311 | ||
6312 | pipe_config->fdi_lanes = lane; | |
6313 | ||
2bd89a07 | 6314 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6315 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6316 | |
6d293983 ACO |
6317 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6318 | intel_crtc->pipe, pipe_config); | |
6319 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6320 | pipe_config->pipe_bpp -= 2*3; |
6321 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6322 | pipe_config->pipe_bpp); | |
6323 | needs_recompute = true; | |
6324 | pipe_config->bw_constrained = true; | |
6325 | ||
6326 | goto retry; | |
6327 | } | |
6328 | ||
6329 | if (needs_recompute) | |
6330 | return RETRY; | |
6331 | ||
6d293983 | 6332 | return ret; |
877d48d5 DV |
6333 | } |
6334 | ||
42db64ef | 6335 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6336 | struct intel_crtc_state *pipe_config) |
42db64ef | 6337 | { |
d330a953 | 6338 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6339 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6340 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6341 | } |
6342 | ||
a43f6e0f | 6343 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6344 | struct intel_crtc_state *pipe_config) |
79e53945 | 6345 | { |
a43f6e0f | 6346 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6347 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6348 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6349 | int ret; |
89749350 | 6350 | |
ad3a4479 | 6351 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6352 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6353 | int clock_limit = |
6354 | dev_priv->display.get_display_clock_speed(dev); | |
6355 | ||
6356 | /* | |
6357 | * Enable pixel doubling when the dot clock | |
6358 | * is > 90% of the (display) core speed. | |
6359 | * | |
b397c96b VS |
6360 | * GDG double wide on either pipe, |
6361 | * otherwise pipe A only. | |
cf532bb2 | 6362 | */ |
b397c96b | 6363 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6364 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6365 | clock_limit *= 2; |
cf532bb2 | 6366 | pipe_config->double_wide = true; |
ad3a4479 VS |
6367 | } |
6368 | ||
241bfc38 | 6369 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6370 | return -EINVAL; |
2c07245f | 6371 | } |
89749350 | 6372 | |
1d1d0e27 VS |
6373 | /* |
6374 | * Pipe horizontal size must be even in: | |
6375 | * - DVO ganged mode | |
6376 | * - LVDS dual channel mode | |
6377 | * - Double wide pipe | |
6378 | */ | |
a93e255f | 6379 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6380 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6381 | pipe_config->pipe_src_w &= ~1; | |
6382 | ||
8693a824 DL |
6383 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6384 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6385 | */ |
6386 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6387 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6388 | return -EINVAL; |
44f46b42 | 6389 | |
f5adf94e | 6390 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6391 | hsw_compute_ips_config(crtc, pipe_config); |
6392 | ||
877d48d5 | 6393 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6394 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6395 | |
d03c93d4 CK |
6396 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6397 | * related checks called from atomic_crtc_check function */ | |
6398 | ret = 0; | |
6399 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6400 | crtc, pipe_config->base.state); | |
6401 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6402 | ||
6403 | return ret; | |
79e53945 JB |
6404 | } |
6405 | ||
1652d19e VS |
6406 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6407 | { | |
6408 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6409 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6410 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6411 | uint32_t linkrate; | |
6412 | ||
6413 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6414 | WARN(1, "LCPLL1 not enabled\n"); | |
6415 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6416 | } | |
6417 | ||
6418 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6419 | return 540000; | |
6420 | ||
6421 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6422 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6423 | |
71cd8423 DL |
6424 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6425 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6426 | /* vco 8640 */ |
6427 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6428 | case CDCLK_FREQ_450_432: | |
6429 | return 432000; | |
6430 | case CDCLK_FREQ_337_308: | |
6431 | return 308570; | |
6432 | case CDCLK_FREQ_675_617: | |
6433 | return 617140; | |
6434 | default: | |
6435 | WARN(1, "Unknown cd freq selection\n"); | |
6436 | } | |
6437 | } else { | |
6438 | /* vco 8100 */ | |
6439 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6440 | case CDCLK_FREQ_450_432: | |
6441 | return 450000; | |
6442 | case CDCLK_FREQ_337_308: | |
6443 | return 337500; | |
6444 | case CDCLK_FREQ_675_617: | |
6445 | return 675000; | |
6446 | default: | |
6447 | WARN(1, "Unknown cd freq selection\n"); | |
6448 | } | |
6449 | } | |
6450 | ||
6451 | /* error case, do as if DPLL0 isn't enabled */ | |
6452 | return 24000; | |
6453 | } | |
6454 | ||
6455 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6456 | { | |
6457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6458 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6459 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6460 | ||
6461 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6462 | return 800000; | |
6463 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6464 | return 450000; | |
6465 | else if (freq == LCPLL_CLK_FREQ_450) | |
6466 | return 450000; | |
6467 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6468 | return 540000; | |
6469 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6470 | return 337500; | |
6471 | else | |
6472 | return 675000; | |
6473 | } | |
6474 | ||
6475 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6476 | { | |
6477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6478 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6479 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6480 | ||
6481 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6482 | return 800000; | |
6483 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6484 | return 450000; | |
6485 | else if (freq == LCPLL_CLK_FREQ_450) | |
6486 | return 450000; | |
6487 | else if (IS_HSW_ULT(dev)) | |
6488 | return 337500; | |
6489 | else | |
6490 | return 540000; | |
79e53945 JB |
6491 | } |
6492 | ||
25eb05fc JB |
6493 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6494 | { | |
d197b7d3 | 6495 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6496 | u32 val; |
6497 | int divider; | |
6498 | ||
6bcda4f0 VS |
6499 | if (dev_priv->hpll_freq == 0) |
6500 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6501 | ||
d197b7d3 VS |
6502 | mutex_lock(&dev_priv->dpio_lock); |
6503 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6504 | mutex_unlock(&dev_priv->dpio_lock); | |
6505 | ||
6506 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6507 | ||
7d007f40 VS |
6508 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6509 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6510 | "cdclk change in progress\n"); | |
6511 | ||
6bcda4f0 | 6512 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6513 | } |
6514 | ||
b37a6434 VS |
6515 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6516 | { | |
6517 | return 450000; | |
6518 | } | |
6519 | ||
e70236a8 JB |
6520 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6521 | { | |
6522 | return 400000; | |
6523 | } | |
79e53945 | 6524 | |
e70236a8 | 6525 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6526 | { |
e907f170 | 6527 | return 333333; |
e70236a8 | 6528 | } |
79e53945 | 6529 | |
e70236a8 JB |
6530 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6531 | { | |
6532 | return 200000; | |
6533 | } | |
79e53945 | 6534 | |
257a7ffc DV |
6535 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6536 | { | |
6537 | u16 gcfgc = 0; | |
6538 | ||
6539 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6540 | ||
6541 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6542 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6543 | return 266667; |
257a7ffc | 6544 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6545 | return 333333; |
257a7ffc | 6546 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6547 | return 444444; |
257a7ffc DV |
6548 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6549 | return 200000; | |
6550 | default: | |
6551 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6552 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6553 | return 133333; |
257a7ffc | 6554 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6555 | return 166667; |
257a7ffc DV |
6556 | } |
6557 | } | |
6558 | ||
e70236a8 JB |
6559 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6560 | { | |
6561 | u16 gcfgc = 0; | |
79e53945 | 6562 | |
e70236a8 JB |
6563 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6564 | ||
6565 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6566 | return 133333; |
e70236a8 JB |
6567 | else { |
6568 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6569 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6570 | return 333333; |
e70236a8 JB |
6571 | default: |
6572 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6573 | return 190000; | |
79e53945 | 6574 | } |
e70236a8 JB |
6575 | } |
6576 | } | |
6577 | ||
6578 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6579 | { | |
e907f170 | 6580 | return 266667; |
e70236a8 JB |
6581 | } |
6582 | ||
6583 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6584 | { | |
6585 | u16 hpllcc = 0; | |
6586 | /* Assume that the hardware is in the high speed state. This | |
6587 | * should be the default. | |
6588 | */ | |
6589 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6590 | case GC_CLOCK_133_200: | |
6591 | case GC_CLOCK_100_200: | |
6592 | return 200000; | |
6593 | case GC_CLOCK_166_250: | |
6594 | return 250000; | |
6595 | case GC_CLOCK_100_133: | |
e907f170 | 6596 | return 133333; |
e70236a8 | 6597 | } |
79e53945 | 6598 | |
e70236a8 JB |
6599 | /* Shouldn't happen */ |
6600 | return 0; | |
6601 | } | |
79e53945 | 6602 | |
e70236a8 JB |
6603 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6604 | { | |
e907f170 | 6605 | return 133333; |
79e53945 JB |
6606 | } |
6607 | ||
2c07245f | 6608 | static void |
a65851af | 6609 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6610 | { |
a65851af VS |
6611 | while (*num > DATA_LINK_M_N_MASK || |
6612 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6613 | *num >>= 1; |
6614 | *den >>= 1; | |
6615 | } | |
6616 | } | |
6617 | ||
a65851af VS |
6618 | static void compute_m_n(unsigned int m, unsigned int n, |
6619 | uint32_t *ret_m, uint32_t *ret_n) | |
6620 | { | |
6621 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6622 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6623 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6624 | } | |
6625 | ||
e69d0bc1 DV |
6626 | void |
6627 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6628 | int pixel_clock, int link_clock, | |
6629 | struct intel_link_m_n *m_n) | |
2c07245f | 6630 | { |
e69d0bc1 | 6631 | m_n->tu = 64; |
a65851af VS |
6632 | |
6633 | compute_m_n(bits_per_pixel * pixel_clock, | |
6634 | link_clock * nlanes * 8, | |
6635 | &m_n->gmch_m, &m_n->gmch_n); | |
6636 | ||
6637 | compute_m_n(pixel_clock, link_clock, | |
6638 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6639 | } |
6640 | ||
a7615030 CW |
6641 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6642 | { | |
d330a953 JN |
6643 | if (i915.panel_use_ssc >= 0) |
6644 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6645 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6646 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6647 | } |
6648 | ||
a93e255f ACO |
6649 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6650 | int num_connectors) | |
c65d77d8 | 6651 | { |
a93e255f | 6652 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6653 | struct drm_i915_private *dev_priv = dev->dev_private; |
6654 | int refclk; | |
6655 | ||
a93e255f ACO |
6656 | WARN_ON(!crtc_state->base.state); |
6657 | ||
5ab7b0b7 | 6658 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6659 | refclk = 100000; |
a93e255f | 6660 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6661 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6662 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6663 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6664 | } else if (!IS_GEN2(dev)) { |
6665 | refclk = 96000; | |
6666 | } else { | |
6667 | refclk = 48000; | |
6668 | } | |
6669 | ||
6670 | return refclk; | |
6671 | } | |
6672 | ||
7429e9d4 | 6673 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6674 | { |
7df00d7a | 6675 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6676 | } |
f47709a9 | 6677 | |
7429e9d4 DV |
6678 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6679 | { | |
6680 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6681 | } |
6682 | ||
f47709a9 | 6683 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6684 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6685 | intel_clock_t *reduced_clock) |
6686 | { | |
f47709a9 | 6687 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6688 | u32 fp, fp2 = 0; |
6689 | ||
6690 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6691 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6692 | if (reduced_clock) |
7429e9d4 | 6693 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6694 | } else { |
190f68c5 | 6695 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6696 | if (reduced_clock) |
7429e9d4 | 6697 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6698 | } |
6699 | ||
190f68c5 | 6700 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6701 | |
f47709a9 | 6702 | crtc->lowfreq_avail = false; |
a93e255f | 6703 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6704 | reduced_clock) { |
190f68c5 | 6705 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6706 | crtc->lowfreq_avail = true; |
a7516a05 | 6707 | } else { |
190f68c5 | 6708 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6709 | } |
6710 | } | |
6711 | ||
5e69f97f CML |
6712 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6713 | pipe) | |
89b667f8 JB |
6714 | { |
6715 | u32 reg_val; | |
6716 | ||
6717 | /* | |
6718 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6719 | * and set it to a reasonable value instead. | |
6720 | */ | |
ab3c759a | 6721 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6722 | reg_val &= 0xffffff00; |
6723 | reg_val |= 0x00000030; | |
ab3c759a | 6724 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6725 | |
ab3c759a | 6726 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6727 | reg_val &= 0x8cffffff; |
6728 | reg_val = 0x8c000000; | |
ab3c759a | 6729 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6730 | |
ab3c759a | 6731 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6732 | reg_val &= 0xffffff00; |
ab3c759a | 6733 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6734 | |
ab3c759a | 6735 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6736 | reg_val &= 0x00ffffff; |
6737 | reg_val |= 0xb0000000; | |
ab3c759a | 6738 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6739 | } |
6740 | ||
b551842d DV |
6741 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6742 | struct intel_link_m_n *m_n) | |
6743 | { | |
6744 | struct drm_device *dev = crtc->base.dev; | |
6745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6746 | int pipe = crtc->pipe; | |
6747 | ||
e3b95f1e DV |
6748 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6749 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6750 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6751 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6752 | } |
6753 | ||
6754 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6755 | struct intel_link_m_n *m_n, |
6756 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6757 | { |
6758 | struct drm_device *dev = crtc->base.dev; | |
6759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6760 | int pipe = crtc->pipe; | |
6e3c9717 | 6761 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6762 | |
6763 | if (INTEL_INFO(dev)->gen >= 5) { | |
6764 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6765 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6766 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6767 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6768 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6769 | * for gen < 8) and if DRRS is supported (to make sure the | |
6770 | * registers are not unnecessarily accessed). | |
6771 | */ | |
44395bfe | 6772 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6773 | crtc->config->has_drrs) { |
f769cd24 VK |
6774 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6775 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6776 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6777 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6778 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6779 | } | |
b551842d | 6780 | } else { |
e3b95f1e DV |
6781 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6782 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6783 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6784 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6785 | } |
6786 | } | |
6787 | ||
fe3cd48d | 6788 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6789 | { |
fe3cd48d R |
6790 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6791 | ||
6792 | if (m_n == M1_N1) { | |
6793 | dp_m_n = &crtc->config->dp_m_n; | |
6794 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6795 | } else if (m_n == M2_N2) { | |
6796 | ||
6797 | /* | |
6798 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6799 | * needs to be programmed into M1_N1. | |
6800 | */ | |
6801 | dp_m_n = &crtc->config->dp_m2_n2; | |
6802 | } else { | |
6803 | DRM_ERROR("Unsupported divider value\n"); | |
6804 | return; | |
6805 | } | |
6806 | ||
6e3c9717 ACO |
6807 | if (crtc->config->has_pch_encoder) |
6808 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6809 | else |
fe3cd48d | 6810 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6811 | } |
6812 | ||
d288f65f | 6813 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6814 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6815 | { |
6816 | u32 dpll, dpll_md; | |
6817 | ||
6818 | /* | |
6819 | * Enable DPIO clock input. We should never disable the reference | |
6820 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6821 | * on it. | |
6822 | */ | |
6823 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6824 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6825 | /* We should never disable this, set it here for state tracking */ | |
6826 | if (crtc->pipe == PIPE_B) | |
6827 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6828 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6829 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6830 | |
d288f65f | 6831 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6832 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6833 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6834 | } |
6835 | ||
d288f65f | 6836 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6837 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6838 | { |
f47709a9 | 6839 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6840 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6841 | int pipe = crtc->pipe; |
bdd4b6a6 | 6842 | u32 mdiv; |
a0c4da24 | 6843 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6844 | u32 coreclk, reg_val; |
a0c4da24 | 6845 | |
09153000 DV |
6846 | mutex_lock(&dev_priv->dpio_lock); |
6847 | ||
d288f65f VS |
6848 | bestn = pipe_config->dpll.n; |
6849 | bestm1 = pipe_config->dpll.m1; | |
6850 | bestm2 = pipe_config->dpll.m2; | |
6851 | bestp1 = pipe_config->dpll.p1; | |
6852 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6853 | |
89b667f8 JB |
6854 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6855 | ||
6856 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6857 | if (pipe == PIPE_B) |
5e69f97f | 6858 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6859 | |
6860 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6861 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6862 | |
6863 | /* Disable target IRef on PLL */ | |
ab3c759a | 6864 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6865 | reg_val &= 0x00ffffff; |
ab3c759a | 6866 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6867 | |
6868 | /* Disable fast lock */ | |
ab3c759a | 6869 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6870 | |
6871 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6872 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6873 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6874 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6875 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6876 | |
6877 | /* | |
6878 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6879 | * but we don't support that). | |
6880 | * Note: don't use the DAC post divider as it seems unstable. | |
6881 | */ | |
6882 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6883 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6884 | |
a0c4da24 | 6885 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6886 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6887 | |
89b667f8 | 6888 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6889 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6890 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6891 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6892 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6893 | 0x009f0003); |
89b667f8 | 6894 | else |
ab3c759a | 6895 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6896 | 0x00d0000f); |
6897 | ||
681a8504 | 6898 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6899 | /* Use SSC source */ |
bdd4b6a6 | 6900 | if (pipe == PIPE_A) |
ab3c759a | 6901 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6902 | 0x0df40000); |
6903 | else | |
ab3c759a | 6904 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6905 | 0x0df70000); |
6906 | } else { /* HDMI or VGA */ | |
6907 | /* Use bend source */ | |
bdd4b6a6 | 6908 | if (pipe == PIPE_A) |
ab3c759a | 6909 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6910 | 0x0df70000); |
6911 | else | |
ab3c759a | 6912 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6913 | 0x0df40000); |
6914 | } | |
a0c4da24 | 6915 | |
ab3c759a | 6916 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6917 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6918 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6919 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6920 | coreclk |= 0x01000000; |
ab3c759a | 6921 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6922 | |
ab3c759a | 6923 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6924 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6925 | } |
6926 | ||
d288f65f | 6927 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6928 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6929 | { |
d288f65f | 6930 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6931 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6932 | DPLL_VCO_ENABLE; | |
6933 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6934 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6935 | |
d288f65f VS |
6936 | pipe_config->dpll_hw_state.dpll_md = |
6937 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6938 | } |
6939 | ||
d288f65f | 6940 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6941 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6942 | { |
6943 | struct drm_device *dev = crtc->base.dev; | |
6944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6945 | int pipe = crtc->pipe; | |
6946 | int dpll_reg = DPLL(crtc->pipe); | |
6947 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6948 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6949 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6950 | u32 dpio_val; |
9cbe40c1 | 6951 | int vco; |
9d556c99 | 6952 | |
d288f65f VS |
6953 | bestn = pipe_config->dpll.n; |
6954 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6955 | bestm1 = pipe_config->dpll.m1; | |
6956 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6957 | bestp1 = pipe_config->dpll.p1; | |
6958 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6959 | vco = pipe_config->dpll.vco; |
a945ce7e | 6960 | dpio_val = 0; |
9cbe40c1 | 6961 | loopfilter = 0; |
9d556c99 CML |
6962 | |
6963 | /* | |
6964 | * Enable Refclk and SSC | |
6965 | */ | |
a11b0703 | 6966 | I915_WRITE(dpll_reg, |
d288f65f | 6967 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6968 | |
6969 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6970 | |
9d556c99 CML |
6971 | /* p1 and p2 divider */ |
6972 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6973 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6974 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6975 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6976 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6977 | ||
6978 | /* Feedback post-divider - m2 */ | |
6979 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6980 | ||
6981 | /* Feedback refclk divider - n and m1 */ | |
6982 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6983 | DPIO_CHV_M1_DIV_BY_2 | | |
6984 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6985 | ||
6986 | /* M2 fraction division */ | |
a945ce7e VP |
6987 | if (bestm2_frac) |
6988 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6989 | |
6990 | /* M2 fraction division enable */ | |
a945ce7e VP |
6991 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6992 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6993 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6994 | if (bestm2_frac) | |
6995 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6996 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6997 | |
de3a0fde VP |
6998 | /* Program digital lock detect threshold */ |
6999 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7000 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7001 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7002 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7003 | if (!bestm2_frac) | |
7004 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7005 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7006 | ||
9d556c99 | 7007 | /* Loop filter */ |
9cbe40c1 VP |
7008 | if (vco == 5400000) { |
7009 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7010 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7011 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7012 | tribuf_calcntr = 0x9; | |
7013 | } else if (vco <= 6200000) { | |
7014 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7015 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7016 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7017 | tribuf_calcntr = 0x9; | |
7018 | } else if (vco <= 6480000) { | |
7019 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7020 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7021 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7022 | tribuf_calcntr = 0x8; | |
7023 | } else { | |
7024 | /* Not supported. Apply the same limits as in the max case */ | |
7025 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7026 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7027 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7028 | tribuf_calcntr = 0; | |
7029 | } | |
9d556c99 CML |
7030 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7031 | ||
968040b2 | 7032 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7033 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7034 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7035 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7036 | ||
9d556c99 CML |
7037 | /* AFC Recal */ |
7038 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7039 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7040 | DPIO_AFC_RECAL); | |
7041 | ||
7042 | mutex_unlock(&dev_priv->dpio_lock); | |
7043 | } | |
7044 | ||
d288f65f VS |
7045 | /** |
7046 | * vlv_force_pll_on - forcibly enable just the PLL | |
7047 | * @dev_priv: i915 private structure | |
7048 | * @pipe: pipe PLL to enable | |
7049 | * @dpll: PLL configuration | |
7050 | * | |
7051 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7052 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7053 | * be enabled. | |
7054 | */ | |
7055 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7056 | const struct dpll *dpll) | |
7057 | { | |
7058 | struct intel_crtc *crtc = | |
7059 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7060 | struct intel_crtc_state pipe_config = { |
a93e255f | 7061 | .base.crtc = &crtc->base, |
d288f65f VS |
7062 | .pixel_multiplier = 1, |
7063 | .dpll = *dpll, | |
7064 | }; | |
7065 | ||
7066 | if (IS_CHERRYVIEW(dev)) { | |
7067 | chv_update_pll(crtc, &pipe_config); | |
7068 | chv_prepare_pll(crtc, &pipe_config); | |
7069 | chv_enable_pll(crtc, &pipe_config); | |
7070 | } else { | |
7071 | vlv_update_pll(crtc, &pipe_config); | |
7072 | vlv_prepare_pll(crtc, &pipe_config); | |
7073 | vlv_enable_pll(crtc, &pipe_config); | |
7074 | } | |
7075 | } | |
7076 | ||
7077 | /** | |
7078 | * vlv_force_pll_off - forcibly disable just the PLL | |
7079 | * @dev_priv: i915 private structure | |
7080 | * @pipe: pipe PLL to disable | |
7081 | * | |
7082 | * Disable the PLL for @pipe. To be used in cases where we need | |
7083 | * the PLL enabled even when @pipe is not going to be enabled. | |
7084 | */ | |
7085 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7086 | { | |
7087 | if (IS_CHERRYVIEW(dev)) | |
7088 | chv_disable_pll(to_i915(dev), pipe); | |
7089 | else | |
7090 | vlv_disable_pll(to_i915(dev), pipe); | |
7091 | } | |
7092 | ||
f47709a9 | 7093 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7094 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7095 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7096 | int num_connectors) |
7097 | { | |
f47709a9 | 7098 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7099 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7100 | u32 dpll; |
7101 | bool is_sdvo; | |
190f68c5 | 7102 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7103 | |
190f68c5 | 7104 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7105 | |
a93e255f ACO |
7106 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7107 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7108 | |
7109 | dpll = DPLL_VGA_MODE_DIS; | |
7110 | ||
a93e255f | 7111 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7112 | dpll |= DPLLB_MODE_LVDS; |
7113 | else | |
7114 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7115 | |
ef1b460d | 7116 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7117 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7118 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7119 | } |
198a037f DV |
7120 | |
7121 | if (is_sdvo) | |
4a33e48d | 7122 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7123 | |
190f68c5 | 7124 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7125 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7126 | |
7127 | /* compute bitmask from p1 value */ | |
7128 | if (IS_PINEVIEW(dev)) | |
7129 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7130 | else { | |
7131 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7132 | if (IS_G4X(dev) && reduced_clock) | |
7133 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7134 | } | |
7135 | switch (clock->p2) { | |
7136 | case 5: | |
7137 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7138 | break; | |
7139 | case 7: | |
7140 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7141 | break; | |
7142 | case 10: | |
7143 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7144 | break; | |
7145 | case 14: | |
7146 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7147 | break; | |
7148 | } | |
7149 | if (INTEL_INFO(dev)->gen >= 4) | |
7150 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7151 | ||
190f68c5 | 7152 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7153 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7154 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7155 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7156 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7157 | else | |
7158 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7159 | ||
7160 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7161 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7162 | |
eb1cbe48 | 7163 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7164 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7165 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7166 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7167 | } |
7168 | } | |
7169 | ||
f47709a9 | 7170 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7171 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7172 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7173 | int num_connectors) |
7174 | { | |
f47709a9 | 7175 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7176 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7177 | u32 dpll; |
190f68c5 | 7178 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7179 | |
190f68c5 | 7180 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7181 | |
eb1cbe48 DV |
7182 | dpll = DPLL_VGA_MODE_DIS; |
7183 | ||
a93e255f | 7184 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7185 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7186 | } else { | |
7187 | if (clock->p1 == 2) | |
7188 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7189 | else | |
7190 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7191 | if (clock->p2 == 4) | |
7192 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7193 | } | |
7194 | ||
a93e255f | 7195 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7196 | dpll |= DPLL_DVO_2X_MODE; |
7197 | ||
a93e255f | 7198 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7199 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7200 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7201 | else | |
7202 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7203 | ||
7204 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7205 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7206 | } |
7207 | ||
8a654f3b | 7208 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7209 | { |
7210 | struct drm_device *dev = intel_crtc->base.dev; | |
7211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7212 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7213 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7214 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7215 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7216 | uint32_t crtc_vtotal, crtc_vblank_end; |
7217 | int vsyncshift = 0; | |
4d8a62ea DV |
7218 | |
7219 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7220 | * the hw state checker will get angry at the mismatch. */ | |
7221 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7222 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7223 | |
609aeaca | 7224 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7225 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7226 | crtc_vtotal -= 1; |
7227 | crtc_vblank_end -= 1; | |
609aeaca | 7228 | |
409ee761 | 7229 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7230 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7231 | else | |
7232 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7233 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7234 | if (vsyncshift < 0) |
7235 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7236 | } |
7237 | ||
7238 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7239 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7240 | |
fe2b8f9d | 7241 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7242 | (adjusted_mode->crtc_hdisplay - 1) | |
7243 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7244 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7245 | (adjusted_mode->crtc_hblank_start - 1) | |
7246 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7247 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7248 | (adjusted_mode->crtc_hsync_start - 1) | |
7249 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7250 | ||
fe2b8f9d | 7251 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7252 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7253 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7254 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7255 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7256 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7257 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7258 | (adjusted_mode->crtc_vsync_start - 1) | |
7259 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7260 | ||
b5e508d4 PZ |
7261 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7262 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7263 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7264 | * bits. */ | |
7265 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7266 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7267 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7268 | ||
b0e77b9c PZ |
7269 | /* pipesrc controls the size that is scaled from, which should |
7270 | * always be the user's requested size. | |
7271 | */ | |
7272 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7273 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7274 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7275 | } |
7276 | ||
1bd1bd80 | 7277 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7278 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7279 | { |
7280 | struct drm_device *dev = crtc->base.dev; | |
7281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7282 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7283 | uint32_t tmp; | |
7284 | ||
7285 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7286 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7287 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7288 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7289 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7290 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7291 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7292 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7293 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7294 | |
7295 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7296 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7297 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7298 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7299 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7300 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7301 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7302 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7303 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7304 | |
7305 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7306 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7307 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7308 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7309 | } |
7310 | ||
7311 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7312 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7313 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7314 | ||
2d112de7 ACO |
7315 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7316 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7317 | } |
7318 | ||
f6a83288 | 7319 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7320 | struct intel_crtc_state *pipe_config) |
babea61d | 7321 | { |
2d112de7 ACO |
7322 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7323 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7324 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7325 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7326 | |
2d112de7 ACO |
7327 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7328 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7329 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7330 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7331 | |
2d112de7 | 7332 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7333 | |
2d112de7 ACO |
7334 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7335 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7336 | } |
7337 | ||
84b046f3 DV |
7338 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7339 | { | |
7340 | struct drm_device *dev = intel_crtc->base.dev; | |
7341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7342 | uint32_t pipeconf; | |
7343 | ||
9f11a9e4 | 7344 | pipeconf = 0; |
84b046f3 | 7345 | |
b6b5d049 VS |
7346 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7347 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7348 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7349 | |
6e3c9717 | 7350 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7351 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7352 | |
ff9ce46e DV |
7353 | /* only g4x and later have fancy bpc/dither controls */ |
7354 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7355 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7356 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7357 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7358 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7359 | |
6e3c9717 | 7360 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7361 | case 18: |
7362 | pipeconf |= PIPECONF_6BPC; | |
7363 | break; | |
7364 | case 24: | |
7365 | pipeconf |= PIPECONF_8BPC; | |
7366 | break; | |
7367 | case 30: | |
7368 | pipeconf |= PIPECONF_10BPC; | |
7369 | break; | |
7370 | default: | |
7371 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7372 | BUG(); | |
84b046f3 DV |
7373 | } |
7374 | } | |
7375 | ||
7376 | if (HAS_PIPE_CXSR(dev)) { | |
7377 | if (intel_crtc->lowfreq_avail) { | |
7378 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7379 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7380 | } else { | |
7381 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7382 | } |
7383 | } | |
7384 | ||
6e3c9717 | 7385 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7386 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7387 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7388 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7389 | else | |
7390 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7391 | } else | |
84b046f3 DV |
7392 | pipeconf |= PIPECONF_PROGRESSIVE; |
7393 | ||
6e3c9717 | 7394 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7395 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7396 | |
84b046f3 DV |
7397 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7398 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7399 | } | |
7400 | ||
190f68c5 ACO |
7401 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7402 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7403 | { |
c7653199 | 7404 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7405 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7406 | int refclk, num_connectors = 0; |
652c393a | 7407 | intel_clock_t clock, reduced_clock; |
a16af721 | 7408 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7409 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7410 | struct intel_encoder *encoder; |
d4906093 | 7411 | const intel_limit_t *limit; |
55bb9992 ACO |
7412 | struct drm_atomic_state *state = crtc_state->base.state; |
7413 | struct drm_connector_state *connector_state; | |
7414 | int i; | |
79e53945 | 7415 | |
55bb9992 ACO |
7416 | for (i = 0; i < state->num_connector; i++) { |
7417 | if (!state->connectors[i]) | |
d0737e1d ACO |
7418 | continue; |
7419 | ||
55bb9992 ACO |
7420 | connector_state = state->connector_states[i]; |
7421 | if (connector_state->crtc != &crtc->base) | |
7422 | continue; | |
7423 | ||
7424 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7425 | ||
5eddb70b | 7426 | switch (encoder->type) { |
79e53945 JB |
7427 | case INTEL_OUTPUT_LVDS: |
7428 | is_lvds = true; | |
7429 | break; | |
e9fd1c02 JN |
7430 | case INTEL_OUTPUT_DSI: |
7431 | is_dsi = true; | |
7432 | break; | |
6847d71b PZ |
7433 | default: |
7434 | break; | |
79e53945 | 7435 | } |
43565a06 | 7436 | |
c751ce4f | 7437 | num_connectors++; |
79e53945 JB |
7438 | } |
7439 | ||
f2335330 | 7440 | if (is_dsi) |
5b18e57c | 7441 | return 0; |
f2335330 | 7442 | |
190f68c5 | 7443 | if (!crtc_state->clock_set) { |
a93e255f | 7444 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7445 | |
e9fd1c02 JN |
7446 | /* |
7447 | * Returns a set of divisors for the desired target clock with | |
7448 | * the given refclk, or FALSE. The returned values represent | |
7449 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7450 | * 2) / p1 / p2. | |
7451 | */ | |
a93e255f ACO |
7452 | limit = intel_limit(crtc_state, refclk); |
7453 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7454 | crtc_state->port_clock, |
e9fd1c02 | 7455 | refclk, NULL, &clock); |
f2335330 | 7456 | if (!ok) { |
e9fd1c02 JN |
7457 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7458 | return -EINVAL; | |
7459 | } | |
79e53945 | 7460 | |
f2335330 JN |
7461 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7462 | /* | |
7463 | * Ensure we match the reduced clock's P to the target | |
7464 | * clock. If the clocks don't match, we can't switch | |
7465 | * the display clock by using the FP0/FP1. In such case | |
7466 | * we will disable the LVDS downclock feature. | |
7467 | */ | |
7468 | has_reduced_clock = | |
a93e255f | 7469 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7470 | dev_priv->lvds_downclock, |
7471 | refclk, &clock, | |
7472 | &reduced_clock); | |
7473 | } | |
7474 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7475 | crtc_state->dpll.n = clock.n; |
7476 | crtc_state->dpll.m1 = clock.m1; | |
7477 | crtc_state->dpll.m2 = clock.m2; | |
7478 | crtc_state->dpll.p1 = clock.p1; | |
7479 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7480 | } |
7026d4ac | 7481 | |
e9fd1c02 | 7482 | if (IS_GEN2(dev)) { |
190f68c5 | 7483 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7484 | has_reduced_clock ? &reduced_clock : NULL, |
7485 | num_connectors); | |
9d556c99 | 7486 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7487 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7488 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7489 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7490 | } else { |
190f68c5 | 7491 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7492 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7493 | num_connectors); |
e9fd1c02 | 7494 | } |
79e53945 | 7495 | |
c8f7a0db | 7496 | return 0; |
f564048e EA |
7497 | } |
7498 | ||
2fa2fe9a | 7499 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7500 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7501 | { |
7502 | struct drm_device *dev = crtc->base.dev; | |
7503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7504 | uint32_t tmp; | |
7505 | ||
dc9e7dec VS |
7506 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7507 | return; | |
7508 | ||
2fa2fe9a | 7509 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7510 | if (!(tmp & PFIT_ENABLE)) |
7511 | return; | |
2fa2fe9a | 7512 | |
06922821 | 7513 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7514 | if (INTEL_INFO(dev)->gen < 4) { |
7515 | if (crtc->pipe != PIPE_B) | |
7516 | return; | |
2fa2fe9a DV |
7517 | } else { |
7518 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7519 | return; | |
7520 | } | |
7521 | ||
06922821 | 7522 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7523 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7524 | if (INTEL_INFO(dev)->gen < 5) | |
7525 | pipe_config->gmch_pfit.lvds_border_bits = | |
7526 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7527 | } | |
7528 | ||
acbec814 | 7529 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7530 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7531 | { |
7532 | struct drm_device *dev = crtc->base.dev; | |
7533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7534 | int pipe = pipe_config->cpu_transcoder; | |
7535 | intel_clock_t clock; | |
7536 | u32 mdiv; | |
662c6ecb | 7537 | int refclk = 100000; |
acbec814 | 7538 | |
f573de5a SK |
7539 | /* In case of MIPI DPLL will not even be used */ |
7540 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7541 | return; | |
7542 | ||
acbec814 | 7543 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7544 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7545 | mutex_unlock(&dev_priv->dpio_lock); |
7546 | ||
7547 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7548 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7549 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7550 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7551 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7552 | ||
f646628b | 7553 | vlv_clock(refclk, &clock); |
acbec814 | 7554 | |
f646628b VS |
7555 | /* clock.dot is the fast clock */ |
7556 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7557 | } |
7558 | ||
5724dbd1 DL |
7559 | static void |
7560 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7561 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7562 | { |
7563 | struct drm_device *dev = crtc->base.dev; | |
7564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7565 | u32 val, base, offset; | |
7566 | int pipe = crtc->pipe, plane = crtc->plane; | |
7567 | int fourcc, pixel_format; | |
6761dd31 | 7568 | unsigned int aligned_height; |
b113d5ee | 7569 | struct drm_framebuffer *fb; |
1b842c89 | 7570 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7571 | |
42a7b088 DL |
7572 | val = I915_READ(DSPCNTR(plane)); |
7573 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7574 | return; | |
7575 | ||
d9806c9f | 7576 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7577 | if (!intel_fb) { |
1ad292b5 JB |
7578 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7579 | return; | |
7580 | } | |
7581 | ||
1b842c89 DL |
7582 | fb = &intel_fb->base; |
7583 | ||
18c5247e DV |
7584 | if (INTEL_INFO(dev)->gen >= 4) { |
7585 | if (val & DISPPLANE_TILED) { | |
49af449b | 7586 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7587 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7588 | } | |
7589 | } | |
1ad292b5 JB |
7590 | |
7591 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7592 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7593 | fb->pixel_format = fourcc; |
7594 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7595 | |
7596 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7597 | if (plane_config->tiling) |
1ad292b5 JB |
7598 | offset = I915_READ(DSPTILEOFF(plane)); |
7599 | else | |
7600 | offset = I915_READ(DSPLINOFF(plane)); | |
7601 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7602 | } else { | |
7603 | base = I915_READ(DSPADDR(plane)); | |
7604 | } | |
7605 | plane_config->base = base; | |
7606 | ||
7607 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7608 | fb->width = ((val >> 16) & 0xfff) + 1; |
7609 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7610 | |
7611 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7612 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7613 | |
b113d5ee | 7614 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7615 | fb->pixel_format, |
7616 | fb->modifier[0]); | |
1ad292b5 | 7617 | |
f37b5c2b | 7618 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7619 | |
2844a921 DL |
7620 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7621 | pipe_name(pipe), plane, fb->width, fb->height, | |
7622 | fb->bits_per_pixel, base, fb->pitches[0], | |
7623 | plane_config->size); | |
1ad292b5 | 7624 | |
2d14030b | 7625 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7626 | } |
7627 | ||
70b23a98 | 7628 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7629 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7630 | { |
7631 | struct drm_device *dev = crtc->base.dev; | |
7632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7633 | int pipe = pipe_config->cpu_transcoder; | |
7634 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7635 | intel_clock_t clock; | |
7636 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7637 | int refclk = 100000; | |
7638 | ||
7639 | mutex_lock(&dev_priv->dpio_lock); | |
7640 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7641 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7642 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7643 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7644 | mutex_unlock(&dev_priv->dpio_lock); | |
7645 | ||
7646 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7647 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7648 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7649 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7650 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7651 | ||
7652 | chv_clock(refclk, &clock); | |
7653 | ||
7654 | /* clock.dot is the fast clock */ | |
7655 | pipe_config->port_clock = clock.dot / 5; | |
7656 | } | |
7657 | ||
0e8ffe1b | 7658 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7659 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7660 | { |
7661 | struct drm_device *dev = crtc->base.dev; | |
7662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7663 | uint32_t tmp; | |
7664 | ||
f458ebbc DV |
7665 | if (!intel_display_power_is_enabled(dev_priv, |
7666 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7667 | return false; |
7668 | ||
e143a21c | 7669 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7670 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7671 | |
0e8ffe1b DV |
7672 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7673 | if (!(tmp & PIPECONF_ENABLE)) | |
7674 | return false; | |
7675 | ||
42571aef VS |
7676 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7677 | switch (tmp & PIPECONF_BPC_MASK) { | |
7678 | case PIPECONF_6BPC: | |
7679 | pipe_config->pipe_bpp = 18; | |
7680 | break; | |
7681 | case PIPECONF_8BPC: | |
7682 | pipe_config->pipe_bpp = 24; | |
7683 | break; | |
7684 | case PIPECONF_10BPC: | |
7685 | pipe_config->pipe_bpp = 30; | |
7686 | break; | |
7687 | default: | |
7688 | break; | |
7689 | } | |
7690 | } | |
7691 | ||
b5a9fa09 DV |
7692 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7693 | pipe_config->limited_color_range = true; | |
7694 | ||
282740f7 VS |
7695 | if (INTEL_INFO(dev)->gen < 4) |
7696 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7697 | ||
1bd1bd80 DV |
7698 | intel_get_pipe_timings(crtc, pipe_config); |
7699 | ||
2fa2fe9a DV |
7700 | i9xx_get_pfit_config(crtc, pipe_config); |
7701 | ||
6c49f241 DV |
7702 | if (INTEL_INFO(dev)->gen >= 4) { |
7703 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7704 | pipe_config->pixel_multiplier = | |
7705 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7706 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7707 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7708 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7709 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7710 | pipe_config->pixel_multiplier = | |
7711 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7712 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7713 | } else { | |
7714 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7715 | * port and will be fixed up in the encoder->get_config | |
7716 | * function. */ | |
7717 | pipe_config->pixel_multiplier = 1; | |
7718 | } | |
8bcc2795 DV |
7719 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7720 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7721 | /* |
7722 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7723 | * on 830. Filter it out here so that we don't | |
7724 | * report errors due to that. | |
7725 | */ | |
7726 | if (IS_I830(dev)) | |
7727 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7728 | ||
8bcc2795 DV |
7729 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7730 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7731 | } else { |
7732 | /* Mask out read-only status bits. */ | |
7733 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7734 | DPLL_PORTC_READY_MASK | | |
7735 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7736 | } |
6c49f241 | 7737 | |
70b23a98 VS |
7738 | if (IS_CHERRYVIEW(dev)) |
7739 | chv_crtc_clock_get(crtc, pipe_config); | |
7740 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7741 | vlv_crtc_clock_get(crtc, pipe_config); |
7742 | else | |
7743 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7744 | |
0e8ffe1b DV |
7745 | return true; |
7746 | } | |
7747 | ||
dde86e2d | 7748 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7749 | { |
7750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7751 | struct intel_encoder *encoder; |
74cfd7ac | 7752 | u32 val, final; |
13d83a67 | 7753 | bool has_lvds = false; |
199e5d79 | 7754 | bool has_cpu_edp = false; |
199e5d79 | 7755 | bool has_panel = false; |
99eb6a01 KP |
7756 | bool has_ck505 = false; |
7757 | bool can_ssc = false; | |
13d83a67 JB |
7758 | |
7759 | /* We need to take the global config into account */ | |
b2784e15 | 7760 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7761 | switch (encoder->type) { |
7762 | case INTEL_OUTPUT_LVDS: | |
7763 | has_panel = true; | |
7764 | has_lvds = true; | |
7765 | break; | |
7766 | case INTEL_OUTPUT_EDP: | |
7767 | has_panel = true; | |
2de6905f | 7768 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7769 | has_cpu_edp = true; |
7770 | break; | |
6847d71b PZ |
7771 | default: |
7772 | break; | |
13d83a67 JB |
7773 | } |
7774 | } | |
7775 | ||
99eb6a01 | 7776 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7777 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7778 | can_ssc = has_ck505; |
7779 | } else { | |
7780 | has_ck505 = false; | |
7781 | can_ssc = true; | |
7782 | } | |
7783 | ||
2de6905f ID |
7784 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7785 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7786 | |
7787 | /* Ironlake: try to setup display ref clock before DPLL | |
7788 | * enabling. This is only under driver's control after | |
7789 | * PCH B stepping, previous chipset stepping should be | |
7790 | * ignoring this setting. | |
7791 | */ | |
74cfd7ac CW |
7792 | val = I915_READ(PCH_DREF_CONTROL); |
7793 | ||
7794 | /* As we must carefully and slowly disable/enable each source in turn, | |
7795 | * compute the final state we want first and check if we need to | |
7796 | * make any changes at all. | |
7797 | */ | |
7798 | final = val; | |
7799 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7800 | if (has_ck505) | |
7801 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7802 | else | |
7803 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7804 | ||
7805 | final &= ~DREF_SSC_SOURCE_MASK; | |
7806 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7807 | final &= ~DREF_SSC1_ENABLE; | |
7808 | ||
7809 | if (has_panel) { | |
7810 | final |= DREF_SSC_SOURCE_ENABLE; | |
7811 | ||
7812 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7813 | final |= DREF_SSC1_ENABLE; | |
7814 | ||
7815 | if (has_cpu_edp) { | |
7816 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7817 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7818 | else | |
7819 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7820 | } else | |
7821 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7822 | } else { | |
7823 | final |= DREF_SSC_SOURCE_DISABLE; | |
7824 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7825 | } | |
7826 | ||
7827 | if (final == val) | |
7828 | return; | |
7829 | ||
13d83a67 | 7830 | /* Always enable nonspread source */ |
74cfd7ac | 7831 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7832 | |
99eb6a01 | 7833 | if (has_ck505) |
74cfd7ac | 7834 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7835 | else |
74cfd7ac | 7836 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7837 | |
199e5d79 | 7838 | if (has_panel) { |
74cfd7ac CW |
7839 | val &= ~DREF_SSC_SOURCE_MASK; |
7840 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7841 | |
199e5d79 | 7842 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7843 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7844 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7845 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7846 | } else |
74cfd7ac | 7847 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7848 | |
7849 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7850 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7851 | POSTING_READ(PCH_DREF_CONTROL); |
7852 | udelay(200); | |
7853 | ||
74cfd7ac | 7854 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7855 | |
7856 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7857 | if (has_cpu_edp) { |
99eb6a01 | 7858 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7859 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7860 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7861 | } else |
74cfd7ac | 7862 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7863 | } else |
74cfd7ac | 7864 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7865 | |
74cfd7ac | 7866 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7867 | POSTING_READ(PCH_DREF_CONTROL); |
7868 | udelay(200); | |
7869 | } else { | |
7870 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7871 | ||
74cfd7ac | 7872 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7873 | |
7874 | /* Turn off CPU output */ | |
74cfd7ac | 7875 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7876 | |
74cfd7ac | 7877 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7878 | POSTING_READ(PCH_DREF_CONTROL); |
7879 | udelay(200); | |
7880 | ||
7881 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7882 | val &= ~DREF_SSC_SOURCE_MASK; |
7883 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7884 | |
7885 | /* Turn off SSC1 */ | |
74cfd7ac | 7886 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7887 | |
74cfd7ac | 7888 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7889 | POSTING_READ(PCH_DREF_CONTROL); |
7890 | udelay(200); | |
7891 | } | |
74cfd7ac CW |
7892 | |
7893 | BUG_ON(val != final); | |
13d83a67 JB |
7894 | } |
7895 | ||
f31f2d55 | 7896 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7897 | { |
f31f2d55 | 7898 | uint32_t tmp; |
dde86e2d | 7899 | |
0ff066a9 PZ |
7900 | tmp = I915_READ(SOUTH_CHICKEN2); |
7901 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7902 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7903 | |
0ff066a9 PZ |
7904 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7905 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7906 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7907 | |
0ff066a9 PZ |
7908 | tmp = I915_READ(SOUTH_CHICKEN2); |
7909 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7910 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7911 | |
0ff066a9 PZ |
7912 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7913 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7914 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7915 | } |
7916 | ||
7917 | /* WaMPhyProgramming:hsw */ | |
7918 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7919 | { | |
7920 | uint32_t tmp; | |
dde86e2d PZ |
7921 | |
7922 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7923 | tmp &= ~(0xFF << 24); | |
7924 | tmp |= (0x12 << 24); | |
7925 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7926 | ||
dde86e2d PZ |
7927 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7928 | tmp |= (1 << 11); | |
7929 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7930 | ||
7931 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7932 | tmp |= (1 << 11); | |
7933 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7934 | ||
dde86e2d PZ |
7935 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7936 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7937 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7938 | ||
7939 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7940 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7941 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7942 | ||
0ff066a9 PZ |
7943 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7944 | tmp &= ~(7 << 13); | |
7945 | tmp |= (5 << 13); | |
7946 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7947 | |
0ff066a9 PZ |
7948 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7949 | tmp &= ~(7 << 13); | |
7950 | tmp |= (5 << 13); | |
7951 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7952 | |
7953 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7954 | tmp &= ~0xFF; | |
7955 | tmp |= 0x1C; | |
7956 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7957 | ||
7958 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7959 | tmp &= ~0xFF; | |
7960 | tmp |= 0x1C; | |
7961 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7962 | ||
7963 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7964 | tmp &= ~(0xFF << 16); | |
7965 | tmp |= (0x1C << 16); | |
7966 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7967 | ||
7968 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7969 | tmp &= ~(0xFF << 16); | |
7970 | tmp |= (0x1C << 16); | |
7971 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7972 | ||
0ff066a9 PZ |
7973 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7974 | tmp |= (1 << 27); | |
7975 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7976 | |
0ff066a9 PZ |
7977 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7978 | tmp |= (1 << 27); | |
7979 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7980 | |
0ff066a9 PZ |
7981 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7982 | tmp &= ~(0xF << 28); | |
7983 | tmp |= (4 << 28); | |
7984 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7985 | |
0ff066a9 PZ |
7986 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7987 | tmp &= ~(0xF << 28); | |
7988 | tmp |= (4 << 28); | |
7989 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7990 | } |
7991 | ||
2fa86a1f PZ |
7992 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7993 | * Programming" based on the parameters passed: | |
7994 | * - Sequence to enable CLKOUT_DP | |
7995 | * - Sequence to enable CLKOUT_DP without spread | |
7996 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7997 | */ | |
7998 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7999 | bool with_fdi) | |
f31f2d55 PZ |
8000 | { |
8001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8002 | uint32_t reg, tmp; |
8003 | ||
8004 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8005 | with_spread = true; | |
8006 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8007 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8008 | with_fdi = false; | |
f31f2d55 PZ |
8009 | |
8010 | mutex_lock(&dev_priv->dpio_lock); | |
8011 | ||
8012 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8013 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8014 | tmp |= SBI_SSCCTL_PATHALT; | |
8015 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8016 | ||
8017 | udelay(24); | |
8018 | ||
2fa86a1f PZ |
8019 | if (with_spread) { |
8020 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8021 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8022 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8023 | |
2fa86a1f PZ |
8024 | if (with_fdi) { |
8025 | lpt_reset_fdi_mphy(dev_priv); | |
8026 | lpt_program_fdi_mphy(dev_priv); | |
8027 | } | |
8028 | } | |
dde86e2d | 8029 | |
2fa86a1f PZ |
8030 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8031 | SBI_GEN0 : SBI_DBUFF0; | |
8032 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8033 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8034 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
8035 | |
8036 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
8037 | } |
8038 | ||
47701c3b PZ |
8039 | /* Sequence to disable CLKOUT_DP */ |
8040 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8041 | { | |
8042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8043 | uint32_t reg, tmp; | |
8044 | ||
8045 | mutex_lock(&dev_priv->dpio_lock); | |
8046 | ||
8047 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8048 | SBI_GEN0 : SBI_DBUFF0; | |
8049 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8050 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8051 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8052 | ||
8053 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8054 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8055 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8056 | tmp |= SBI_SSCCTL_PATHALT; | |
8057 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8058 | udelay(32); | |
8059 | } | |
8060 | tmp |= SBI_SSCCTL_DISABLE; | |
8061 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8062 | } | |
8063 | ||
8064 | mutex_unlock(&dev_priv->dpio_lock); | |
8065 | } | |
8066 | ||
bf8fa3d3 PZ |
8067 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8068 | { | |
bf8fa3d3 PZ |
8069 | struct intel_encoder *encoder; |
8070 | bool has_vga = false; | |
8071 | ||
b2784e15 | 8072 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8073 | switch (encoder->type) { |
8074 | case INTEL_OUTPUT_ANALOG: | |
8075 | has_vga = true; | |
8076 | break; | |
6847d71b PZ |
8077 | default: |
8078 | break; | |
bf8fa3d3 PZ |
8079 | } |
8080 | } | |
8081 | ||
47701c3b PZ |
8082 | if (has_vga) |
8083 | lpt_enable_clkout_dp(dev, true, true); | |
8084 | else | |
8085 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8086 | } |
8087 | ||
dde86e2d PZ |
8088 | /* |
8089 | * Initialize reference clocks when the driver loads | |
8090 | */ | |
8091 | void intel_init_pch_refclk(struct drm_device *dev) | |
8092 | { | |
8093 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8094 | ironlake_init_pch_refclk(dev); | |
8095 | else if (HAS_PCH_LPT(dev)) | |
8096 | lpt_init_pch_refclk(dev); | |
8097 | } | |
8098 | ||
55bb9992 | 8099 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8100 | { |
55bb9992 | 8101 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8102 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 ACO |
8103 | struct drm_atomic_state *state = crtc_state->base.state; |
8104 | struct drm_connector_state *connector_state; | |
d9d444cb | 8105 | struct intel_encoder *encoder; |
55bb9992 | 8106 | int num_connectors = 0, i; |
d9d444cb JB |
8107 | bool is_lvds = false; |
8108 | ||
55bb9992 ACO |
8109 | for (i = 0; i < state->num_connector; i++) { |
8110 | if (!state->connectors[i]) | |
d0737e1d ACO |
8111 | continue; |
8112 | ||
55bb9992 ACO |
8113 | connector_state = state->connector_states[i]; |
8114 | if (connector_state->crtc != crtc_state->base.crtc) | |
8115 | continue; | |
8116 | ||
8117 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8118 | ||
d9d444cb JB |
8119 | switch (encoder->type) { |
8120 | case INTEL_OUTPUT_LVDS: | |
8121 | is_lvds = true; | |
8122 | break; | |
6847d71b PZ |
8123 | default: |
8124 | break; | |
d9d444cb JB |
8125 | } |
8126 | num_connectors++; | |
8127 | } | |
8128 | ||
8129 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8130 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8131 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8132 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8133 | } |
8134 | ||
8135 | return 120000; | |
8136 | } | |
8137 | ||
6ff93609 | 8138 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8139 | { |
c8203565 | 8140 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8141 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8142 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8143 | uint32_t val; |
8144 | ||
78114071 | 8145 | val = 0; |
c8203565 | 8146 | |
6e3c9717 | 8147 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8148 | case 18: |
dfd07d72 | 8149 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8150 | break; |
8151 | case 24: | |
dfd07d72 | 8152 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8153 | break; |
8154 | case 30: | |
dfd07d72 | 8155 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8156 | break; |
8157 | case 36: | |
dfd07d72 | 8158 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8159 | break; |
8160 | default: | |
cc769b62 PZ |
8161 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8162 | BUG(); | |
c8203565 PZ |
8163 | } |
8164 | ||
6e3c9717 | 8165 | if (intel_crtc->config->dither) |
c8203565 PZ |
8166 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8167 | ||
6e3c9717 | 8168 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8169 | val |= PIPECONF_INTERLACED_ILK; |
8170 | else | |
8171 | val |= PIPECONF_PROGRESSIVE; | |
8172 | ||
6e3c9717 | 8173 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8174 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8175 | |
c8203565 PZ |
8176 | I915_WRITE(PIPECONF(pipe), val); |
8177 | POSTING_READ(PIPECONF(pipe)); | |
8178 | } | |
8179 | ||
86d3efce VS |
8180 | /* |
8181 | * Set up the pipe CSC unit. | |
8182 | * | |
8183 | * Currently only full range RGB to limited range RGB conversion | |
8184 | * is supported, but eventually this should handle various | |
8185 | * RGB<->YCbCr scenarios as well. | |
8186 | */ | |
50f3b016 | 8187 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8188 | { |
8189 | struct drm_device *dev = crtc->dev; | |
8190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8192 | int pipe = intel_crtc->pipe; | |
8193 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8194 | ||
8195 | /* | |
8196 | * TODO: Check what kind of values actually come out of the pipe | |
8197 | * with these coeff/postoff values and adjust to get the best | |
8198 | * accuracy. Perhaps we even need to take the bpc value into | |
8199 | * consideration. | |
8200 | */ | |
8201 | ||
6e3c9717 | 8202 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8203 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8204 | ||
8205 | /* | |
8206 | * GY/GU and RY/RU should be the other way around according | |
8207 | * to BSpec, but reality doesn't agree. Just set them up in | |
8208 | * a way that results in the correct picture. | |
8209 | */ | |
8210 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8211 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8212 | ||
8213 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8214 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8215 | ||
8216 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8217 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8218 | ||
8219 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8220 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8221 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8222 | ||
8223 | if (INTEL_INFO(dev)->gen > 6) { | |
8224 | uint16_t postoff = 0; | |
8225 | ||
6e3c9717 | 8226 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8227 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8228 | |
8229 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8230 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8231 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8232 | ||
8233 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8234 | } else { | |
8235 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8236 | ||
6e3c9717 | 8237 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8238 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8239 | ||
8240 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8241 | } | |
8242 | } | |
8243 | ||
6ff93609 | 8244 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8245 | { |
756f85cf PZ |
8246 | struct drm_device *dev = crtc->dev; |
8247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8249 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8250 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8251 | uint32_t val; |
8252 | ||
3eff4faa | 8253 | val = 0; |
ee2b0b38 | 8254 | |
6e3c9717 | 8255 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8256 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8257 | ||
6e3c9717 | 8258 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8259 | val |= PIPECONF_INTERLACED_ILK; |
8260 | else | |
8261 | val |= PIPECONF_PROGRESSIVE; | |
8262 | ||
702e7a56 PZ |
8263 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8264 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8265 | |
8266 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8267 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8268 | |
3cdf122c | 8269 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8270 | val = 0; |
8271 | ||
6e3c9717 | 8272 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8273 | case 18: |
8274 | val |= PIPEMISC_DITHER_6_BPC; | |
8275 | break; | |
8276 | case 24: | |
8277 | val |= PIPEMISC_DITHER_8_BPC; | |
8278 | break; | |
8279 | case 30: | |
8280 | val |= PIPEMISC_DITHER_10_BPC; | |
8281 | break; | |
8282 | case 36: | |
8283 | val |= PIPEMISC_DITHER_12_BPC; | |
8284 | break; | |
8285 | default: | |
8286 | /* Case prevented by pipe_config_set_bpp. */ | |
8287 | BUG(); | |
8288 | } | |
8289 | ||
6e3c9717 | 8290 | if (intel_crtc->config->dither) |
756f85cf PZ |
8291 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8292 | ||
8293 | I915_WRITE(PIPEMISC(pipe), val); | |
8294 | } | |
ee2b0b38 PZ |
8295 | } |
8296 | ||
6591c6e4 | 8297 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8298 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8299 | intel_clock_t *clock, |
8300 | bool *has_reduced_clock, | |
8301 | intel_clock_t *reduced_clock) | |
8302 | { | |
8303 | struct drm_device *dev = crtc->dev; | |
8304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8305 | int refclk; |
d4906093 | 8306 | const intel_limit_t *limit; |
a16af721 | 8307 | bool ret, is_lvds = false; |
79e53945 | 8308 | |
a93e255f | 8309 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8310 | |
55bb9992 | 8311 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8312 | |
d4906093 ML |
8313 | /* |
8314 | * Returns a set of divisors for the desired target clock with the given | |
8315 | * refclk, or FALSE. The returned values represent the clock equation: | |
8316 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8317 | */ | |
a93e255f ACO |
8318 | limit = intel_limit(crtc_state, refclk); |
8319 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8320 | crtc_state->port_clock, |
ee9300bb | 8321 | refclk, NULL, clock); |
6591c6e4 PZ |
8322 | if (!ret) |
8323 | return false; | |
cda4b7d3 | 8324 | |
ddc9003c | 8325 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8326 | /* |
8327 | * Ensure we match the reduced clock's P to the target clock. | |
8328 | * If the clocks don't match, we can't switch the display clock | |
8329 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8330 | * downclock feature. | |
8331 | */ | |
ee9300bb | 8332 | *has_reduced_clock = |
a93e255f | 8333 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8334 | dev_priv->lvds_downclock, |
8335 | refclk, clock, | |
8336 | reduced_clock); | |
652c393a | 8337 | } |
61e9653f | 8338 | |
6591c6e4 PZ |
8339 | return true; |
8340 | } | |
8341 | ||
d4b1931c PZ |
8342 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8343 | { | |
8344 | /* | |
8345 | * Account for spread spectrum to avoid | |
8346 | * oversubscribing the link. Max center spread | |
8347 | * is 2.5%; use 5% for safety's sake. | |
8348 | */ | |
8349 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8350 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8351 | } |
8352 | ||
7429e9d4 | 8353 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8354 | { |
7429e9d4 | 8355 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8356 | } |
8357 | ||
de13a2e3 | 8358 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8359 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8360 | u32 *fp, |
9a7c7890 | 8361 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8362 | { |
de13a2e3 | 8363 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8364 | struct drm_device *dev = crtc->dev; |
8365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 ACO |
8366 | struct drm_atomic_state *state = crtc_state->base.state; |
8367 | struct drm_connector_state *connector_state; | |
8368 | struct intel_encoder *encoder; | |
de13a2e3 | 8369 | uint32_t dpll; |
55bb9992 | 8370 | int factor, num_connectors = 0, i; |
09ede541 | 8371 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8372 | |
55bb9992 ACO |
8373 | for (i = 0; i < state->num_connector; i++) { |
8374 | if (!state->connectors[i]) | |
d0737e1d ACO |
8375 | continue; |
8376 | ||
55bb9992 ACO |
8377 | connector_state = state->connector_states[i]; |
8378 | if (connector_state->crtc != crtc_state->base.crtc) | |
8379 | continue; | |
8380 | ||
8381 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8382 | ||
8383 | switch (encoder->type) { | |
79e53945 JB |
8384 | case INTEL_OUTPUT_LVDS: |
8385 | is_lvds = true; | |
8386 | break; | |
8387 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8388 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8389 | is_sdvo = true; |
79e53945 | 8390 | break; |
6847d71b PZ |
8391 | default: |
8392 | break; | |
79e53945 | 8393 | } |
43565a06 | 8394 | |
c751ce4f | 8395 | num_connectors++; |
79e53945 | 8396 | } |
79e53945 | 8397 | |
c1858123 | 8398 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8399 | factor = 21; |
8400 | if (is_lvds) { | |
8401 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8402 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8403 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8404 | factor = 25; |
190f68c5 | 8405 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8406 | factor = 20; |
c1858123 | 8407 | |
190f68c5 | 8408 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8409 | *fp |= FP_CB_TUNE; |
2c07245f | 8410 | |
9a7c7890 DV |
8411 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8412 | *fp2 |= FP_CB_TUNE; | |
8413 | ||
5eddb70b | 8414 | dpll = 0; |
2c07245f | 8415 | |
a07d6787 EA |
8416 | if (is_lvds) |
8417 | dpll |= DPLLB_MODE_LVDS; | |
8418 | else | |
8419 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8420 | |
190f68c5 | 8421 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8422 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8423 | |
8424 | if (is_sdvo) | |
4a33e48d | 8425 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8426 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8427 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8428 | |
a07d6787 | 8429 | /* compute bitmask from p1 value */ |
190f68c5 | 8430 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8431 | /* also FPA1 */ |
190f68c5 | 8432 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8433 | |
190f68c5 | 8434 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8435 | case 5: |
8436 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8437 | break; | |
8438 | case 7: | |
8439 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8440 | break; | |
8441 | case 10: | |
8442 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8443 | break; | |
8444 | case 14: | |
8445 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8446 | break; | |
79e53945 JB |
8447 | } |
8448 | ||
b4c09f3b | 8449 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8450 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8451 | else |
8452 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8453 | ||
959e16d6 | 8454 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8455 | } |
8456 | ||
190f68c5 ACO |
8457 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8458 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8459 | { |
c7653199 | 8460 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8461 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8462 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8463 | bool ok, has_reduced_clock = false; |
8b47047b | 8464 | bool is_lvds = false; |
e2b78267 | 8465 | struct intel_shared_dpll *pll; |
de13a2e3 | 8466 | |
409ee761 | 8467 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8468 | |
5dc5298b PZ |
8469 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8470 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8471 | |
190f68c5 | 8472 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8473 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8474 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8475 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8476 | return -EINVAL; | |
79e53945 | 8477 | } |
f47709a9 | 8478 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8479 | if (!crtc_state->clock_set) { |
8480 | crtc_state->dpll.n = clock.n; | |
8481 | crtc_state->dpll.m1 = clock.m1; | |
8482 | crtc_state->dpll.m2 = clock.m2; | |
8483 | crtc_state->dpll.p1 = clock.p1; | |
8484 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8485 | } |
79e53945 | 8486 | |
5dc5298b | 8487 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8488 | if (crtc_state->has_pch_encoder) { |
8489 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8490 | if (has_reduced_clock) |
7429e9d4 | 8491 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8492 | |
190f68c5 | 8493 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8494 | &fp, &reduced_clock, |
8495 | has_reduced_clock ? &fp2 : NULL); | |
8496 | ||
190f68c5 ACO |
8497 | crtc_state->dpll_hw_state.dpll = dpll; |
8498 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8499 | if (has_reduced_clock) |
190f68c5 | 8500 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8501 | else |
190f68c5 | 8502 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8503 | |
190f68c5 | 8504 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8505 | if (pll == NULL) { |
84f44ce7 | 8506 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8507 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8508 | return -EINVAL; |
8509 | } | |
3fb37703 | 8510 | } |
79e53945 | 8511 | |
ab585dea | 8512 | if (is_lvds && has_reduced_clock) |
c7653199 | 8513 | crtc->lowfreq_avail = true; |
bcd644e0 | 8514 | else |
c7653199 | 8515 | crtc->lowfreq_avail = false; |
e2b78267 | 8516 | |
c8f7a0db | 8517 | return 0; |
79e53945 JB |
8518 | } |
8519 | ||
eb14cb74 VS |
8520 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8521 | struct intel_link_m_n *m_n) | |
8522 | { | |
8523 | struct drm_device *dev = crtc->base.dev; | |
8524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8525 | enum pipe pipe = crtc->pipe; | |
8526 | ||
8527 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8528 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8529 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8530 | & ~TU_SIZE_MASK; | |
8531 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8532 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8533 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8534 | } | |
8535 | ||
8536 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8537 | enum transcoder transcoder, | |
b95af8be VK |
8538 | struct intel_link_m_n *m_n, |
8539 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8540 | { |
8541 | struct drm_device *dev = crtc->base.dev; | |
8542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8543 | enum pipe pipe = crtc->pipe; |
72419203 | 8544 | |
eb14cb74 VS |
8545 | if (INTEL_INFO(dev)->gen >= 5) { |
8546 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8547 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8548 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8549 | & ~TU_SIZE_MASK; | |
8550 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8551 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8552 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8553 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8554 | * gen < 8) and if DRRS is supported (to make sure the | |
8555 | * registers are not unnecessarily read). | |
8556 | */ | |
8557 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8558 | crtc->config->has_drrs) { |
b95af8be VK |
8559 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8560 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8561 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8562 | & ~TU_SIZE_MASK; | |
8563 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8564 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8565 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8566 | } | |
eb14cb74 VS |
8567 | } else { |
8568 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8569 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8570 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8571 | & ~TU_SIZE_MASK; | |
8572 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8573 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8574 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8575 | } | |
8576 | } | |
8577 | ||
8578 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8579 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8580 | { |
681a8504 | 8581 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8582 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8583 | else | |
8584 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8585 | &pipe_config->dp_m_n, |
8586 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8587 | } |
72419203 | 8588 | |
eb14cb74 | 8589 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8590 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8591 | { |
8592 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8593 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8594 | } |
8595 | ||
bd2e244f | 8596 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8597 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8598 | { |
8599 | struct drm_device *dev = crtc->base.dev; | |
8600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8601 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8602 | uint32_t ps_ctrl = 0; | |
8603 | int id = -1; | |
8604 | int i; | |
bd2e244f | 8605 | |
a1b2278e CK |
8606 | /* find scaler attached to this pipe */ |
8607 | for (i = 0; i < crtc->num_scalers; i++) { | |
8608 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8609 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8610 | id = i; | |
8611 | pipe_config->pch_pfit.enabled = true; | |
8612 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8613 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8614 | break; | |
8615 | } | |
8616 | } | |
bd2e244f | 8617 | |
a1b2278e CK |
8618 | scaler_state->scaler_id = id; |
8619 | if (id >= 0) { | |
8620 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8621 | } else { | |
8622 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8623 | } |
8624 | } | |
8625 | ||
5724dbd1 DL |
8626 | static void |
8627 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8628 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8629 | { |
8630 | struct drm_device *dev = crtc->base.dev; | |
8631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8632 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8633 | int pipe = crtc->pipe; |
8634 | int fourcc, pixel_format; | |
6761dd31 | 8635 | unsigned int aligned_height; |
bc8d7dff | 8636 | struct drm_framebuffer *fb; |
1b842c89 | 8637 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8638 | |
d9806c9f | 8639 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8640 | if (!intel_fb) { |
bc8d7dff DL |
8641 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8642 | return; | |
8643 | } | |
8644 | ||
1b842c89 DL |
8645 | fb = &intel_fb->base; |
8646 | ||
bc8d7dff | 8647 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8648 | if (!(val & PLANE_CTL_ENABLE)) |
8649 | goto error; | |
8650 | ||
bc8d7dff DL |
8651 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8652 | fourcc = skl_format_to_fourcc(pixel_format, | |
8653 | val & PLANE_CTL_ORDER_RGBX, | |
8654 | val & PLANE_CTL_ALPHA_MASK); | |
8655 | fb->pixel_format = fourcc; | |
8656 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8657 | ||
40f46283 DL |
8658 | tiling = val & PLANE_CTL_TILED_MASK; |
8659 | switch (tiling) { | |
8660 | case PLANE_CTL_TILED_LINEAR: | |
8661 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8662 | break; | |
8663 | case PLANE_CTL_TILED_X: | |
8664 | plane_config->tiling = I915_TILING_X; | |
8665 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8666 | break; | |
8667 | case PLANE_CTL_TILED_Y: | |
8668 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8669 | break; | |
8670 | case PLANE_CTL_TILED_YF: | |
8671 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8672 | break; | |
8673 | default: | |
8674 | MISSING_CASE(tiling); | |
8675 | goto error; | |
8676 | } | |
8677 | ||
bc8d7dff DL |
8678 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8679 | plane_config->base = base; | |
8680 | ||
8681 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8682 | ||
8683 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8684 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8685 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8686 | ||
8687 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8688 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8689 | fb->pixel_format); | |
bc8d7dff DL |
8690 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8691 | ||
8692 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8693 | fb->pixel_format, |
8694 | fb->modifier[0]); | |
bc8d7dff | 8695 | |
f37b5c2b | 8696 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8697 | |
8698 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8699 | pipe_name(pipe), fb->width, fb->height, | |
8700 | fb->bits_per_pixel, base, fb->pitches[0], | |
8701 | plane_config->size); | |
8702 | ||
2d14030b | 8703 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8704 | return; |
8705 | ||
8706 | error: | |
8707 | kfree(fb); | |
8708 | } | |
8709 | ||
2fa2fe9a | 8710 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8711 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8712 | { |
8713 | struct drm_device *dev = crtc->base.dev; | |
8714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8715 | uint32_t tmp; | |
8716 | ||
8717 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8718 | ||
8719 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8720 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8721 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8722 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8723 | |
8724 | /* We currently do not free assignements of panel fitters on | |
8725 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8726 | * differentiates them) so just WARN about this case for now. */ | |
8727 | if (IS_GEN7(dev)) { | |
8728 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8729 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8730 | } | |
2fa2fe9a | 8731 | } |
79e53945 JB |
8732 | } |
8733 | ||
5724dbd1 DL |
8734 | static void |
8735 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8736 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8737 | { |
8738 | struct drm_device *dev = crtc->base.dev; | |
8739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8740 | u32 val, base, offset; | |
aeee5a49 | 8741 | int pipe = crtc->pipe; |
4c6baa59 | 8742 | int fourcc, pixel_format; |
6761dd31 | 8743 | unsigned int aligned_height; |
b113d5ee | 8744 | struct drm_framebuffer *fb; |
1b842c89 | 8745 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8746 | |
42a7b088 DL |
8747 | val = I915_READ(DSPCNTR(pipe)); |
8748 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8749 | return; | |
8750 | ||
d9806c9f | 8751 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8752 | if (!intel_fb) { |
4c6baa59 JB |
8753 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8754 | return; | |
8755 | } | |
8756 | ||
1b842c89 DL |
8757 | fb = &intel_fb->base; |
8758 | ||
18c5247e DV |
8759 | if (INTEL_INFO(dev)->gen >= 4) { |
8760 | if (val & DISPPLANE_TILED) { | |
49af449b | 8761 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8762 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8763 | } | |
8764 | } | |
4c6baa59 JB |
8765 | |
8766 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8767 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8768 | fb->pixel_format = fourcc; |
8769 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8770 | |
aeee5a49 | 8771 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8772 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8773 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8774 | } else { |
49af449b | 8775 | if (plane_config->tiling) |
aeee5a49 | 8776 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8777 | else |
aeee5a49 | 8778 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8779 | } |
8780 | plane_config->base = base; | |
8781 | ||
8782 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8783 | fb->width = ((val >> 16) & 0xfff) + 1; |
8784 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8785 | |
8786 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8787 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8788 | |
b113d5ee | 8789 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8790 | fb->pixel_format, |
8791 | fb->modifier[0]); | |
4c6baa59 | 8792 | |
f37b5c2b | 8793 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8794 | |
2844a921 DL |
8795 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8796 | pipe_name(pipe), fb->width, fb->height, | |
8797 | fb->bits_per_pixel, base, fb->pitches[0], | |
8798 | plane_config->size); | |
b113d5ee | 8799 | |
2d14030b | 8800 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8801 | } |
8802 | ||
0e8ffe1b | 8803 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8804 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8805 | { |
8806 | struct drm_device *dev = crtc->base.dev; | |
8807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8808 | uint32_t tmp; | |
8809 | ||
f458ebbc DV |
8810 | if (!intel_display_power_is_enabled(dev_priv, |
8811 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8812 | return false; |
8813 | ||
e143a21c | 8814 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8815 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8816 | |
0e8ffe1b DV |
8817 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8818 | if (!(tmp & PIPECONF_ENABLE)) | |
8819 | return false; | |
8820 | ||
42571aef VS |
8821 | switch (tmp & PIPECONF_BPC_MASK) { |
8822 | case PIPECONF_6BPC: | |
8823 | pipe_config->pipe_bpp = 18; | |
8824 | break; | |
8825 | case PIPECONF_8BPC: | |
8826 | pipe_config->pipe_bpp = 24; | |
8827 | break; | |
8828 | case PIPECONF_10BPC: | |
8829 | pipe_config->pipe_bpp = 30; | |
8830 | break; | |
8831 | case PIPECONF_12BPC: | |
8832 | pipe_config->pipe_bpp = 36; | |
8833 | break; | |
8834 | default: | |
8835 | break; | |
8836 | } | |
8837 | ||
b5a9fa09 DV |
8838 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8839 | pipe_config->limited_color_range = true; | |
8840 | ||
ab9412ba | 8841 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8842 | struct intel_shared_dpll *pll; |
8843 | ||
88adfff1 DV |
8844 | pipe_config->has_pch_encoder = true; |
8845 | ||
627eb5a3 DV |
8846 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8847 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8848 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8849 | |
8850 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8851 | |
c0d43d62 | 8852 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8853 | pipe_config->shared_dpll = |
8854 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8855 | } else { |
8856 | tmp = I915_READ(PCH_DPLL_SEL); | |
8857 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8858 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8859 | else | |
8860 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8861 | } | |
66e985c0 DV |
8862 | |
8863 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8864 | ||
8865 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8866 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8867 | |
8868 | tmp = pipe_config->dpll_hw_state.dpll; | |
8869 | pipe_config->pixel_multiplier = | |
8870 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8871 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8872 | |
8873 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8874 | } else { |
8875 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8876 | } |
8877 | ||
1bd1bd80 DV |
8878 | intel_get_pipe_timings(crtc, pipe_config); |
8879 | ||
2fa2fe9a DV |
8880 | ironlake_get_pfit_config(crtc, pipe_config); |
8881 | ||
0e8ffe1b DV |
8882 | return true; |
8883 | } | |
8884 | ||
be256dc7 PZ |
8885 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8886 | { | |
8887 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8888 | struct intel_crtc *crtc; |
be256dc7 | 8889 | |
d3fcc808 | 8890 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8891 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8892 | pipe_name(crtc->pipe)); |
8893 | ||
e2c719b7 RC |
8894 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8895 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8896 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8897 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8898 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8899 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8900 | "CPU PWM1 enabled\n"); |
c5107b87 | 8901 | if (IS_HASWELL(dev)) |
e2c719b7 | 8902 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8903 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8904 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8905 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8906 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8907 | "Utility pin enabled\n"); |
e2c719b7 | 8908 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8909 | |
9926ada1 PZ |
8910 | /* |
8911 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8912 | * interrupts remain enabled. We used to check for that, but since it's | |
8913 | * gen-specific and since we only disable LCPLL after we fully disable | |
8914 | * the interrupts, the check below should be enough. | |
8915 | */ | |
e2c719b7 | 8916 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8917 | } |
8918 | ||
9ccd5aeb PZ |
8919 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8920 | { | |
8921 | struct drm_device *dev = dev_priv->dev; | |
8922 | ||
8923 | if (IS_HASWELL(dev)) | |
8924 | return I915_READ(D_COMP_HSW); | |
8925 | else | |
8926 | return I915_READ(D_COMP_BDW); | |
8927 | } | |
8928 | ||
3c4c9b81 PZ |
8929 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8930 | { | |
8931 | struct drm_device *dev = dev_priv->dev; | |
8932 | ||
8933 | if (IS_HASWELL(dev)) { | |
8934 | mutex_lock(&dev_priv->rps.hw_lock); | |
8935 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8936 | val)) | |
f475dadf | 8937 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8938 | mutex_unlock(&dev_priv->rps.hw_lock); |
8939 | } else { | |
9ccd5aeb PZ |
8940 | I915_WRITE(D_COMP_BDW, val); |
8941 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8942 | } |
be256dc7 PZ |
8943 | } |
8944 | ||
8945 | /* | |
8946 | * This function implements pieces of two sequences from BSpec: | |
8947 | * - Sequence for display software to disable LCPLL | |
8948 | * - Sequence for display software to allow package C8+ | |
8949 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8950 | * register. Callers should take care of disabling all the display engine | |
8951 | * functions, doing the mode unset, fixing interrupts, etc. | |
8952 | */ | |
6ff58d53 PZ |
8953 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8954 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8955 | { |
8956 | uint32_t val; | |
8957 | ||
8958 | assert_can_disable_lcpll(dev_priv); | |
8959 | ||
8960 | val = I915_READ(LCPLL_CTL); | |
8961 | ||
8962 | if (switch_to_fclk) { | |
8963 | val |= LCPLL_CD_SOURCE_FCLK; | |
8964 | I915_WRITE(LCPLL_CTL, val); | |
8965 | ||
8966 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8967 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8968 | DRM_ERROR("Switching to FCLK failed\n"); | |
8969 | ||
8970 | val = I915_READ(LCPLL_CTL); | |
8971 | } | |
8972 | ||
8973 | val |= LCPLL_PLL_DISABLE; | |
8974 | I915_WRITE(LCPLL_CTL, val); | |
8975 | POSTING_READ(LCPLL_CTL); | |
8976 | ||
8977 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8978 | DRM_ERROR("LCPLL still locked\n"); | |
8979 | ||
9ccd5aeb | 8980 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8981 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8982 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8983 | ndelay(100); |
8984 | ||
9ccd5aeb PZ |
8985 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8986 | 1)) | |
be256dc7 PZ |
8987 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8988 | ||
8989 | if (allow_power_down) { | |
8990 | val = I915_READ(LCPLL_CTL); | |
8991 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8992 | I915_WRITE(LCPLL_CTL, val); | |
8993 | POSTING_READ(LCPLL_CTL); | |
8994 | } | |
8995 | } | |
8996 | ||
8997 | /* | |
8998 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8999 | * source. | |
9000 | */ | |
6ff58d53 | 9001 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9002 | { |
9003 | uint32_t val; | |
9004 | ||
9005 | val = I915_READ(LCPLL_CTL); | |
9006 | ||
9007 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9008 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9009 | return; | |
9010 | ||
a8a8bd54 PZ |
9011 | /* |
9012 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9013 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9014 | */ |
59bad947 | 9015 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9016 | |
be256dc7 PZ |
9017 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9018 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9019 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9020 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9021 | } |
9022 | ||
9ccd5aeb | 9023 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9024 | val |= D_COMP_COMP_FORCE; |
9025 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9026 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9027 | |
9028 | val = I915_READ(LCPLL_CTL); | |
9029 | val &= ~LCPLL_PLL_DISABLE; | |
9030 | I915_WRITE(LCPLL_CTL, val); | |
9031 | ||
9032 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9033 | DRM_ERROR("LCPLL not locked yet\n"); | |
9034 | ||
9035 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9036 | val = I915_READ(LCPLL_CTL); | |
9037 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9038 | I915_WRITE(LCPLL_CTL, val); | |
9039 | ||
9040 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9041 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9042 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9043 | } | |
215733fa | 9044 | |
59bad947 | 9045 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9046 | } |
9047 | ||
765dab67 PZ |
9048 | /* |
9049 | * Package states C8 and deeper are really deep PC states that can only be | |
9050 | * reached when all the devices on the system allow it, so even if the graphics | |
9051 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9052 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9053 | * | |
9054 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9055 | * well is disabled and most interrupts are disabled, and these are also | |
9056 | * requirements for runtime PM. When these conditions are met, we manually do | |
9057 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9058 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9059 | * hang the machine. | |
9060 | * | |
9061 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9062 | * the state of some registers, so when we come back from PC8+ we need to | |
9063 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9064 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9065 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9066 | * because of the runtime PM support). | |
9067 | * | |
9068 | * For more, read "Display Sequences for Package C8" on the hardware | |
9069 | * documentation. | |
9070 | */ | |
a14cb6fc | 9071 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9072 | { |
c67a470b PZ |
9073 | struct drm_device *dev = dev_priv->dev; |
9074 | uint32_t val; | |
9075 | ||
c67a470b PZ |
9076 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9077 | ||
c67a470b PZ |
9078 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9079 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9080 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9081 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9082 | } | |
9083 | ||
9084 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9085 | hsw_disable_lcpll(dev_priv, true, true); |
9086 | } | |
9087 | ||
a14cb6fc | 9088 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9089 | { |
9090 | struct drm_device *dev = dev_priv->dev; | |
9091 | uint32_t val; | |
9092 | ||
c67a470b PZ |
9093 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9094 | ||
9095 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9096 | lpt_init_pch_refclk(dev); |
9097 | ||
9098 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9099 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9100 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9101 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9102 | } | |
9103 | ||
9104 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9105 | } |
9106 | ||
f8437dd1 VK |
9107 | static void broxton_modeset_global_resources(struct drm_atomic_state *state) |
9108 | { | |
9109 | struct drm_device *dev = state->dev; | |
9110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9111 | int max_pixclk = intel_mode_max_pixclk(state); | |
9112 | int req_cdclk; | |
9113 | ||
9114 | /* see the comment in valleyview_modeset_global_resources */ | |
9115 | if (WARN_ON(max_pixclk < 0)) | |
9116 | return; | |
9117 | ||
9118 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9119 | ||
9120 | if (req_cdclk != dev_priv->cdclk_freq) | |
9121 | broxton_set_cdclk(dev, req_cdclk); | |
9122 | } | |
9123 | ||
190f68c5 ACO |
9124 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9125 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9126 | { |
190f68c5 | 9127 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9128 | return -EINVAL; |
716c2e55 | 9129 | |
c7653199 | 9130 | crtc->lowfreq_avail = false; |
644cef34 | 9131 | |
c8f7a0db | 9132 | return 0; |
79e53945 JB |
9133 | } |
9134 | ||
3760b59c S |
9135 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9136 | enum port port, | |
9137 | struct intel_crtc_state *pipe_config) | |
9138 | { | |
9139 | switch (port) { | |
9140 | case PORT_A: | |
9141 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9142 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9143 | break; | |
9144 | case PORT_B: | |
9145 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9146 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9147 | break; | |
9148 | case PORT_C: | |
9149 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9150 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9151 | break; | |
9152 | default: | |
9153 | DRM_ERROR("Incorrect port type\n"); | |
9154 | } | |
9155 | } | |
9156 | ||
96b7dfb7 S |
9157 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9158 | enum port port, | |
5cec258b | 9159 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9160 | { |
3148ade7 | 9161 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9162 | |
9163 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9164 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9165 | ||
9166 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9167 | case SKL_DPLL0: |
9168 | /* | |
9169 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9170 | * of the shared DPLL framework and thus needs to be read out | |
9171 | * separately | |
9172 | */ | |
9173 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9174 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9175 | break; | |
96b7dfb7 S |
9176 | case SKL_DPLL1: |
9177 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9178 | break; | |
9179 | case SKL_DPLL2: | |
9180 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9181 | break; | |
9182 | case SKL_DPLL3: | |
9183 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9184 | break; | |
96b7dfb7 S |
9185 | } |
9186 | } | |
9187 | ||
7d2c8175 DL |
9188 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9189 | enum port port, | |
5cec258b | 9190 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9191 | { |
9192 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9193 | ||
9194 | switch (pipe_config->ddi_pll_sel) { | |
9195 | case PORT_CLK_SEL_WRPLL1: | |
9196 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9197 | break; | |
9198 | case PORT_CLK_SEL_WRPLL2: | |
9199 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9200 | break; | |
9201 | } | |
9202 | } | |
9203 | ||
26804afd | 9204 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9205 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9206 | { |
9207 | struct drm_device *dev = crtc->base.dev; | |
9208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9209 | struct intel_shared_dpll *pll; |
26804afd DV |
9210 | enum port port; |
9211 | uint32_t tmp; | |
9212 | ||
9213 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9214 | ||
9215 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9216 | ||
96b7dfb7 S |
9217 | if (IS_SKYLAKE(dev)) |
9218 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9219 | else if (IS_BROXTON(dev)) |
9220 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9221 | else |
9222 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9223 | |
d452c5b6 DV |
9224 | if (pipe_config->shared_dpll >= 0) { |
9225 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9226 | ||
9227 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9228 | &pipe_config->dpll_hw_state)); | |
9229 | } | |
9230 | ||
26804afd DV |
9231 | /* |
9232 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9233 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9234 | * the PCH transcoder is on. | |
9235 | */ | |
ca370455 DL |
9236 | if (INTEL_INFO(dev)->gen < 9 && |
9237 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9238 | pipe_config->has_pch_encoder = true; |
9239 | ||
9240 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9241 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9242 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9243 | ||
9244 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9245 | } | |
9246 | } | |
9247 | ||
0e8ffe1b | 9248 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9249 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9250 | { |
9251 | struct drm_device *dev = crtc->base.dev; | |
9252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9253 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9254 | uint32_t tmp; |
9255 | ||
f458ebbc | 9256 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9257 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9258 | return false; | |
9259 | ||
e143a21c | 9260 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9261 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9262 | ||
eccb140b DV |
9263 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9264 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9265 | enum pipe trans_edp_pipe; | |
9266 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9267 | default: | |
9268 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9269 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9270 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9271 | trans_edp_pipe = PIPE_A; | |
9272 | break; | |
9273 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9274 | trans_edp_pipe = PIPE_B; | |
9275 | break; | |
9276 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9277 | trans_edp_pipe = PIPE_C; | |
9278 | break; | |
9279 | } | |
9280 | ||
9281 | if (trans_edp_pipe == crtc->pipe) | |
9282 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9283 | } | |
9284 | ||
f458ebbc | 9285 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9286 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9287 | return false; |
9288 | ||
eccb140b | 9289 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9290 | if (!(tmp & PIPECONF_ENABLE)) |
9291 | return false; | |
9292 | ||
26804afd | 9293 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9294 | |
1bd1bd80 DV |
9295 | intel_get_pipe_timings(crtc, pipe_config); |
9296 | ||
a1b2278e CK |
9297 | if (INTEL_INFO(dev)->gen >= 9) { |
9298 | skl_init_scalers(dev, crtc, pipe_config); | |
9299 | } | |
9300 | ||
2fa2fe9a | 9301 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f | 9302 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9303 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9304 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9305 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9306 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9307 | else |
9308 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
9309 | ||
a1b2278e CK |
9310 | } else { |
9311 | pipe_config->scaler_state.scaler_id = -1; | |
9312 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f | 9313 | } |
88adfff1 | 9314 | |
e59150dc JB |
9315 | if (IS_HASWELL(dev)) |
9316 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9317 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9318 | |
ebb69c95 CT |
9319 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9320 | pipe_config->pixel_multiplier = | |
9321 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9322 | } else { | |
9323 | pipe_config->pixel_multiplier = 1; | |
9324 | } | |
6c49f241 | 9325 | |
0e8ffe1b DV |
9326 | return true; |
9327 | } | |
9328 | ||
560b85bb CW |
9329 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9330 | { | |
9331 | struct drm_device *dev = crtc->dev; | |
9332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9333 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9334 | uint32_t cntl = 0, size = 0; |
560b85bb | 9335 | |
dc41c154 | 9336 | if (base) { |
3dd512fb MR |
9337 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9338 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9339 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9340 | ||
9341 | switch (stride) { | |
9342 | default: | |
9343 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9344 | width, stride); | |
9345 | stride = 256; | |
9346 | /* fallthrough */ | |
9347 | case 256: | |
9348 | case 512: | |
9349 | case 1024: | |
9350 | case 2048: | |
9351 | break; | |
4b0e333e CW |
9352 | } |
9353 | ||
dc41c154 VS |
9354 | cntl |= CURSOR_ENABLE | |
9355 | CURSOR_GAMMA_ENABLE | | |
9356 | CURSOR_FORMAT_ARGB | | |
9357 | CURSOR_STRIDE(stride); | |
9358 | ||
9359 | size = (height << 12) | width; | |
4b0e333e | 9360 | } |
560b85bb | 9361 | |
dc41c154 VS |
9362 | if (intel_crtc->cursor_cntl != 0 && |
9363 | (intel_crtc->cursor_base != base || | |
9364 | intel_crtc->cursor_size != size || | |
9365 | intel_crtc->cursor_cntl != cntl)) { | |
9366 | /* On these chipsets we can only modify the base/size/stride | |
9367 | * whilst the cursor is disabled. | |
9368 | */ | |
9369 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9370 | POSTING_READ(_CURACNTR); |
dc41c154 | 9371 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9372 | } |
560b85bb | 9373 | |
99d1f387 | 9374 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9375 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9376 | intel_crtc->cursor_base = base; |
9377 | } | |
4726e0b0 | 9378 | |
dc41c154 VS |
9379 | if (intel_crtc->cursor_size != size) { |
9380 | I915_WRITE(CURSIZE, size); | |
9381 | intel_crtc->cursor_size = size; | |
4b0e333e | 9382 | } |
560b85bb | 9383 | |
4b0e333e | 9384 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9385 | I915_WRITE(_CURACNTR, cntl); |
9386 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9387 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9388 | } |
560b85bb CW |
9389 | } |
9390 | ||
560b85bb | 9391 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9392 | { |
9393 | struct drm_device *dev = crtc->dev; | |
9394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9396 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9397 | uint32_t cntl; |
9398 | ||
9399 | cntl = 0; | |
9400 | if (base) { | |
9401 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9402 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9403 | case 64: |
9404 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9405 | break; | |
9406 | case 128: | |
9407 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9408 | break; | |
9409 | case 256: | |
9410 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9411 | break; | |
9412 | default: | |
3dd512fb | 9413 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9414 | return; |
65a21cd6 | 9415 | } |
4b0e333e | 9416 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9417 | |
9418 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9419 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9420 | } |
65a21cd6 | 9421 | |
8e7d688b | 9422 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9423 | cntl |= CURSOR_ROTATE_180; |
9424 | ||
4b0e333e CW |
9425 | if (intel_crtc->cursor_cntl != cntl) { |
9426 | I915_WRITE(CURCNTR(pipe), cntl); | |
9427 | POSTING_READ(CURCNTR(pipe)); | |
9428 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9429 | } |
4b0e333e | 9430 | |
65a21cd6 | 9431 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9432 | I915_WRITE(CURBASE(pipe), base); |
9433 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9434 | |
9435 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9436 | } |
9437 | ||
cda4b7d3 | 9438 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9439 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9440 | bool on) | |
cda4b7d3 CW |
9441 | { |
9442 | struct drm_device *dev = crtc->dev; | |
9443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9445 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9446 | int x = crtc->cursor_x; |
9447 | int y = crtc->cursor_y; | |
d6e4db15 | 9448 | u32 base = 0, pos = 0; |
cda4b7d3 | 9449 | |
d6e4db15 | 9450 | if (on) |
cda4b7d3 | 9451 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9452 | |
6e3c9717 | 9453 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9454 | base = 0; |
9455 | ||
6e3c9717 | 9456 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9457 | base = 0; |
9458 | ||
9459 | if (x < 0) { | |
3dd512fb | 9460 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9461 | base = 0; |
9462 | ||
9463 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9464 | x = -x; | |
9465 | } | |
9466 | pos |= x << CURSOR_X_SHIFT; | |
9467 | ||
9468 | if (y < 0) { | |
3dd512fb | 9469 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9470 | base = 0; |
9471 | ||
9472 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9473 | y = -y; | |
9474 | } | |
9475 | pos |= y << CURSOR_Y_SHIFT; | |
9476 | ||
4b0e333e | 9477 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9478 | return; |
9479 | ||
5efb3e28 VS |
9480 | I915_WRITE(CURPOS(pipe), pos); |
9481 | ||
4398ad45 VS |
9482 | /* ILK+ do this automagically */ |
9483 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9484 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9485 | base += (intel_crtc->base.cursor->state->crtc_h * |
9486 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9487 | } |
9488 | ||
8ac54669 | 9489 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9490 | i845_update_cursor(crtc, base); |
9491 | else | |
9492 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9493 | } |
9494 | ||
dc41c154 VS |
9495 | static bool cursor_size_ok(struct drm_device *dev, |
9496 | uint32_t width, uint32_t height) | |
9497 | { | |
9498 | if (width == 0 || height == 0) | |
9499 | return false; | |
9500 | ||
9501 | /* | |
9502 | * 845g/865g are special in that they are only limited by | |
9503 | * the width of their cursors, the height is arbitrary up to | |
9504 | * the precision of the register. Everything else requires | |
9505 | * square cursors, limited to a few power-of-two sizes. | |
9506 | */ | |
9507 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9508 | if ((width & 63) != 0) | |
9509 | return false; | |
9510 | ||
9511 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9512 | return false; | |
9513 | ||
9514 | if (height > 1023) | |
9515 | return false; | |
9516 | } else { | |
9517 | switch (width | height) { | |
9518 | case 256: | |
9519 | case 128: | |
9520 | if (IS_GEN2(dev)) | |
9521 | return false; | |
9522 | case 64: | |
9523 | break; | |
9524 | default: | |
9525 | return false; | |
9526 | } | |
9527 | } | |
9528 | ||
9529 | return true; | |
9530 | } | |
9531 | ||
79e53945 | 9532 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9533 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9534 | { |
7203425a | 9535 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9536 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9537 | |
7203425a | 9538 | for (i = start; i < end; i++) { |
79e53945 JB |
9539 | intel_crtc->lut_r[i] = red[i] >> 8; |
9540 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9541 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9542 | } | |
9543 | ||
9544 | intel_crtc_load_lut(crtc); | |
9545 | } | |
9546 | ||
79e53945 JB |
9547 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9548 | static struct drm_display_mode load_detect_mode = { | |
9549 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9550 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9551 | }; | |
9552 | ||
a8bb6818 DV |
9553 | struct drm_framebuffer * |
9554 | __intel_framebuffer_create(struct drm_device *dev, | |
9555 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9556 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9557 | { |
9558 | struct intel_framebuffer *intel_fb; | |
9559 | int ret; | |
9560 | ||
9561 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9562 | if (!intel_fb) { | |
6ccb81f2 | 9563 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9564 | return ERR_PTR(-ENOMEM); |
9565 | } | |
9566 | ||
9567 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9568 | if (ret) |
9569 | goto err; | |
d2dff872 CW |
9570 | |
9571 | return &intel_fb->base; | |
dd4916c5 | 9572 | err: |
6ccb81f2 | 9573 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9574 | kfree(intel_fb); |
9575 | ||
9576 | return ERR_PTR(ret); | |
d2dff872 CW |
9577 | } |
9578 | ||
b5ea642a | 9579 | static struct drm_framebuffer * |
a8bb6818 DV |
9580 | intel_framebuffer_create(struct drm_device *dev, |
9581 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9582 | struct drm_i915_gem_object *obj) | |
9583 | { | |
9584 | struct drm_framebuffer *fb; | |
9585 | int ret; | |
9586 | ||
9587 | ret = i915_mutex_lock_interruptible(dev); | |
9588 | if (ret) | |
9589 | return ERR_PTR(ret); | |
9590 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9591 | mutex_unlock(&dev->struct_mutex); | |
9592 | ||
9593 | return fb; | |
9594 | } | |
9595 | ||
d2dff872 CW |
9596 | static u32 |
9597 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9598 | { | |
9599 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9600 | return ALIGN(pitch, 64); | |
9601 | } | |
9602 | ||
9603 | static u32 | |
9604 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9605 | { | |
9606 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9607 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9608 | } |
9609 | ||
9610 | static struct drm_framebuffer * | |
9611 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9612 | struct drm_display_mode *mode, | |
9613 | int depth, int bpp) | |
9614 | { | |
9615 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9616 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9617 | |
9618 | obj = i915_gem_alloc_object(dev, | |
9619 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9620 | if (obj == NULL) | |
9621 | return ERR_PTR(-ENOMEM); | |
9622 | ||
9623 | mode_cmd.width = mode->hdisplay; | |
9624 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9625 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9626 | bpp); | |
5ca0c34a | 9627 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9628 | |
9629 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9630 | } | |
9631 | ||
9632 | static struct drm_framebuffer * | |
9633 | mode_fits_in_fbdev(struct drm_device *dev, | |
9634 | struct drm_display_mode *mode) | |
9635 | { | |
4520f53a | 9636 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9637 | struct drm_i915_private *dev_priv = dev->dev_private; |
9638 | struct drm_i915_gem_object *obj; | |
9639 | struct drm_framebuffer *fb; | |
9640 | ||
4c0e5528 | 9641 | if (!dev_priv->fbdev) |
d2dff872 CW |
9642 | return NULL; |
9643 | ||
4c0e5528 | 9644 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9645 | return NULL; |
9646 | ||
4c0e5528 DV |
9647 | obj = dev_priv->fbdev->fb->obj; |
9648 | BUG_ON(!obj); | |
9649 | ||
8bcd4553 | 9650 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9651 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9652 | fb->bits_per_pixel)) | |
d2dff872 CW |
9653 | return NULL; |
9654 | ||
01f2c773 | 9655 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9656 | return NULL; |
9657 | ||
9658 | return fb; | |
4520f53a DV |
9659 | #else |
9660 | return NULL; | |
9661 | #endif | |
d2dff872 CW |
9662 | } |
9663 | ||
d2434ab7 | 9664 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9665 | struct drm_display_mode *mode, |
51fd371b RC |
9666 | struct intel_load_detect_pipe *old, |
9667 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9668 | { |
9669 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9670 | struct intel_encoder *intel_encoder = |
9671 | intel_attached_encoder(connector); | |
79e53945 | 9672 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9673 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9674 | struct drm_crtc *crtc = NULL; |
9675 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9676 | struct drm_framebuffer *fb; |
51fd371b | 9677 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9678 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9679 | struct drm_connector_state *connector_state; |
51fd371b | 9680 | int ret, i = -1; |
79e53945 | 9681 | |
d2dff872 | 9682 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9683 | connector->base.id, connector->name, |
8e329a03 | 9684 | encoder->base.id, encoder->name); |
d2dff872 | 9685 | |
51fd371b RC |
9686 | retry: |
9687 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9688 | if (ret) | |
9689 | goto fail_unlock; | |
6e9f798d | 9690 | |
79e53945 JB |
9691 | /* |
9692 | * Algorithm gets a little messy: | |
7a5e4805 | 9693 | * |
79e53945 JB |
9694 | * - if the connector already has an assigned crtc, use it (but make |
9695 | * sure it's on first) | |
7a5e4805 | 9696 | * |
79e53945 JB |
9697 | * - try to find the first unused crtc that can drive this connector, |
9698 | * and use that if we find one | |
79e53945 JB |
9699 | */ |
9700 | ||
9701 | /* See if we already have a CRTC for this connector */ | |
9702 | if (encoder->crtc) { | |
9703 | crtc = encoder->crtc; | |
8261b191 | 9704 | |
51fd371b | 9705 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9706 | if (ret) |
9707 | goto fail_unlock; | |
9708 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9709 | if (ret) |
9710 | goto fail_unlock; | |
7b24056b | 9711 | |
24218aac | 9712 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9713 | old->load_detect_temp = false; |
9714 | ||
9715 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9716 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9717 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9718 | |
7173188d | 9719 | return true; |
79e53945 JB |
9720 | } |
9721 | ||
9722 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9723 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9724 | i++; |
9725 | if (!(encoder->possible_crtcs & (1 << i))) | |
9726 | continue; | |
83d65738 | 9727 | if (possible_crtc->state->enable) |
a459249c VS |
9728 | continue; |
9729 | /* This can occur when applying the pipe A quirk on resume. */ | |
9730 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9731 | continue; | |
9732 | ||
9733 | crtc = possible_crtc; | |
9734 | break; | |
79e53945 JB |
9735 | } |
9736 | ||
9737 | /* | |
9738 | * If we didn't find an unused CRTC, don't use any. | |
9739 | */ | |
9740 | if (!crtc) { | |
7173188d | 9741 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9742 | goto fail_unlock; |
79e53945 JB |
9743 | } |
9744 | ||
51fd371b RC |
9745 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9746 | if (ret) | |
4d02e2de DV |
9747 | goto fail_unlock; |
9748 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9749 | if (ret) | |
51fd371b | 9750 | goto fail_unlock; |
fc303101 DV |
9751 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9752 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9753 | |
9754 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9755 | intel_crtc->new_enabled = true; |
24218aac | 9756 | old->dpms_mode = connector->dpms; |
8261b191 | 9757 | old->load_detect_temp = true; |
d2dff872 | 9758 | old->release_fb = NULL; |
79e53945 | 9759 | |
83a57153 ACO |
9760 | state = drm_atomic_state_alloc(dev); |
9761 | if (!state) | |
9762 | return false; | |
9763 | ||
9764 | state->acquire_ctx = ctx; | |
9765 | ||
944b0c76 ACO |
9766 | connector_state = drm_atomic_get_connector_state(state, connector); |
9767 | if (IS_ERR(connector_state)) { | |
9768 | ret = PTR_ERR(connector_state); | |
9769 | goto fail; | |
9770 | } | |
9771 | ||
9772 | connector_state->crtc = crtc; | |
9773 | connector_state->best_encoder = &intel_encoder->base; | |
9774 | ||
6492711d CW |
9775 | if (!mode) |
9776 | mode = &load_detect_mode; | |
79e53945 | 9777 | |
d2dff872 CW |
9778 | /* We need a framebuffer large enough to accommodate all accesses |
9779 | * that the plane may generate whilst we perform load detection. | |
9780 | * We can not rely on the fbcon either being present (we get called | |
9781 | * during its initialisation to detect all boot displays, or it may | |
9782 | * not even exist) or that it is large enough to satisfy the | |
9783 | * requested mode. | |
9784 | */ | |
94352cf9 DV |
9785 | fb = mode_fits_in_fbdev(dev, mode); |
9786 | if (fb == NULL) { | |
d2dff872 | 9787 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9788 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9789 | old->release_fb = fb; | |
d2dff872 CW |
9790 | } else |
9791 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9792 | if (IS_ERR(fb)) { |
d2dff872 | 9793 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9794 | goto fail; |
79e53945 | 9795 | } |
79e53945 | 9796 | |
83a57153 | 9797 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9798 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9799 | if (old->release_fb) |
9800 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9801 | goto fail; |
79e53945 | 9802 | } |
9128b040 | 9803 | crtc->primary->crtc = crtc; |
7173188d | 9804 | |
79e53945 | 9805 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9806 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9807 | return true; |
412b61d8 VS |
9808 | |
9809 | fail: | |
83d65738 | 9810 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9811 | fail_unlock: |
83a57153 ACO |
9812 | if (state) { |
9813 | drm_atomic_state_free(state); | |
9814 | state = NULL; | |
9815 | } | |
9816 | ||
51fd371b RC |
9817 | if (ret == -EDEADLK) { |
9818 | drm_modeset_backoff(ctx); | |
9819 | goto retry; | |
9820 | } | |
9821 | ||
412b61d8 | 9822 | return false; |
79e53945 JB |
9823 | } |
9824 | ||
d2434ab7 | 9825 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9826 | struct intel_load_detect_pipe *old, |
9827 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9828 | { |
83a57153 | 9829 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9830 | struct intel_encoder *intel_encoder = |
9831 | intel_attached_encoder(connector); | |
4ef69c7a | 9832 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9833 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9835 | struct drm_atomic_state *state; |
944b0c76 | 9836 | struct drm_connector_state *connector_state; |
79e53945 | 9837 | |
d2dff872 | 9838 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9839 | connector->base.id, connector->name, |
8e329a03 | 9840 | encoder->base.id, encoder->name); |
d2dff872 | 9841 | |
8261b191 | 9842 | if (old->load_detect_temp) { |
83a57153 | 9843 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9844 | if (!state) |
9845 | goto fail; | |
83a57153 ACO |
9846 | |
9847 | state->acquire_ctx = ctx; | |
9848 | ||
944b0c76 ACO |
9849 | connector_state = drm_atomic_get_connector_state(state, connector); |
9850 | if (IS_ERR(connector_state)) | |
9851 | goto fail; | |
9852 | ||
fc303101 DV |
9853 | to_intel_connector(connector)->new_encoder = NULL; |
9854 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9855 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9856 | |
9857 | connector_state->best_encoder = NULL; | |
9858 | connector_state->crtc = NULL; | |
9859 | ||
83a57153 ACO |
9860 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9861 | ||
9862 | drm_atomic_state_free(state); | |
d2dff872 | 9863 | |
36206361 DV |
9864 | if (old->release_fb) { |
9865 | drm_framebuffer_unregister_private(old->release_fb); | |
9866 | drm_framebuffer_unreference(old->release_fb); | |
9867 | } | |
d2dff872 | 9868 | |
0622a53c | 9869 | return; |
79e53945 JB |
9870 | } |
9871 | ||
c751ce4f | 9872 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9873 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9874 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9875 | |
9876 | return; | |
9877 | fail: | |
9878 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9879 | drm_atomic_state_free(state); | |
79e53945 JB |
9880 | } |
9881 | ||
da4a1efa | 9882 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9883 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9884 | { |
9885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9886 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9887 | ||
9888 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9889 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9890 | else if (HAS_PCH_SPLIT(dev)) |
9891 | return 120000; | |
9892 | else if (!IS_GEN2(dev)) | |
9893 | return 96000; | |
9894 | else | |
9895 | return 48000; | |
9896 | } | |
9897 | ||
79e53945 | 9898 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9899 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9900 | struct intel_crtc_state *pipe_config) |
79e53945 | 9901 | { |
f1f644dc | 9902 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9903 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9904 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9905 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9906 | u32 fp; |
9907 | intel_clock_t clock; | |
da4a1efa | 9908 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9909 | |
9910 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9911 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9912 | else |
293623f7 | 9913 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9914 | |
9915 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9916 | if (IS_PINEVIEW(dev)) { |
9917 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9918 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9919 | } else { |
9920 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9921 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9922 | } | |
9923 | ||
a6c45cf0 | 9924 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9925 | if (IS_PINEVIEW(dev)) |
9926 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9927 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9928 | else |
9929 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9930 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9931 | ||
9932 | switch (dpll & DPLL_MODE_MASK) { | |
9933 | case DPLLB_MODE_DAC_SERIAL: | |
9934 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9935 | 5 : 10; | |
9936 | break; | |
9937 | case DPLLB_MODE_LVDS: | |
9938 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9939 | 7 : 14; | |
9940 | break; | |
9941 | default: | |
28c97730 | 9942 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9943 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9944 | return; |
79e53945 JB |
9945 | } |
9946 | ||
ac58c3f0 | 9947 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9948 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9949 | else |
da4a1efa | 9950 | i9xx_clock(refclk, &clock); |
79e53945 | 9951 | } else { |
0fb58223 | 9952 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9953 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9954 | |
9955 | if (is_lvds) { | |
9956 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9957 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9958 | |
9959 | if (lvds & LVDS_CLKB_POWER_UP) | |
9960 | clock.p2 = 7; | |
9961 | else | |
9962 | clock.p2 = 14; | |
79e53945 JB |
9963 | } else { |
9964 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9965 | clock.p1 = 2; | |
9966 | else { | |
9967 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9968 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9969 | } | |
9970 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9971 | clock.p2 = 4; | |
9972 | else | |
9973 | clock.p2 = 2; | |
79e53945 | 9974 | } |
da4a1efa VS |
9975 | |
9976 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9977 | } |
9978 | ||
18442d08 VS |
9979 | /* |
9980 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9981 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9982 | * encoder's get_config() function. |
9983 | */ | |
9984 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9985 | } |
9986 | ||
6878da05 VS |
9987 | int intel_dotclock_calculate(int link_freq, |
9988 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9989 | { |
f1f644dc JB |
9990 | /* |
9991 | * The calculation for the data clock is: | |
1041a02f | 9992 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9993 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9994 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9995 | * |
9996 | * and the link clock is simpler: | |
1041a02f | 9997 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9998 | */ |
9999 | ||
6878da05 VS |
10000 | if (!m_n->link_n) |
10001 | return 0; | |
f1f644dc | 10002 | |
6878da05 VS |
10003 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10004 | } | |
f1f644dc | 10005 | |
18442d08 | 10006 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10007 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10008 | { |
10009 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10010 | |
18442d08 VS |
10011 | /* read out port_clock from the DPLL */ |
10012 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10013 | |
f1f644dc | 10014 | /* |
18442d08 | 10015 | * This value does not include pixel_multiplier. |
241bfc38 | 10016 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10017 | * agree once we know their relationship in the encoder's |
10018 | * get_config() function. | |
79e53945 | 10019 | */ |
2d112de7 | 10020 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10021 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10022 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10023 | } |
10024 | ||
10025 | /** Returns the currently programmed mode of the given pipe. */ | |
10026 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10027 | struct drm_crtc *crtc) | |
10028 | { | |
548f245b | 10029 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10031 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10032 | struct drm_display_mode *mode; |
5cec258b | 10033 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10034 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10035 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10036 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10037 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10038 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10039 | |
10040 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10041 | if (!mode) | |
10042 | return NULL; | |
10043 | ||
f1f644dc JB |
10044 | /* |
10045 | * Construct a pipe_config sufficient for getting the clock info | |
10046 | * back out of crtc_clock_get. | |
10047 | * | |
10048 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10049 | * to use a real value here instead. | |
10050 | */ | |
293623f7 | 10051 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10052 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10053 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10054 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10055 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10056 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10057 | ||
773ae034 | 10058 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10059 | mode->hdisplay = (htot & 0xffff) + 1; |
10060 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10061 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10062 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10063 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10064 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10065 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10066 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10067 | ||
10068 | drm_mode_set_name(mode); | |
79e53945 JB |
10069 | |
10070 | return mode; | |
10071 | } | |
10072 | ||
652c393a JB |
10073 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10074 | { | |
10075 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10076 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10078 | |
baff296c | 10079 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10080 | return; |
10081 | ||
10082 | if (!dev_priv->lvds_downclock_avail) | |
10083 | return; | |
10084 | ||
10085 | /* | |
10086 | * Since this is called by a timer, we should never get here in | |
10087 | * the manual case. | |
10088 | */ | |
10089 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10090 | int pipe = intel_crtc->pipe; |
10091 | int dpll_reg = DPLL(pipe); | |
10092 | int dpll; | |
f6e5b160 | 10093 | |
44d98a61 | 10094 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10095 | |
8ac5a6d5 | 10096 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10097 | |
dc257cf1 | 10098 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10099 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10100 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10101 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10102 | dpll = I915_READ(dpll_reg); |
10103 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10104 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10105 | } |
10106 | ||
10107 | } | |
10108 | ||
f047e395 CW |
10109 | void intel_mark_busy(struct drm_device *dev) |
10110 | { | |
c67a470b PZ |
10111 | struct drm_i915_private *dev_priv = dev->dev_private; |
10112 | ||
f62a0076 CW |
10113 | if (dev_priv->mm.busy) |
10114 | return; | |
10115 | ||
43694d69 | 10116 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10117 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10118 | if (INTEL_INFO(dev)->gen >= 6) |
10119 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10120 | dev_priv->mm.busy = true; |
f047e395 CW |
10121 | } |
10122 | ||
10123 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10124 | { |
c67a470b | 10125 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10126 | struct drm_crtc *crtc; |
652c393a | 10127 | |
f62a0076 CW |
10128 | if (!dev_priv->mm.busy) |
10129 | return; | |
10130 | ||
10131 | dev_priv->mm.busy = false; | |
10132 | ||
70e1e0ec | 10133 | for_each_crtc(dev, crtc) { |
f4510a27 | 10134 | if (!crtc->primary->fb) |
652c393a JB |
10135 | continue; |
10136 | ||
725a5b54 | 10137 | intel_decrease_pllclock(crtc); |
652c393a | 10138 | } |
b29c19b6 | 10139 | |
3d13ef2e | 10140 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10141 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10142 | |
43694d69 | 10143 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10144 | } |
10145 | ||
f5de6e07 ACO |
10146 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
10147 | struct intel_crtc_state *crtc_state) | |
10148 | { | |
10149 | kfree(crtc->config); | |
10150 | crtc->config = crtc_state; | |
16f3f658 | 10151 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
10152 | } |
10153 | ||
79e53945 JB |
10154 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10155 | { | |
10156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10157 | struct drm_device *dev = crtc->dev; |
10158 | struct intel_unpin_work *work; | |
67e77c5a | 10159 | |
5e2d7afc | 10160 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10161 | work = intel_crtc->unpin_work; |
10162 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10163 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10164 | |
10165 | if (work) { | |
10166 | cancel_work_sync(&work->work); | |
10167 | kfree(work); | |
10168 | } | |
79e53945 | 10169 | |
f5de6e07 | 10170 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 10171 | drm_crtc_cleanup(crtc); |
67e77c5a | 10172 | |
79e53945 JB |
10173 | kfree(intel_crtc); |
10174 | } | |
10175 | ||
6b95a207 KH |
10176 | static void intel_unpin_work_fn(struct work_struct *__work) |
10177 | { | |
10178 | struct intel_unpin_work *work = | |
10179 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10180 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10181 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10182 | |
b4a98e57 | 10183 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10184 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10185 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10186 | |
7ff0ebcc | 10187 | intel_fbc_update(dev); |
f06cc1b9 JH |
10188 | |
10189 | if (work->flip_queued_req) | |
146d84f0 | 10190 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10191 | mutex_unlock(&dev->struct_mutex); |
10192 | ||
f99d7069 | 10193 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10194 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10195 | |
b4a98e57 CW |
10196 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10197 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10198 | ||
6b95a207 KH |
10199 | kfree(work); |
10200 | } | |
10201 | ||
1afe3e9d | 10202 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10203 | struct drm_crtc *crtc) |
6b95a207 | 10204 | { |
6b95a207 KH |
10205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10206 | struct intel_unpin_work *work; | |
6b95a207 KH |
10207 | unsigned long flags; |
10208 | ||
10209 | /* Ignore early vblank irqs */ | |
10210 | if (intel_crtc == NULL) | |
10211 | return; | |
10212 | ||
f326038a DV |
10213 | /* |
10214 | * This is called both by irq handlers and the reset code (to complete | |
10215 | * lost pageflips) so needs the full irqsave spinlocks. | |
10216 | */ | |
6b95a207 KH |
10217 | spin_lock_irqsave(&dev->event_lock, flags); |
10218 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10219 | |
10220 | /* Ensure we don't miss a work->pending update ... */ | |
10221 | smp_rmb(); | |
10222 | ||
10223 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10224 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10225 | return; | |
10226 | } | |
10227 | ||
d6bbafa1 | 10228 | page_flip_completed(intel_crtc); |
0af7e4df | 10229 | |
6b95a207 | 10230 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10231 | } |
10232 | ||
1afe3e9d JB |
10233 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10234 | { | |
fbee40df | 10235 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10236 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10237 | ||
49b14a5c | 10238 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10239 | } |
10240 | ||
10241 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10242 | { | |
fbee40df | 10243 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10244 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10245 | ||
49b14a5c | 10246 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10247 | } |
10248 | ||
75f7f3ec VS |
10249 | /* Is 'a' after or equal to 'b'? */ |
10250 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10251 | { | |
10252 | return !((a - b) & 0x80000000); | |
10253 | } | |
10254 | ||
10255 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10256 | { | |
10257 | struct drm_device *dev = crtc->base.dev; | |
10258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10259 | ||
bdfa7542 VS |
10260 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10261 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10262 | return true; | |
10263 | ||
75f7f3ec VS |
10264 | /* |
10265 | * The relevant registers doen't exist on pre-ctg. | |
10266 | * As the flip done interrupt doesn't trigger for mmio | |
10267 | * flips on gmch platforms, a flip count check isn't | |
10268 | * really needed there. But since ctg has the registers, | |
10269 | * include it in the check anyway. | |
10270 | */ | |
10271 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10272 | return true; | |
10273 | ||
10274 | /* | |
10275 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10276 | * used the same base address. In that case the mmio flip might | |
10277 | * have completed, but the CS hasn't even executed the flip yet. | |
10278 | * | |
10279 | * A flip count check isn't enough as the CS might have updated | |
10280 | * the base address just after start of vblank, but before we | |
10281 | * managed to process the interrupt. This means we'd complete the | |
10282 | * CS flip too soon. | |
10283 | * | |
10284 | * Combining both checks should get us a good enough result. It may | |
10285 | * still happen that the CS flip has been executed, but has not | |
10286 | * yet actually completed. But in case the base address is the same | |
10287 | * anyway, we don't really care. | |
10288 | */ | |
10289 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10290 | crtc->unpin_work->gtt_offset && | |
10291 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10292 | crtc->unpin_work->flip_count); | |
10293 | } | |
10294 | ||
6b95a207 KH |
10295 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10296 | { | |
fbee40df | 10297 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10298 | struct intel_crtc *intel_crtc = |
10299 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10300 | unsigned long flags; | |
10301 | ||
f326038a DV |
10302 | |
10303 | /* | |
10304 | * This is called both by irq handlers and the reset code (to complete | |
10305 | * lost pageflips) so needs the full irqsave spinlocks. | |
10306 | * | |
10307 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10308 | * generate a page-flip completion irq, i.e. every modeset |
10309 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10310 | */ | |
6b95a207 | 10311 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10312 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10313 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10314 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10315 | } | |
10316 | ||
eba905b2 | 10317 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10318 | { |
10319 | /* Ensure that the work item is consistent when activating it ... */ | |
10320 | smp_wmb(); | |
10321 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10322 | /* and that it is marked active as soon as the irq could fire. */ | |
10323 | smp_wmb(); | |
10324 | } | |
10325 | ||
8c9f3aaf JB |
10326 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10327 | struct drm_crtc *crtc, | |
10328 | struct drm_framebuffer *fb, | |
ed8d1975 | 10329 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10330 | struct intel_engine_cs *ring, |
ed8d1975 | 10331 | uint32_t flags) |
8c9f3aaf | 10332 | { |
8c9f3aaf | 10333 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10334 | u32 flip_mask; |
10335 | int ret; | |
10336 | ||
6d90c952 | 10337 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10338 | if (ret) |
4fa62c89 | 10339 | return ret; |
8c9f3aaf JB |
10340 | |
10341 | /* Can't queue multiple flips, so wait for the previous | |
10342 | * one to finish before executing the next. | |
10343 | */ | |
10344 | if (intel_crtc->plane) | |
10345 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10346 | else | |
10347 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10348 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10349 | intel_ring_emit(ring, MI_NOOP); | |
10350 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10351 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10352 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10353 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10354 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10355 | |
10356 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10357 | __intel_ring_advance(ring); |
83d4092b | 10358 | return 0; |
8c9f3aaf JB |
10359 | } |
10360 | ||
10361 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10362 | struct drm_crtc *crtc, | |
10363 | struct drm_framebuffer *fb, | |
ed8d1975 | 10364 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10365 | struct intel_engine_cs *ring, |
ed8d1975 | 10366 | uint32_t flags) |
8c9f3aaf | 10367 | { |
8c9f3aaf | 10368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10369 | u32 flip_mask; |
10370 | int ret; | |
10371 | ||
6d90c952 | 10372 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10373 | if (ret) |
4fa62c89 | 10374 | return ret; |
8c9f3aaf JB |
10375 | |
10376 | if (intel_crtc->plane) | |
10377 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10378 | else | |
10379 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10380 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10381 | intel_ring_emit(ring, MI_NOOP); | |
10382 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10383 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10384 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10385 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10386 | intel_ring_emit(ring, MI_NOOP); |
10387 | ||
e7d841ca | 10388 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10389 | __intel_ring_advance(ring); |
83d4092b | 10390 | return 0; |
8c9f3aaf JB |
10391 | } |
10392 | ||
10393 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10394 | struct drm_crtc *crtc, | |
10395 | struct drm_framebuffer *fb, | |
ed8d1975 | 10396 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10397 | struct intel_engine_cs *ring, |
ed8d1975 | 10398 | uint32_t flags) |
8c9f3aaf JB |
10399 | { |
10400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10402 | uint32_t pf, pipesrc; | |
10403 | int ret; | |
10404 | ||
6d90c952 | 10405 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10406 | if (ret) |
4fa62c89 | 10407 | return ret; |
8c9f3aaf JB |
10408 | |
10409 | /* i965+ uses the linear or tiled offsets from the | |
10410 | * Display Registers (which do not change across a page-flip) | |
10411 | * so we need only reprogram the base address. | |
10412 | */ | |
6d90c952 DV |
10413 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10414 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10415 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10416 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10417 | obj->tiling_mode); |
8c9f3aaf JB |
10418 | |
10419 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10420 | * untested on non-native modes, so ignore it for now. | |
10421 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10422 | */ | |
10423 | pf = 0; | |
10424 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10425 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10426 | |
10427 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10428 | __intel_ring_advance(ring); |
83d4092b | 10429 | return 0; |
8c9f3aaf JB |
10430 | } |
10431 | ||
10432 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10433 | struct drm_crtc *crtc, | |
10434 | struct drm_framebuffer *fb, | |
ed8d1975 | 10435 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10436 | struct intel_engine_cs *ring, |
ed8d1975 | 10437 | uint32_t flags) |
8c9f3aaf JB |
10438 | { |
10439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10440 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10441 | uint32_t pf, pipesrc; | |
10442 | int ret; | |
10443 | ||
6d90c952 | 10444 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10445 | if (ret) |
4fa62c89 | 10446 | return ret; |
8c9f3aaf | 10447 | |
6d90c952 DV |
10448 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10449 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10450 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10451 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10452 | |
dc257cf1 DV |
10453 | /* Contrary to the suggestions in the documentation, |
10454 | * "Enable Panel Fitter" does not seem to be required when page | |
10455 | * flipping with a non-native mode, and worse causes a normal | |
10456 | * modeset to fail. | |
10457 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10458 | */ | |
10459 | pf = 0; | |
8c9f3aaf | 10460 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10461 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10462 | |
10463 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10464 | __intel_ring_advance(ring); |
83d4092b | 10465 | return 0; |
8c9f3aaf JB |
10466 | } |
10467 | ||
7c9017e5 JB |
10468 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10469 | struct drm_crtc *crtc, | |
10470 | struct drm_framebuffer *fb, | |
ed8d1975 | 10471 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10472 | struct intel_engine_cs *ring, |
ed8d1975 | 10473 | uint32_t flags) |
7c9017e5 | 10474 | { |
7c9017e5 | 10475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10476 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10477 | int len, ret; |
10478 | ||
eba905b2 | 10479 | switch (intel_crtc->plane) { |
cb05d8de DV |
10480 | case PLANE_A: |
10481 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10482 | break; | |
10483 | case PLANE_B: | |
10484 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10485 | break; | |
10486 | case PLANE_C: | |
10487 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10488 | break; | |
10489 | default: | |
10490 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10491 | return -ENODEV; |
cb05d8de DV |
10492 | } |
10493 | ||
ffe74d75 | 10494 | len = 4; |
f476828a | 10495 | if (ring->id == RCS) { |
ffe74d75 | 10496 | len += 6; |
f476828a DL |
10497 | /* |
10498 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10499 | * 48bits addresses, and we need a NOOP for the batch size to | |
10500 | * stay even. | |
10501 | */ | |
10502 | if (IS_GEN8(dev)) | |
10503 | len += 2; | |
10504 | } | |
ffe74d75 | 10505 | |
f66fab8e VS |
10506 | /* |
10507 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10508 | * "The full packet must be contained within the same cache line." | |
10509 | * | |
10510 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10511 | * cacheline, if we ever start emitting more commands before | |
10512 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10513 | * then do the cacheline alignment, and finally emit the | |
10514 | * MI_DISPLAY_FLIP. | |
10515 | */ | |
10516 | ret = intel_ring_cacheline_align(ring); | |
10517 | if (ret) | |
4fa62c89 | 10518 | return ret; |
f66fab8e | 10519 | |
ffe74d75 | 10520 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10521 | if (ret) |
4fa62c89 | 10522 | return ret; |
7c9017e5 | 10523 | |
ffe74d75 CW |
10524 | /* Unmask the flip-done completion message. Note that the bspec says that |
10525 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10526 | * more than one flip event at any time (or ensure that one flip message | |
10527 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10528 | * Experimentation says that BCS works despite DERRMR masking all | |
10529 | * flip-done completion events and that unmasking all planes at once | |
10530 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10531 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10532 | */ | |
10533 | if (ring->id == RCS) { | |
10534 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10535 | intel_ring_emit(ring, DERRMR); | |
10536 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10537 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10538 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10539 | if (IS_GEN8(dev)) |
10540 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10541 | MI_SRM_LRM_GLOBAL_GTT); | |
10542 | else | |
10543 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10544 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10545 | intel_ring_emit(ring, DERRMR); |
10546 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10547 | if (IS_GEN8(dev)) { |
10548 | intel_ring_emit(ring, 0); | |
10549 | intel_ring_emit(ring, MI_NOOP); | |
10550 | } | |
ffe74d75 CW |
10551 | } |
10552 | ||
cb05d8de | 10553 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10554 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10555 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10556 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10557 | |
10558 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10559 | __intel_ring_advance(ring); |
83d4092b | 10560 | return 0; |
7c9017e5 JB |
10561 | } |
10562 | ||
84c33a64 SG |
10563 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10564 | struct drm_i915_gem_object *obj) | |
10565 | { | |
10566 | /* | |
10567 | * This is not being used for older platforms, because | |
10568 | * non-availability of flip done interrupt forces us to use | |
10569 | * CS flips. Older platforms derive flip done using some clever | |
10570 | * tricks involving the flip_pending status bits and vblank irqs. | |
10571 | * So using MMIO flips there would disrupt this mechanism. | |
10572 | */ | |
10573 | ||
8e09bf83 CW |
10574 | if (ring == NULL) |
10575 | return true; | |
10576 | ||
84c33a64 SG |
10577 | if (INTEL_INFO(ring->dev)->gen < 5) |
10578 | return false; | |
10579 | ||
10580 | if (i915.use_mmio_flip < 0) | |
10581 | return false; | |
10582 | else if (i915.use_mmio_flip > 0) | |
10583 | return true; | |
14bf993e OM |
10584 | else if (i915.enable_execlists) |
10585 | return true; | |
84c33a64 | 10586 | else |
41c52415 | 10587 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10588 | } |
10589 | ||
ff944564 DL |
10590 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10591 | { | |
10592 | struct drm_device *dev = intel_crtc->base.dev; | |
10593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10594 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
10595 | const enum pipe pipe = intel_crtc->pipe; |
10596 | u32 ctl, stride; | |
10597 | ||
10598 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10599 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
10600 | switch (fb->modifier[0]) { |
10601 | case DRM_FORMAT_MOD_NONE: | |
10602 | break; | |
10603 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 10604 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
10605 | break; |
10606 | case I915_FORMAT_MOD_Y_TILED: | |
10607 | ctl |= PLANE_CTL_TILED_Y; | |
10608 | break; | |
10609 | case I915_FORMAT_MOD_Yf_TILED: | |
10610 | ctl |= PLANE_CTL_TILED_YF; | |
10611 | break; | |
10612 | default: | |
10613 | MISSING_CASE(fb->modifier[0]); | |
10614 | } | |
ff944564 DL |
10615 | |
10616 | /* | |
10617 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10618 | * linear buffers or in number of tiles for tiled buffers. | |
10619 | */ | |
2ebef630 TU |
10620 | stride = fb->pitches[0] / |
10621 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
10622 | fb->pixel_format); | |
ff944564 DL |
10623 | |
10624 | /* | |
10625 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10626 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10627 | */ | |
10628 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10629 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10630 | ||
10631 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10632 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10633 | } | |
10634 | ||
10635 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10636 | { |
10637 | struct drm_device *dev = intel_crtc->base.dev; | |
10638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10639 | struct intel_framebuffer *intel_fb = | |
10640 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10641 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10642 | u32 dspcntr; | |
10643 | u32 reg; | |
10644 | ||
84c33a64 SG |
10645 | reg = DSPCNTR(intel_crtc->plane); |
10646 | dspcntr = I915_READ(reg); | |
10647 | ||
c5d97472 DL |
10648 | if (obj->tiling_mode != I915_TILING_NONE) |
10649 | dspcntr |= DISPPLANE_TILED; | |
10650 | else | |
10651 | dspcntr &= ~DISPPLANE_TILED; | |
10652 | ||
84c33a64 SG |
10653 | I915_WRITE(reg, dspcntr); |
10654 | ||
10655 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10656 | intel_crtc->unpin_work->gtt_offset); | |
10657 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10658 | |
ff944564 DL |
10659 | } |
10660 | ||
10661 | /* | |
10662 | * XXX: This is the temporary way to update the plane registers until we get | |
10663 | * around to using the usual plane update functions for MMIO flips | |
10664 | */ | |
10665 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10666 | { | |
10667 | struct drm_device *dev = intel_crtc->base.dev; | |
10668 | bool atomic_update; | |
10669 | u32 start_vbl_count; | |
10670 | ||
10671 | intel_mark_page_flip_active(intel_crtc); | |
10672 | ||
10673 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10674 | ||
10675 | if (INTEL_INFO(dev)->gen >= 9) | |
10676 | skl_do_mmio_flip(intel_crtc); | |
10677 | else | |
10678 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10679 | ilk_do_mmio_flip(intel_crtc); | |
10680 | ||
9362c7c5 ACO |
10681 | if (atomic_update) |
10682 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10683 | } |
10684 | ||
9362c7c5 | 10685 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10686 | { |
cc8c4cc2 | 10687 | struct intel_crtc *crtc = |
9362c7c5 | 10688 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10689 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10690 | |
cc8c4cc2 JH |
10691 | mmio_flip = &crtc->mmio_flip; |
10692 | if (mmio_flip->req) | |
9c654818 JH |
10693 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10694 | crtc->reset_counter, | |
10695 | false, NULL, NULL) != 0); | |
84c33a64 | 10696 | |
cc8c4cc2 JH |
10697 | intel_do_mmio_flip(crtc); |
10698 | if (mmio_flip->req) { | |
10699 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10700 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10701 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10702 | } | |
84c33a64 SG |
10703 | } |
10704 | ||
10705 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10706 | struct drm_crtc *crtc, | |
10707 | struct drm_framebuffer *fb, | |
10708 | struct drm_i915_gem_object *obj, | |
10709 | struct intel_engine_cs *ring, | |
10710 | uint32_t flags) | |
10711 | { | |
84c33a64 | 10712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10713 | |
cc8c4cc2 JH |
10714 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10715 | obj->last_write_req); | |
536f5b5e ACO |
10716 | |
10717 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10718 | |
84c33a64 SG |
10719 | return 0; |
10720 | } | |
10721 | ||
8c9f3aaf JB |
10722 | static int intel_default_queue_flip(struct drm_device *dev, |
10723 | struct drm_crtc *crtc, | |
10724 | struct drm_framebuffer *fb, | |
ed8d1975 | 10725 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10726 | struct intel_engine_cs *ring, |
ed8d1975 | 10727 | uint32_t flags) |
8c9f3aaf JB |
10728 | { |
10729 | return -ENODEV; | |
10730 | } | |
10731 | ||
d6bbafa1 CW |
10732 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10733 | struct drm_crtc *crtc) | |
10734 | { | |
10735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10737 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10738 | u32 addr; | |
10739 | ||
10740 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10741 | return true; | |
10742 | ||
10743 | if (!work->enable_stall_check) | |
10744 | return false; | |
10745 | ||
10746 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10747 | if (work->flip_queued_req && |
10748 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10749 | return false; |
10750 | ||
1e3feefd | 10751 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10752 | } |
10753 | ||
1e3feefd | 10754 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10755 | return false; |
10756 | ||
10757 | /* Potential stall - if we see that the flip has happened, | |
10758 | * assume a missed interrupt. */ | |
10759 | if (INTEL_INFO(dev)->gen >= 4) | |
10760 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10761 | else | |
10762 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10763 | ||
10764 | /* There is a potential issue here with a false positive after a flip | |
10765 | * to the same address. We could address this by checking for a | |
10766 | * non-incrementing frame counter. | |
10767 | */ | |
10768 | return addr == work->gtt_offset; | |
10769 | } | |
10770 | ||
10771 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10772 | { | |
10773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10774 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10776 | struct intel_unpin_work *work; |
f326038a | 10777 | |
6c51d46f | 10778 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10779 | |
10780 | if (crtc == NULL) | |
10781 | return; | |
10782 | ||
f326038a | 10783 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10784 | work = intel_crtc->unpin_work; |
10785 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10786 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10787 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10788 | page_flip_completed(intel_crtc); |
6ad790c0 | 10789 | work = NULL; |
d6bbafa1 | 10790 | } |
6ad790c0 CW |
10791 | if (work != NULL && |
10792 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10793 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10794 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10795 | } |
10796 | ||
6b95a207 KH |
10797 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10798 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10799 | struct drm_pending_vblank_event *event, |
10800 | uint32_t page_flip_flags) | |
6b95a207 KH |
10801 | { |
10802 | struct drm_device *dev = crtc->dev; | |
10803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10804 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10805 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10807 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10808 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10809 | struct intel_unpin_work *work; |
a4872ba6 | 10810 | struct intel_engine_cs *ring; |
cf5d8a46 | 10811 | bool mmio_flip; |
52e68630 | 10812 | int ret; |
6b95a207 | 10813 | |
2ff8fde1 MR |
10814 | /* |
10815 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10816 | * check to be safe. In the future we may enable pageflipping from | |
10817 | * a disabled primary plane. | |
10818 | */ | |
10819 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10820 | return -EBUSY; | |
10821 | ||
e6a595d2 | 10822 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10823 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10824 | return -EINVAL; |
10825 | ||
10826 | /* | |
10827 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10828 | * Note that pitch changes could also affect these register. | |
10829 | */ | |
10830 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10831 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10832 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10833 | return -EINVAL; |
10834 | ||
f900db47 CW |
10835 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10836 | goto out_hang; | |
10837 | ||
b14c5679 | 10838 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10839 | if (work == NULL) |
10840 | return -ENOMEM; | |
10841 | ||
6b95a207 | 10842 | work->event = event; |
b4a98e57 | 10843 | work->crtc = crtc; |
ab8d6675 | 10844 | work->old_fb = old_fb; |
6b95a207 KH |
10845 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10846 | ||
87b6b101 | 10847 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10848 | if (ret) |
10849 | goto free_work; | |
10850 | ||
6b95a207 | 10851 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10852 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10853 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10854 | /* Before declaring the flip queue wedged, check if |
10855 | * the hardware completed the operation behind our backs. | |
10856 | */ | |
10857 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10858 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10859 | page_flip_completed(intel_crtc); | |
10860 | } else { | |
10861 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10862 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10863 | |
d6bbafa1 CW |
10864 | drm_crtc_vblank_put(crtc); |
10865 | kfree(work); | |
10866 | return -EBUSY; | |
10867 | } | |
6b95a207 KH |
10868 | } |
10869 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10870 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10871 | |
b4a98e57 CW |
10872 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10873 | flush_workqueue(dev_priv->wq); | |
10874 | ||
75dfca80 | 10875 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10876 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10877 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10878 | |
f4510a27 | 10879 | crtc->primary->fb = fb; |
afd65eb4 | 10880 | update_state_fb(crtc->primary); |
1ed1f968 | 10881 | |
e1f99ce6 | 10882 | work->pending_flip_obj = obj; |
e1f99ce6 | 10883 | |
89ed88ba CW |
10884 | ret = i915_mutex_lock_interruptible(dev); |
10885 | if (ret) | |
10886 | goto cleanup; | |
10887 | ||
b4a98e57 | 10888 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10889 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10890 | |
75f7f3ec | 10891 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10892 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10893 | |
4fa62c89 VS |
10894 | if (IS_VALLEYVIEW(dev)) { |
10895 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10896 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10897 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10898 | ring = NULL; | |
48bf5b2d | 10899 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10900 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10901 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10902 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10903 | if (ring == NULL || ring->id != RCS) |
10904 | ring = &dev_priv->ring[BCS]; | |
10905 | } else { | |
10906 | ring = &dev_priv->ring[RCS]; | |
10907 | } | |
10908 | ||
cf5d8a46 CW |
10909 | mmio_flip = use_mmio_flip(ring, obj); |
10910 | ||
10911 | /* When using CS flips, we want to emit semaphores between rings. | |
10912 | * However, when using mmio flips we will create a task to do the | |
10913 | * synchronisation, so all we want here is to pin the framebuffer | |
10914 | * into the display plane and skip any waits. | |
10915 | */ | |
82bc3b2d | 10916 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10917 | crtc->primary->state, |
10918 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10919 | if (ret) |
10920 | goto cleanup_pending; | |
6b95a207 | 10921 | |
121920fa TU |
10922 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10923 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10924 | |
cf5d8a46 | 10925 | if (mmio_flip) { |
84c33a64 SG |
10926 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10927 | page_flip_flags); | |
d6bbafa1 CW |
10928 | if (ret) |
10929 | goto cleanup_unpin; | |
10930 | ||
f06cc1b9 JH |
10931 | i915_gem_request_assign(&work->flip_queued_req, |
10932 | obj->last_write_req); | |
d6bbafa1 | 10933 | } else { |
84c33a64 | 10934 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10935 | page_flip_flags); |
10936 | if (ret) | |
10937 | goto cleanup_unpin; | |
10938 | ||
f06cc1b9 JH |
10939 | i915_gem_request_assign(&work->flip_queued_req, |
10940 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10941 | } |
10942 | ||
1e3feefd | 10943 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10944 | work->enable_stall_check = true; |
4fa62c89 | 10945 | |
ab8d6675 | 10946 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10947 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10948 | ||
7ff0ebcc | 10949 | intel_fbc_disable(dev); |
f99d7069 | 10950 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10951 | mutex_unlock(&dev->struct_mutex); |
10952 | ||
e5510fac JB |
10953 | trace_i915_flip_request(intel_crtc->plane, obj); |
10954 | ||
6b95a207 | 10955 | return 0; |
96b099fd | 10956 | |
4fa62c89 | 10957 | cleanup_unpin: |
82bc3b2d | 10958 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10959 | cleanup_pending: |
b4a98e57 | 10960 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10961 | mutex_unlock(&dev->struct_mutex); |
10962 | cleanup: | |
f4510a27 | 10963 | crtc->primary->fb = old_fb; |
afd65eb4 | 10964 | update_state_fb(crtc->primary); |
89ed88ba CW |
10965 | |
10966 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10967 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10968 | |
5e2d7afc | 10969 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10970 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10971 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10972 | |
87b6b101 | 10973 | drm_crtc_vblank_put(crtc); |
7317c75e | 10974 | free_work: |
96b099fd CW |
10975 | kfree(work); |
10976 | ||
f900db47 CW |
10977 | if (ret == -EIO) { |
10978 | out_hang: | |
53a366b9 | 10979 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10980 | if (ret == 0 && event) { |
5e2d7afc | 10981 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10982 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10983 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10984 | } |
f900db47 | 10985 | } |
96b099fd | 10986 | return ret; |
6b95a207 KH |
10987 | } |
10988 | ||
65b38e0d | 10989 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10990 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10991 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10992 | .atomic_begin = intel_begin_crtc_commit, |
10993 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10994 | }; |
10995 | ||
9a935856 DV |
10996 | /** |
10997 | * intel_modeset_update_staged_output_state | |
10998 | * | |
10999 | * Updates the staged output configuration state, e.g. after we've read out the | |
11000 | * current hw state. | |
11001 | */ | |
11002 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11003 | { |
7668851f | 11004 | struct intel_crtc *crtc; |
9a935856 DV |
11005 | struct intel_encoder *encoder; |
11006 | struct intel_connector *connector; | |
f6e5b160 | 11007 | |
3a3371ff | 11008 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11009 | connector->new_encoder = |
11010 | to_intel_encoder(connector->base.encoder); | |
11011 | } | |
f6e5b160 | 11012 | |
b2784e15 | 11013 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11014 | encoder->new_crtc = |
11015 | to_intel_crtc(encoder->base.crtc); | |
11016 | } | |
7668851f | 11017 | |
d3fcc808 | 11018 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11019 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11020 | } |
f6e5b160 CW |
11021 | } |
11022 | ||
d29b2f9d ACO |
11023 | /* Transitional helper to copy current connector/encoder state to |
11024 | * connector->state. This is needed so that code that is partially | |
11025 | * converted to atomic does the right thing. | |
11026 | */ | |
11027 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11028 | { | |
11029 | struct intel_connector *connector; | |
11030 | ||
11031 | for_each_intel_connector(dev, connector) { | |
11032 | if (connector->base.encoder) { | |
11033 | connector->base.state->best_encoder = | |
11034 | connector->base.encoder; | |
11035 | connector->base.state->crtc = | |
11036 | connector->base.encoder->crtc; | |
11037 | } else { | |
11038 | connector->base.state->best_encoder = NULL; | |
11039 | connector->base.state->crtc = NULL; | |
11040 | } | |
11041 | } | |
11042 | } | |
11043 | ||
9a935856 DV |
11044 | /** |
11045 | * intel_modeset_commit_output_state | |
11046 | * | |
11047 | * This function copies the stage display pipe configuration to the real one. | |
11048 | */ | |
11049 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
11050 | { | |
7668851f | 11051 | struct intel_crtc *crtc; |
9a935856 DV |
11052 | struct intel_encoder *encoder; |
11053 | struct intel_connector *connector; | |
f6e5b160 | 11054 | |
3a3371ff | 11055 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11056 | connector->base.encoder = &connector->new_encoder->base; |
11057 | } | |
f6e5b160 | 11058 | |
b2784e15 | 11059 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11060 | encoder->base.crtc = &encoder->new_crtc->base; |
11061 | } | |
7668851f | 11062 | |
d3fcc808 | 11063 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11064 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
11065 | crtc->base.enabled = crtc->new_enabled; |
11066 | } | |
d29b2f9d ACO |
11067 | |
11068 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
11069 | } |
11070 | ||
050f7aeb | 11071 | static void |
eba905b2 | 11072 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11073 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11074 | { |
11075 | int bpp = pipe_config->pipe_bpp; | |
11076 | ||
11077 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11078 | connector->base.base.id, | |
c23cc417 | 11079 | connector->base.name); |
050f7aeb DV |
11080 | |
11081 | /* Don't use an invalid EDID bpc value */ | |
11082 | if (connector->base.display_info.bpc && | |
11083 | connector->base.display_info.bpc * 3 < bpp) { | |
11084 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11085 | bpp, connector->base.display_info.bpc*3); | |
11086 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11087 | } | |
11088 | ||
11089 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11090 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11091 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11092 | bpp); | |
11093 | pipe_config->pipe_bpp = 24; | |
11094 | } | |
11095 | } | |
11096 | ||
4e53c2e0 | 11097 | static int |
050f7aeb | 11098 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11099 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11100 | { |
050f7aeb | 11101 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11102 | struct drm_atomic_state *state; |
050f7aeb | 11103 | struct intel_connector *connector; |
1486017f | 11104 | int bpp, i; |
4e53c2e0 | 11105 | |
d328c9d7 | 11106 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11107 | bpp = 10*3; |
d328c9d7 DV |
11108 | else if (INTEL_INFO(dev)->gen >= 5) |
11109 | bpp = 12*3; | |
11110 | else | |
11111 | bpp = 8*3; | |
11112 | ||
4e53c2e0 | 11113 | |
4e53c2e0 DV |
11114 | pipe_config->pipe_bpp = bpp; |
11115 | ||
1486017f ACO |
11116 | state = pipe_config->base.state; |
11117 | ||
4e53c2e0 | 11118 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
11119 | for (i = 0; i < state->num_connector; i++) { |
11120 | if (!state->connectors[i]) | |
11121 | continue; | |
11122 | ||
11123 | connector = to_intel_connector(state->connectors[i]); | |
11124 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
11125 | continue; |
11126 | ||
050f7aeb | 11127 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
11128 | } |
11129 | ||
11130 | return bpp; | |
11131 | } | |
11132 | ||
644db711 DV |
11133 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11134 | { | |
11135 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11136 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11137 | mode->crtc_clock, |
644db711 DV |
11138 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11139 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11140 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11141 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11142 | } | |
11143 | ||
c0b03411 | 11144 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11145 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11146 | const char *context) |
11147 | { | |
6a60cd87 CK |
11148 | struct drm_device *dev = crtc->base.dev; |
11149 | struct drm_plane *plane; | |
11150 | struct intel_plane *intel_plane; | |
11151 | struct intel_plane_state *state; | |
11152 | struct drm_framebuffer *fb; | |
11153 | ||
11154 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11155 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11156 | |
11157 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11158 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11159 | pipe_config->pipe_bpp, pipe_config->dither); | |
11160 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11161 | pipe_config->has_pch_encoder, | |
11162 | pipe_config->fdi_lanes, | |
11163 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11164 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11165 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11166 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11167 | pipe_config->has_dp_encoder, | |
11168 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11169 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11170 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11171 | |
11172 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11173 | pipe_config->has_dp_encoder, | |
11174 | pipe_config->dp_m2_n2.gmch_m, | |
11175 | pipe_config->dp_m2_n2.gmch_n, | |
11176 | pipe_config->dp_m2_n2.link_m, | |
11177 | pipe_config->dp_m2_n2.link_n, | |
11178 | pipe_config->dp_m2_n2.tu); | |
11179 | ||
55072d19 DV |
11180 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11181 | pipe_config->has_audio, | |
11182 | pipe_config->has_infoframe); | |
11183 | ||
c0b03411 | 11184 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11185 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11186 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11187 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11188 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11189 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11190 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11191 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
11192 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
11193 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
11194 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11195 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11196 | pipe_config->gmch_pfit.control, | |
11197 | pipe_config->gmch_pfit.pgm_ratios, | |
11198 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11199 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11200 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11201 | pipe_config->pch_pfit.size, |
11202 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11203 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11204 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
11205 | |
11206 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
11207 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11208 | intel_plane = to_intel_plane(plane); | |
11209 | if (intel_plane->pipe != crtc->pipe) | |
11210 | continue; | |
11211 | ||
11212 | state = to_intel_plane_state(plane->state); | |
11213 | fb = state->base.fb; | |
11214 | if (!fb) { | |
11215 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11216 | "disabled, scaler_id = %d\n", | |
11217 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11218 | plane->base.id, intel_plane->pipe, | |
11219 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11220 | drm_plane_index(plane), state->scaler_id); | |
11221 | continue; | |
11222 | } | |
11223 | ||
11224 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11225 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11226 | plane->base.id, intel_plane->pipe, | |
11227 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11228 | drm_plane_index(plane)); | |
11229 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11230 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11231 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11232 | state->scaler_id, | |
11233 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11234 | drm_rect_width(&state->src) >> 16, | |
11235 | drm_rect_height(&state->src) >> 16, | |
11236 | state->dst.x1, state->dst.y1, | |
11237 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11238 | } | |
c0b03411 DV |
11239 | } |
11240 | ||
bc079e8b VS |
11241 | static bool encoders_cloneable(const struct intel_encoder *a, |
11242 | const struct intel_encoder *b) | |
accfc0c5 | 11243 | { |
bc079e8b VS |
11244 | /* masks could be asymmetric, so check both ways */ |
11245 | return a == b || (a->cloneable & (1 << b->type) && | |
11246 | b->cloneable & (1 << a->type)); | |
11247 | } | |
11248 | ||
98a221da ACO |
11249 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11250 | struct intel_crtc *crtc, | |
bc079e8b VS |
11251 | struct intel_encoder *encoder) |
11252 | { | |
bc079e8b | 11253 | struct intel_encoder *source_encoder; |
98a221da ACO |
11254 | struct drm_connector_state *connector_state; |
11255 | int i; | |
bc079e8b | 11256 | |
98a221da ACO |
11257 | for (i = 0; i < state->num_connector; i++) { |
11258 | if (!state->connectors[i]) | |
11259 | continue; | |
bc079e8b | 11260 | |
98a221da ACO |
11261 | connector_state = state->connector_states[i]; |
11262 | if (connector_state->crtc != &crtc->base) | |
bc079e8b VS |
11263 | continue; |
11264 | ||
98a221da ACO |
11265 | source_encoder = |
11266 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11267 | if (!encoders_cloneable(encoder, source_encoder)) |
11268 | return false; | |
11269 | } | |
11270 | ||
11271 | return true; | |
11272 | } | |
11273 | ||
98a221da ACO |
11274 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11275 | struct intel_crtc *crtc) | |
bc079e8b | 11276 | { |
accfc0c5 | 11277 | struct intel_encoder *encoder; |
98a221da ACO |
11278 | struct drm_connector_state *connector_state; |
11279 | int i; | |
accfc0c5 | 11280 | |
98a221da ACO |
11281 | for (i = 0; i < state->num_connector; i++) { |
11282 | if (!state->connectors[i]) | |
accfc0c5 DV |
11283 | continue; |
11284 | ||
98a221da ACO |
11285 | connector_state = state->connector_states[i]; |
11286 | if (connector_state->crtc != &crtc->base) | |
11287 | continue; | |
11288 | ||
11289 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11290 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11291 | return false; |
accfc0c5 DV |
11292 | } |
11293 | ||
bc079e8b | 11294 | return true; |
accfc0c5 DV |
11295 | } |
11296 | ||
5448a00d | 11297 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11298 | { |
5448a00d ACO |
11299 | struct drm_device *dev = state->dev; |
11300 | struct intel_encoder *encoder; | |
11301 | struct drm_connector_state *connector_state; | |
00f0b378 | 11302 | unsigned int used_ports = 0; |
5448a00d | 11303 | int i; |
00f0b378 VS |
11304 | |
11305 | /* | |
11306 | * Walk the connector list instead of the encoder | |
11307 | * list to detect the problem on ddi platforms | |
11308 | * where there's just one encoder per digital port. | |
11309 | */ | |
5448a00d ACO |
11310 | for (i = 0; i < state->num_connector; i++) { |
11311 | if (!state->connectors[i]) | |
11312 | continue; | |
00f0b378 | 11313 | |
5448a00d ACO |
11314 | connector_state = state->connector_states[i]; |
11315 | if (!connector_state->best_encoder) | |
00f0b378 VS |
11316 | continue; |
11317 | ||
5448a00d ACO |
11318 | encoder = to_intel_encoder(connector_state->best_encoder); |
11319 | ||
11320 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11321 | |
11322 | switch (encoder->type) { | |
11323 | unsigned int port_mask; | |
11324 | case INTEL_OUTPUT_UNKNOWN: | |
11325 | if (WARN_ON(!HAS_DDI(dev))) | |
11326 | break; | |
11327 | case INTEL_OUTPUT_DISPLAYPORT: | |
11328 | case INTEL_OUTPUT_HDMI: | |
11329 | case INTEL_OUTPUT_EDP: | |
11330 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11331 | ||
11332 | /* the same port mustn't appear more than once */ | |
11333 | if (used_ports & port_mask) | |
11334 | return false; | |
11335 | ||
11336 | used_ports |= port_mask; | |
11337 | default: | |
11338 | break; | |
11339 | } | |
11340 | } | |
11341 | ||
11342 | return true; | |
11343 | } | |
11344 | ||
83a57153 ACO |
11345 | static void |
11346 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11347 | { | |
11348 | struct drm_crtc_state tmp_state; | |
663a3640 | 11349 | struct intel_crtc_scaler_state scaler_state; |
83a57153 | 11350 | |
663a3640 | 11351 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11352 | tmp_state = crtc_state->base; |
663a3640 | 11353 | scaler_state = crtc_state->scaler_state; |
83a57153 ACO |
11354 | memset(crtc_state, 0, sizeof *crtc_state); |
11355 | crtc_state->base = tmp_state; | |
663a3640 | 11356 | crtc_state->scaler_state = scaler_state; |
83a57153 ACO |
11357 | } |
11358 | ||
5cec258b | 11359 | static struct intel_crtc_state * |
b8cecdf5 | 11360 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
83a57153 ACO |
11361 | struct drm_display_mode *mode, |
11362 | struct drm_atomic_state *state) | |
ee7b9f93 | 11363 | { |
7758a113 | 11364 | struct intel_encoder *encoder; |
0b901879 ACO |
11365 | struct intel_connector *connector; |
11366 | struct drm_connector_state *connector_state; | |
5cec258b | 11367 | struct intel_crtc_state *pipe_config; |
d328c9d7 | 11368 | int base_bpp, ret = -EINVAL; |
0b901879 | 11369 | int i; |
e29c22c0 | 11370 | bool retry = true; |
ee7b9f93 | 11371 | |
98a221da | 11372 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 DV |
11373 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
11374 | return ERR_PTR(-EINVAL); | |
11375 | } | |
11376 | ||
5448a00d | 11377 | if (!check_digital_port_conflicts(state)) { |
00f0b378 VS |
11378 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
11379 | return ERR_PTR(-EINVAL); | |
11380 | } | |
11381 | ||
83a57153 ACO |
11382 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
11383 | if (IS_ERR(pipe_config)) | |
11384 | return pipe_config; | |
11385 | ||
11386 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 11387 | |
07878248 | 11388 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
11389 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
11390 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 11391 | |
e143a21c DV |
11392 | pipe_config->cpu_transcoder = |
11393 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 11394 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 11395 | |
2960bc9c ID |
11396 | /* |
11397 | * Sanitize sync polarity flags based on requested ones. If neither | |
11398 | * positive or negative polarity is requested, treat this as meaning | |
11399 | * negative polarity. | |
11400 | */ | |
2d112de7 | 11401 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11402 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11403 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11404 | |
2d112de7 | 11405 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11406 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11407 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11408 | |
050f7aeb DV |
11409 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11410 | * plane pixel format and any sink constraints into account. Returns the | |
11411 | * source plane bpp so that dithering can be selected on mismatches | |
11412 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11413 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11414 | pipe_config); | |
11415 | if (base_bpp < 0) | |
4e53c2e0 DV |
11416 | goto fail; |
11417 | ||
e41a56be VS |
11418 | /* |
11419 | * Determine the real pipe dimensions. Note that stereo modes can | |
11420 | * increase the actual pipe size due to the frame doubling and | |
11421 | * insertion of additional space for blanks between the frame. This | |
11422 | * is stored in the crtc timings. We use the requested mode to do this | |
11423 | * computation to clearly distinguish it from the adjusted mode, which | |
11424 | * can be changed by the connectors in the below retry loop. | |
11425 | */ | |
2d112de7 | 11426 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11427 | &pipe_config->pipe_src_w, |
11428 | &pipe_config->pipe_src_h); | |
e41a56be | 11429 | |
e29c22c0 | 11430 | encoder_retry: |
ef1b460d | 11431 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11432 | pipe_config->port_clock = 0; |
ef1b460d | 11433 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11434 | |
135c81b8 | 11435 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11436 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11437 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11438 | |
7758a113 DV |
11439 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11440 | * adjust it according to limitations or connector properties, and also | |
11441 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11442 | */ |
0b901879 ACO |
11443 | for (i = 0; i < state->num_connector; i++) { |
11444 | connector = to_intel_connector(state->connectors[i]); | |
11445 | if (!connector) | |
11446 | continue; | |
47f1c6c9 | 11447 | |
0b901879 ACO |
11448 | connector_state = state->connector_states[i]; |
11449 | if (connector_state->crtc != crtc) | |
7758a113 | 11450 | continue; |
7ae89233 | 11451 | |
0b901879 ACO |
11452 | encoder = to_intel_encoder(connector_state->best_encoder); |
11453 | ||
efea6e8e DV |
11454 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11455 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11456 | goto fail; |
11457 | } | |
ee7b9f93 | 11458 | } |
47f1c6c9 | 11459 | |
ff9a6750 DV |
11460 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11461 | * done afterwards in case the encoder adjusts the mode. */ | |
11462 | if (!pipe_config->port_clock) | |
2d112de7 | 11463 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11464 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11465 | |
a43f6e0f | 11466 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11467 | if (ret < 0) { |
7758a113 DV |
11468 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11469 | goto fail; | |
ee7b9f93 | 11470 | } |
e29c22c0 DV |
11471 | |
11472 | if (ret == RETRY) { | |
11473 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11474 | ret = -EINVAL; | |
11475 | goto fail; | |
11476 | } | |
11477 | ||
11478 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11479 | retry = false; | |
11480 | goto encoder_retry; | |
11481 | } | |
11482 | ||
d328c9d7 | 11483 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11484 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11485 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11486 | |
b8cecdf5 | 11487 | return pipe_config; |
7758a113 | 11488 | fail: |
e29c22c0 | 11489 | return ERR_PTR(ret); |
ee7b9f93 | 11490 | } |
47f1c6c9 | 11491 | |
e2e1ed41 DV |
11492 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
11493 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
11494 | static void | |
11495 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
11496 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
11497 | { |
11498 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
11499 | struct drm_device *dev = crtc->dev; |
11500 | struct intel_encoder *encoder; | |
11501 | struct intel_connector *connector; | |
11502 | struct drm_crtc *tmp_crtc; | |
79e53945 | 11503 | |
e2e1ed41 | 11504 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 11505 | |
e2e1ed41 DV |
11506 | /* Check which crtcs have changed outputs connected to them, these need |
11507 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
11508 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
11509 | * bit set at most. */ | |
3a3371ff | 11510 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
11511 | if (connector->base.encoder == &connector->new_encoder->base) |
11512 | continue; | |
79e53945 | 11513 | |
e2e1ed41 DV |
11514 | if (connector->base.encoder) { |
11515 | tmp_crtc = connector->base.encoder->crtc; | |
11516 | ||
11517 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11518 | } | |
11519 | ||
11520 | if (connector->new_encoder) | |
11521 | *prepare_pipes |= | |
11522 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
11523 | } |
11524 | ||
b2784e15 | 11525 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
11526 | if (encoder->base.crtc == &encoder->new_crtc->base) |
11527 | continue; | |
11528 | ||
11529 | if (encoder->base.crtc) { | |
11530 | tmp_crtc = encoder->base.crtc; | |
11531 | ||
11532 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11533 | } | |
11534 | ||
11535 | if (encoder->new_crtc) | |
11536 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
11537 | } |
11538 | ||
7668851f | 11539 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 11540 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11541 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 11542 | continue; |
7e7d76c3 | 11543 | |
7668851f | 11544 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 11545 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
11546 | else |
11547 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
11548 | } |
11549 | ||
e2e1ed41 DV |
11550 | |
11551 | /* set_mode is also used to update properties on life display pipes. */ | |
11552 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 11553 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11554 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11555 | ||
b6c5164d DV |
11556 | /* |
11557 | * For simplicity do a full modeset on any pipe where the output routing | |
11558 | * changed. We could be more clever, but that would require us to be | |
11559 | * more careful with calling the relevant encoder->mode_set functions. | |
11560 | */ | |
e2e1ed41 DV |
11561 | if (*prepare_pipes) |
11562 | *modeset_pipes = *prepare_pipes; | |
11563 | ||
11564 | /* ... and mask these out. */ | |
11565 | *modeset_pipes &= ~(*disable_pipes); | |
11566 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11567 | |
11568 | /* | |
11569 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11570 | * obies this rule, but the modeset restore mode of | |
11571 | * intel_modeset_setup_hw_state does not. | |
11572 | */ | |
11573 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11574 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11575 | |
11576 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11577 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11578 | } |
79e53945 | 11579 | |
ea9d758d | 11580 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11581 | { |
ea9d758d | 11582 | struct drm_encoder *encoder; |
f6e5b160 | 11583 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11584 | |
ea9d758d DV |
11585 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11586 | if (encoder->crtc == crtc) | |
11587 | return true; | |
11588 | ||
11589 | return false; | |
11590 | } | |
11591 | ||
11592 | static void | |
11593 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11594 | { | |
ba41c0de | 11595 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11596 | struct intel_encoder *intel_encoder; |
11597 | struct intel_crtc *intel_crtc; | |
11598 | struct drm_connector *connector; | |
11599 | ||
ba41c0de DV |
11600 | intel_shared_dpll_commit(dev_priv); |
11601 | ||
b2784e15 | 11602 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11603 | if (!intel_encoder->base.crtc) |
11604 | continue; | |
11605 | ||
11606 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11607 | ||
11608 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11609 | intel_encoder->connectors_active = false; | |
11610 | } | |
11611 | ||
11612 | intel_modeset_commit_output_state(dev); | |
11613 | ||
7668851f | 11614 | /* Double check state. */ |
d3fcc808 | 11615 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11616 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11617 | } |
11618 | ||
11619 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11620 | if (!connector->encoder || !connector->encoder->crtc) | |
11621 | continue; | |
11622 | ||
11623 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11624 | ||
11625 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11626 | struct drm_property *dpms_property = |
11627 | dev->mode_config.dpms_property; | |
11628 | ||
ea9d758d | 11629 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11630 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11631 | dpms_property, |
11632 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11633 | |
11634 | intel_encoder = to_intel_encoder(connector->encoder); | |
11635 | intel_encoder->connectors_active = true; | |
11636 | } | |
11637 | } | |
11638 | ||
11639 | } | |
11640 | ||
3bd26263 | 11641 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11642 | { |
3bd26263 | 11643 | int diff; |
f1f644dc JB |
11644 | |
11645 | if (clock1 == clock2) | |
11646 | return true; | |
11647 | ||
11648 | if (!clock1 || !clock2) | |
11649 | return false; | |
11650 | ||
11651 | diff = abs(clock1 - clock2); | |
11652 | ||
11653 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11654 | return true; | |
11655 | ||
11656 | return false; | |
11657 | } | |
11658 | ||
25c5b266 DV |
11659 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11660 | list_for_each_entry((intel_crtc), \ | |
11661 | &(dev)->mode_config.crtc_list, \ | |
11662 | base.head) \ | |
0973f18f | 11663 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11664 | |
0e8ffe1b | 11665 | static bool |
2fa2fe9a | 11666 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11667 | struct intel_crtc_state *current_config, |
11668 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11669 | { |
66e985c0 DV |
11670 | #define PIPE_CONF_CHECK_X(name) \ |
11671 | if (current_config->name != pipe_config->name) { \ | |
11672 | DRM_ERROR("mismatch in " #name " " \ | |
11673 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11674 | current_config->name, \ | |
11675 | pipe_config->name); \ | |
11676 | return false; \ | |
11677 | } | |
11678 | ||
08a24034 DV |
11679 | #define PIPE_CONF_CHECK_I(name) \ |
11680 | if (current_config->name != pipe_config->name) { \ | |
11681 | DRM_ERROR("mismatch in " #name " " \ | |
11682 | "(expected %i, found %i)\n", \ | |
11683 | current_config->name, \ | |
11684 | pipe_config->name); \ | |
11685 | return false; \ | |
88adfff1 DV |
11686 | } |
11687 | ||
b95af8be VK |
11688 | /* This is required for BDW+ where there is only one set of registers for |
11689 | * switching between high and low RR. | |
11690 | * This macro can be used whenever a comparison has to be made between one | |
11691 | * hw state and multiple sw state variables. | |
11692 | */ | |
11693 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11694 | if ((current_config->name != pipe_config->name) && \ | |
11695 | (current_config->alt_name != pipe_config->name)) { \ | |
11696 | DRM_ERROR("mismatch in " #name " " \ | |
11697 | "(expected %i or %i, found %i)\n", \ | |
11698 | current_config->name, \ | |
11699 | current_config->alt_name, \ | |
11700 | pipe_config->name); \ | |
11701 | return false; \ | |
11702 | } | |
11703 | ||
1bd1bd80 DV |
11704 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11705 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11706 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11707 | "(expected %i, found %i)\n", \ |
11708 | current_config->name & (mask), \ | |
11709 | pipe_config->name & (mask)); \ | |
11710 | return false; \ | |
11711 | } | |
11712 | ||
5e550656 VS |
11713 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11714 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11715 | DRM_ERROR("mismatch in " #name " " \ | |
11716 | "(expected %i, found %i)\n", \ | |
11717 | current_config->name, \ | |
11718 | pipe_config->name); \ | |
11719 | return false; \ | |
11720 | } | |
11721 | ||
bb760063 DV |
11722 | #define PIPE_CONF_QUIRK(quirk) \ |
11723 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11724 | ||
eccb140b DV |
11725 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11726 | ||
08a24034 DV |
11727 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11728 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11729 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11730 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11731 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11732 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11733 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11734 | |
eb14cb74 | 11735 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11736 | |
11737 | if (INTEL_INFO(dev)->gen < 8) { | |
11738 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11739 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11740 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11741 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11742 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11743 | ||
11744 | if (current_config->has_drrs) { | |
11745 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11746 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11747 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11748 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11749 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11750 | } | |
11751 | } else { | |
11752 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11753 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11754 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11755 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11756 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11757 | } | |
eb14cb74 | 11758 | |
2d112de7 ACO |
11759 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11760 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11761 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11762 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11763 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11764 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11765 | |
2d112de7 ACO |
11766 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11767 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11768 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11769 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11770 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11771 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11772 | |
c93f54cf | 11773 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11774 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11775 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11776 | IS_VALLEYVIEW(dev)) | |
11777 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11778 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11779 | |
9ed109a7 DV |
11780 | PIPE_CONF_CHECK_I(has_audio); |
11781 | ||
2d112de7 | 11782 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11783 | DRM_MODE_FLAG_INTERLACE); |
11784 | ||
bb760063 | 11785 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11786 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11787 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11788 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11789 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11790 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11791 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11792 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11793 | DRM_MODE_FLAG_NVSYNC); |
11794 | } | |
045ac3b5 | 11795 | |
37327abd VS |
11796 | PIPE_CONF_CHECK_I(pipe_src_w); |
11797 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11798 | |
9953599b DV |
11799 | /* |
11800 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11801 | * screen. Since we don't yet re-compute the pipe config when moving | |
11802 | * just the lvds port away to another pipe the sw tracking won't match. | |
11803 | * | |
11804 | * Proper atomic modesets with recomputed global state will fix this. | |
11805 | * Until then just don't check gmch state for inherited modes. | |
11806 | */ | |
11807 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11808 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11809 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11810 | if (INTEL_INFO(dev)->gen < 4) | |
11811 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11812 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11813 | } | |
11814 | ||
fd4daa9c CW |
11815 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11816 | if (current_config->pch_pfit.enabled) { | |
11817 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11818 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11819 | } | |
2fa2fe9a | 11820 | |
a1b2278e CK |
11821 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11822 | ||
e59150dc JB |
11823 | /* BDW+ don't expose a synchronous way to read the state */ |
11824 | if (IS_HASWELL(dev)) | |
11825 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11826 | |
282740f7 VS |
11827 | PIPE_CONF_CHECK_I(double_wide); |
11828 | ||
26804afd DV |
11829 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11830 | ||
c0d43d62 | 11831 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11832 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11833 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11834 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11835 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11836 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11837 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11838 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11839 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11840 | |
42571aef VS |
11841 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11842 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11843 | ||
2d112de7 | 11844 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11845 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11846 | |
66e985c0 | 11847 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11848 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11849 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11850 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11851 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11852 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11853 | |
0e8ffe1b DV |
11854 | return true; |
11855 | } | |
11856 | ||
08db6652 DL |
11857 | static void check_wm_state(struct drm_device *dev) |
11858 | { | |
11859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11860 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11861 | struct intel_crtc *intel_crtc; | |
11862 | int plane; | |
11863 | ||
11864 | if (INTEL_INFO(dev)->gen < 9) | |
11865 | return; | |
11866 | ||
11867 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11868 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11869 | ||
11870 | for_each_intel_crtc(dev, intel_crtc) { | |
11871 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11872 | const enum pipe pipe = intel_crtc->pipe; | |
11873 | ||
11874 | if (!intel_crtc->active) | |
11875 | continue; | |
11876 | ||
11877 | /* planes */ | |
dd740780 | 11878 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11879 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11880 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11881 | ||
11882 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11883 | continue; | |
11884 | ||
11885 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11886 | "(expected (%u,%u), found (%u,%u))\n", | |
11887 | pipe_name(pipe), plane + 1, | |
11888 | sw_entry->start, sw_entry->end, | |
11889 | hw_entry->start, hw_entry->end); | |
11890 | } | |
11891 | ||
11892 | /* cursor */ | |
11893 | hw_entry = &hw_ddb.cursor[pipe]; | |
11894 | sw_entry = &sw_ddb->cursor[pipe]; | |
11895 | ||
11896 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11897 | continue; | |
11898 | ||
11899 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11900 | "(expected (%u,%u), found (%u,%u))\n", | |
11901 | pipe_name(pipe), | |
11902 | sw_entry->start, sw_entry->end, | |
11903 | hw_entry->start, hw_entry->end); | |
11904 | } | |
11905 | } | |
11906 | ||
91d1b4bd DV |
11907 | static void |
11908 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11909 | { |
8af6cf88 DV |
11910 | struct intel_connector *connector; |
11911 | ||
3a3371ff | 11912 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11913 | /* This also checks the encoder/connector hw state with the |
11914 | * ->get_hw_state callbacks. */ | |
11915 | intel_connector_check_state(connector); | |
11916 | ||
e2c719b7 | 11917 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11918 | "connector's staged encoder doesn't match current encoder\n"); |
11919 | } | |
91d1b4bd DV |
11920 | } |
11921 | ||
11922 | static void | |
11923 | check_encoder_state(struct drm_device *dev) | |
11924 | { | |
11925 | struct intel_encoder *encoder; | |
11926 | struct intel_connector *connector; | |
8af6cf88 | 11927 | |
b2784e15 | 11928 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11929 | bool enabled = false; |
11930 | bool active = false; | |
11931 | enum pipe pipe, tracked_pipe; | |
11932 | ||
11933 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11934 | encoder->base.base.id, | |
8e329a03 | 11935 | encoder->base.name); |
8af6cf88 | 11936 | |
e2c719b7 | 11937 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11938 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11939 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11940 | "encoder's active_connectors set, but no crtc\n"); |
11941 | ||
3a3371ff | 11942 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11943 | if (connector->base.encoder != &encoder->base) |
11944 | continue; | |
11945 | enabled = true; | |
11946 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11947 | active = true; | |
11948 | } | |
0e32b39c DA |
11949 | /* |
11950 | * for MST connectors if we unplug the connector is gone | |
11951 | * away but the encoder is still connected to a crtc | |
11952 | * until a modeset happens in response to the hotplug. | |
11953 | */ | |
11954 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11955 | continue; | |
11956 | ||
e2c719b7 | 11957 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11958 | "encoder's enabled state mismatch " |
11959 | "(expected %i, found %i)\n", | |
11960 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11961 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11962 | "active encoder with no crtc\n"); |
11963 | ||
e2c719b7 | 11964 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11965 | "encoder's computed active state doesn't match tracked active state " |
11966 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11967 | ||
11968 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11969 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11970 | "encoder's hw state doesn't match sw tracking " |
11971 | "(expected %i, found %i)\n", | |
11972 | encoder->connectors_active, active); | |
11973 | ||
11974 | if (!encoder->base.crtc) | |
11975 | continue; | |
11976 | ||
11977 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11978 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11979 | "active encoder's pipe doesn't match" |
11980 | "(expected %i, found %i)\n", | |
11981 | tracked_pipe, pipe); | |
11982 | ||
11983 | } | |
91d1b4bd DV |
11984 | } |
11985 | ||
11986 | static void | |
11987 | check_crtc_state(struct drm_device *dev) | |
11988 | { | |
fbee40df | 11989 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11990 | struct intel_crtc *crtc; |
11991 | struct intel_encoder *encoder; | |
5cec258b | 11992 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11993 | |
d3fcc808 | 11994 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11995 | bool enabled = false; |
11996 | bool active = false; | |
11997 | ||
045ac3b5 JB |
11998 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11999 | ||
8af6cf88 DV |
12000 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12001 | crtc->base.base.id); | |
12002 | ||
83d65738 | 12003 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12004 | "active crtc, but not enabled in sw tracking\n"); |
12005 | ||
b2784e15 | 12006 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12007 | if (encoder->base.crtc != &crtc->base) |
12008 | continue; | |
12009 | enabled = true; | |
12010 | if (encoder->connectors_active) | |
12011 | active = true; | |
12012 | } | |
6c49f241 | 12013 | |
e2c719b7 | 12014 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12015 | "crtc's computed active state doesn't match tracked active state " |
12016 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12017 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12018 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12019 | "(expected %i, found %i)\n", enabled, |
12020 | crtc->base.state->enable); | |
8af6cf88 | 12021 | |
0e8ffe1b DV |
12022 | active = dev_priv->display.get_pipe_config(crtc, |
12023 | &pipe_config); | |
d62cf62a | 12024 | |
b6b5d049 VS |
12025 | /* hw state is inconsistent with the pipe quirk */ |
12026 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12027 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12028 | active = crtc->active; |
12029 | ||
b2784e15 | 12030 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12031 | enum pipe pipe; |
6c49f241 DV |
12032 | if (encoder->base.crtc != &crtc->base) |
12033 | continue; | |
1d37b689 | 12034 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12035 | encoder->get_config(encoder, &pipe_config); |
12036 | } | |
12037 | ||
e2c719b7 | 12038 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12039 | "crtc active state doesn't match with hw state " |
12040 | "(expected %i, found %i)\n", crtc->active, active); | |
12041 | ||
c0b03411 | 12042 | if (active && |
6e3c9717 | 12043 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12044 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12045 | intel_dump_pipe_config(crtc, &pipe_config, |
12046 | "[hw state]"); | |
6e3c9717 | 12047 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12048 | "[sw state]"); |
12049 | } | |
8af6cf88 DV |
12050 | } |
12051 | } | |
12052 | ||
91d1b4bd DV |
12053 | static void |
12054 | check_shared_dpll_state(struct drm_device *dev) | |
12055 | { | |
fbee40df | 12056 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12057 | struct intel_crtc *crtc; |
12058 | struct intel_dpll_hw_state dpll_hw_state; | |
12059 | int i; | |
5358901f DV |
12060 | |
12061 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12062 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12063 | int enabled_crtcs = 0, active_crtcs = 0; | |
12064 | bool active; | |
12065 | ||
12066 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12067 | ||
12068 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12069 | ||
12070 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12071 | ||
e2c719b7 | 12072 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12073 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12074 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12075 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12076 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12077 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12078 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12079 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12080 | "pll on state mismatch (expected %i, found %i)\n", |
12081 | pll->on, active); | |
12082 | ||
d3fcc808 | 12083 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12084 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12085 | enabled_crtcs++; |
12086 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12087 | active_crtcs++; | |
12088 | } | |
e2c719b7 | 12089 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12090 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12091 | pll->active, active_crtcs); | |
e2c719b7 | 12092 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12093 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12094 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12095 | |
e2c719b7 | 12096 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12097 | sizeof(dpll_hw_state)), |
12098 | "pll hw state mismatch\n"); | |
5358901f | 12099 | } |
8af6cf88 DV |
12100 | } |
12101 | ||
91d1b4bd DV |
12102 | void |
12103 | intel_modeset_check_state(struct drm_device *dev) | |
12104 | { | |
08db6652 | 12105 | check_wm_state(dev); |
91d1b4bd DV |
12106 | check_connector_state(dev); |
12107 | check_encoder_state(dev); | |
12108 | check_crtc_state(dev); | |
12109 | check_shared_dpll_state(dev); | |
12110 | } | |
12111 | ||
5cec258b | 12112 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12113 | int dotclock) |
12114 | { | |
12115 | /* | |
12116 | * FDI already provided one idea for the dotclock. | |
12117 | * Yell if the encoder disagrees. | |
12118 | */ | |
2d112de7 | 12119 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12120 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12121 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12122 | } |
12123 | ||
80715b2f VS |
12124 | static void update_scanline_offset(struct intel_crtc *crtc) |
12125 | { | |
12126 | struct drm_device *dev = crtc->base.dev; | |
12127 | ||
12128 | /* | |
12129 | * The scanline counter increments at the leading edge of hsync. | |
12130 | * | |
12131 | * On most platforms it starts counting from vtotal-1 on the | |
12132 | * first active line. That means the scanline counter value is | |
12133 | * always one less than what we would expect. Ie. just after | |
12134 | * start of vblank, which also occurs at start of hsync (on the | |
12135 | * last active line), the scanline counter will read vblank_start-1. | |
12136 | * | |
12137 | * On gen2 the scanline counter starts counting from 1 instead | |
12138 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12139 | * to keep the value positive), instead of adding one. | |
12140 | * | |
12141 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12142 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12143 | * there's an extra 1 line difference. So we need to add two instead of | |
12144 | * one to the value. | |
12145 | */ | |
12146 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12147 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12148 | int vtotal; |
12149 | ||
12150 | vtotal = mode->crtc_vtotal; | |
12151 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12152 | vtotal /= 2; | |
12153 | ||
12154 | crtc->scanline_offset = vtotal - 1; | |
12155 | } else if (HAS_DDI(dev) && | |
409ee761 | 12156 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12157 | crtc->scanline_offset = 2; |
12158 | } else | |
12159 | crtc->scanline_offset = 1; | |
12160 | } | |
12161 | ||
5cec258b | 12162 | static struct intel_crtc_state * |
7f27126e JB |
12163 | intel_modeset_compute_config(struct drm_crtc *crtc, |
12164 | struct drm_display_mode *mode, | |
83a57153 | 12165 | struct drm_atomic_state *state, |
7f27126e JB |
12166 | unsigned *modeset_pipes, |
12167 | unsigned *prepare_pipes, | |
12168 | unsigned *disable_pipes) | |
12169 | { | |
db7542dd | 12170 | struct drm_device *dev = crtc->dev; |
5cec258b | 12171 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 12172 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
12173 | int ret = 0; |
12174 | ||
12175 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12176 | if (ret) | |
12177 | return ERR_PTR(ret); | |
7f27126e JB |
12178 | |
12179 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
12180 | prepare_pipes, disable_pipes); | |
12181 | ||
db7542dd ACO |
12182 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
12183 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12184 | if (IS_ERR(pipe_config)) | |
12185 | return pipe_config; | |
12186 | ||
12187 | pipe_config->base.enable = false; | |
12188 | } | |
7f27126e JB |
12189 | |
12190 | /* | |
12191 | * Note this needs changes when we start tracking multiple modes | |
12192 | * and crtcs. At that point we'll need to compute the whole config | |
12193 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12194 | * for this crtc. | |
12195 | */ | |
db7542dd ACO |
12196 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
12197 | /* FIXME: For now we still expect modeset_pipes has at most | |
12198 | * one bit set. */ | |
12199 | if (WARN_ON(&intel_crtc->base != crtc)) | |
12200 | continue; | |
83a57153 | 12201 | |
8805aa71 | 12202 | pipe_config = intel_modeset_pipe_config(crtc, mode, state); |
db7542dd ACO |
12203 | if (IS_ERR(pipe_config)) |
12204 | return pipe_config; | |
7f27126e | 12205 | |
304603f4 ACO |
12206 | pipe_config->base.enable = true; |
12207 | ||
db7542dd ACO |
12208 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12209 | "[modeset]"); | |
12210 | } | |
12211 | ||
12212 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
12213 | } |
12214 | ||
225da59b | 12215 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
12216 | unsigned modeset_pipes, |
12217 | unsigned disable_pipes) | |
12218 | { | |
225da59b | 12219 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
12220 | struct drm_i915_private *dev_priv = to_i915(dev); |
12221 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
12222 | struct intel_crtc *intel_crtc; | |
12223 | int ret = 0; | |
12224 | ||
12225 | if (!dev_priv->display.crtc_compute_clock) | |
12226 | return 0; | |
12227 | ||
12228 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
12229 | if (ret) | |
12230 | goto done; | |
12231 | ||
12232 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
12233 | struct intel_crtc_state *crtc_state = |
12234 | intel_atomic_get_crtc_state(state, intel_crtc); | |
12235 | ||
12236 | /* Modeset pipes should have a new state by now */ | |
12237 | if (WARN_ON(IS_ERR(crtc_state))) | |
12238 | continue; | |
12239 | ||
ed6739ef | 12240 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 12241 | crtc_state); |
ed6739ef ACO |
12242 | if (ret) { |
12243 | intel_shared_dpll_abort_config(dev_priv); | |
12244 | goto done; | |
12245 | } | |
12246 | } | |
12247 | ||
12248 | done: | |
12249 | return ret; | |
12250 | } | |
12251 | ||
f30da187 DV |
12252 | static int __intel_set_mode(struct drm_crtc *crtc, |
12253 | struct drm_display_mode *mode, | |
7f27126e | 12254 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 12255 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12256 | unsigned modeset_pipes, |
12257 | unsigned prepare_pipes, | |
12258 | unsigned disable_pipes) | |
a6778b3c DV |
12259 | { |
12260 | struct drm_device *dev = crtc->dev; | |
fbee40df | 12261 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 12262 | struct drm_display_mode *saved_mode; |
304603f4 | 12263 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 12264 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 12265 | struct intel_crtc *intel_crtc; |
c0c36b94 | 12266 | int ret = 0; |
a6778b3c | 12267 | |
4b4b9238 | 12268 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
12269 | if (!saved_mode) |
12270 | return -ENOMEM; | |
a6778b3c | 12271 | |
83a57153 ACO |
12272 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
12273 | if (!crtc_state_copy) { | |
12274 | ret = -ENOMEM; | |
12275 | goto done; | |
12276 | } | |
12277 | ||
3ac18232 | 12278 | *saved_mode = crtc->mode; |
a6778b3c | 12279 | |
30a970c6 JB |
12280 | /* |
12281 | * See if the config requires any additional preparation, e.g. | |
12282 | * to adjust global state with pipes off. We need to do this | |
12283 | * here so we can get the modeset_pipe updated config for the new | |
12284 | * mode set on this crtc. For other crtcs we need to use the | |
12285 | * adjusted_mode bits in the crtc directly. | |
12286 | */ | |
f8437dd1 | 12287 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
304603f4 ACO |
12288 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
12289 | if (ret) | |
12290 | goto done; | |
30a970c6 | 12291 | |
c164f833 VS |
12292 | /* may have added more to prepare_pipes than we should */ |
12293 | prepare_pipes &= ~disable_pipes; | |
12294 | } | |
12295 | ||
225da59b | 12296 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
12297 | if (ret) |
12298 | goto done; | |
8bd31e67 | 12299 | |
460da916 DV |
12300 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
12301 | intel_crtc_disable(&intel_crtc->base); | |
12302 | ||
ea9d758d | 12303 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 12304 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
12305 | dev_priv->display.crtc_disable(&intel_crtc->base); |
12306 | } | |
a6778b3c | 12307 | |
6c4c86f5 DV |
12308 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12309 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12310 | * |
12311 | * Note we'll need to fix this up when we start tracking multiple | |
12312 | * pipes; here we assume a single modeset_pipe and only track the | |
12313 | * single crtc and mode. | |
f6e5b160 | 12314 | */ |
b8cecdf5 | 12315 | if (modeset_pipes) { |
25c5b266 | 12316 | crtc->mode = *mode; |
b8cecdf5 DV |
12317 | /* mode_set/enable/disable functions rely on a correct pipe |
12318 | * config. */ | |
f5de6e07 | 12319 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
12320 | |
12321 | /* | |
12322 | * Calculate and store various constants which | |
12323 | * are later needed by vblank and swap-completion | |
12324 | * timestamping. They are derived from true hwmode. | |
12325 | */ | |
12326 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 12327 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12328 | } |
7758a113 | 12329 | |
ea9d758d DV |
12330 | /* Only after disabling all output pipelines that will be changed can we |
12331 | * update the the output configuration. */ | |
12332 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 12333 | |
304603f4 | 12334 | modeset_update_crtc_power_domains(state); |
47fab737 | 12335 | |
25c5b266 | 12336 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
12337 | struct drm_plane *primary = intel_crtc->base.primary; |
12338 | int vdisplay, hdisplay; | |
4c10794f | 12339 | |
455a6808 | 12340 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12341 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
12342 | fb, 0, 0, | |
12343 | hdisplay, vdisplay, | |
12344 | x << 16, y << 16, | |
12345 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
12346 | } |
12347 | ||
12348 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
12349 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
12350 | update_scanline_offset(intel_crtc); | |
12351 | ||
25c5b266 | 12352 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 12353 | } |
a6778b3c | 12354 | |
a6778b3c DV |
12355 | /* FIXME: add subpixel order */ |
12356 | done: | |
83d65738 | 12357 | if (ret && crtc->state->enable) |
3ac18232 | 12358 | crtc->mode = *saved_mode; |
a6778b3c | 12359 | |
83a57153 ACO |
12360 | if (ret == 0 && pipe_config) { |
12361 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12362 | ||
12363 | /* The pipe_config will be freed with the atomic state, so | |
12364 | * make a copy. */ | |
12365 | memcpy(crtc_state_copy, intel_crtc->config, | |
12366 | sizeof *crtc_state_copy); | |
12367 | intel_crtc->config = crtc_state_copy; | |
12368 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
12369 | } else { |
12370 | kfree(crtc_state_copy); | |
12371 | } | |
12372 | ||
3ac18232 | 12373 | kfree(saved_mode); |
a6778b3c | 12374 | return ret; |
f6e5b160 CW |
12375 | } |
12376 | ||
7f27126e JB |
12377 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
12378 | struct drm_display_mode *mode, | |
12379 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 12380 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12381 | unsigned modeset_pipes, |
12382 | unsigned prepare_pipes, | |
12383 | unsigned disable_pipes) | |
f30da187 DV |
12384 | { |
12385 | int ret; | |
12386 | ||
7f27126e JB |
12387 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
12388 | prepare_pipes, disable_pipes); | |
f30da187 DV |
12389 | |
12390 | if (ret == 0) | |
12391 | intel_modeset_check_state(crtc->dev); | |
12392 | ||
12393 | return ret; | |
12394 | } | |
12395 | ||
7f27126e JB |
12396 | static int intel_set_mode(struct drm_crtc *crtc, |
12397 | struct drm_display_mode *mode, | |
83a57153 ACO |
12398 | int x, int y, struct drm_framebuffer *fb, |
12399 | struct drm_atomic_state *state) | |
7f27126e | 12400 | { |
5cec258b | 12401 | struct intel_crtc_state *pipe_config; |
7f27126e | 12402 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 12403 | int ret = 0; |
7f27126e | 12404 | |
8805aa71 | 12405 | pipe_config = intel_modeset_compute_config(crtc, mode, state, |
7f27126e JB |
12406 | &modeset_pipes, |
12407 | &prepare_pipes, | |
12408 | &disable_pipes); | |
12409 | ||
83a57153 ACO |
12410 | if (IS_ERR(pipe_config)) { |
12411 | ret = PTR_ERR(pipe_config); | |
12412 | goto out; | |
12413 | } | |
12414 | ||
12415 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
12416 | modeset_pipes, prepare_pipes, | |
12417 | disable_pipes); | |
12418 | if (ret) | |
12419 | goto out; | |
7f27126e | 12420 | |
83a57153 ACO |
12421 | out: |
12422 | return ret; | |
7f27126e JB |
12423 | } |
12424 | ||
c0c36b94 CW |
12425 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12426 | { | |
83a57153 ACO |
12427 | struct drm_device *dev = crtc->dev; |
12428 | struct drm_atomic_state *state; | |
12429 | struct intel_encoder *encoder; | |
12430 | struct intel_connector *connector; | |
12431 | struct drm_connector_state *connector_state; | |
12432 | ||
12433 | state = drm_atomic_state_alloc(dev); | |
12434 | if (!state) { | |
12435 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12436 | crtc->base.id); | |
12437 | return; | |
12438 | } | |
12439 | ||
12440 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12441 | ||
12442 | /* The force restore path in the HW readout code relies on the staged | |
12443 | * config still keeping the user requested config while the actual | |
12444 | * state has been overwritten by the configuration read from HW. We | |
12445 | * need to copy the staged config to the atomic state, otherwise the | |
12446 | * mode set will just reapply the state the HW is already in. */ | |
12447 | for_each_intel_encoder(dev, encoder) { | |
12448 | if (&encoder->new_crtc->base != crtc) | |
12449 | continue; | |
12450 | ||
12451 | for_each_intel_connector(dev, connector) { | |
12452 | if (connector->new_encoder != encoder) | |
12453 | continue; | |
12454 | ||
12455 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12456 | if (IS_ERR(connector_state)) { | |
12457 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12458 | connector->base.base.id, | |
12459 | connector->base.name, | |
12460 | PTR_ERR(connector_state)); | |
12461 | continue; | |
12462 | } | |
12463 | ||
12464 | connector_state->crtc = crtc; | |
12465 | connector_state->best_encoder = &encoder->base; | |
12466 | } | |
12467 | } | |
12468 | ||
12469 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
12470 | state); | |
12471 | ||
12472 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12473 | } |
12474 | ||
25c5b266 DV |
12475 | #undef for_each_intel_crtc_masked |
12476 | ||
d9e55608 DV |
12477 | static void intel_set_config_free(struct intel_set_config *config) |
12478 | { | |
12479 | if (!config) | |
12480 | return; | |
12481 | ||
1aa4b628 DV |
12482 | kfree(config->save_connector_encoders); |
12483 | kfree(config->save_encoder_crtcs); | |
7668851f | 12484 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
12485 | kfree(config); |
12486 | } | |
12487 | ||
85f9eb71 DV |
12488 | static int intel_set_config_save_state(struct drm_device *dev, |
12489 | struct intel_set_config *config) | |
12490 | { | |
7668851f | 12491 | struct drm_crtc *crtc; |
85f9eb71 DV |
12492 | struct drm_encoder *encoder; |
12493 | struct drm_connector *connector; | |
12494 | int count; | |
12495 | ||
7668851f VS |
12496 | config->save_crtc_enabled = |
12497 | kcalloc(dev->mode_config.num_crtc, | |
12498 | sizeof(bool), GFP_KERNEL); | |
12499 | if (!config->save_crtc_enabled) | |
12500 | return -ENOMEM; | |
12501 | ||
1aa4b628 DV |
12502 | config->save_encoder_crtcs = |
12503 | kcalloc(dev->mode_config.num_encoder, | |
12504 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
12505 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
12506 | return -ENOMEM; |
12507 | ||
1aa4b628 DV |
12508 | config->save_connector_encoders = |
12509 | kcalloc(dev->mode_config.num_connector, | |
12510 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
12511 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
12512 | return -ENOMEM; |
12513 | ||
12514 | /* Copy data. Note that driver private data is not affected. | |
12515 | * Should anything bad happen only the expected state is | |
12516 | * restored, not the drivers personal bookkeeping. | |
12517 | */ | |
7668851f | 12518 | count = 0; |
70e1e0ec | 12519 | for_each_crtc(dev, crtc) { |
83d65738 | 12520 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
12521 | } |
12522 | ||
85f9eb71 DV |
12523 | count = 0; |
12524 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 12525 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
12526 | } |
12527 | ||
12528 | count = 0; | |
12529 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 12530 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
12531 | } |
12532 | ||
12533 | return 0; | |
12534 | } | |
12535 | ||
12536 | static void intel_set_config_restore_state(struct drm_device *dev, | |
12537 | struct intel_set_config *config) | |
12538 | { | |
7668851f | 12539 | struct intel_crtc *crtc; |
9a935856 DV |
12540 | struct intel_encoder *encoder; |
12541 | struct intel_connector *connector; | |
85f9eb71 DV |
12542 | int count; |
12543 | ||
7668851f | 12544 | count = 0; |
d3fcc808 | 12545 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12546 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
12547 | } | |
12548 | ||
85f9eb71 | 12549 | count = 0; |
b2784e15 | 12550 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
12551 | encoder->new_crtc = |
12552 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
12553 | } |
12554 | ||
12555 | count = 0; | |
3a3371ff | 12556 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12557 | connector->new_encoder = |
12558 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12559 | } |
12560 | } | |
12561 | ||
e3de42b6 | 12562 | static bool |
2e57f47d | 12563 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12564 | { |
12565 | int i; | |
12566 | ||
2e57f47d CW |
12567 | if (set->num_connectors == 0) |
12568 | return false; | |
12569 | ||
12570 | if (WARN_ON(set->connectors == NULL)) | |
12571 | return false; | |
12572 | ||
12573 | for (i = 0; i < set->num_connectors; i++) | |
12574 | if (set->connectors[i]->encoder && | |
12575 | set->connectors[i]->encoder->crtc == set->crtc && | |
12576 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12577 | return true; |
12578 | ||
12579 | return false; | |
12580 | } | |
12581 | ||
5e2b584e DV |
12582 | static void |
12583 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12584 | struct intel_set_config *config) | |
12585 | { | |
12586 | ||
12587 | /* We should be able to check here if the fb has the same properties | |
12588 | * and then just flip_or_move it */ | |
2e57f47d CW |
12589 | if (is_crtc_connector_off(set)) { |
12590 | config->mode_changed = true; | |
f4510a27 | 12591 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12592 | /* |
12593 | * If we have no fb, we can only flip as long as the crtc is | |
12594 | * active, otherwise we need a full mode set. The crtc may | |
12595 | * be active if we've only disabled the primary plane, or | |
12596 | * in fastboot situations. | |
12597 | */ | |
f4510a27 | 12598 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12599 | struct intel_crtc *intel_crtc = |
12600 | to_intel_crtc(set->crtc); | |
12601 | ||
3b150f08 | 12602 | if (intel_crtc->active) { |
319d9827 JB |
12603 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12604 | config->fb_changed = true; | |
12605 | } else { | |
12606 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12607 | config->mode_changed = true; | |
12608 | } | |
5e2b584e DV |
12609 | } else if (set->fb == NULL) { |
12610 | config->mode_changed = true; | |
72f4901e | 12611 | } else if (set->fb->pixel_format != |
f4510a27 | 12612 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12613 | config->mode_changed = true; |
e3de42b6 | 12614 | } else { |
5e2b584e | 12615 | config->fb_changed = true; |
e3de42b6 | 12616 | } |
5e2b584e DV |
12617 | } |
12618 | ||
835c5873 | 12619 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12620 | config->fb_changed = true; |
12621 | ||
12622 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12623 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12624 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12625 | drm_mode_debug_printmodeline(set->mode); | |
12626 | config->mode_changed = true; | |
12627 | } | |
a1d95703 CW |
12628 | |
12629 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
12630 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12631 | } |
12632 | ||
2e431051 | 12633 | static int |
9a935856 DV |
12634 | intel_modeset_stage_output_state(struct drm_device *dev, |
12635 | struct drm_mode_set *set, | |
944b0c76 ACO |
12636 | struct intel_set_config *config, |
12637 | struct drm_atomic_state *state) | |
50f56119 | 12638 | { |
9a935856 | 12639 | struct intel_connector *connector; |
944b0c76 | 12640 | struct drm_connector_state *connector_state; |
9a935856 | 12641 | struct intel_encoder *encoder; |
7668851f | 12642 | struct intel_crtc *crtc; |
f3f08572 | 12643 | int ro; |
50f56119 | 12644 | |
9abdda74 | 12645 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12646 | * of connectors. For paranoia, double-check this. */ |
12647 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12648 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12649 | ||
3a3371ff | 12650 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12651 | /* Otherwise traverse passed in connector list and get encoders |
12652 | * for them. */ | |
50f56119 | 12653 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12654 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12655 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12656 | break; |
12657 | } | |
12658 | } | |
12659 | ||
9a935856 DV |
12660 | /* If we disable the crtc, disable all its connectors. Also, if |
12661 | * the connector is on the changing crtc but not on the new | |
12662 | * connector list, disable it. */ | |
12663 | if ((!set->fb || ro == set->num_connectors) && | |
12664 | connector->base.encoder && | |
12665 | connector->base.encoder->crtc == set->crtc) { | |
12666 | connector->new_encoder = NULL; | |
12667 | ||
12668 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12669 | connector->base.base.id, | |
c23cc417 | 12670 | connector->base.name); |
9a935856 DV |
12671 | } |
12672 | ||
12673 | ||
12674 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
12675 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
12676 | connector->base.base.id, | |
12677 | connector->base.name); | |
5e2b584e | 12678 | config->mode_changed = true; |
50f56119 DV |
12679 | } |
12680 | } | |
9a935856 | 12681 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12682 | |
9a935856 | 12683 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12684 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12685 | struct drm_crtc *new_crtc; |
12686 | ||
9a935856 | 12687 | if (!connector->new_encoder) |
50f56119 DV |
12688 | continue; |
12689 | ||
9a935856 | 12690 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12691 | |
12692 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12693 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12694 | new_crtc = set->crtc; |
12695 | } | |
12696 | ||
12697 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12698 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12699 | new_crtc)) { | |
5e2b584e | 12700 | return -EINVAL; |
50f56119 | 12701 | } |
0e32b39c | 12702 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12703 | |
944b0c76 ACO |
12704 | connector_state = |
12705 | drm_atomic_get_connector_state(state, &connector->base); | |
12706 | if (IS_ERR(connector_state)) | |
12707 | return PTR_ERR(connector_state); | |
12708 | ||
12709 | connector_state->crtc = new_crtc; | |
12710 | connector_state->best_encoder = &connector->new_encoder->base; | |
12711 | ||
9a935856 DV |
12712 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12713 | connector->base.base.id, | |
c23cc417 | 12714 | connector->base.name, |
9a935856 DV |
12715 | new_crtc->base.id); |
12716 | } | |
12717 | ||
12718 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12719 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12720 | int num_connectors = 0; |
3a3371ff | 12721 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12722 | if (connector->new_encoder == encoder) { |
12723 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12724 | num_connectors++; |
9a935856 DV |
12725 | } |
12726 | } | |
5a65f358 PZ |
12727 | |
12728 | if (num_connectors == 0) | |
12729 | encoder->new_crtc = NULL; | |
12730 | else if (num_connectors > 1) | |
12731 | return -EINVAL; | |
12732 | ||
9a935856 DV |
12733 | /* Only now check for crtc changes so we don't miss encoders |
12734 | * that will be disabled. */ | |
12735 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
12736 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
12737 | encoder->base.base.id, | |
12738 | encoder->base.name); | |
5e2b584e | 12739 | config->mode_changed = true; |
50f56119 DV |
12740 | } |
12741 | } | |
9a935856 | 12742 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12743 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12744 | connector_state = |
12745 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12746 | if (IS_ERR(connector_state)) |
12747 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12748 | |
12749 | if (connector->new_encoder) { | |
0e32b39c DA |
12750 | if (connector->new_encoder != connector->encoder) |
12751 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12752 | } else { |
12753 | connector_state->crtc = NULL; | |
f61cccf3 | 12754 | connector_state->best_encoder = NULL; |
944b0c76 | 12755 | } |
0e32b39c | 12756 | } |
d3fcc808 | 12757 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12758 | crtc->new_enabled = false; |
12759 | ||
b2784e15 | 12760 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12761 | if (encoder->new_crtc == crtc) { |
12762 | crtc->new_enabled = true; | |
12763 | break; | |
12764 | } | |
12765 | } | |
12766 | ||
83d65738 | 12767 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
12768 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
12769 | crtc->base.base.id, | |
7668851f VS |
12770 | crtc->new_enabled ? "en" : "dis"); |
12771 | config->mode_changed = true; | |
12772 | } | |
12773 | } | |
12774 | ||
2e431051 DV |
12775 | return 0; |
12776 | } | |
12777 | ||
7d00a1f5 VS |
12778 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12779 | { | |
12780 | struct drm_device *dev = crtc->base.dev; | |
12781 | struct intel_encoder *encoder; | |
12782 | struct intel_connector *connector; | |
12783 | ||
12784 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12785 | pipe_name(crtc->pipe)); | |
12786 | ||
3a3371ff | 12787 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12788 | if (connector->new_encoder && |
12789 | connector->new_encoder->new_crtc == crtc) | |
12790 | connector->new_encoder = NULL; | |
12791 | } | |
12792 | ||
b2784e15 | 12793 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12794 | if (encoder->new_crtc == crtc) |
12795 | encoder->new_crtc = NULL; | |
12796 | } | |
12797 | ||
12798 | crtc->new_enabled = false; | |
12799 | } | |
12800 | ||
2e431051 DV |
12801 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12802 | { | |
12803 | struct drm_device *dev; | |
2e431051 | 12804 | struct drm_mode_set save_set; |
83a57153 | 12805 | struct drm_atomic_state *state = NULL; |
2e431051 | 12806 | struct intel_set_config *config; |
5cec258b | 12807 | struct intel_crtc_state *pipe_config; |
50f52756 | 12808 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12809 | int ret; |
2e431051 | 12810 | |
8d3e375e DV |
12811 | BUG_ON(!set); |
12812 | BUG_ON(!set->crtc); | |
12813 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12814 | |
7e53f3a4 DV |
12815 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12816 | BUG_ON(!set->mode && set->fb); | |
12817 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12818 | |
2e431051 DV |
12819 | if (set->fb) { |
12820 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12821 | set->crtc->base.id, set->fb->base.id, | |
12822 | (int)set->num_connectors, set->x, set->y); | |
12823 | } else { | |
12824 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12825 | } |
12826 | ||
12827 | dev = set->crtc->dev; | |
12828 | ||
12829 | ret = -ENOMEM; | |
12830 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12831 | if (!config) | |
12832 | goto out_config; | |
12833 | ||
12834 | ret = intel_set_config_save_state(dev, config); | |
12835 | if (ret) | |
12836 | goto out_config; | |
12837 | ||
12838 | save_set.crtc = set->crtc; | |
12839 | save_set.mode = &set->crtc->mode; | |
12840 | save_set.x = set->crtc->x; | |
12841 | save_set.y = set->crtc->y; | |
f4510a27 | 12842 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12843 | |
12844 | /* Compute whether we need a full modeset, only an fb base update or no | |
12845 | * change at all. In the future we might also check whether only the | |
12846 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12847 | * such cases. */ | |
12848 | intel_set_config_compute_mode_changes(set, config); | |
12849 | ||
83a57153 ACO |
12850 | state = drm_atomic_state_alloc(dev); |
12851 | if (!state) { | |
12852 | ret = -ENOMEM; | |
12853 | goto out_config; | |
12854 | } | |
12855 | ||
12856 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12857 | ||
944b0c76 | 12858 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12859 | if (ret) |
12860 | goto fail; | |
12861 | ||
50f52756 | 12862 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
8805aa71 | 12863 | state, |
50f52756 JB |
12864 | &modeset_pipes, |
12865 | &prepare_pipes, | |
12866 | &disable_pipes); | |
20664591 | 12867 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12868 | ret = PTR_ERR(pipe_config); |
50f52756 | 12869 | goto fail; |
20664591 | 12870 | } else if (pipe_config) { |
b9950a13 | 12871 | if (pipe_config->has_audio != |
6e3c9717 | 12872 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12873 | config->mode_changed = true; |
12874 | ||
af15d2ce JB |
12875 | /* |
12876 | * Note we have an issue here with infoframes: current code | |
12877 | * only updates them on the full mode set path per hw | |
12878 | * requirements. So here we should be checking for any | |
12879 | * required changes and forcing a mode set. | |
12880 | */ | |
20664591 | 12881 | } |
50f52756 | 12882 | |
1f9954d0 JB |
12883 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12884 | ||
5e2b584e | 12885 | if (config->mode_changed) { |
50f52756 JB |
12886 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12887 | set->x, set->y, set->fb, pipe_config, | |
12888 | modeset_pipes, prepare_pipes, | |
12889 | disable_pipes); | |
5e2b584e | 12890 | } else if (config->fb_changed) { |
3b150f08 | 12891 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 | 12892 | struct drm_plane *primary = set->crtc->primary; |
b70709a6 ML |
12893 | struct intel_plane_state *plane_state = |
12894 | to_intel_plane_state(primary->state); | |
12895 | bool was_visible = plane_state->visible; | |
455a6808 | 12896 | int vdisplay, hdisplay; |
3b150f08 | 12897 | |
455a6808 | 12898 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12899 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12900 | 0, 0, hdisplay, vdisplay, | |
12901 | set->x << 16, set->y << 16, | |
12902 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12903 | |
12904 | /* | |
12905 | * We need to make sure the primary plane is re-enabled if it | |
12906 | * has previously been turned off. | |
12907 | */ | |
b70709a6 ML |
12908 | plane_state = to_intel_plane_state(primary->state); |
12909 | if (ret == 0 && !was_visible && plane_state->visible) { | |
3b150f08 | 12910 | WARN_ON(!intel_crtc->active); |
fdd508a6 | 12911 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12912 | } |
12913 | ||
7ca51a3a JB |
12914 | /* |
12915 | * In the fastboot case this may be our only check of the | |
12916 | * state after boot. It would be better to only do it on | |
12917 | * the first update, but we don't have a nice way of doing that | |
12918 | * (and really, set_config isn't used much for high freq page | |
12919 | * flipping, so increasing its cost here shouldn't be a big | |
12920 | * deal). | |
12921 | */ | |
d330a953 | 12922 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12923 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12924 | } |
12925 | ||
2d05eae1 | 12926 | if (ret) { |
bf67dfeb DV |
12927 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12928 | set->crtc->base.id, ret); | |
50f56119 | 12929 | fail: |
2d05eae1 | 12930 | intel_set_config_restore_state(dev, config); |
50f56119 | 12931 | |
83a57153 ACO |
12932 | drm_atomic_state_clear(state); |
12933 | ||
7d00a1f5 VS |
12934 | /* |
12935 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12936 | * force the pipe off to avoid oopsing in the modeset code | |
12937 | * due to fb==NULL. This should only happen during boot since | |
12938 | * we don't yet reconstruct the FB from the hardware state. | |
12939 | */ | |
12940 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12941 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12942 | ||
2d05eae1 CW |
12943 | /* Try to restore the config */ |
12944 | if (config->mode_changed && | |
12945 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12946 | save_set.x, save_set.y, save_set.fb, |
12947 | state)) | |
2d05eae1 CW |
12948 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12949 | } | |
50f56119 | 12950 | |
d9e55608 | 12951 | out_config: |
83a57153 ACO |
12952 | if (state) |
12953 | drm_atomic_state_free(state); | |
12954 | ||
d9e55608 | 12955 | intel_set_config_free(config); |
50f56119 DV |
12956 | return ret; |
12957 | } | |
f6e5b160 CW |
12958 | |
12959 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12960 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12961 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12962 | .destroy = intel_crtc_destroy, |
12963 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12964 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12965 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12966 | }; |
12967 | ||
5358901f DV |
12968 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12969 | struct intel_shared_dpll *pll, | |
12970 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12971 | { |
5358901f | 12972 | uint32_t val; |
ee7b9f93 | 12973 | |
f458ebbc | 12974 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12975 | return false; |
12976 | ||
5358901f | 12977 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12978 | hw_state->dpll = val; |
12979 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12980 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12981 | |
12982 | return val & DPLL_VCO_ENABLE; | |
12983 | } | |
12984 | ||
15bdd4cf DV |
12985 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12986 | struct intel_shared_dpll *pll) | |
12987 | { | |
3e369b76 ACO |
12988 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12989 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12990 | } |
12991 | ||
e7b903d2 DV |
12992 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12993 | struct intel_shared_dpll *pll) | |
12994 | { | |
e7b903d2 | 12995 | /* PCH refclock must be enabled first */ |
89eff4be | 12996 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12997 | |
3e369b76 | 12998 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12999 | |
13000 | /* Wait for the clocks to stabilize. */ | |
13001 | POSTING_READ(PCH_DPLL(pll->id)); | |
13002 | udelay(150); | |
13003 | ||
13004 | /* The pixel multiplier can only be updated once the | |
13005 | * DPLL is enabled and the clocks are stable. | |
13006 | * | |
13007 | * So write it again. | |
13008 | */ | |
3e369b76 | 13009 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13010 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13011 | udelay(200); |
13012 | } | |
13013 | ||
13014 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13015 | struct intel_shared_dpll *pll) | |
13016 | { | |
13017 | struct drm_device *dev = dev_priv->dev; | |
13018 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13019 | |
13020 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13021 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13022 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13023 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13024 | } |
13025 | ||
15bdd4cf DV |
13026 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13027 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13028 | udelay(200); |
13029 | } | |
13030 | ||
46edb027 DV |
13031 | static char *ibx_pch_dpll_names[] = { |
13032 | "PCH DPLL A", | |
13033 | "PCH DPLL B", | |
13034 | }; | |
13035 | ||
7c74ade1 | 13036 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13037 | { |
e7b903d2 | 13038 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13039 | int i; |
13040 | ||
7c74ade1 | 13041 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13042 | |
e72f9fbf | 13043 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13044 | dev_priv->shared_dplls[i].id = i; |
13045 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13046 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13047 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13048 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13049 | dev_priv->shared_dplls[i].get_hw_state = |
13050 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13051 | } |
13052 | } | |
13053 | ||
7c74ade1 DV |
13054 | static void intel_shared_dpll_init(struct drm_device *dev) |
13055 | { | |
e7b903d2 | 13056 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13057 | |
9cd86933 DV |
13058 | if (HAS_DDI(dev)) |
13059 | intel_ddi_pll_init(dev); | |
13060 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13061 | ibx_pch_dpll_init(dev); |
13062 | else | |
13063 | dev_priv->num_shared_dpll = 0; | |
13064 | ||
13065 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13066 | } |
13067 | ||
1fc0a8f7 TU |
13068 | /** |
13069 | * intel_wm_need_update - Check whether watermarks need updating | |
13070 | * @plane: drm plane | |
13071 | * @state: new plane state | |
13072 | * | |
13073 | * Check current plane state versus the new one to determine whether | |
13074 | * watermarks need to be recalculated. | |
13075 | * | |
13076 | * Returns true or false. | |
13077 | */ | |
13078 | bool intel_wm_need_update(struct drm_plane *plane, | |
13079 | struct drm_plane_state *state) | |
13080 | { | |
13081 | /* Update watermarks on tiling changes. */ | |
13082 | if (!plane->state->fb || !state->fb || | |
13083 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13084 | plane->state->rotation != state->rotation) | |
13085 | return true; | |
13086 | ||
13087 | return false; | |
13088 | } | |
13089 | ||
6beb8c23 MR |
13090 | /** |
13091 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13092 | * @plane: drm plane to prepare for | |
13093 | * @fb: framebuffer to prepare for presentation | |
13094 | * | |
13095 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13096 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13097 | * bits. Some older platforms need special physical address handling for | |
13098 | * cursor planes. | |
13099 | * | |
13100 | * Returns 0 on success, negative error code on failure. | |
13101 | */ | |
13102 | int | |
13103 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13104 | struct drm_framebuffer *fb, |
13105 | const struct drm_plane_state *new_state) | |
465c120c MR |
13106 | { |
13107 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13108 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13109 | enum pipe pipe = intel_plane->pipe; | |
13110 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13111 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13112 | unsigned frontbuffer_bits = 0; | |
13113 | int ret = 0; | |
465c120c | 13114 | |
ea2c67bb | 13115 | if (!obj) |
465c120c MR |
13116 | return 0; |
13117 | ||
6beb8c23 MR |
13118 | switch (plane->type) { |
13119 | case DRM_PLANE_TYPE_PRIMARY: | |
13120 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13121 | break; | |
13122 | case DRM_PLANE_TYPE_CURSOR: | |
13123 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13124 | break; | |
13125 | case DRM_PLANE_TYPE_OVERLAY: | |
13126 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13127 | break; | |
13128 | } | |
465c120c | 13129 | |
6beb8c23 | 13130 | mutex_lock(&dev->struct_mutex); |
465c120c | 13131 | |
6beb8c23 MR |
13132 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13133 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13134 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13135 | ret = i915_gem_object_attach_phys(obj, align); | |
13136 | if (ret) | |
13137 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13138 | } else { | |
82bc3b2d | 13139 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13140 | } |
465c120c | 13141 | |
6beb8c23 MR |
13142 | if (ret == 0) |
13143 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13144 | |
4c34574f | 13145 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13146 | |
6beb8c23 MR |
13147 | return ret; |
13148 | } | |
13149 | ||
38f3ce3a MR |
13150 | /** |
13151 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13152 | * @plane: drm plane to clean up for | |
13153 | * @fb: old framebuffer that was on plane | |
13154 | * | |
13155 | * Cleans up a framebuffer that has just been removed from a plane. | |
13156 | */ | |
13157 | void | |
13158 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13159 | struct drm_framebuffer *fb, |
13160 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13161 | { |
13162 | struct drm_device *dev = plane->dev; | |
13163 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13164 | ||
13165 | if (WARN_ON(!obj)) | |
13166 | return; | |
13167 | ||
13168 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13169 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13170 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13171 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13172 | mutex_unlock(&dev->struct_mutex); |
13173 | } | |
465c120c MR |
13174 | } |
13175 | ||
6156a456 CK |
13176 | int |
13177 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13178 | { | |
13179 | int max_scale; | |
13180 | struct drm_device *dev; | |
13181 | struct drm_i915_private *dev_priv; | |
13182 | int crtc_clock, cdclk; | |
13183 | ||
13184 | if (!intel_crtc || !crtc_state) | |
13185 | return DRM_PLANE_HELPER_NO_SCALING; | |
13186 | ||
13187 | dev = intel_crtc->base.dev; | |
13188 | dev_priv = dev->dev_private; | |
13189 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13190 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13191 | ||
13192 | if (!crtc_clock || !cdclk) | |
13193 | return DRM_PLANE_HELPER_NO_SCALING; | |
13194 | ||
13195 | /* | |
13196 | * skl max scale is lower of: | |
13197 | * close to 3 but not 3, -1 is for that purpose | |
13198 | * or | |
13199 | * cdclk/crtc_clock | |
13200 | */ | |
13201 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13202 | ||
13203 | return max_scale; | |
13204 | } | |
13205 | ||
465c120c | 13206 | static int |
3c692a41 GP |
13207 | intel_check_primary_plane(struct drm_plane *plane, |
13208 | struct intel_plane_state *state) | |
13209 | { | |
32b7eeec MR |
13210 | struct drm_device *dev = plane->dev; |
13211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13212 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13213 | struct intel_crtc *intel_crtc; |
6156a456 | 13214 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13215 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13216 | struct drm_rect *dest = &state->dst; |
13217 | struct drm_rect *src = &state->src; | |
13218 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13219 | bool can_position = false; |
6156a456 CK |
13220 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13221 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13222 | int ret; |
13223 | ||
ea2c67bb MR |
13224 | crtc = crtc ? crtc : plane->crtc; |
13225 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13226 | crtc_state = state->base.state ? |
13227 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13228 | |
6156a456 CK |
13229 | if (INTEL_INFO(dev)->gen >= 9) { |
13230 | min_scale = 1; | |
13231 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
d8106366 | 13232 | can_position = true; |
6156a456 | 13233 | } |
d8106366 | 13234 | |
c59cb179 MR |
13235 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13236 | src, dest, clip, | |
6156a456 CK |
13237 | min_scale, |
13238 | max_scale, | |
d8106366 SJ |
13239 | can_position, true, |
13240 | &state->visible); | |
c59cb179 MR |
13241 | if (ret) |
13242 | return ret; | |
465c120c | 13243 | |
32b7eeec | 13244 | if (intel_crtc->active) { |
b70709a6 ML |
13245 | struct intel_plane_state *old_state = |
13246 | to_intel_plane_state(plane->state); | |
13247 | ||
32b7eeec MR |
13248 | intel_crtc->atomic.wait_for_flips = true; |
13249 | ||
13250 | /* | |
13251 | * FBC does not work on some platforms for rotated | |
13252 | * planes, so disable it when rotation is not 0 and | |
13253 | * update it when rotation is set back to 0. | |
13254 | * | |
13255 | * FIXME: This is redundant with the fbc update done in | |
13256 | * the primary plane enable function except that that | |
13257 | * one is done too late. We eventually need to unify | |
13258 | * this. | |
13259 | */ | |
b70709a6 | 13260 | if (state->visible && |
32b7eeec | 13261 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13262 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13263 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13264 | intel_crtc->atomic.disable_fbc = true; |
13265 | } | |
13266 | ||
b70709a6 | 13267 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13268 | /* |
13269 | * BDW signals flip done immediately if the plane | |
13270 | * is disabled, even if the plane enable is already | |
13271 | * armed to occur at the next vblank :( | |
13272 | */ | |
b70709a6 | 13273 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13274 | intel_crtc->atomic.wait_vblank = true; |
13275 | } | |
13276 | ||
13277 | intel_crtc->atomic.fb_bits |= | |
13278 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13279 | ||
13280 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13281 | |
1fc0a8f7 | 13282 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13283 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13284 | } |
13285 | ||
6156a456 CK |
13286 | if (INTEL_INFO(dev)->gen >= 9) { |
13287 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13288 | to_intel_plane(plane), state, 0); | |
13289 | if (ret) | |
13290 | return ret; | |
13291 | } | |
13292 | ||
14af293f GP |
13293 | return 0; |
13294 | } | |
13295 | ||
13296 | static void | |
13297 | intel_commit_primary_plane(struct drm_plane *plane, | |
13298 | struct intel_plane_state *state) | |
13299 | { | |
2b875c22 MR |
13300 | struct drm_crtc *crtc = state->base.crtc; |
13301 | struct drm_framebuffer *fb = state->base.fb; | |
13302 | struct drm_device *dev = plane->dev; | |
14af293f | 13303 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13304 | struct intel_crtc *intel_crtc; |
14af293f GP |
13305 | struct drm_rect *src = &state->src; |
13306 | ||
ea2c67bb MR |
13307 | crtc = crtc ? crtc : plane->crtc; |
13308 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13309 | |
13310 | plane->fb = fb; | |
9dc806fc MR |
13311 | crtc->x = src->x1 >> 16; |
13312 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13313 | |
ccc759dc | 13314 | if (intel_crtc->active) { |
27321ae8 | 13315 | if (state->visible) |
ccc759dc GP |
13316 | /* FIXME: kill this fastboot hack */ |
13317 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13318 | |
27321ae8 ML |
13319 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13320 | crtc->x, crtc->y); | |
ccc759dc | 13321 | } |
465c120c MR |
13322 | } |
13323 | ||
a8ad0d8e ML |
13324 | static void |
13325 | intel_disable_primary_plane(struct drm_plane *plane, | |
13326 | struct drm_crtc *crtc, | |
13327 | bool force) | |
13328 | { | |
13329 | struct drm_device *dev = plane->dev; | |
13330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13331 | ||
a8ad0d8e ML |
13332 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13333 | } | |
13334 | ||
32b7eeec | 13335 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13336 | { |
32b7eeec | 13337 | struct drm_device *dev = crtc->dev; |
140fd38d | 13338 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13340 | struct intel_plane *intel_plane; |
13341 | struct drm_plane *p; | |
13342 | unsigned fb_bits = 0; | |
13343 | ||
13344 | /* Track fb's for any planes being disabled */ | |
13345 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13346 | intel_plane = to_intel_plane(p); | |
13347 | ||
13348 | if (intel_crtc->atomic.disabled_planes & | |
13349 | (1 << drm_plane_index(p))) { | |
13350 | switch (p->type) { | |
13351 | case DRM_PLANE_TYPE_PRIMARY: | |
13352 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13353 | break; | |
13354 | case DRM_PLANE_TYPE_CURSOR: | |
13355 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13356 | break; | |
13357 | case DRM_PLANE_TYPE_OVERLAY: | |
13358 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13359 | break; | |
13360 | } | |
3c692a41 | 13361 | |
ea2c67bb MR |
13362 | mutex_lock(&dev->struct_mutex); |
13363 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13364 | mutex_unlock(&dev->struct_mutex); | |
13365 | } | |
13366 | } | |
3c692a41 | 13367 | |
32b7eeec MR |
13368 | if (intel_crtc->atomic.wait_for_flips) |
13369 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13370 | |
32b7eeec MR |
13371 | if (intel_crtc->atomic.disable_fbc) |
13372 | intel_fbc_disable(dev); | |
3c692a41 | 13373 | |
32b7eeec MR |
13374 | if (intel_crtc->atomic.pre_disable_primary) |
13375 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13376 | |
32b7eeec MR |
13377 | if (intel_crtc->atomic.update_wm) |
13378 | intel_update_watermarks(crtc); | |
3c692a41 | 13379 | |
32b7eeec | 13380 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13381 | |
c34c9ee4 MR |
13382 | /* Perform vblank evasion around commit operation */ |
13383 | if (intel_crtc->active) | |
13384 | intel_crtc->atomic.evade = | |
13385 | intel_pipe_update_start(intel_crtc, | |
13386 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13387 | } |
13388 | ||
13389 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13390 | { | |
13391 | struct drm_device *dev = crtc->dev; | |
13392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13394 | struct drm_plane *p; | |
13395 | ||
c34c9ee4 MR |
13396 | if (intel_crtc->atomic.evade) |
13397 | intel_pipe_update_end(intel_crtc, | |
13398 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13399 | |
140fd38d | 13400 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13401 | |
32b7eeec MR |
13402 | if (intel_crtc->atomic.wait_vblank) |
13403 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13404 | ||
13405 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13406 | ||
13407 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13408 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13409 | intel_fbc_update(dev); |
ccc759dc | 13410 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13411 | } |
3c692a41 | 13412 | |
32b7eeec MR |
13413 | if (intel_crtc->atomic.post_enable_primary) |
13414 | intel_post_enable_primary(crtc); | |
3c692a41 | 13415 | |
32b7eeec MR |
13416 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13417 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13418 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13419 | false, false); | |
13420 | ||
13421 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13422 | } |
13423 | ||
cf4c7c12 | 13424 | /** |
4a3b8769 MR |
13425 | * intel_plane_destroy - destroy a plane |
13426 | * @plane: plane to destroy | |
cf4c7c12 | 13427 | * |
4a3b8769 MR |
13428 | * Common destruction function for all types of planes (primary, cursor, |
13429 | * sprite). | |
cf4c7c12 | 13430 | */ |
4a3b8769 | 13431 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13432 | { |
13433 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13434 | drm_plane_cleanup(plane); | |
13435 | kfree(intel_plane); | |
13436 | } | |
13437 | ||
65a3fea0 | 13438 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13439 | .update_plane = drm_atomic_helper_update_plane, |
13440 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13441 | .destroy = intel_plane_destroy, |
c196e1d6 | 13442 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13443 | .atomic_get_property = intel_plane_atomic_get_property, |
13444 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13445 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13446 | .atomic_destroy_state = intel_plane_destroy_state, | |
13447 | ||
465c120c MR |
13448 | }; |
13449 | ||
13450 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13451 | int pipe) | |
13452 | { | |
13453 | struct intel_plane *primary; | |
8e7d688b | 13454 | struct intel_plane_state *state; |
465c120c MR |
13455 | const uint32_t *intel_primary_formats; |
13456 | int num_formats; | |
13457 | ||
13458 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13459 | if (primary == NULL) | |
13460 | return NULL; | |
13461 | ||
8e7d688b MR |
13462 | state = intel_create_plane_state(&primary->base); |
13463 | if (!state) { | |
ea2c67bb MR |
13464 | kfree(primary); |
13465 | return NULL; | |
13466 | } | |
8e7d688b | 13467 | primary->base.state = &state->base; |
ea2c67bb | 13468 | |
465c120c MR |
13469 | primary->can_scale = false; |
13470 | primary->max_downscale = 1; | |
6156a456 CK |
13471 | if (INTEL_INFO(dev)->gen >= 9) { |
13472 | primary->can_scale = true; | |
13473 | } | |
549e2bfb | 13474 | state->scaler_id = -1; |
465c120c MR |
13475 | primary->pipe = pipe; |
13476 | primary->plane = pipe; | |
c59cb179 MR |
13477 | primary->check_plane = intel_check_primary_plane; |
13478 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13479 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13480 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13481 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13482 | primary->plane = !pipe; | |
13483 | ||
13484 | if (INTEL_INFO(dev)->gen <= 3) { | |
13485 | intel_primary_formats = intel_primary_formats_gen2; | |
13486 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
13487 | } else { | |
13488 | intel_primary_formats = intel_primary_formats_gen4; | |
13489 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
13490 | } | |
13491 | ||
13492 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13493 | &intel_plane_funcs, |
465c120c MR |
13494 | intel_primary_formats, num_formats, |
13495 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13496 | |
3b7a5119 SJ |
13497 | if (INTEL_INFO(dev)->gen >= 4) |
13498 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13499 | |
ea2c67bb MR |
13500 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13501 | ||
465c120c MR |
13502 | return &primary->base; |
13503 | } | |
13504 | ||
3b7a5119 SJ |
13505 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13506 | { | |
13507 | if (!dev->mode_config.rotation_property) { | |
13508 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13509 | BIT(DRM_ROTATE_180); | |
13510 | ||
13511 | if (INTEL_INFO(dev)->gen >= 9) | |
13512 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13513 | ||
13514 | dev->mode_config.rotation_property = | |
13515 | drm_mode_create_rotation_property(dev, flags); | |
13516 | } | |
13517 | if (dev->mode_config.rotation_property) | |
13518 | drm_object_attach_property(&plane->base.base, | |
13519 | dev->mode_config.rotation_property, | |
13520 | plane->base.state->rotation); | |
13521 | } | |
13522 | ||
3d7d6510 | 13523 | static int |
852e787c GP |
13524 | intel_check_cursor_plane(struct drm_plane *plane, |
13525 | struct intel_plane_state *state) | |
3d7d6510 | 13526 | { |
2b875c22 | 13527 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13528 | struct drm_device *dev = plane->dev; |
2b875c22 | 13529 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13530 | struct drm_rect *dest = &state->dst; |
13531 | struct drm_rect *src = &state->src; | |
13532 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13533 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13534 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13535 | unsigned stride; |
13536 | int ret; | |
3d7d6510 | 13537 | |
ea2c67bb MR |
13538 | crtc = crtc ? crtc : plane->crtc; |
13539 | intel_crtc = to_intel_crtc(crtc); | |
13540 | ||
757f9a3e | 13541 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13542 | src, dest, clip, |
3d7d6510 MR |
13543 | DRM_PLANE_HELPER_NO_SCALING, |
13544 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13545 | true, true, &state->visible); |
757f9a3e GP |
13546 | if (ret) |
13547 | return ret; | |
13548 | ||
13549 | ||
13550 | /* if we want to turn off the cursor ignore width and height */ | |
13551 | if (!obj) | |
32b7eeec | 13552 | goto finish; |
757f9a3e | 13553 | |
757f9a3e | 13554 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13555 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13556 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13557 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13558 | return -EINVAL; |
13559 | } | |
13560 | ||
ea2c67bb MR |
13561 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13562 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13563 | DRM_DEBUG_KMS("buffer is too small\n"); |
13564 | return -ENOMEM; | |
13565 | } | |
13566 | ||
3a656b54 | 13567 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13568 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13569 | ret = -EINVAL; | |
13570 | } | |
757f9a3e | 13571 | |
32b7eeec MR |
13572 | finish: |
13573 | if (intel_crtc->active) { | |
3749f463 | 13574 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13575 | intel_crtc->atomic.update_wm = true; |
13576 | ||
13577 | intel_crtc->atomic.fb_bits |= | |
13578 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13579 | } | |
13580 | ||
757f9a3e | 13581 | return ret; |
852e787c | 13582 | } |
3d7d6510 | 13583 | |
a8ad0d8e ML |
13584 | static void |
13585 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13586 | struct drm_crtc *crtc, | |
13587 | bool force) | |
13588 | { | |
13589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13590 | ||
13591 | if (!force) { | |
13592 | plane->fb = NULL; | |
13593 | intel_crtc->cursor_bo = NULL; | |
13594 | intel_crtc->cursor_addr = 0; | |
13595 | } | |
13596 | ||
13597 | intel_crtc_update_cursor(crtc, false); | |
13598 | } | |
13599 | ||
f4a2cf29 | 13600 | static void |
852e787c GP |
13601 | intel_commit_cursor_plane(struct drm_plane *plane, |
13602 | struct intel_plane_state *state) | |
13603 | { | |
2b875c22 | 13604 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13605 | struct drm_device *dev = plane->dev; |
13606 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13607 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13608 | uint32_t addr; |
852e787c | 13609 | |
ea2c67bb MR |
13610 | crtc = crtc ? crtc : plane->crtc; |
13611 | intel_crtc = to_intel_crtc(crtc); | |
13612 | ||
2b875c22 | 13613 | plane->fb = state->base.fb; |
ea2c67bb MR |
13614 | crtc->cursor_x = state->base.crtc_x; |
13615 | crtc->cursor_y = state->base.crtc_y; | |
13616 | ||
a912f12f GP |
13617 | if (intel_crtc->cursor_bo == obj) |
13618 | goto update; | |
4ed91096 | 13619 | |
f4a2cf29 | 13620 | if (!obj) |
a912f12f | 13621 | addr = 0; |
f4a2cf29 | 13622 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13623 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13624 | else |
a912f12f | 13625 | addr = obj->phys_handle->busaddr; |
852e787c | 13626 | |
a912f12f GP |
13627 | intel_crtc->cursor_addr = addr; |
13628 | intel_crtc->cursor_bo = obj; | |
13629 | update: | |
852e787c | 13630 | |
32b7eeec | 13631 | if (intel_crtc->active) |
a912f12f | 13632 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13633 | } |
13634 | ||
3d7d6510 MR |
13635 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13636 | int pipe) | |
13637 | { | |
13638 | struct intel_plane *cursor; | |
8e7d688b | 13639 | struct intel_plane_state *state; |
3d7d6510 MR |
13640 | |
13641 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13642 | if (cursor == NULL) | |
13643 | return NULL; | |
13644 | ||
8e7d688b MR |
13645 | state = intel_create_plane_state(&cursor->base); |
13646 | if (!state) { | |
ea2c67bb MR |
13647 | kfree(cursor); |
13648 | return NULL; | |
13649 | } | |
8e7d688b | 13650 | cursor->base.state = &state->base; |
ea2c67bb | 13651 | |
3d7d6510 MR |
13652 | cursor->can_scale = false; |
13653 | cursor->max_downscale = 1; | |
13654 | cursor->pipe = pipe; | |
13655 | cursor->plane = pipe; | |
549e2bfb | 13656 | state->scaler_id = -1; |
c59cb179 MR |
13657 | cursor->check_plane = intel_check_cursor_plane; |
13658 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13659 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13660 | |
13661 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13662 | &intel_plane_funcs, |
3d7d6510 MR |
13663 | intel_cursor_formats, |
13664 | ARRAY_SIZE(intel_cursor_formats), | |
13665 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13666 | |
13667 | if (INTEL_INFO(dev)->gen >= 4) { | |
13668 | if (!dev->mode_config.rotation_property) | |
13669 | dev->mode_config.rotation_property = | |
13670 | drm_mode_create_rotation_property(dev, | |
13671 | BIT(DRM_ROTATE_0) | | |
13672 | BIT(DRM_ROTATE_180)); | |
13673 | if (dev->mode_config.rotation_property) | |
13674 | drm_object_attach_property(&cursor->base.base, | |
13675 | dev->mode_config.rotation_property, | |
8e7d688b | 13676 | state->base.rotation); |
4398ad45 VS |
13677 | } |
13678 | ||
ea2c67bb MR |
13679 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13680 | ||
3d7d6510 MR |
13681 | return &cursor->base; |
13682 | } | |
13683 | ||
549e2bfb CK |
13684 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13685 | struct intel_crtc_state *crtc_state) | |
13686 | { | |
13687 | int i; | |
13688 | struct intel_scaler *intel_scaler; | |
13689 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13690 | ||
13691 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13692 | intel_scaler = &scaler_state->scalers[i]; | |
13693 | intel_scaler->in_use = 0; | |
13694 | intel_scaler->id = i; | |
13695 | ||
13696 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13697 | } | |
13698 | ||
13699 | scaler_state->scaler_id = -1; | |
13700 | } | |
13701 | ||
b358d0a6 | 13702 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13703 | { |
fbee40df | 13704 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13705 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13706 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13707 | struct drm_plane *primary = NULL; |
13708 | struct drm_plane *cursor = NULL; | |
465c120c | 13709 | int i, ret; |
79e53945 | 13710 | |
955382f3 | 13711 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13712 | if (intel_crtc == NULL) |
13713 | return; | |
13714 | ||
f5de6e07 ACO |
13715 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13716 | if (!crtc_state) | |
13717 | goto fail; | |
13718 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13719 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13720 | |
549e2bfb CK |
13721 | /* initialize shared scalers */ |
13722 | if (INTEL_INFO(dev)->gen >= 9) { | |
13723 | if (pipe == PIPE_C) | |
13724 | intel_crtc->num_scalers = 1; | |
13725 | else | |
13726 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13727 | ||
13728 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13729 | } | |
13730 | ||
465c120c | 13731 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13732 | if (!primary) |
13733 | goto fail; | |
13734 | ||
13735 | cursor = intel_cursor_plane_create(dev, pipe); | |
13736 | if (!cursor) | |
13737 | goto fail; | |
13738 | ||
465c120c | 13739 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13740 | cursor, &intel_crtc_funcs); |
13741 | if (ret) | |
13742 | goto fail; | |
79e53945 JB |
13743 | |
13744 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13745 | for (i = 0; i < 256; i++) { |
13746 | intel_crtc->lut_r[i] = i; | |
13747 | intel_crtc->lut_g[i] = i; | |
13748 | intel_crtc->lut_b[i] = i; | |
13749 | } | |
13750 | ||
1f1c2e24 VS |
13751 | /* |
13752 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13753 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13754 | */ |
80824003 JB |
13755 | intel_crtc->pipe = pipe; |
13756 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13757 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13758 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13759 | intel_crtc->plane = !pipe; |
80824003 JB |
13760 | } |
13761 | ||
4b0e333e CW |
13762 | intel_crtc->cursor_base = ~0; |
13763 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13764 | intel_crtc->cursor_size = ~0; |
8d7849db | 13765 | |
22fd0fab JB |
13766 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13767 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13768 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13769 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13770 | ||
9362c7c5 ACO |
13771 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13772 | ||
79e53945 | 13773 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13774 | |
13775 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13776 | return; |
13777 | ||
13778 | fail: | |
13779 | if (primary) | |
13780 | drm_plane_cleanup(primary); | |
13781 | if (cursor) | |
13782 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13783 | kfree(crtc_state); |
3d7d6510 | 13784 | kfree(intel_crtc); |
79e53945 JB |
13785 | } |
13786 | ||
752aa88a JB |
13787 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13788 | { | |
13789 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13790 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13791 | |
51fd371b | 13792 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13793 | |
d3babd3f | 13794 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13795 | return INVALID_PIPE; |
13796 | ||
13797 | return to_intel_crtc(encoder->crtc)->pipe; | |
13798 | } | |
13799 | ||
08d7b3d1 | 13800 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13801 | struct drm_file *file) |
08d7b3d1 | 13802 | { |
08d7b3d1 | 13803 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13804 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13805 | struct intel_crtc *crtc; |
08d7b3d1 | 13806 | |
7707e653 | 13807 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13808 | |
7707e653 | 13809 | if (!drmmode_crtc) { |
08d7b3d1 | 13810 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13811 | return -ENOENT; |
08d7b3d1 CW |
13812 | } |
13813 | ||
7707e653 | 13814 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13815 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13816 | |
c05422d5 | 13817 | return 0; |
08d7b3d1 CW |
13818 | } |
13819 | ||
66a9278e | 13820 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13821 | { |
66a9278e DV |
13822 | struct drm_device *dev = encoder->base.dev; |
13823 | struct intel_encoder *source_encoder; | |
79e53945 | 13824 | int index_mask = 0; |
79e53945 JB |
13825 | int entry = 0; |
13826 | ||
b2784e15 | 13827 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13828 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13829 | index_mask |= (1 << entry); |
13830 | ||
79e53945 JB |
13831 | entry++; |
13832 | } | |
4ef69c7a | 13833 | |
79e53945 JB |
13834 | return index_mask; |
13835 | } | |
13836 | ||
4d302442 CW |
13837 | static bool has_edp_a(struct drm_device *dev) |
13838 | { | |
13839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13840 | ||
13841 | if (!IS_MOBILE(dev)) | |
13842 | return false; | |
13843 | ||
13844 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13845 | return false; | |
13846 | ||
e3589908 | 13847 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13848 | return false; |
13849 | ||
13850 | return true; | |
13851 | } | |
13852 | ||
84b4e042 JB |
13853 | static bool intel_crt_present(struct drm_device *dev) |
13854 | { | |
13855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13856 | ||
884497ed DL |
13857 | if (INTEL_INFO(dev)->gen >= 9) |
13858 | return false; | |
13859 | ||
cf404ce4 | 13860 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13861 | return false; |
13862 | ||
13863 | if (IS_CHERRYVIEW(dev)) | |
13864 | return false; | |
13865 | ||
13866 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13867 | return false; | |
13868 | ||
13869 | return true; | |
13870 | } | |
13871 | ||
79e53945 JB |
13872 | static void intel_setup_outputs(struct drm_device *dev) |
13873 | { | |
725e30ad | 13874 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13875 | struct intel_encoder *encoder; |
cb0953d7 | 13876 | bool dpd_is_edp = false; |
79e53945 | 13877 | |
c9093354 | 13878 | intel_lvds_init(dev); |
79e53945 | 13879 | |
84b4e042 | 13880 | if (intel_crt_present(dev)) |
79935fca | 13881 | intel_crt_init(dev); |
cb0953d7 | 13882 | |
c776eb2e VK |
13883 | if (IS_BROXTON(dev)) { |
13884 | /* | |
13885 | * FIXME: Broxton doesn't support port detection via the | |
13886 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13887 | * detect the ports. | |
13888 | */ | |
13889 | intel_ddi_init(dev, PORT_A); | |
13890 | intel_ddi_init(dev, PORT_B); | |
13891 | intel_ddi_init(dev, PORT_C); | |
13892 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13893 | int found; |
13894 | ||
de31facd JB |
13895 | /* |
13896 | * Haswell uses DDI functions to detect digital outputs. | |
13897 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13898 | * it's there. | |
13899 | */ | |
0e72a5b5 | 13900 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13901 | /* WaIgnoreDDIAStrap: skl */ |
13902 | if (found || | |
13903 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13904 | intel_ddi_init(dev, PORT_A); |
13905 | ||
13906 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13907 | * register */ | |
13908 | found = I915_READ(SFUSE_STRAP); | |
13909 | ||
13910 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13911 | intel_ddi_init(dev, PORT_B); | |
13912 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13913 | intel_ddi_init(dev, PORT_C); | |
13914 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13915 | intel_ddi_init(dev, PORT_D); | |
13916 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13917 | int found; |
5d8a7752 | 13918 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13919 | |
13920 | if (has_edp_a(dev)) | |
13921 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13922 | |
dc0fa718 | 13923 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13924 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13925 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13926 | if (!found) |
e2debe91 | 13927 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13928 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13929 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13930 | } |
13931 | ||
dc0fa718 | 13932 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13933 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13934 | |
dc0fa718 | 13935 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13936 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13937 | |
5eb08b69 | 13938 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13939 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13940 | |
270b3042 | 13941 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13942 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13943 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13944 | /* |
13945 | * The DP_DETECTED bit is the latched state of the DDC | |
13946 | * SDA pin at boot. However since eDP doesn't require DDC | |
13947 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13948 | * eDP ports may have been muxed to an alternate function. | |
13949 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13950 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13951 | * detect eDP ports. | |
13952 | */ | |
d2182a66 VS |
13953 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13954 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13955 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13956 | PORT_B); | |
e17ac6db VS |
13957 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13958 | intel_dp_is_edp(dev, PORT_B)) | |
13959 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13960 | |
d2182a66 VS |
13961 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13962 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13963 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13964 | PORT_C); | |
e17ac6db VS |
13965 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13966 | intel_dp_is_edp(dev, PORT_C)) | |
13967 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13968 | |
9418c1f1 | 13969 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13970 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13971 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13972 | PORT_D); | |
e17ac6db VS |
13973 | /* eDP not supported on port D, so don't check VBT */ |
13974 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13975 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13976 | } |
13977 | ||
3cfca973 | 13978 | intel_dsi_init(dev); |
103a196f | 13979 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13980 | bool found = false; |
7d57382e | 13981 | |
e2debe91 | 13982 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13983 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13984 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13985 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13986 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13987 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13988 | } |
27185ae1 | 13989 | |
e7281eab | 13990 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13991 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13992 | } |
13520b05 KH |
13993 | |
13994 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13995 | |
e2debe91 | 13996 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13997 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13998 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13999 | } |
27185ae1 | 14000 | |
e2debe91 | 14001 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14002 | |
b01f2c3a JB |
14003 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
14004 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 14005 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14006 | } |
e7281eab | 14007 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14008 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14009 | } |
27185ae1 | 14010 | |
b01f2c3a | 14011 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 14012 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14013 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14014 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14015 | intel_dvo_init(dev); |
14016 | ||
103a196f | 14017 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14018 | intel_tv_init(dev); |
14019 | ||
0bc12bcb | 14020 | intel_psr_init(dev); |
7c8f8a70 | 14021 | |
b2784e15 | 14022 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14023 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14024 | encoder->base.possible_clones = | |
66a9278e | 14025 | intel_encoder_clones(encoder); |
79e53945 | 14026 | } |
47356eb6 | 14027 | |
dde86e2d | 14028 | intel_init_pch_refclk(dev); |
270b3042 DV |
14029 | |
14030 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14031 | } |
14032 | ||
14033 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14034 | { | |
60a5ca01 | 14035 | struct drm_device *dev = fb->dev; |
79e53945 | 14036 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14037 | |
ef2d633e | 14038 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14039 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14040 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14041 | drm_gem_object_unreference(&intel_fb->obj->base); |
14042 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14043 | kfree(intel_fb); |
14044 | } | |
14045 | ||
14046 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14047 | struct drm_file *file, |
79e53945 JB |
14048 | unsigned int *handle) |
14049 | { | |
14050 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14051 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14052 | |
05394f39 | 14053 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14054 | } |
14055 | ||
14056 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14057 | .destroy = intel_user_framebuffer_destroy, | |
14058 | .create_handle = intel_user_framebuffer_create_handle, | |
14059 | }; | |
14060 | ||
b321803d DL |
14061 | static |
14062 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14063 | uint32_t pixel_format) | |
14064 | { | |
14065 | u32 gen = INTEL_INFO(dev)->gen; | |
14066 | ||
14067 | if (gen >= 9) { | |
14068 | /* "The stride in bytes must not exceed the of the size of 8K | |
14069 | * pixels and 32K bytes." | |
14070 | */ | |
14071 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14072 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14073 | return 32*1024; | |
14074 | } else if (gen >= 4) { | |
14075 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14076 | return 16*1024; | |
14077 | else | |
14078 | return 32*1024; | |
14079 | } else if (gen >= 3) { | |
14080 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14081 | return 8*1024; | |
14082 | else | |
14083 | return 16*1024; | |
14084 | } else { | |
14085 | /* XXX DSPC is limited to 4k tiled */ | |
14086 | return 8*1024; | |
14087 | } | |
14088 | } | |
14089 | ||
b5ea642a DV |
14090 | static int intel_framebuffer_init(struct drm_device *dev, |
14091 | struct intel_framebuffer *intel_fb, | |
14092 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14093 | struct drm_i915_gem_object *obj) | |
79e53945 | 14094 | { |
6761dd31 | 14095 | unsigned int aligned_height; |
79e53945 | 14096 | int ret; |
b321803d | 14097 | u32 pitch_limit, stride_alignment; |
79e53945 | 14098 | |
dd4916c5 DV |
14099 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14100 | ||
2a80eada DV |
14101 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14102 | /* Enforce that fb modifier and tiling mode match, but only for | |
14103 | * X-tiled. This is needed for FBC. */ | |
14104 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14105 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14106 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14107 | return -EINVAL; | |
14108 | } | |
14109 | } else { | |
14110 | if (obj->tiling_mode == I915_TILING_X) | |
14111 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14112 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14113 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14114 | return -EINVAL; | |
14115 | } | |
14116 | } | |
14117 | ||
9a8f0a12 TU |
14118 | /* Passed in modifier sanity checking. */ |
14119 | switch (mode_cmd->modifier[0]) { | |
14120 | case I915_FORMAT_MOD_Y_TILED: | |
14121 | case I915_FORMAT_MOD_Yf_TILED: | |
14122 | if (INTEL_INFO(dev)->gen < 9) { | |
14123 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14124 | mode_cmd->modifier[0]); | |
14125 | return -EINVAL; | |
14126 | } | |
14127 | case DRM_FORMAT_MOD_NONE: | |
14128 | case I915_FORMAT_MOD_X_TILED: | |
14129 | break; | |
14130 | default: | |
c0f40428 JB |
14131 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14132 | mode_cmd->modifier[0]); | |
57cd6508 | 14133 | return -EINVAL; |
c16ed4be | 14134 | } |
57cd6508 | 14135 | |
b321803d DL |
14136 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14137 | mode_cmd->pixel_format); | |
14138 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14139 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14140 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14141 | return -EINVAL; |
c16ed4be | 14142 | } |
57cd6508 | 14143 | |
b321803d DL |
14144 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14145 | mode_cmd->pixel_format); | |
a35cdaa0 | 14146 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14147 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14148 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14149 | "tiled" : "linear", |
a35cdaa0 | 14150 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14151 | return -EINVAL; |
c16ed4be | 14152 | } |
5d7bd705 | 14153 | |
2a80eada | 14154 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14155 | mode_cmd->pitches[0] != obj->stride) { |
14156 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14157 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14158 | return -EINVAL; |
c16ed4be | 14159 | } |
5d7bd705 | 14160 | |
57779d06 | 14161 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14162 | switch (mode_cmd->pixel_format) { |
57779d06 | 14163 | case DRM_FORMAT_C8: |
04b3924d VS |
14164 | case DRM_FORMAT_RGB565: |
14165 | case DRM_FORMAT_XRGB8888: | |
14166 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14167 | break; |
14168 | case DRM_FORMAT_XRGB1555: | |
14169 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 14170 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14171 | DRM_DEBUG("unsupported pixel format: %s\n", |
14172 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14173 | return -EINVAL; |
c16ed4be | 14174 | } |
57779d06 VS |
14175 | break; |
14176 | case DRM_FORMAT_XBGR8888: | |
14177 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
14178 | case DRM_FORMAT_XRGB2101010: |
14179 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
14180 | case DRM_FORMAT_XBGR2101010: |
14181 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 14182 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14183 | DRM_DEBUG("unsupported pixel format: %s\n", |
14184 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14185 | return -EINVAL; |
c16ed4be | 14186 | } |
b5626747 | 14187 | break; |
04b3924d VS |
14188 | case DRM_FORMAT_YUYV: |
14189 | case DRM_FORMAT_UYVY: | |
14190 | case DRM_FORMAT_YVYU: | |
14191 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14192 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14193 | DRM_DEBUG("unsupported pixel format: %s\n", |
14194 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14195 | return -EINVAL; |
c16ed4be | 14196 | } |
57cd6508 CW |
14197 | break; |
14198 | default: | |
4ee62c76 VS |
14199 | DRM_DEBUG("unsupported pixel format: %s\n", |
14200 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14201 | return -EINVAL; |
14202 | } | |
14203 | ||
90f9a336 VS |
14204 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14205 | if (mode_cmd->offsets[0] != 0) | |
14206 | return -EINVAL; | |
14207 | ||
ec2c981e | 14208 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14209 | mode_cmd->pixel_format, |
14210 | mode_cmd->modifier[0]); | |
53155c0a DV |
14211 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14212 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14213 | return -EINVAL; | |
14214 | ||
c7d73f6a DV |
14215 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14216 | intel_fb->obj = obj; | |
80075d49 | 14217 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14218 | |
79e53945 JB |
14219 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14220 | if (ret) { | |
14221 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14222 | return ret; | |
14223 | } | |
14224 | ||
79e53945 JB |
14225 | return 0; |
14226 | } | |
14227 | ||
79e53945 JB |
14228 | static struct drm_framebuffer * |
14229 | intel_user_framebuffer_create(struct drm_device *dev, | |
14230 | struct drm_file *filp, | |
308e5bcb | 14231 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14232 | { |
05394f39 | 14233 | struct drm_i915_gem_object *obj; |
79e53945 | 14234 | |
308e5bcb JB |
14235 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14236 | mode_cmd->handles[0])); | |
c8725226 | 14237 | if (&obj->base == NULL) |
cce13ff7 | 14238 | return ERR_PTR(-ENOENT); |
79e53945 | 14239 | |
d2dff872 | 14240 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14241 | } |
14242 | ||
4520f53a | 14243 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14244 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14245 | { |
14246 | } | |
14247 | #endif | |
14248 | ||
79e53945 | 14249 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14250 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14251 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14252 | .atomic_check = intel_atomic_check, |
14253 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14254 | }; |
14255 | ||
e70236a8 JB |
14256 | /* Set up chip specific display functions */ |
14257 | static void intel_init_display(struct drm_device *dev) | |
14258 | { | |
14259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14260 | ||
ee9300bb DV |
14261 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14262 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14263 | else if (IS_CHERRYVIEW(dev)) |
14264 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14265 | else if (IS_VALLEYVIEW(dev)) |
14266 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14267 | else if (IS_PINEVIEW(dev)) | |
14268 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14269 | else | |
14270 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14271 | ||
bc8d7dff DL |
14272 | if (INTEL_INFO(dev)->gen >= 9) { |
14273 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14274 | dev_priv->display.get_initial_plane_config = |
14275 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14276 | dev_priv->display.crtc_compute_clock = |
14277 | haswell_crtc_compute_clock; | |
14278 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14279 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14280 | dev_priv->display.off = ironlake_crtc_off; | |
14281 | dev_priv->display.update_primary_plane = | |
14282 | skylake_update_primary_plane; | |
14283 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14284 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14285 | dev_priv->display.get_initial_plane_config = |
14286 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14287 | dev_priv->display.crtc_compute_clock = |
14288 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14289 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14290 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14291 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14292 | dev_priv->display.update_primary_plane = |
14293 | ironlake_update_primary_plane; | |
09b4ddf9 | 14294 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14295 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14296 | dev_priv->display.get_initial_plane_config = |
14297 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14298 | dev_priv->display.crtc_compute_clock = |
14299 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14300 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14301 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14302 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14303 | dev_priv->display.update_primary_plane = |
14304 | ironlake_update_primary_plane; | |
89b667f8 JB |
14305 | } else if (IS_VALLEYVIEW(dev)) { |
14306 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14307 | dev_priv->display.get_initial_plane_config = |
14308 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14309 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14310 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14311 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14312 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14313 | dev_priv->display.update_primary_plane = |
14314 | i9xx_update_primary_plane; | |
f564048e | 14315 | } else { |
0e8ffe1b | 14316 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14317 | dev_priv->display.get_initial_plane_config = |
14318 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14319 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14320 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14321 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14322 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14323 | dev_priv->display.update_primary_plane = |
14324 | i9xx_update_primary_plane; | |
f564048e | 14325 | } |
e70236a8 | 14326 | |
e70236a8 | 14327 | /* Returns the core display clock speed */ |
1652d19e VS |
14328 | if (IS_SKYLAKE(dev)) |
14329 | dev_priv->display.get_display_clock_speed = | |
14330 | skylake_get_display_clock_speed; | |
14331 | else if (IS_BROADWELL(dev)) | |
14332 | dev_priv->display.get_display_clock_speed = | |
14333 | broadwell_get_display_clock_speed; | |
14334 | else if (IS_HASWELL(dev)) | |
14335 | dev_priv->display.get_display_clock_speed = | |
14336 | haswell_get_display_clock_speed; | |
14337 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14338 | dev_priv->display.get_display_clock_speed = |
14339 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14340 | else if (IS_GEN5(dev)) |
14341 | dev_priv->display.get_display_clock_speed = | |
14342 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14343 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14344 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14345 | dev_priv->display.get_display_clock_speed = |
14346 | i945_get_display_clock_speed; | |
14347 | else if (IS_I915G(dev)) | |
14348 | dev_priv->display.get_display_clock_speed = | |
14349 | i915_get_display_clock_speed; | |
257a7ffc | 14350 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14351 | dev_priv->display.get_display_clock_speed = |
14352 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14353 | else if (IS_PINEVIEW(dev)) |
14354 | dev_priv->display.get_display_clock_speed = | |
14355 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14356 | else if (IS_I915GM(dev)) |
14357 | dev_priv->display.get_display_clock_speed = | |
14358 | i915gm_get_display_clock_speed; | |
14359 | else if (IS_I865G(dev)) | |
14360 | dev_priv->display.get_display_clock_speed = | |
14361 | i865_get_display_clock_speed; | |
f0f8a9ce | 14362 | else if (IS_I85X(dev)) |
e70236a8 JB |
14363 | dev_priv->display.get_display_clock_speed = |
14364 | i855_get_display_clock_speed; | |
14365 | else /* 852, 830 */ | |
14366 | dev_priv->display.get_display_clock_speed = | |
14367 | i830_get_display_clock_speed; | |
14368 | ||
7c10a2b5 | 14369 | if (IS_GEN5(dev)) { |
3bb11b53 | 14370 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14371 | } else if (IS_GEN6(dev)) { |
14372 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14373 | } else if (IS_IVYBRIDGE(dev)) { |
14374 | /* FIXME: detect B0+ stepping and use auto training */ | |
14375 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14376 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14377 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14378 | } else if (IS_VALLEYVIEW(dev)) { |
14379 | dev_priv->display.modeset_global_resources = | |
14380 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14381 | } else if (IS_BROXTON(dev)) { |
14382 | dev_priv->display.modeset_global_resources = | |
14383 | broxton_modeset_global_resources; | |
e70236a8 | 14384 | } |
8c9f3aaf | 14385 | |
8c9f3aaf JB |
14386 | switch (INTEL_INFO(dev)->gen) { |
14387 | case 2: | |
14388 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14389 | break; | |
14390 | ||
14391 | case 3: | |
14392 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14393 | break; | |
14394 | ||
14395 | case 4: | |
14396 | case 5: | |
14397 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14398 | break; | |
14399 | ||
14400 | case 6: | |
14401 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14402 | break; | |
7c9017e5 | 14403 | case 7: |
4e0bbc31 | 14404 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14405 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14406 | break; | |
830c81db | 14407 | case 9: |
ba343e02 TU |
14408 | /* Drop through - unsupported since execlist only. */ |
14409 | default: | |
14410 | /* Default just returns -ENODEV to indicate unsupported */ | |
14411 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14412 | } |
7bd688cd JN |
14413 | |
14414 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14415 | |
14416 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14417 | } |
14418 | ||
b690e96c JB |
14419 | /* |
14420 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14421 | * resume, or other times. This quirk makes sure that's the case for | |
14422 | * affected systems. | |
14423 | */ | |
0206e353 | 14424 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14425 | { |
14426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14427 | ||
14428 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14429 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14430 | } |
14431 | ||
b6b5d049 VS |
14432 | static void quirk_pipeb_force(struct drm_device *dev) |
14433 | { | |
14434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14435 | ||
14436 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14437 | DRM_INFO("applying pipe b force quirk\n"); | |
14438 | } | |
14439 | ||
435793df KP |
14440 | /* |
14441 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14442 | */ | |
14443 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14444 | { | |
14445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14446 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14447 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14448 | } |
14449 | ||
4dca20ef | 14450 | /* |
5a15ab5b CE |
14451 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14452 | * brightness value | |
4dca20ef CE |
14453 | */ |
14454 | static void quirk_invert_brightness(struct drm_device *dev) | |
14455 | { | |
14456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14457 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14458 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14459 | } |
14460 | ||
9c72cc6f SD |
14461 | /* Some VBT's incorrectly indicate no backlight is present */ |
14462 | static void quirk_backlight_present(struct drm_device *dev) | |
14463 | { | |
14464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14465 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14466 | DRM_INFO("applying backlight present quirk\n"); | |
14467 | } | |
14468 | ||
b690e96c JB |
14469 | struct intel_quirk { |
14470 | int device; | |
14471 | int subsystem_vendor; | |
14472 | int subsystem_device; | |
14473 | void (*hook)(struct drm_device *dev); | |
14474 | }; | |
14475 | ||
5f85f176 EE |
14476 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14477 | struct intel_dmi_quirk { | |
14478 | void (*hook)(struct drm_device *dev); | |
14479 | const struct dmi_system_id (*dmi_id_list)[]; | |
14480 | }; | |
14481 | ||
14482 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14483 | { | |
14484 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14485 | return 1; | |
14486 | } | |
14487 | ||
14488 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14489 | { | |
14490 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14491 | { | |
14492 | .callback = intel_dmi_reverse_brightness, | |
14493 | .ident = "NCR Corporation", | |
14494 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14495 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14496 | }, | |
14497 | }, | |
14498 | { } /* terminating entry */ | |
14499 | }, | |
14500 | .hook = quirk_invert_brightness, | |
14501 | }, | |
14502 | }; | |
14503 | ||
c43b5634 | 14504 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 14505 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 14506 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 14507 | |
b690e96c JB |
14508 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14509 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14510 | ||
b690e96c JB |
14511 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14512 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14513 | ||
5f080c0f VS |
14514 | /* 830 needs to leave pipe A & dpll A up */ |
14515 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14516 | ||
b6b5d049 VS |
14517 | /* 830 needs to leave pipe B & dpll B up */ |
14518 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14519 | ||
435793df KP |
14520 | /* Lenovo U160 cannot use SSC on LVDS */ |
14521 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14522 | |
14523 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14524 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14525 | |
be505f64 AH |
14526 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14527 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14528 | ||
14529 | /* Acer/eMachines G725 */ | |
14530 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14531 | ||
14532 | /* Acer/eMachines e725 */ | |
14533 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14534 | ||
14535 | /* Acer/Packard Bell NCL20 */ | |
14536 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14537 | ||
14538 | /* Acer Aspire 4736Z */ | |
14539 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14540 | |
14541 | /* Acer Aspire 5336 */ | |
14542 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14543 | |
14544 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14545 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14546 | |
dfb3d47b SD |
14547 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14548 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14549 | ||
b2a9601c | 14550 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14551 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14552 | ||
d4967d8c SD |
14553 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14554 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14555 | |
14556 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14557 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14558 | |
14559 | /* Dell Chromebook 11 */ | |
14560 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14561 | }; |
14562 | ||
14563 | static void intel_init_quirks(struct drm_device *dev) | |
14564 | { | |
14565 | struct pci_dev *d = dev->pdev; | |
14566 | int i; | |
14567 | ||
14568 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14569 | struct intel_quirk *q = &intel_quirks[i]; | |
14570 | ||
14571 | if (d->device == q->device && | |
14572 | (d->subsystem_vendor == q->subsystem_vendor || | |
14573 | q->subsystem_vendor == PCI_ANY_ID) && | |
14574 | (d->subsystem_device == q->subsystem_device || | |
14575 | q->subsystem_device == PCI_ANY_ID)) | |
14576 | q->hook(dev); | |
14577 | } | |
5f85f176 EE |
14578 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14579 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14580 | intel_dmi_quirks[i].hook(dev); | |
14581 | } | |
b690e96c JB |
14582 | } |
14583 | ||
9cce37f4 JB |
14584 | /* Disable the VGA plane that we never use */ |
14585 | static void i915_disable_vga(struct drm_device *dev) | |
14586 | { | |
14587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14588 | u8 sr1; | |
766aa1c4 | 14589 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14590 | |
2b37c616 | 14591 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14592 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14593 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14594 | sr1 = inb(VGA_SR_DATA); |
14595 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14596 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14597 | udelay(300); | |
14598 | ||
01f5a626 | 14599 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14600 | POSTING_READ(vga_reg); |
14601 | } | |
14602 | ||
f817586c DV |
14603 | void intel_modeset_init_hw(struct drm_device *dev) |
14604 | { | |
a8f78b58 ED |
14605 | intel_prepare_ddi(dev); |
14606 | ||
f8bf63fd VS |
14607 | if (IS_VALLEYVIEW(dev)) |
14608 | vlv_update_cdclk(dev); | |
14609 | ||
f817586c DV |
14610 | intel_init_clock_gating(dev); |
14611 | ||
8090c6b9 | 14612 | intel_enable_gt_powersave(dev); |
f817586c DV |
14613 | } |
14614 | ||
79e53945 JB |
14615 | void intel_modeset_init(struct drm_device *dev) |
14616 | { | |
652c393a | 14617 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14618 | int sprite, ret; |
8cc87b75 | 14619 | enum pipe pipe; |
46f297fb | 14620 | struct intel_crtc *crtc; |
79e53945 JB |
14621 | |
14622 | drm_mode_config_init(dev); | |
14623 | ||
14624 | dev->mode_config.min_width = 0; | |
14625 | dev->mode_config.min_height = 0; | |
14626 | ||
019d96cb DA |
14627 | dev->mode_config.preferred_depth = 24; |
14628 | dev->mode_config.prefer_shadow = 1; | |
14629 | ||
25bab385 TU |
14630 | dev->mode_config.allow_fb_modifiers = true; |
14631 | ||
e6ecefaa | 14632 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14633 | |
b690e96c JB |
14634 | intel_init_quirks(dev); |
14635 | ||
1fa61106 ED |
14636 | intel_init_pm(dev); |
14637 | ||
e3c74757 BW |
14638 | if (INTEL_INFO(dev)->num_pipes == 0) |
14639 | return; | |
14640 | ||
e70236a8 | 14641 | intel_init_display(dev); |
7c10a2b5 | 14642 | intel_init_audio(dev); |
e70236a8 | 14643 | |
a6c45cf0 CW |
14644 | if (IS_GEN2(dev)) { |
14645 | dev->mode_config.max_width = 2048; | |
14646 | dev->mode_config.max_height = 2048; | |
14647 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14648 | dev->mode_config.max_width = 4096; |
14649 | dev->mode_config.max_height = 4096; | |
79e53945 | 14650 | } else { |
a6c45cf0 CW |
14651 | dev->mode_config.max_width = 8192; |
14652 | dev->mode_config.max_height = 8192; | |
79e53945 | 14653 | } |
068be561 | 14654 | |
dc41c154 VS |
14655 | if (IS_845G(dev) || IS_I865G(dev)) { |
14656 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14657 | dev->mode_config.cursor_height = 1023; | |
14658 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14659 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14660 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14661 | } else { | |
14662 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14663 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14664 | } | |
14665 | ||
5d4545ae | 14666 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14667 | |
28c97730 | 14668 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14669 | INTEL_INFO(dev)->num_pipes, |
14670 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14671 | |
055e393f | 14672 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14673 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14674 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14675 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14676 | if (ret) |
06da8da2 | 14677 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14678 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14679 | } |
79e53945 JB |
14680 | } |
14681 | ||
f42bb70d JB |
14682 | intel_init_dpio(dev); |
14683 | ||
e72f9fbf | 14684 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14685 | |
9cce37f4 JB |
14686 | /* Just disable it once at startup */ |
14687 | i915_disable_vga(dev); | |
79e53945 | 14688 | intel_setup_outputs(dev); |
11be49eb CW |
14689 | |
14690 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14691 | intel_fbc_disable(dev); |
fa9fa083 | 14692 | |
6e9f798d | 14693 | drm_modeset_lock_all(dev); |
fa9fa083 | 14694 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14695 | drm_modeset_unlock_all(dev); |
46f297fb | 14696 | |
d3fcc808 | 14697 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14698 | if (!crtc->active) |
14699 | continue; | |
14700 | ||
46f297fb | 14701 | /* |
46f297fb JB |
14702 | * Note that reserving the BIOS fb up front prevents us |
14703 | * from stuffing other stolen allocations like the ring | |
14704 | * on top. This prevents some ugliness at boot time, and | |
14705 | * can even allow for smooth boot transitions if the BIOS | |
14706 | * fb is large enough for the active pipe configuration. | |
14707 | */ | |
5724dbd1 DL |
14708 | if (dev_priv->display.get_initial_plane_config) { |
14709 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14710 | &crtc->plane_config); |
14711 | /* | |
14712 | * If the fb is shared between multiple heads, we'll | |
14713 | * just get the first one. | |
14714 | */ | |
f6936e29 | 14715 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14716 | } |
46f297fb | 14717 | } |
2c7111db CW |
14718 | } |
14719 | ||
7fad798e DV |
14720 | static void intel_enable_pipe_a(struct drm_device *dev) |
14721 | { | |
14722 | struct intel_connector *connector; | |
14723 | struct drm_connector *crt = NULL; | |
14724 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14725 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14726 | |
14727 | /* We can't just switch on the pipe A, we need to set things up with a | |
14728 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14729 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14730 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14731 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14732 | crt = &connector->base; | |
14733 | break; | |
14734 | } | |
14735 | } | |
14736 | ||
14737 | if (!crt) | |
14738 | return; | |
14739 | ||
208bf9fd | 14740 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14741 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14742 | } |
14743 | ||
fa555837 DV |
14744 | static bool |
14745 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14746 | { | |
7eb552ae BW |
14747 | struct drm_device *dev = crtc->base.dev; |
14748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14749 | u32 reg, val; |
14750 | ||
7eb552ae | 14751 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14752 | return true; |
14753 | ||
14754 | reg = DSPCNTR(!crtc->plane); | |
14755 | val = I915_READ(reg); | |
14756 | ||
14757 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14758 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14759 | return false; | |
14760 | ||
14761 | return true; | |
14762 | } | |
14763 | ||
24929352 DV |
14764 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14765 | { | |
14766 | struct drm_device *dev = crtc->base.dev; | |
14767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14768 | u32 reg; |
24929352 | 14769 | |
24929352 | 14770 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14771 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14772 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14773 | ||
d3eaf884 | 14774 | /* restore vblank interrupts to correct state */ |
9625604c | 14775 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14776 | if (crtc->active) { |
14777 | update_scanline_offset(crtc); | |
9625604c DV |
14778 | drm_crtc_vblank_on(&crtc->base); |
14779 | } | |
d3eaf884 | 14780 | |
24929352 | 14781 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14782 | * disable the crtc (and hence change the state) if it is wrong. Note |
14783 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14784 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14785 | struct intel_connector *connector; |
14786 | bool plane; | |
14787 | ||
24929352 DV |
14788 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14789 | crtc->base.base.id); | |
14790 | ||
14791 | /* Pipe has the wrong plane attached and the plane is active. | |
14792 | * Temporarily change the plane mapping and disable everything | |
14793 | * ... */ | |
14794 | plane = crtc->plane; | |
b70709a6 | 14795 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 DV |
14796 | crtc->plane = !plane; |
14797 | dev_priv->display.crtc_disable(&crtc->base); | |
14798 | crtc->plane = plane; | |
14799 | ||
14800 | /* ... and break all links. */ | |
3a3371ff | 14801 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14802 | if (connector->encoder->base.crtc != &crtc->base) |
14803 | continue; | |
14804 | ||
7f1950fb EE |
14805 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14806 | connector->base.encoder = NULL; | |
24929352 | 14807 | } |
7f1950fb EE |
14808 | /* multiple connectors may have the same encoder: |
14809 | * handle them and break crtc link separately */ | |
3a3371ff | 14810 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14811 | if (connector->encoder->base.crtc == &crtc->base) { |
14812 | connector->encoder->base.crtc = NULL; | |
14813 | connector->encoder->connectors_active = false; | |
14814 | } | |
24929352 DV |
14815 | |
14816 | WARN_ON(crtc->active); | |
83d65738 | 14817 | crtc->base.state->enable = false; |
24929352 DV |
14818 | crtc->base.enabled = false; |
14819 | } | |
24929352 | 14820 | |
7fad798e DV |
14821 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14822 | crtc->pipe == PIPE_A && !crtc->active) { | |
14823 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14824 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14825 | * call below we restore the pipe to the right state, but leave | |
14826 | * the required bits on. */ | |
14827 | intel_enable_pipe_a(dev); | |
14828 | } | |
14829 | ||
24929352 DV |
14830 | /* Adjust the state of the output pipe according to whether we |
14831 | * have active connectors/encoders. */ | |
14832 | intel_crtc_update_dpms(&crtc->base); | |
14833 | ||
83d65738 | 14834 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14835 | struct intel_encoder *encoder; |
14836 | ||
14837 | /* This can happen either due to bugs in the get_hw_state | |
14838 | * functions or because the pipe is force-enabled due to the | |
14839 | * pipe A quirk. */ | |
14840 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14841 | crtc->base.base.id, | |
83d65738 | 14842 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14843 | crtc->active ? "enabled" : "disabled"); |
14844 | ||
83d65738 | 14845 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14846 | crtc->base.enabled = crtc->active; |
14847 | ||
14848 | /* Because we only establish the connector -> encoder -> | |
14849 | * crtc links if something is active, this means the | |
14850 | * crtc is now deactivated. Break the links. connector | |
14851 | * -> encoder links are only establish when things are | |
14852 | * actually up, hence no need to break them. */ | |
14853 | WARN_ON(crtc->active); | |
14854 | ||
14855 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14856 | WARN_ON(encoder->connectors_active); | |
14857 | encoder->base.crtc = NULL; | |
14858 | } | |
14859 | } | |
c5ab3bc0 | 14860 | |
a3ed6aad | 14861 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14862 | /* |
14863 | * We start out with underrun reporting disabled to avoid races. | |
14864 | * For correct bookkeeping mark this on active crtcs. | |
14865 | * | |
c5ab3bc0 DV |
14866 | * Also on gmch platforms we dont have any hardware bits to |
14867 | * disable the underrun reporting. Which means we need to start | |
14868 | * out with underrun reporting disabled also on inactive pipes, | |
14869 | * since otherwise we'll complain about the garbage we read when | |
14870 | * e.g. coming up after runtime pm. | |
14871 | * | |
4cc31489 DV |
14872 | * No protection against concurrent access is required - at |
14873 | * worst a fifo underrun happens which also sets this to false. | |
14874 | */ | |
14875 | crtc->cpu_fifo_underrun_disabled = true; | |
14876 | crtc->pch_fifo_underrun_disabled = true; | |
14877 | } | |
24929352 DV |
14878 | } |
14879 | ||
14880 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14881 | { | |
14882 | struct intel_connector *connector; | |
14883 | struct drm_device *dev = encoder->base.dev; | |
14884 | ||
14885 | /* We need to check both for a crtc link (meaning that the | |
14886 | * encoder is active and trying to read from a pipe) and the | |
14887 | * pipe itself being active. */ | |
14888 | bool has_active_crtc = encoder->base.crtc && | |
14889 | to_intel_crtc(encoder->base.crtc)->active; | |
14890 | ||
14891 | if (encoder->connectors_active && !has_active_crtc) { | |
14892 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14893 | encoder->base.base.id, | |
8e329a03 | 14894 | encoder->base.name); |
24929352 DV |
14895 | |
14896 | /* Connector is active, but has no active pipe. This is | |
14897 | * fallout from our resume register restoring. Disable | |
14898 | * the encoder manually again. */ | |
14899 | if (encoder->base.crtc) { | |
14900 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14901 | encoder->base.base.id, | |
8e329a03 | 14902 | encoder->base.name); |
24929352 | 14903 | encoder->disable(encoder); |
a62d1497 VS |
14904 | if (encoder->post_disable) |
14905 | encoder->post_disable(encoder); | |
24929352 | 14906 | } |
7f1950fb EE |
14907 | encoder->base.crtc = NULL; |
14908 | encoder->connectors_active = false; | |
24929352 DV |
14909 | |
14910 | /* Inconsistent output/port/pipe state happens presumably due to | |
14911 | * a bug in one of the get_hw_state functions. Or someplace else | |
14912 | * in our code, like the register restore mess on resume. Clamp | |
14913 | * things to off as a safer default. */ | |
3a3371ff | 14914 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14915 | if (connector->encoder != encoder) |
14916 | continue; | |
7f1950fb EE |
14917 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14918 | connector->base.encoder = NULL; | |
24929352 DV |
14919 | } |
14920 | } | |
14921 | /* Enabled encoders without active connectors will be fixed in | |
14922 | * the crtc fixup. */ | |
14923 | } | |
14924 | ||
04098753 | 14925 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14926 | { |
14927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14928 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14929 | |
04098753 ID |
14930 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14931 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14932 | i915_disable_vga(dev); | |
14933 | } | |
14934 | } | |
14935 | ||
14936 | void i915_redisable_vga(struct drm_device *dev) | |
14937 | { | |
14938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14939 | ||
8dc8a27c PZ |
14940 | /* This function can be called both from intel_modeset_setup_hw_state or |
14941 | * at a very early point in our resume sequence, where the power well | |
14942 | * structures are not yet restored. Since this function is at a very | |
14943 | * paranoid "someone might have enabled VGA while we were not looking" | |
14944 | * level, just check if the power well is enabled instead of trying to | |
14945 | * follow the "don't touch the power well if we don't need it" policy | |
14946 | * the rest of the driver uses. */ | |
f458ebbc | 14947 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14948 | return; |
14949 | ||
04098753 | 14950 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14951 | } |
14952 | ||
98ec7739 VS |
14953 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14954 | { | |
14955 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14956 | ||
14957 | if (!crtc->active) | |
14958 | return false; | |
14959 | ||
14960 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14961 | } | |
14962 | ||
30e984df | 14963 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14964 | { |
14965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14966 | enum pipe pipe; | |
24929352 DV |
14967 | struct intel_crtc *crtc; |
14968 | struct intel_encoder *encoder; | |
14969 | struct intel_connector *connector; | |
5358901f | 14970 | int i; |
24929352 | 14971 | |
d3fcc808 | 14972 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
14973 | struct drm_plane *primary = crtc->base.primary; |
14974 | struct intel_plane_state *plane_state; | |
14975 | ||
6e3c9717 | 14976 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14977 | |
6e3c9717 | 14978 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14979 | |
0e8ffe1b | 14980 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14981 | crtc->config); |
24929352 | 14982 | |
83d65738 | 14983 | crtc->base.state->enable = crtc->active; |
24929352 | 14984 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
14985 | |
14986 | plane_state = to_intel_plane_state(primary->state); | |
14987 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
14988 | |
14989 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14990 | crtc->base.base.id, | |
14991 | crtc->active ? "enabled" : "disabled"); | |
14992 | } | |
14993 | ||
5358901f DV |
14994 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14995 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14996 | ||
3e369b76 ACO |
14997 | pll->on = pll->get_hw_state(dev_priv, pll, |
14998 | &pll->config.hw_state); | |
5358901f | 14999 | pll->active = 0; |
3e369b76 | 15000 | pll->config.crtc_mask = 0; |
d3fcc808 | 15001 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15002 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15003 | pll->active++; |
3e369b76 | 15004 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15005 | } |
5358901f | 15006 | } |
5358901f | 15007 | |
1e6f2ddc | 15008 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15009 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15010 | |
3e369b76 | 15011 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15012 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15013 | } |
15014 | ||
b2784e15 | 15015 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15016 | pipe = 0; |
15017 | ||
15018 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15019 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15020 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15021 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15022 | } else { |
15023 | encoder->base.crtc = NULL; | |
15024 | } | |
15025 | ||
15026 | encoder->connectors_active = false; | |
6f2bcceb | 15027 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15028 | encoder->base.base.id, |
8e329a03 | 15029 | encoder->base.name, |
24929352 | 15030 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15031 | pipe_name(pipe)); |
24929352 DV |
15032 | } |
15033 | ||
3a3371ff | 15034 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15035 | if (connector->get_hw_state(connector)) { |
15036 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15037 | connector->encoder->connectors_active = true; | |
15038 | connector->base.encoder = &connector->encoder->base; | |
15039 | } else { | |
15040 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15041 | connector->base.encoder = NULL; | |
15042 | } | |
15043 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15044 | connector->base.base.id, | |
c23cc417 | 15045 | connector->base.name, |
24929352 DV |
15046 | connector->base.encoder ? "enabled" : "disabled"); |
15047 | } | |
30e984df DV |
15048 | } |
15049 | ||
15050 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
15051 | * and i915 state tracking structures. */ | |
15052 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
15053 | bool force_restore) | |
15054 | { | |
15055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15056 | enum pipe pipe; | |
30e984df DV |
15057 | struct intel_crtc *crtc; |
15058 | struct intel_encoder *encoder; | |
35c95375 | 15059 | int i; |
30e984df DV |
15060 | |
15061 | intel_modeset_readout_hw_state(dev); | |
24929352 | 15062 | |
babea61d JB |
15063 | /* |
15064 | * Now that we have the config, copy it to each CRTC struct | |
15065 | * Note that this could go away if we move to using crtc_config | |
15066 | * checking everywhere. | |
15067 | */ | |
d3fcc808 | 15068 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 15069 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
15070 | intel_mode_from_pipe_config(&crtc->base.mode, |
15071 | crtc->config); | |
babea61d JB |
15072 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
15073 | crtc->base.base.id); | |
15074 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
15075 | } | |
15076 | } | |
15077 | ||
24929352 | 15078 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 15079 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15080 | intel_sanitize_encoder(encoder); |
15081 | } | |
15082 | ||
055e393f | 15083 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15084 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15085 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15086 | intel_dump_pipe_config(crtc, crtc->config, |
15087 | "[setup_hw_state]"); | |
24929352 | 15088 | } |
9a935856 | 15089 | |
d29b2f9d ACO |
15090 | intel_modeset_update_connector_atomic_state(dev); |
15091 | ||
35c95375 DV |
15092 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15093 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15094 | ||
15095 | if (!pll->on || pll->active) | |
15096 | continue; | |
15097 | ||
15098 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15099 | ||
15100 | pll->disable(dev_priv, pll); | |
15101 | pll->on = false; | |
15102 | } | |
15103 | ||
3078999f PB |
15104 | if (IS_GEN9(dev)) |
15105 | skl_wm_get_hw_state(dev); | |
15106 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
15107 | ilk_wm_get_hw_state(dev); |
15108 | ||
45e2b5f6 | 15109 | if (force_restore) { |
7d0bc1ea VS |
15110 | i915_redisable_vga(dev); |
15111 | ||
f30da187 DV |
15112 | /* |
15113 | * We need to use raw interfaces for restoring state to avoid | |
15114 | * checking (bogus) intermediate states. | |
15115 | */ | |
055e393f | 15116 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
15117 | struct drm_crtc *crtc = |
15118 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 15119 | |
83a57153 | 15120 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
15121 | } |
15122 | } else { | |
15123 | intel_modeset_update_staged_output_state(dev); | |
15124 | } | |
8af6cf88 DV |
15125 | |
15126 | intel_modeset_check_state(dev); | |
2c7111db CW |
15127 | } |
15128 | ||
15129 | void intel_modeset_gem_init(struct drm_device *dev) | |
15130 | { | |
92122789 | 15131 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15132 | struct drm_crtc *c; |
2ff8fde1 | 15133 | struct drm_i915_gem_object *obj; |
e0d6149b | 15134 | int ret; |
484b41dd | 15135 | |
ae48434c ID |
15136 | mutex_lock(&dev->struct_mutex); |
15137 | intel_init_gt_powersave(dev); | |
15138 | mutex_unlock(&dev->struct_mutex); | |
15139 | ||
92122789 JB |
15140 | /* |
15141 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15142 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15143 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15144 | * indicates as much. | |
15145 | */ | |
15146 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15147 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15148 | DREF_SSC1_ENABLE); | |
15149 | ||
1833b134 | 15150 | intel_modeset_init_hw(dev); |
02e792fb DV |
15151 | |
15152 | intel_setup_overlay(dev); | |
484b41dd JB |
15153 | |
15154 | /* | |
15155 | * Make sure any fbs we allocated at startup are properly | |
15156 | * pinned & fenced. When we do the allocation it's too early | |
15157 | * for this. | |
15158 | */ | |
70e1e0ec | 15159 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15160 | obj = intel_fb_obj(c->primary->fb); |
15161 | if (obj == NULL) | |
484b41dd JB |
15162 | continue; |
15163 | ||
e0d6149b TU |
15164 | mutex_lock(&dev->struct_mutex); |
15165 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15166 | c->primary->fb, | |
15167 | c->primary->state, | |
15168 | NULL); | |
15169 | mutex_unlock(&dev->struct_mutex); | |
15170 | if (ret) { | |
484b41dd JB |
15171 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15172 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15173 | drm_framebuffer_unreference(c->primary->fb); |
15174 | c->primary->fb = NULL; | |
afd65eb4 | 15175 | update_state_fb(c->primary); |
484b41dd JB |
15176 | } |
15177 | } | |
0962c3c9 VS |
15178 | |
15179 | intel_backlight_register(dev); | |
79e53945 JB |
15180 | } |
15181 | ||
4932e2c3 ID |
15182 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15183 | { | |
15184 | struct drm_connector *connector = &intel_connector->base; | |
15185 | ||
15186 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15187 | drm_connector_unregister(connector); |
4932e2c3 ID |
15188 | } |
15189 | ||
79e53945 JB |
15190 | void intel_modeset_cleanup(struct drm_device *dev) |
15191 | { | |
652c393a | 15192 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15193 | struct drm_connector *connector; |
652c393a | 15194 | |
2eb5252e ID |
15195 | intel_disable_gt_powersave(dev); |
15196 | ||
0962c3c9 VS |
15197 | intel_backlight_unregister(dev); |
15198 | ||
fd0c0642 DV |
15199 | /* |
15200 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15201 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15202 | * experience fancy races otherwise. |
15203 | */ | |
2aeb7d3a | 15204 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15205 | |
fd0c0642 DV |
15206 | /* |
15207 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15208 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15209 | */ | |
f87ea761 | 15210 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15211 | |
652c393a JB |
15212 | mutex_lock(&dev->struct_mutex); |
15213 | ||
723bfd70 JB |
15214 | intel_unregister_dsm_handler(); |
15215 | ||
7ff0ebcc | 15216 | intel_fbc_disable(dev); |
e70236a8 | 15217 | |
69341a5e KH |
15218 | mutex_unlock(&dev->struct_mutex); |
15219 | ||
1630fe75 CW |
15220 | /* flush any delayed tasks or pending work */ |
15221 | flush_scheduled_work(); | |
15222 | ||
db31af1d JN |
15223 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15225 | struct intel_connector *intel_connector; |
15226 | ||
15227 | intel_connector = to_intel_connector(connector); | |
15228 | intel_connector->unregister(intel_connector); | |
db31af1d | 15229 | } |
d9255d57 | 15230 | |
79e53945 | 15231 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15232 | |
15233 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15234 | |
15235 | mutex_lock(&dev->struct_mutex); | |
15236 | intel_cleanup_gt_powersave(dev); | |
15237 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15238 | } |
15239 | ||
f1c79df3 ZW |
15240 | /* |
15241 | * Return which encoder is currently attached for connector. | |
15242 | */ | |
df0e9248 | 15243 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15244 | { |
df0e9248 CW |
15245 | return &intel_attached_encoder(connector)->base; |
15246 | } | |
f1c79df3 | 15247 | |
df0e9248 CW |
15248 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15249 | struct intel_encoder *encoder) | |
15250 | { | |
15251 | connector->encoder = encoder; | |
15252 | drm_mode_connector_attach_encoder(&connector->base, | |
15253 | &encoder->base); | |
79e53945 | 15254 | } |
28d52043 DA |
15255 | |
15256 | /* | |
15257 | * set vga decode state - true == enable VGA decode | |
15258 | */ | |
15259 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15260 | { | |
15261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15262 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15263 | u16 gmch_ctrl; |
15264 | ||
75fa041d CW |
15265 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15266 | DRM_ERROR("failed to read control word\n"); | |
15267 | return -EIO; | |
15268 | } | |
15269 | ||
c0cc8a55 CW |
15270 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15271 | return 0; | |
15272 | ||
28d52043 DA |
15273 | if (state) |
15274 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15275 | else | |
15276 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15277 | |
15278 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15279 | DRM_ERROR("failed to write control word\n"); | |
15280 | return -EIO; | |
15281 | } | |
15282 | ||
28d52043 DA |
15283 | return 0; |
15284 | } | |
c4a1d9e4 | 15285 | |
c4a1d9e4 | 15286 | struct intel_display_error_state { |
ff57f1b0 PZ |
15287 | |
15288 | u32 power_well_driver; | |
15289 | ||
63b66e5b CW |
15290 | int num_transcoders; |
15291 | ||
c4a1d9e4 CW |
15292 | struct intel_cursor_error_state { |
15293 | u32 control; | |
15294 | u32 position; | |
15295 | u32 base; | |
15296 | u32 size; | |
52331309 | 15297 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15298 | |
15299 | struct intel_pipe_error_state { | |
ddf9c536 | 15300 | bool power_domain_on; |
c4a1d9e4 | 15301 | u32 source; |
f301b1e1 | 15302 | u32 stat; |
52331309 | 15303 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15304 | |
15305 | struct intel_plane_error_state { | |
15306 | u32 control; | |
15307 | u32 stride; | |
15308 | u32 size; | |
15309 | u32 pos; | |
15310 | u32 addr; | |
15311 | u32 surface; | |
15312 | u32 tile_offset; | |
52331309 | 15313 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15314 | |
15315 | struct intel_transcoder_error_state { | |
ddf9c536 | 15316 | bool power_domain_on; |
63b66e5b CW |
15317 | enum transcoder cpu_transcoder; |
15318 | ||
15319 | u32 conf; | |
15320 | ||
15321 | u32 htotal; | |
15322 | u32 hblank; | |
15323 | u32 hsync; | |
15324 | u32 vtotal; | |
15325 | u32 vblank; | |
15326 | u32 vsync; | |
15327 | } transcoder[4]; | |
c4a1d9e4 CW |
15328 | }; |
15329 | ||
15330 | struct intel_display_error_state * | |
15331 | intel_display_capture_error_state(struct drm_device *dev) | |
15332 | { | |
fbee40df | 15333 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15334 | struct intel_display_error_state *error; |
63b66e5b CW |
15335 | int transcoders[] = { |
15336 | TRANSCODER_A, | |
15337 | TRANSCODER_B, | |
15338 | TRANSCODER_C, | |
15339 | TRANSCODER_EDP, | |
15340 | }; | |
c4a1d9e4 CW |
15341 | int i; |
15342 | ||
63b66e5b CW |
15343 | if (INTEL_INFO(dev)->num_pipes == 0) |
15344 | return NULL; | |
15345 | ||
9d1cb914 | 15346 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15347 | if (error == NULL) |
15348 | return NULL; | |
15349 | ||
190be112 | 15350 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15351 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15352 | ||
055e393f | 15353 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15354 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15355 | __intel_display_power_is_enabled(dev_priv, |
15356 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15357 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15358 | continue; |
15359 | ||
5efb3e28 VS |
15360 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15361 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15362 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15363 | |
15364 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15365 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15366 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15367 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15368 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15369 | } | |
ca291363 PZ |
15370 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15371 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15372 | if (INTEL_INFO(dev)->gen >= 4) { |
15373 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15374 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15375 | } | |
15376 | ||
c4a1d9e4 | 15377 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15378 | |
3abfce77 | 15379 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15380 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15381 | } |
15382 | ||
15383 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15384 | if (HAS_DDI(dev_priv->dev)) | |
15385 | error->num_transcoders++; /* Account for eDP. */ | |
15386 | ||
15387 | for (i = 0; i < error->num_transcoders; i++) { | |
15388 | enum transcoder cpu_transcoder = transcoders[i]; | |
15389 | ||
ddf9c536 | 15390 | error->transcoder[i].power_domain_on = |
f458ebbc | 15391 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15392 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15393 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15394 | continue; |
15395 | ||
63b66e5b CW |
15396 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15397 | ||
15398 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15399 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15400 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15401 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15402 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15403 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15404 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15405 | } |
15406 | ||
15407 | return error; | |
15408 | } | |
15409 | ||
edc3d884 MK |
15410 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15411 | ||
c4a1d9e4 | 15412 | void |
edc3d884 | 15413 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15414 | struct drm_device *dev, |
15415 | struct intel_display_error_state *error) | |
15416 | { | |
055e393f | 15417 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15418 | int i; |
15419 | ||
63b66e5b CW |
15420 | if (!error) |
15421 | return; | |
15422 | ||
edc3d884 | 15423 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15424 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15425 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15426 | error->power_well_driver); |
055e393f | 15427 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15428 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15429 | err_printf(m, " Power: %s\n", |
15430 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15431 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15432 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15433 | |
15434 | err_printf(m, "Plane [%d]:\n", i); | |
15435 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15436 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15437 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15438 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15439 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15440 | } |
4b71a570 | 15441 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15442 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15443 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15444 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15445 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15446 | } |
15447 | ||
edc3d884 MK |
15448 | err_printf(m, "Cursor [%d]:\n", i); |
15449 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15450 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15451 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15452 | } |
63b66e5b CW |
15453 | |
15454 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15455 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15456 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15457 | err_printf(m, " Power: %s\n", |
15458 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15459 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15460 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15461 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15462 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15463 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15464 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15465 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15466 | } | |
c4a1d9e4 | 15467 | } |
e2fcdaa9 VS |
15468 | |
15469 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15470 | { | |
15471 | struct intel_crtc *crtc; | |
15472 | ||
15473 | for_each_intel_crtc(dev, crtc) { | |
15474 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15475 | |
5e2d7afc | 15476 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15477 | |
15478 | work = crtc->unpin_work; | |
15479 | ||
15480 | if (work && work->event && | |
15481 | work->event->base.file_priv == file) { | |
15482 | kfree(work->event); | |
15483 | work->event = NULL; | |
15484 | } | |
15485 | ||
5e2d7afc | 15486 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15487 | } |
15488 | } |