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02e792fb DV |
1 | /* |
2 | * Copyright © 2009 | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Daniel Vetter <daniel@ffwll.ch> | |
25 | * | |
26 | * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c | |
27 | */ | |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
02e792fb DV |
30 | #include "i915_drv.h" |
31 | #include "i915_reg.h" | |
32 | #include "intel_drv.h" | |
5d723d7a | 33 | #include "intel_frontbuffer.h" |
02e792fb DV |
34 | |
35 | /* Limits for overlay size. According to intel doc, the real limits are: | |
36 | * Y width: 4095, UV width (planar): 2047, Y height: 2047, | |
37 | * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use | |
38 | * the mininum of both. */ | |
39 | #define IMAGE_MAX_WIDTH 2048 | |
40 | #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ | |
41 | /* on 830 and 845 these large limits result in the card hanging */ | |
42 | #define IMAGE_MAX_WIDTH_LEGACY 1024 | |
43 | #define IMAGE_MAX_HEIGHT_LEGACY 1088 | |
44 | ||
45 | /* overlay register definitions */ | |
46 | /* OCMD register */ | |
47 | #define OCMD_TILED_SURFACE (0x1<<19) | |
48 | #define OCMD_MIRROR_MASK (0x3<<17) | |
49 | #define OCMD_MIRROR_MODE (0x3<<17) | |
50 | #define OCMD_MIRROR_HORIZONTAL (0x1<<17) | |
51 | #define OCMD_MIRROR_VERTICAL (0x2<<17) | |
52 | #define OCMD_MIRROR_BOTH (0x3<<17) | |
53 | #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ | |
54 | #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ | |
55 | #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ | |
56 | #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ | |
57 | #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) | |
58 | #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ | |
59 | #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ | |
60 | #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ | |
61 | #define OCMD_YUV_422_PACKED (0x8<<10) | |
62 | #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ | |
63 | #define OCMD_YUV_420_PLANAR (0xc<<10) | |
64 | #define OCMD_YUV_422_PLANAR (0xd<<10) | |
65 | #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ | |
66 | #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) | |
67 | #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) | |
d7961364 | 68 | #define OCMD_BUF_TYPE_MASK (0x1<<5) |
02e792fb DV |
69 | #define OCMD_BUF_TYPE_FRAME (0x0<<5) |
70 | #define OCMD_BUF_TYPE_FIELD (0x1<<5) | |
71 | #define OCMD_TEST_MODE (0x1<<4) | |
72 | #define OCMD_BUFFER_SELECT (0x3<<2) | |
73 | #define OCMD_BUFFER0 (0x0<<2) | |
74 | #define OCMD_BUFFER1 (0x1<<2) | |
75 | #define OCMD_FIELD_SELECT (0x1<<2) | |
76 | #define OCMD_FIELD0 (0x0<<1) | |
77 | #define OCMD_FIELD1 (0x1<<1) | |
78 | #define OCMD_ENABLE (0x1<<0) | |
79 | ||
80 | /* OCONFIG register */ | |
81 | #define OCONF_PIPE_MASK (0x1<<18) | |
82 | #define OCONF_PIPE_A (0x0<<18) | |
83 | #define OCONF_PIPE_B (0x1<<18) | |
84 | #define OCONF_GAMMA2_ENABLE (0x1<<16) | |
85 | #define OCONF_CSC_MODE_BT601 (0x0<<5) | |
86 | #define OCONF_CSC_MODE_BT709 (0x1<<5) | |
87 | #define OCONF_CSC_BYPASS (0x1<<4) | |
88 | #define OCONF_CC_OUT_8BIT (0x1<<3) | |
89 | #define OCONF_TEST_MODE (0x1<<2) | |
90 | #define OCONF_THREE_LINE_BUFFER (0x1<<0) | |
91 | #define OCONF_TWO_LINE_BUFFER (0x0<<0) | |
92 | ||
93 | /* DCLRKM (dst-key) register */ | |
94 | #define DST_KEY_ENABLE (0x1<<31) | |
95 | #define CLK_RGB24_MASK 0x0 | |
96 | #define CLK_RGB16_MASK 0x070307 | |
97 | #define CLK_RGB15_MASK 0x070707 | |
98 | #define CLK_RGB8I_MASK 0xffffff | |
99 | ||
100 | #define RGB16_TO_COLORKEY(c) \ | |
101 | (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) | |
102 | #define RGB15_TO_COLORKEY(c) \ | |
103 | (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) | |
104 | ||
105 | /* overlay flip addr flag */ | |
106 | #define OFC_UPDATE 0x1 | |
107 | ||
108 | /* polyphase filter coefficients */ | |
109 | #define N_HORIZ_Y_TAPS 5 | |
110 | #define N_VERT_Y_TAPS 3 | |
111 | #define N_HORIZ_UV_TAPS 3 | |
112 | #define N_VERT_UV_TAPS 3 | |
113 | #define N_PHASES 17 | |
114 | #define MAX_TAPS 5 | |
115 | ||
116 | /* memory bufferd overlay registers */ | |
117 | struct overlay_registers { | |
0206e353 AJ |
118 | u32 OBUF_0Y; |
119 | u32 OBUF_1Y; | |
120 | u32 OBUF_0U; | |
121 | u32 OBUF_0V; | |
122 | u32 OBUF_1U; | |
123 | u32 OBUF_1V; | |
124 | u32 OSTRIDE; | |
125 | u32 YRGB_VPH; | |
126 | u32 UV_VPH; | |
127 | u32 HORZ_PH; | |
128 | u32 INIT_PHS; | |
129 | u32 DWINPOS; | |
130 | u32 DWINSZ; | |
131 | u32 SWIDTH; | |
132 | u32 SWIDTHSW; | |
133 | u32 SHEIGHT; | |
134 | u32 YRGBSCALE; | |
135 | u32 UVSCALE; | |
136 | u32 OCLRC0; | |
137 | u32 OCLRC1; | |
138 | u32 DCLRKV; | |
139 | u32 DCLRKM; | |
140 | u32 SCLRKVH; | |
141 | u32 SCLRKVL; | |
142 | u32 SCLRKEN; | |
143 | u32 OCONFIG; | |
144 | u32 OCMD; | |
145 | u32 RESERVED1; /* 0x6C */ | |
146 | u32 OSTART_0Y; | |
147 | u32 OSTART_1Y; | |
148 | u32 OSTART_0U; | |
149 | u32 OSTART_0V; | |
150 | u32 OSTART_1U; | |
151 | u32 OSTART_1V; | |
152 | u32 OTILEOFF_0Y; | |
153 | u32 OTILEOFF_1Y; | |
154 | u32 OTILEOFF_0U; | |
155 | u32 OTILEOFF_0V; | |
156 | u32 OTILEOFF_1U; | |
157 | u32 OTILEOFF_1V; | |
158 | u32 FASTHSCALE; /* 0xA0 */ | |
159 | u32 UVSCALEV; /* 0xA4 */ | |
160 | u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ | |
161 | u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ | |
162 | u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; | |
163 | u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ | |
164 | u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; | |
165 | u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ | |
166 | u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; | |
167 | u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ | |
168 | u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; | |
02e792fb DV |
169 | }; |
170 | ||
23f09ce3 | 171 | struct intel_overlay { |
1ee8da6d | 172 | struct drm_i915_private *i915; |
23f09ce3 | 173 | struct intel_crtc *crtc; |
9b3b7841 CW |
174 | struct i915_vma *vma; |
175 | struct i915_vma *old_vma; | |
209c2a5e VS |
176 | bool active; |
177 | bool pfit_active; | |
23f09ce3 | 178 | u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ |
ea9da4e4 CW |
179 | u32 color_key:24; |
180 | u32 color_key_enabled:1; | |
23f09ce3 CW |
181 | u32 brightness, contrast, saturation; |
182 | u32 old_xscale, old_yscale; | |
183 | /* register access */ | |
184 | u32 flip_addr; | |
185 | struct drm_i915_gem_object *reg_bo; | |
186 | /* flip handling */ | |
0d9bdd88 | 187 | struct i915_gem_active last_flip; |
23f09ce3 | 188 | }; |
02e792fb | 189 | |
8fdded82 VS |
190 | static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, |
191 | bool enable) | |
192 | { | |
193 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
194 | u8 val; | |
195 | ||
196 | /* WA_OVERLAY_CLKGATE:alm */ | |
197 | if (enable) | |
198 | I915_WRITE(DSPCLK_GATE_D, 0); | |
199 | else | |
200 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
201 | ||
202 | /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ | |
203 | pci_bus_read_config_byte(pdev->bus, | |
204 | PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); | |
205 | if (enable) | |
206 | val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; | |
207 | else | |
208 | val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; | |
209 | pci_bus_write_config_byte(pdev->bus, | |
210 | PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); | |
211 | } | |
212 | ||
75020bc1 | 213 | static struct overlay_registers __iomem * |
8d74f656 | 214 | intel_overlay_map_regs(struct intel_overlay *overlay) |
02e792fb | 215 | { |
1ee8da6d | 216 | struct drm_i915_private *dev_priv = overlay->i915; |
75020bc1 | 217 | struct overlay_registers __iomem *regs; |
02e792fb | 218 | |
1ee8da6d | 219 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) |
00731155 | 220 | regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; |
9bb2ff73 | 221 | else |
b06f4c80 | 222 | regs = io_mapping_map_wc(&dev_priv->ggtt.iomap, |
d8dab00d CW |
223 | overlay->flip_addr, |
224 | PAGE_SIZE); | |
02e792fb | 225 | |
9bb2ff73 | 226 | return regs; |
8d74f656 | 227 | } |
02e792fb | 228 | |
9bb2ff73 | 229 | static void intel_overlay_unmap_regs(struct intel_overlay *overlay, |
75020bc1 | 230 | struct overlay_registers __iomem *regs) |
8d74f656 | 231 | { |
1ee8da6d | 232 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) |
9bb2ff73 | 233 | io_mapping_unmap(regs); |
02e792fb DV |
234 | } |
235 | ||
0d9bdd88 | 236 | static void intel_overlay_submit_request(struct intel_overlay *overlay, |
dad540ce | 237 | struct drm_i915_gem_request *req, |
0d9bdd88 | 238 | i915_gem_retire_fn retire) |
02e792fb | 239 | { |
0d9bdd88 CW |
240 | GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip, |
241 | &overlay->i915->drm.struct_mutex)); | |
ecd9caa0 VS |
242 | i915_gem_active_set_retire_fn(&overlay->last_flip, retire, |
243 | &overlay->i915->drm.struct_mutex); | |
0d9bdd88 | 244 | i915_gem_active_set(&overlay->last_flip, req); |
75289874 | 245 | i915_add_request(req); |
0d9bdd88 | 246 | } |
acb868d3 | 247 | |
0d9bdd88 CW |
248 | static int intel_overlay_do_wait_request(struct intel_overlay *overlay, |
249 | struct drm_i915_gem_request *req, | |
250 | i915_gem_retire_fn retire) | |
251 | { | |
252 | intel_overlay_submit_request(overlay, req, retire); | |
253 | return i915_gem_active_retire(&overlay->last_flip, | |
254 | &overlay->i915->drm.struct_mutex); | |
02e792fb DV |
255 | } |
256 | ||
8e637178 CW |
257 | static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay) |
258 | { | |
259 | struct drm_i915_private *dev_priv = overlay->i915; | |
3b3f1650 | 260 | struct intel_engine_cs *engine = dev_priv->engine[RCS]; |
8e637178 CW |
261 | |
262 | return i915_gem_request_alloc(engine, dev_priv->kernel_context); | |
263 | } | |
264 | ||
02e792fb DV |
265 | /* overlay needs to be disable in OCMD reg */ |
266 | static int intel_overlay_on(struct intel_overlay *overlay) | |
267 | { | |
1ee8da6d | 268 | struct drm_i915_private *dev_priv = overlay->i915; |
dad540ce | 269 | struct drm_i915_gem_request *req; |
73dec95e | 270 | u32 *cs; |
02e792fb | 271 | |
77589f56 | 272 | WARN_ON(overlay->active); |
106dadac | 273 | |
8e637178 | 274 | req = alloc_request(overlay); |
26827088 DG |
275 | if (IS_ERR(req)) |
276 | return PTR_ERR(req); | |
e1f99ce6 | 277 | |
73dec95e TU |
278 | cs = intel_ring_begin(req, 4); |
279 | if (IS_ERR(cs)) { | |
e642c85b | 280 | i915_add_request(req); |
73dec95e | 281 | return PTR_ERR(cs); |
dad540ce JH |
282 | } |
283 | ||
1c7c4301 VS |
284 | overlay->active = true; |
285 | ||
8fdded82 VS |
286 | if (IS_I830(dev_priv)) |
287 | i830_overlay_clock_gating(dev_priv, false); | |
288 | ||
73dec95e TU |
289 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; |
290 | *cs++ = overlay->flip_addr | OFC_UPDATE; | |
291 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
292 | *cs++ = MI_NOOP; | |
293 | intel_ring_advance(req, cs); | |
02e792fb | 294 | |
dad540ce | 295 | return intel_overlay_do_wait_request(overlay, req, NULL); |
02e792fb DV |
296 | } |
297 | ||
58d09ebd VS |
298 | static void intel_overlay_flip_prepare(struct intel_overlay *overlay, |
299 | struct i915_vma *vma) | |
300 | { | |
301 | enum pipe pipe = overlay->crtc->pipe; | |
302 | ||
303 | WARN_ON(overlay->old_vma); | |
304 | ||
305 | i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, | |
306 | vma ? vma->obj : NULL, | |
307 | INTEL_FRONTBUFFER_OVERLAY(pipe)); | |
308 | ||
309 | intel_frontbuffer_flip_prepare(overlay->i915, | |
310 | INTEL_FRONTBUFFER_OVERLAY(pipe)); | |
311 | ||
312 | overlay->old_vma = overlay->vma; | |
313 | if (vma) | |
314 | overlay->vma = i915_vma_get(vma); | |
315 | else | |
316 | overlay->vma = NULL; | |
317 | } | |
318 | ||
02e792fb | 319 | /* overlay needs to be enabled in OCMD reg */ |
8dc5d147 | 320 | static int intel_overlay_continue(struct intel_overlay *overlay, |
58d09ebd | 321 | struct i915_vma *vma, |
8dc5d147 | 322 | bool load_polyphase_filter) |
02e792fb | 323 | { |
1ee8da6d | 324 | struct drm_i915_private *dev_priv = overlay->i915; |
dad540ce | 325 | struct drm_i915_gem_request *req; |
02e792fb | 326 | u32 flip_addr = overlay->flip_addr; |
73dec95e | 327 | u32 tmp, *cs; |
02e792fb | 328 | |
77589f56 | 329 | WARN_ON(!overlay->active); |
02e792fb DV |
330 | |
331 | if (load_polyphase_filter) | |
332 | flip_addr |= OFC_UPDATE; | |
333 | ||
334 | /* check for underruns */ | |
335 | tmp = I915_READ(DOVSTA); | |
336 | if (tmp & (1 << 17)) | |
337 | DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); | |
338 | ||
8e637178 | 339 | req = alloc_request(overlay); |
26827088 DG |
340 | if (IS_ERR(req)) |
341 | return PTR_ERR(req); | |
acb868d3 | 342 | |
73dec95e TU |
343 | cs = intel_ring_begin(req, 2); |
344 | if (IS_ERR(cs)) { | |
e642c85b | 345 | i915_add_request(req); |
73dec95e | 346 | return PTR_ERR(cs); |
dad540ce JH |
347 | } |
348 | ||
73dec95e TU |
349 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; |
350 | *cs++ = flip_addr; | |
351 | intel_ring_advance(req, cs); | |
5a5a0c64 | 352 | |
58d09ebd VS |
353 | intel_overlay_flip_prepare(overlay, vma); |
354 | ||
0d9bdd88 | 355 | intel_overlay_submit_request(overlay, req, NULL); |
bf7dc5b7 JH |
356 | |
357 | return 0; | |
5a5a0c64 DV |
358 | } |
359 | ||
58d09ebd | 360 | static void intel_overlay_release_old_vma(struct intel_overlay *overlay) |
5a5a0c64 | 361 | { |
9b3b7841 | 362 | struct i915_vma *vma; |
5a5a0c64 | 363 | |
9b3b7841 CW |
364 | vma = fetch_and_zero(&overlay->old_vma); |
365 | if (WARN_ON(!vma)) | |
366 | return; | |
0d9bdd88 | 367 | |
58d09ebd VS |
368 | intel_frontbuffer_flip_complete(overlay->i915, |
369 | INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); | |
5a5a0c64 | 370 | |
058d88c4 | 371 | i915_gem_object_unpin_from_display_plane(vma); |
9b3b7841 | 372 | i915_vma_put(vma); |
b303cf95 | 373 | } |
03f77ea5 | 374 | |
58d09ebd VS |
375 | static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active, |
376 | struct drm_i915_gem_request *req) | |
377 | { | |
378 | struct intel_overlay *overlay = | |
379 | container_of(active, typeof(*overlay), last_flip); | |
380 | ||
381 | intel_overlay_release_old_vma(overlay); | |
382 | } | |
383 | ||
0d9bdd88 CW |
384 | static void intel_overlay_off_tail(struct i915_gem_active *active, |
385 | struct drm_i915_gem_request *req) | |
b303cf95 | 386 | { |
0d9bdd88 CW |
387 | struct intel_overlay *overlay = |
388 | container_of(active, typeof(*overlay), last_flip); | |
8fdded82 | 389 | struct drm_i915_private *dev_priv = overlay->i915; |
02e792fb | 390 | |
58d09ebd | 391 | intel_overlay_release_old_vma(overlay); |
03f77ea5 | 392 | |
b303cf95 CW |
393 | overlay->crtc->overlay = NULL; |
394 | overlay->crtc = NULL; | |
209c2a5e | 395 | overlay->active = false; |
8fdded82 VS |
396 | |
397 | if (IS_I830(dev_priv)) | |
398 | i830_overlay_clock_gating(dev_priv, true); | |
02e792fb DV |
399 | } |
400 | ||
401 | /* overlay needs to be disabled in OCMD reg */ | |
ce453d81 | 402 | static int intel_overlay_off(struct intel_overlay *overlay) |
02e792fb | 403 | { |
dad540ce | 404 | struct drm_i915_gem_request *req; |
73dec95e | 405 | u32 *cs, flip_addr = overlay->flip_addr; |
02e792fb | 406 | |
77589f56 | 407 | WARN_ON(!overlay->active); |
02e792fb DV |
408 | |
409 | /* According to intel docs the overlay hw may hang (when switching | |
410 | * off) without loading the filter coeffs. It is however unclear whether | |
411 | * this applies to the disabling of the overlay or to the switching off | |
412 | * of the hw. Do it in both cases */ | |
413 | flip_addr |= OFC_UPDATE; | |
414 | ||
8e637178 | 415 | req = alloc_request(overlay); |
26827088 DG |
416 | if (IS_ERR(req)) |
417 | return PTR_ERR(req); | |
acb868d3 | 418 | |
73dec95e TU |
419 | cs = intel_ring_begin(req, 6); |
420 | if (IS_ERR(cs)) { | |
e642c85b | 421 | i915_add_request(req); |
73dec95e | 422 | return PTR_ERR(cs); |
dad540ce JH |
423 | } |
424 | ||
02e792fb | 425 | /* wait for overlay to go idle */ |
73dec95e TU |
426 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; |
427 | *cs++ = flip_addr; | |
428 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
4c5cfcc3 | 429 | |
02e792fb | 430 | /* turn overlay off */ |
73dec95e TU |
431 | *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; |
432 | *cs++ = flip_addr; | |
433 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; | |
4c5cfcc3 | 434 | |
73dec95e | 435 | intel_ring_advance(req, cs); |
02e792fb | 436 | |
58d09ebd VS |
437 | intel_overlay_flip_prepare(overlay, NULL); |
438 | ||
0d9bdd88 CW |
439 | return intel_overlay_do_wait_request(overlay, req, |
440 | intel_overlay_off_tail); | |
12ca45fe DV |
441 | } |
442 | ||
03f77ea5 DV |
443 | /* recover from an interruption due to a signal |
444 | * We have to be careful not to repeat work forever an make forward progess. */ | |
ce453d81 | 445 | static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) |
03f77ea5 | 446 | { |
0d9bdd88 CW |
447 | return i915_gem_active_retire(&overlay->last_flip, |
448 | &overlay->i915->drm.struct_mutex); | |
03f77ea5 DV |
449 | } |
450 | ||
5a5a0c64 DV |
451 | /* Wait for pending overlay flip and release old frame. |
452 | * Needs to be called before the overlay register are changed | |
8d74f656 CW |
453 | * via intel_overlay_(un)map_regs |
454 | */ | |
02e792fb DV |
455 | static int intel_overlay_release_old_vid(struct intel_overlay *overlay) |
456 | { | |
1ee8da6d | 457 | struct drm_i915_private *dev_priv = overlay->i915; |
73dec95e | 458 | u32 *cs; |
02e792fb | 459 | int ret; |
02e792fb | 460 | |
91c8a326 | 461 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1362b776 | 462 | |
5cd68c98 CW |
463 | /* Only wait if there is actually an old frame to release to |
464 | * guarantee forward progress. | |
465 | */ | |
9b3b7841 | 466 | if (!overlay->old_vma) |
03f77ea5 DV |
467 | return 0; |
468 | ||
5cd68c98 CW |
469 | if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { |
470 | /* synchronous slowpath */ | |
dad540ce JH |
471 | struct drm_i915_gem_request *req; |
472 | ||
8e637178 | 473 | req = alloc_request(overlay); |
26827088 DG |
474 | if (IS_ERR(req)) |
475 | return PTR_ERR(req); | |
e1f99ce6 | 476 | |
73dec95e TU |
477 | cs = intel_ring_begin(req, 2); |
478 | if (IS_ERR(cs)) { | |
e642c85b | 479 | i915_add_request(req); |
73dec95e | 480 | return PTR_ERR(cs); |
dad540ce JH |
481 | } |
482 | ||
73dec95e TU |
483 | *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; |
484 | *cs++ = MI_NOOP; | |
485 | intel_ring_advance(req, cs); | |
5cd68c98 | 486 | |
dad540ce | 487 | ret = intel_overlay_do_wait_request(overlay, req, |
b303cf95 | 488 | intel_overlay_release_old_vid_tail); |
5cd68c98 CW |
489 | if (ret) |
490 | return ret; | |
0d9bdd88 CW |
491 | } else |
492 | intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); | |
02e792fb DV |
493 | |
494 | return 0; | |
495 | } | |
496 | ||
1362b776 VS |
497 | void intel_overlay_reset(struct drm_i915_private *dev_priv) |
498 | { | |
499 | struct intel_overlay *overlay = dev_priv->overlay; | |
500 | ||
501 | if (!overlay) | |
502 | return; | |
503 | ||
504 | intel_overlay_release_old_vid(overlay); | |
505 | ||
1362b776 VS |
506 | overlay->old_xscale = 0; |
507 | overlay->old_yscale = 0; | |
508 | overlay->crtc = NULL; | |
509 | overlay->active = false; | |
510 | } | |
511 | ||
02e792fb DV |
512 | struct put_image_params { |
513 | int format; | |
514 | short dst_x; | |
515 | short dst_y; | |
516 | short dst_w; | |
517 | short dst_h; | |
518 | short src_w; | |
519 | short src_scan_h; | |
520 | short src_scan_w; | |
521 | short src_h; | |
522 | short stride_Y; | |
523 | short stride_UV; | |
524 | int offset_Y; | |
525 | int offset_U; | |
526 | int offset_V; | |
527 | }; | |
528 | ||
529 | static int packed_depth_bytes(u32 format) | |
530 | { | |
531 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
532 | case I915_OVERLAY_YUV422: |
533 | return 4; | |
534 | case I915_OVERLAY_YUV411: | |
535 | /* return 6; not implemented */ | |
536 | default: | |
537 | return -EINVAL; | |
02e792fb DV |
538 | } |
539 | } | |
540 | ||
541 | static int packed_width_bytes(u32 format, short width) | |
542 | { | |
543 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
544 | case I915_OVERLAY_YUV422: |
545 | return width << 1; | |
546 | default: | |
547 | return -EINVAL; | |
02e792fb DV |
548 | } |
549 | } | |
550 | ||
551 | static int uv_hsubsampling(u32 format) | |
552 | { | |
553 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
554 | case I915_OVERLAY_YUV422: |
555 | case I915_OVERLAY_YUV420: | |
556 | return 2; | |
557 | case I915_OVERLAY_YUV411: | |
558 | case I915_OVERLAY_YUV410: | |
559 | return 4; | |
560 | default: | |
561 | return -EINVAL; | |
02e792fb DV |
562 | } |
563 | } | |
564 | ||
565 | static int uv_vsubsampling(u32 format) | |
566 | { | |
567 | switch (format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
568 | case I915_OVERLAY_YUV420: |
569 | case I915_OVERLAY_YUV410: | |
570 | return 2; | |
571 | case I915_OVERLAY_YUV422: | |
572 | case I915_OVERLAY_YUV411: | |
573 | return 1; | |
574 | default: | |
575 | return -EINVAL; | |
02e792fb DV |
576 | } |
577 | } | |
578 | ||
1ee8da6d | 579 | static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) |
02e792fb | 580 | { |
7039a6dc VS |
581 | u32 sw; |
582 | ||
583 | if (IS_GEN2(dev_priv)) | |
584 | sw = ALIGN((offset & 31) + width, 32); | |
585 | else | |
586 | sw = ALIGN((offset & 63) + width, 64); | |
587 | ||
588 | if (sw == 0) | |
589 | return 0; | |
590 | ||
591 | return (sw - 32) >> 3; | |
02e792fb DV |
592 | } |
593 | ||
2daac462 VS |
594 | static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { |
595 | [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, | |
596 | [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, | |
597 | [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, | |
598 | [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, | |
599 | [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, | |
600 | [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, | |
601 | [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, | |
602 | [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, | |
603 | [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, | |
604 | [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, | |
605 | [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, | |
606 | [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, | |
607 | [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, | |
608 | [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, | |
609 | [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, | |
610 | [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, | |
611 | [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, | |
722506f0 CW |
612 | }; |
613 | ||
2daac462 VS |
614 | static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { |
615 | [ 0] = { 0x3000, 0x1800, 0x1800, }, | |
616 | [ 1] = { 0xb000, 0x18d0, 0x2e60, }, | |
617 | [ 2] = { 0xb000, 0x1990, 0x2ce0, }, | |
618 | [ 3] = { 0xb020, 0x1a68, 0x2b40, }, | |
619 | [ 4] = { 0xb040, 0x1b20, 0x29e0, }, | |
620 | [ 5] = { 0xb060, 0x1bd8, 0x2880, }, | |
621 | [ 6] = { 0xb080, 0x1c88, 0x3e60, }, | |
622 | [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, | |
623 | [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, | |
624 | [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, | |
625 | [10] = { 0xb100, 0x1eb8, 0x3620, }, | |
626 | [11] = { 0xb100, 0x1f18, 0x34a0, }, | |
627 | [12] = { 0xb100, 0x1f68, 0x3360, }, | |
628 | [13] = { 0xb0e0, 0x1fa8, 0x3240, }, | |
629 | [14] = { 0xb0c0, 0x1fe0, 0x3140, }, | |
630 | [15] = { 0xb060, 0x1ff0, 0x30a0, }, | |
631 | [16] = { 0x3000, 0x0800, 0x3000, }, | |
722506f0 | 632 | }; |
02e792fb | 633 | |
75020bc1 | 634 | static void update_polyphase_filter(struct overlay_registers __iomem *regs) |
02e792fb | 635 | { |
75020bc1 BW |
636 | memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); |
637 | memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, | |
638 | sizeof(uv_static_hcoeffs)); | |
02e792fb DV |
639 | } |
640 | ||
641 | static bool update_scaling_factors(struct intel_overlay *overlay, | |
75020bc1 | 642 | struct overlay_registers __iomem *regs, |
02e792fb DV |
643 | struct put_image_params *params) |
644 | { | |
645 | /* fixed point with a 12 bit shift */ | |
646 | u32 xscale, yscale, xscale_UV, yscale_UV; | |
647 | #define FP_SHIFT 12 | |
648 | #define FRACT_MASK 0xfff | |
649 | bool scale_changed = false; | |
650 | int uv_hscale = uv_hsubsampling(params->format); | |
651 | int uv_vscale = uv_vsubsampling(params->format); | |
652 | ||
653 | if (params->dst_w > 1) | |
654 | xscale = ((params->src_scan_w - 1) << FP_SHIFT) | |
655 | /(params->dst_w); | |
656 | else | |
657 | xscale = 1 << FP_SHIFT; | |
658 | ||
659 | if (params->dst_h > 1) | |
660 | yscale = ((params->src_scan_h - 1) << FP_SHIFT) | |
661 | /(params->dst_h); | |
662 | else | |
663 | yscale = 1 << FP_SHIFT; | |
664 | ||
665 | /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ | |
722506f0 CW |
666 | xscale_UV = xscale/uv_hscale; |
667 | yscale_UV = yscale/uv_vscale; | |
668 | /* make the Y scale to UV scale ratio an exact multiply */ | |
669 | xscale = xscale_UV * uv_hscale; | |
670 | yscale = yscale_UV * uv_vscale; | |
02e792fb | 671 | /*} else { |
722506f0 CW |
672 | xscale_UV = 0; |
673 | yscale_UV = 0; | |
674 | }*/ | |
02e792fb DV |
675 | |
676 | if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) | |
677 | scale_changed = true; | |
678 | overlay->old_xscale = xscale; | |
679 | overlay->old_yscale = yscale; | |
680 | ||
75020bc1 BW |
681 | iowrite32(((yscale & FRACT_MASK) << 20) | |
682 | ((xscale >> FP_SHIFT) << 16) | | |
683 | ((xscale & FRACT_MASK) << 3), | |
684 | ®s->YRGBSCALE); | |
722506f0 | 685 | |
75020bc1 BW |
686 | iowrite32(((yscale_UV & FRACT_MASK) << 20) | |
687 | ((xscale_UV >> FP_SHIFT) << 16) | | |
688 | ((xscale_UV & FRACT_MASK) << 3), | |
689 | ®s->UVSCALE); | |
722506f0 | 690 | |
75020bc1 BW |
691 | iowrite32((((yscale >> FP_SHIFT) << 16) | |
692 | ((yscale_UV >> FP_SHIFT) << 0)), | |
693 | ®s->UVSCALEV); | |
02e792fb DV |
694 | |
695 | if (scale_changed) | |
696 | update_polyphase_filter(regs); | |
697 | ||
698 | return scale_changed; | |
699 | } | |
700 | ||
701 | static void update_colorkey(struct intel_overlay *overlay, | |
75020bc1 | 702 | struct overlay_registers __iomem *regs) |
02e792fb | 703 | { |
39ccc04e VS |
704 | const struct intel_plane_state *state = |
705 | to_intel_plane_state(overlay->crtc->base.primary->state); | |
02e792fb | 706 | u32 key = overlay->color_key; |
39ccc04e VS |
707 | u32 format = 0; |
708 | u32 flags = 0; | |
ea9da4e4 | 709 | |
ea9da4e4 CW |
710 | if (overlay->color_key_enabled) |
711 | flags |= DST_KEY_ENABLE; | |
6ba3ddd9 | 712 | |
39ccc04e | 713 | if (state->base.visible) |
ef426c10 | 714 | format = state->base.fb->format->format; |
39ccc04e VS |
715 | |
716 | switch (format) { | |
717 | case DRM_FORMAT_C8: | |
ea9da4e4 CW |
718 | key = 0; |
719 | flags |= CLK_RGB8I_MASK; | |
6ba3ddd9 | 720 | break; |
39ccc04e VS |
721 | case DRM_FORMAT_XRGB1555: |
722 | key = RGB15_TO_COLORKEY(key); | |
723 | flags |= CLK_RGB15_MASK; | |
6ba3ddd9 | 724 | break; |
39ccc04e VS |
725 | case DRM_FORMAT_RGB565: |
726 | key = RGB16_TO_COLORKEY(key); | |
727 | flags |= CLK_RGB16_MASK; | |
728 | break; | |
729 | default: | |
ea9da4e4 | 730 | flags |= CLK_RGB24_MASK; |
6ba3ddd9 | 731 | break; |
02e792fb | 732 | } |
ea9da4e4 CW |
733 | |
734 | iowrite32(key, ®s->DCLRKV); | |
735 | iowrite32(flags, ®s->DCLRKM); | |
02e792fb DV |
736 | } |
737 | ||
738 | static u32 overlay_cmd_reg(struct put_image_params *params) | |
739 | { | |
740 | u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; | |
741 | ||
742 | if (params->format & I915_OVERLAY_YUV_PLANAR) { | |
743 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
744 | case I915_OVERLAY_YUV422: |
745 | cmd |= OCMD_YUV_422_PLANAR; | |
746 | break; | |
747 | case I915_OVERLAY_YUV420: | |
748 | cmd |= OCMD_YUV_420_PLANAR; | |
749 | break; | |
750 | case I915_OVERLAY_YUV411: | |
751 | case I915_OVERLAY_YUV410: | |
752 | cmd |= OCMD_YUV_410_PLANAR; | |
753 | break; | |
02e792fb DV |
754 | } |
755 | } else { /* YUV packed */ | |
756 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { | |
722506f0 CW |
757 | case I915_OVERLAY_YUV422: |
758 | cmd |= OCMD_YUV_422_PACKED; | |
759 | break; | |
760 | case I915_OVERLAY_YUV411: | |
761 | cmd |= OCMD_YUV_411_PACKED; | |
762 | break; | |
02e792fb DV |
763 | } |
764 | ||
765 | switch (params->format & I915_OVERLAY_SWAP_MASK) { | |
722506f0 CW |
766 | case I915_OVERLAY_NO_SWAP: |
767 | break; | |
768 | case I915_OVERLAY_UV_SWAP: | |
769 | cmd |= OCMD_UV_SWAP; | |
770 | break; | |
771 | case I915_OVERLAY_Y_SWAP: | |
772 | cmd |= OCMD_Y_SWAP; | |
773 | break; | |
774 | case I915_OVERLAY_Y_AND_UV_SWAP: | |
775 | cmd |= OCMD_Y_AND_UV_SWAP; | |
776 | break; | |
02e792fb DV |
777 | } |
778 | } | |
779 | ||
780 | return cmd; | |
781 | } | |
782 | ||
5fe82c5e | 783 | static int intel_overlay_do_put_image(struct intel_overlay *overlay, |
05394f39 | 784 | struct drm_i915_gem_object *new_bo, |
5fe82c5e | 785 | struct put_image_params *params) |
02e792fb DV |
786 | { |
787 | int ret, tmp_width; | |
75020bc1 | 788 | struct overlay_registers __iomem *regs; |
02e792fb | 789 | bool scale_changed = false; |
1ee8da6d | 790 | struct drm_i915_private *dev_priv = overlay->i915; |
75020bc1 | 791 | u32 swidth, swidthsw, sheight, ostride; |
a071fa00 | 792 | enum pipe pipe = overlay->crtc->pipe; |
9b3b7841 | 793 | struct i915_vma *vma; |
02e792fb | 794 | |
91c8a326 CW |
795 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
796 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
02e792fb | 797 | |
02e792fb DV |
798 | ret = intel_overlay_release_old_vid(overlay); |
799 | if (ret != 0) | |
800 | return ret; | |
801 | ||
9db529aa DV |
802 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
803 | ||
47a8e3f6 | 804 | vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); |
9db529aa DV |
805 | if (IS_ERR(vma)) { |
806 | ret = PTR_ERR(vma); | |
807 | goto out_pin_section; | |
808 | } | |
9b3b7841 | 809 | |
49ef5294 | 810 | ret = i915_vma_put_fence(vma); |
d9e86c0e CW |
811 | if (ret) |
812 | goto out_unpin; | |
813 | ||
02e792fb | 814 | if (!overlay->active) { |
75020bc1 | 815 | u32 oconfig; |
8d74f656 | 816 | regs = intel_overlay_map_regs(overlay); |
02e792fb DV |
817 | if (!regs) { |
818 | ret = -ENOMEM; | |
819 | goto out_unpin; | |
820 | } | |
75020bc1 | 821 | oconfig = OCONF_CC_OUT_8BIT; |
1ee8da6d | 822 | if (IS_GEN4(dev_priv)) |
75020bc1 | 823 | oconfig |= OCONF_CSC_MODE_BT709; |
a071fa00 | 824 | oconfig |= pipe == 0 ? |
02e792fb | 825 | OCONF_PIPE_A : OCONF_PIPE_B; |
75020bc1 | 826 | iowrite32(oconfig, ®s->OCONFIG); |
9bb2ff73 | 827 | intel_overlay_unmap_regs(overlay, regs); |
02e792fb DV |
828 | |
829 | ret = intel_overlay_on(overlay); | |
830 | if (ret != 0) | |
831 | goto out_unpin; | |
832 | } | |
833 | ||
8d74f656 | 834 | regs = intel_overlay_map_regs(overlay); |
02e792fb DV |
835 | if (!regs) { |
836 | ret = -ENOMEM; | |
837 | goto out_unpin; | |
838 | } | |
839 | ||
75020bc1 BW |
840 | iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS); |
841 | iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ); | |
02e792fb DV |
842 | |
843 | if (params->format & I915_OVERLAY_YUV_PACKED) | |
844 | tmp_width = packed_width_bytes(params->format, params->src_w); | |
845 | else | |
846 | tmp_width = params->src_w; | |
847 | ||
75020bc1 | 848 | swidth = params->src_w; |
1ee8da6d | 849 | swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); |
75020bc1 | 850 | sheight = params->src_h; |
bde13ebd | 851 | iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); |
75020bc1 | 852 | ostride = params->stride_Y; |
02e792fb DV |
853 | |
854 | if (params->format & I915_OVERLAY_YUV_PLANAR) { | |
855 | int uv_hscale = uv_hsubsampling(params->format); | |
856 | int uv_vscale = uv_vsubsampling(params->format); | |
857 | u32 tmp_U, tmp_V; | |
75020bc1 | 858 | swidth |= (params->src_w/uv_hscale) << 16; |
1ee8da6d | 859 | tmp_U = calc_swidthsw(dev_priv, params->offset_U, |
722506f0 | 860 | params->src_w/uv_hscale); |
1ee8da6d | 861 | tmp_V = calc_swidthsw(dev_priv, params->offset_V, |
722506f0 | 862 | params->src_w/uv_hscale); |
75020bc1 BW |
863 | swidthsw |= max_t(u32, tmp_U, tmp_V) << 16; |
864 | sheight |= (params->src_h/uv_vscale) << 16; | |
bde13ebd CW |
865 | iowrite32(i915_ggtt_offset(vma) + params->offset_U, |
866 | ®s->OBUF_0U); | |
867 | iowrite32(i915_ggtt_offset(vma) + params->offset_V, | |
868 | ®s->OBUF_0V); | |
75020bc1 | 869 | ostride |= params->stride_UV << 16; |
02e792fb DV |
870 | } |
871 | ||
75020bc1 BW |
872 | iowrite32(swidth, ®s->SWIDTH); |
873 | iowrite32(swidthsw, ®s->SWIDTHSW); | |
874 | iowrite32(sheight, ®s->SHEIGHT); | |
875 | iowrite32(ostride, ®s->OSTRIDE); | |
876 | ||
02e792fb DV |
877 | scale_changed = update_scaling_factors(overlay, regs, params); |
878 | ||
879 | update_colorkey(overlay, regs); | |
880 | ||
75020bc1 | 881 | iowrite32(overlay_cmd_reg(params), ®s->OCMD); |
02e792fb | 882 | |
9bb2ff73 | 883 | intel_overlay_unmap_regs(overlay, regs); |
02e792fb | 884 | |
58d09ebd | 885 | ret = intel_overlay_continue(overlay, vma, scale_changed); |
8dc5d147 CW |
886 | if (ret) |
887 | goto out_unpin; | |
02e792fb | 888 | |
02e792fb DV |
889 | return 0; |
890 | ||
891 | out_unpin: | |
058d88c4 | 892 | i915_gem_object_unpin_from_display_plane(vma); |
9db529aa DV |
893 | out_pin_section: |
894 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); | |
895 | ||
02e792fb DV |
896 | return ret; |
897 | } | |
898 | ||
ce453d81 | 899 | int intel_overlay_switch_off(struct intel_overlay *overlay) |
02e792fb | 900 | { |
1ee8da6d | 901 | struct drm_i915_private *dev_priv = overlay->i915; |
75020bc1 | 902 | struct overlay_registers __iomem *regs; |
5dcdbcb0 | 903 | int ret; |
02e792fb | 904 | |
91c8a326 CW |
905 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
906 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
02e792fb | 907 | |
ce453d81 | 908 | ret = intel_overlay_recover_from_interrupt(overlay); |
b303cf95 CW |
909 | if (ret != 0) |
910 | return ret; | |
9bedb974 | 911 | |
02e792fb DV |
912 | if (!overlay->active) |
913 | return 0; | |
914 | ||
02e792fb DV |
915 | ret = intel_overlay_release_old_vid(overlay); |
916 | if (ret != 0) | |
917 | return ret; | |
918 | ||
8d74f656 | 919 | regs = intel_overlay_map_regs(overlay); |
75020bc1 | 920 | iowrite32(0, ®s->OCMD); |
9bb2ff73 | 921 | intel_overlay_unmap_regs(overlay, regs); |
02e792fb | 922 | |
0d9bdd88 | 923 | return intel_overlay_off(overlay); |
02e792fb DV |
924 | } |
925 | ||
926 | static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, | |
927 | struct intel_crtc *crtc) | |
928 | { | |
f7abfe8b | 929 | if (!crtc->active) |
02e792fb DV |
930 | return -EINVAL; |
931 | ||
02e792fb | 932 | /* can't use the overlay with double wide pipe */ |
6e3c9717 | 933 | if (crtc->config->double_wide) |
02e792fb DV |
934 | return -EINVAL; |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static void update_pfit_vscale_ratio(struct intel_overlay *overlay) | |
940 | { | |
1ee8da6d | 941 | struct drm_i915_private *dev_priv = overlay->i915; |
02e792fb | 942 | u32 pfit_control = I915_READ(PFIT_CONTROL); |
446d2183 | 943 | u32 ratio; |
02e792fb DV |
944 | |
945 | /* XXX: This is not the same logic as in the xorg driver, but more in | |
446d2183 CW |
946 | * line with the intel documentation for the i965 |
947 | */ | |
1ee8da6d | 948 | if (INTEL_GEN(dev_priv) >= 4) { |
0206e353 | 949 | /* on i965 use the PGM reg to read out the autoscaler values */ |
a6c45cf0 CW |
950 | ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; |
951 | } else { | |
446d2183 CW |
952 | if (pfit_control & VERT_AUTO_SCALE) |
953 | ratio = I915_READ(PFIT_AUTO_RATIOS); | |
02e792fb | 954 | else |
446d2183 CW |
955 | ratio = I915_READ(PFIT_PGM_RATIOS); |
956 | ratio >>= PFIT_VERT_SCALE_SHIFT; | |
02e792fb DV |
957 | } |
958 | ||
959 | overlay->pfit_vscale_ratio = ratio; | |
960 | } | |
961 | ||
962 | static int check_overlay_dst(struct intel_overlay *overlay, | |
963 | struct drm_intel_overlay_put_image *rec) | |
964 | { | |
73699147 VS |
965 | const struct intel_crtc_state *pipe_config = |
966 | overlay->crtc->config; | |
02e792fb | 967 | |
73699147 VS |
968 | if (rec->dst_x < pipe_config->pipe_src_w && |
969 | rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && | |
970 | rec->dst_y < pipe_config->pipe_src_h && | |
971 | rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) | |
02e792fb DV |
972 | return 0; |
973 | else | |
974 | return -EINVAL; | |
975 | } | |
976 | ||
977 | static int check_overlay_scaling(struct put_image_params *rec) | |
978 | { | |
979 | u32 tmp; | |
980 | ||
981 | /* downscaling limit is 8.0 */ | |
982 | tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16; | |
983 | if (tmp > 7) | |
984 | return -EINVAL; | |
985 | tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16; | |
986 | if (tmp > 7) | |
987 | return -EINVAL; | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
1ee8da6d | 992 | static int check_overlay_src(struct drm_i915_private *dev_priv, |
02e792fb | 993 | struct drm_intel_overlay_put_image *rec, |
05394f39 | 994 | struct drm_i915_gem_object *new_bo) |
02e792fb | 995 | { |
02e792fb DV |
996 | int uv_hscale = uv_hsubsampling(rec->flags); |
997 | int uv_vscale = uv_vsubsampling(rec->flags); | |
8f28f54a DC |
998 | u32 stride_mask; |
999 | int depth; | |
1000 | u32 tmp; | |
02e792fb DV |
1001 | |
1002 | /* check src dimensions */ | |
2a307c2e | 1003 | if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { |
722506f0 | 1004 | if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || |
9f7c3f44 | 1005 | rec->src_width > IMAGE_MAX_WIDTH_LEGACY) |
02e792fb DV |
1006 | return -EINVAL; |
1007 | } else { | |
722506f0 | 1008 | if (rec->src_height > IMAGE_MAX_HEIGHT || |
9f7c3f44 | 1009 | rec->src_width > IMAGE_MAX_WIDTH) |
02e792fb DV |
1010 | return -EINVAL; |
1011 | } | |
9f7c3f44 | 1012 | |
02e792fb | 1013 | /* better safe than sorry, use 4 as the maximal subsampling ratio */ |
722506f0 | 1014 | if (rec->src_height < N_VERT_Y_TAPS*4 || |
9f7c3f44 | 1015 | rec->src_width < N_HORIZ_Y_TAPS*4) |
02e792fb DV |
1016 | return -EINVAL; |
1017 | ||
a1efd14a | 1018 | /* check alignment constraints */ |
02e792fb | 1019 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { |
722506f0 CW |
1020 | case I915_OVERLAY_RGB: |
1021 | /* not implemented */ | |
1022 | return -EINVAL; | |
9f7c3f44 | 1023 | |
722506f0 | 1024 | case I915_OVERLAY_YUV_PACKED: |
722506f0 | 1025 | if (uv_vscale != 1) |
02e792fb | 1026 | return -EINVAL; |
9f7c3f44 CW |
1027 | |
1028 | depth = packed_depth_bytes(rec->flags); | |
722506f0 CW |
1029 | if (depth < 0) |
1030 | return depth; | |
9f7c3f44 | 1031 | |
722506f0 CW |
1032 | /* ignore UV planes */ |
1033 | rec->stride_UV = 0; | |
1034 | rec->offset_U = 0; | |
1035 | rec->offset_V = 0; | |
1036 | /* check pixel alignment */ | |
1037 | if (rec->offset_Y % depth) | |
1038 | return -EINVAL; | |
1039 | break; | |
9f7c3f44 | 1040 | |
722506f0 CW |
1041 | case I915_OVERLAY_YUV_PLANAR: |
1042 | if (uv_vscale < 0 || uv_hscale < 0) | |
02e792fb | 1043 | return -EINVAL; |
722506f0 CW |
1044 | /* no offset restrictions for planar formats */ |
1045 | break; | |
9f7c3f44 | 1046 | |
722506f0 CW |
1047 | default: |
1048 | return -EINVAL; | |
02e792fb DV |
1049 | } |
1050 | ||
1051 | if (rec->src_width % uv_hscale) | |
1052 | return -EINVAL; | |
1053 | ||
1054 | /* stride checking */ | |
2a307c2e | 1055 | if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
a1efd14a CW |
1056 | stride_mask = 255; |
1057 | else | |
1058 | stride_mask = 63; | |
02e792fb DV |
1059 | |
1060 | if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) | |
1061 | return -EINVAL; | |
1ee8da6d | 1062 | if (IS_GEN4(dev_priv) && rec->stride_Y < 512) |
02e792fb DV |
1063 | return -EINVAL; |
1064 | ||
1065 | tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? | |
9f7c3f44 CW |
1066 | 4096 : 8192; |
1067 | if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) | |
02e792fb DV |
1068 | return -EINVAL; |
1069 | ||
1070 | /* check buffer dimensions */ | |
1071 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { | |
722506f0 CW |
1072 | case I915_OVERLAY_RGB: |
1073 | case I915_OVERLAY_YUV_PACKED: | |
1074 | /* always 4 Y values per depth pixels */ | |
1075 | if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) | |
1076 | return -EINVAL; | |
1077 | ||
1078 | tmp = rec->stride_Y*rec->src_height; | |
05394f39 | 1079 | if (rec->offset_Y + tmp > new_bo->base.size) |
722506f0 CW |
1080 | return -EINVAL; |
1081 | break; | |
1082 | ||
1083 | case I915_OVERLAY_YUV_PLANAR: | |
1084 | if (rec->src_width > rec->stride_Y) | |
1085 | return -EINVAL; | |
1086 | if (rec->src_width/uv_hscale > rec->stride_UV) | |
1087 | return -EINVAL; | |
1088 | ||
9f7c3f44 | 1089 | tmp = rec->stride_Y * rec->src_height; |
05394f39 | 1090 | if (rec->offset_Y + tmp > new_bo->base.size) |
722506f0 | 1091 | return -EINVAL; |
9f7c3f44 CW |
1092 | |
1093 | tmp = rec->stride_UV * (rec->src_height / uv_vscale); | |
05394f39 CW |
1094 | if (rec->offset_U + tmp > new_bo->base.size || |
1095 | rec->offset_V + tmp > new_bo->base.size) | |
722506f0 CW |
1096 | return -EINVAL; |
1097 | break; | |
02e792fb DV |
1098 | } |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1ee8da6d CW |
1103 | int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, |
1104 | struct drm_file *file_priv) | |
02e792fb DV |
1105 | { |
1106 | struct drm_intel_overlay_put_image *put_image_rec = data; | |
fac5e23e | 1107 | struct drm_i915_private *dev_priv = to_i915(dev); |
02e792fb | 1108 | struct intel_overlay *overlay; |
7707e653 | 1109 | struct drm_crtc *drmmode_crtc; |
02e792fb | 1110 | struct intel_crtc *crtc; |
05394f39 | 1111 | struct drm_i915_gem_object *new_bo; |
02e792fb DV |
1112 | struct put_image_params *params; |
1113 | int ret; | |
1114 | ||
02e792fb DV |
1115 | overlay = dev_priv->overlay; |
1116 | if (!overlay) { | |
1117 | DRM_DEBUG("userspace bug: no overlay\n"); | |
1118 | return -ENODEV; | |
1119 | } | |
1120 | ||
1121 | if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) { | |
a0e99e68 | 1122 | drm_modeset_lock_all(dev); |
02e792fb DV |
1123 | mutex_lock(&dev->struct_mutex); |
1124 | ||
ce453d81 | 1125 | ret = intel_overlay_switch_off(overlay); |
02e792fb DV |
1126 | |
1127 | mutex_unlock(&dev->struct_mutex); | |
a0e99e68 | 1128 | drm_modeset_unlock_all(dev); |
02e792fb DV |
1129 | |
1130 | return ret; | |
1131 | } | |
1132 | ||
b14c5679 | 1133 | params = kmalloc(sizeof(*params), GFP_KERNEL); |
02e792fb DV |
1134 | if (!params) |
1135 | return -ENOMEM; | |
1136 | ||
418da172 | 1137 | drmmode_crtc = drm_crtc_find(dev, file_priv, put_image_rec->crtc_id); |
7707e653 | 1138 | if (!drmmode_crtc) { |
915a428e DC |
1139 | ret = -ENOENT; |
1140 | goto out_free; | |
1141 | } | |
7707e653 | 1142 | crtc = to_intel_crtc(drmmode_crtc); |
02e792fb | 1143 | |
03ac0642 CW |
1144 | new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle); |
1145 | if (!new_bo) { | |
915a428e DC |
1146 | ret = -ENOENT; |
1147 | goto out_free; | |
1148 | } | |
02e792fb | 1149 | |
a0e99e68 | 1150 | drm_modeset_lock_all(dev); |
02e792fb DV |
1151 | mutex_lock(&dev->struct_mutex); |
1152 | ||
3e510a8e | 1153 | if (i915_gem_object_is_tiled(new_bo)) { |
3b25b31f | 1154 | DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); |
d9e86c0e CW |
1155 | ret = -EINVAL; |
1156 | goto out_unlock; | |
1157 | } | |
1158 | ||
ce453d81 | 1159 | ret = intel_overlay_recover_from_interrupt(overlay); |
b303cf95 CW |
1160 | if (ret != 0) |
1161 | goto out_unlock; | |
03f77ea5 | 1162 | |
02e792fb | 1163 | if (overlay->crtc != crtc) { |
ce453d81 | 1164 | ret = intel_overlay_switch_off(overlay); |
02e792fb DV |
1165 | if (ret != 0) |
1166 | goto out_unlock; | |
1167 | ||
1168 | ret = check_overlay_possible_on_crtc(overlay, crtc); | |
1169 | if (ret != 0) | |
1170 | goto out_unlock; | |
1171 | ||
1172 | overlay->crtc = crtc; | |
1173 | crtc->overlay = overlay; | |
1174 | ||
e9e331a8 | 1175 | /* line too wide, i.e. one-line-mode */ |
73699147 | 1176 | if (crtc->config->pipe_src_w > 1024 && |
949d8cf8 | 1177 | crtc->config->gmch_pfit.control & PFIT_ENABLE) { |
209c2a5e | 1178 | overlay->pfit_active = true; |
02e792fb DV |
1179 | update_pfit_vscale_ratio(overlay); |
1180 | } else | |
209c2a5e | 1181 | overlay->pfit_active = false; |
02e792fb DV |
1182 | } |
1183 | ||
1184 | ret = check_overlay_dst(overlay, put_image_rec); | |
1185 | if (ret != 0) | |
1186 | goto out_unlock; | |
1187 | ||
1188 | if (overlay->pfit_active) { | |
1189 | params->dst_y = ((((u32)put_image_rec->dst_y) << 12) / | |
722506f0 | 1190 | overlay->pfit_vscale_ratio); |
02e792fb DV |
1191 | /* shifting right rounds downwards, so add 1 */ |
1192 | params->dst_h = ((((u32)put_image_rec->dst_height) << 12) / | |
722506f0 | 1193 | overlay->pfit_vscale_ratio) + 1; |
02e792fb DV |
1194 | } else { |
1195 | params->dst_y = put_image_rec->dst_y; | |
1196 | params->dst_h = put_image_rec->dst_height; | |
1197 | } | |
1198 | params->dst_x = put_image_rec->dst_x; | |
1199 | params->dst_w = put_image_rec->dst_width; | |
1200 | ||
1201 | params->src_w = put_image_rec->src_width; | |
1202 | params->src_h = put_image_rec->src_height; | |
1203 | params->src_scan_w = put_image_rec->src_scan_width; | |
1204 | params->src_scan_h = put_image_rec->src_scan_height; | |
722506f0 CW |
1205 | if (params->src_scan_h > params->src_h || |
1206 | params->src_scan_w > params->src_w) { | |
02e792fb DV |
1207 | ret = -EINVAL; |
1208 | goto out_unlock; | |
1209 | } | |
1210 | ||
1ee8da6d | 1211 | ret = check_overlay_src(dev_priv, put_image_rec, new_bo); |
02e792fb DV |
1212 | if (ret != 0) |
1213 | goto out_unlock; | |
1214 | params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK; | |
1215 | params->stride_Y = put_image_rec->stride_Y; | |
1216 | params->stride_UV = put_image_rec->stride_UV; | |
1217 | params->offset_Y = put_image_rec->offset_Y; | |
1218 | params->offset_U = put_image_rec->offset_U; | |
1219 | params->offset_V = put_image_rec->offset_V; | |
1220 | ||
1221 | /* Check scaling after src size to prevent a divide-by-zero. */ | |
1222 | ret = check_overlay_scaling(params); | |
1223 | if (ret != 0) | |
1224 | goto out_unlock; | |
1225 | ||
1226 | ret = intel_overlay_do_put_image(overlay, new_bo, params); | |
1227 | if (ret != 0) | |
1228 | goto out_unlock; | |
1229 | ||
1230 | mutex_unlock(&dev->struct_mutex); | |
a0e99e68 | 1231 | drm_modeset_unlock_all(dev); |
58d09ebd | 1232 | i915_gem_object_put(new_bo); |
02e792fb DV |
1233 | |
1234 | kfree(params); | |
1235 | ||
1236 | return 0; | |
1237 | ||
1238 | out_unlock: | |
1239 | mutex_unlock(&dev->struct_mutex); | |
a0e99e68 | 1240 | drm_modeset_unlock_all(dev); |
f0cd5182 | 1241 | i915_gem_object_put(new_bo); |
915a428e | 1242 | out_free: |
02e792fb DV |
1243 | kfree(params); |
1244 | ||
1245 | return ret; | |
1246 | } | |
1247 | ||
1248 | static void update_reg_attrs(struct intel_overlay *overlay, | |
75020bc1 | 1249 | struct overlay_registers __iomem *regs) |
02e792fb | 1250 | { |
75020bc1 BW |
1251 | iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), |
1252 | ®s->OCLRC0); | |
1253 | iowrite32(overlay->saturation, ®s->OCLRC1); | |
02e792fb DV |
1254 | } |
1255 | ||
1256 | static bool check_gamma_bounds(u32 gamma1, u32 gamma2) | |
1257 | { | |
1258 | int i; | |
1259 | ||
1260 | if (gamma1 & 0xff000000 || gamma2 & 0xff000000) | |
1261 | return false; | |
1262 | ||
1263 | for (i = 0; i < 3; i++) { | |
722506f0 | 1264 | if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) |
02e792fb DV |
1265 | return false; |
1266 | } | |
1267 | ||
1268 | return true; | |
1269 | } | |
1270 | ||
1271 | static bool check_gamma5_errata(u32 gamma5) | |
1272 | { | |
1273 | int i; | |
1274 | ||
1275 | for (i = 0; i < 3; i++) { | |
1276 | if (((gamma5 >> i*8) & 0xff) == 0x80) | |
1277 | return false; | |
1278 | } | |
1279 | ||
1280 | return true; | |
1281 | } | |
1282 | ||
1283 | static int check_gamma(struct drm_intel_overlay_attrs *attrs) | |
1284 | { | |
722506f0 CW |
1285 | if (!check_gamma_bounds(0, attrs->gamma0) || |
1286 | !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || | |
1287 | !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || | |
1288 | !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || | |
1289 | !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || | |
1290 | !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || | |
1291 | !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) | |
02e792fb | 1292 | return -EINVAL; |
722506f0 | 1293 | |
02e792fb DV |
1294 | if (!check_gamma5_errata(attrs->gamma5)) |
1295 | return -EINVAL; | |
722506f0 | 1296 | |
02e792fb DV |
1297 | return 0; |
1298 | } | |
1299 | ||
1ee8da6d CW |
1300 | int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, |
1301 | struct drm_file *file_priv) | |
02e792fb DV |
1302 | { |
1303 | struct drm_intel_overlay_attrs *attrs = data; | |
fac5e23e | 1304 | struct drm_i915_private *dev_priv = to_i915(dev); |
02e792fb | 1305 | struct intel_overlay *overlay; |
75020bc1 | 1306 | struct overlay_registers __iomem *regs; |
02e792fb DV |
1307 | int ret; |
1308 | ||
02e792fb DV |
1309 | overlay = dev_priv->overlay; |
1310 | if (!overlay) { | |
1311 | DRM_DEBUG("userspace bug: no overlay\n"); | |
1312 | return -ENODEV; | |
1313 | } | |
1314 | ||
a0e99e68 | 1315 | drm_modeset_lock_all(dev); |
02e792fb DV |
1316 | mutex_lock(&dev->struct_mutex); |
1317 | ||
60fc332c | 1318 | ret = -EINVAL; |
02e792fb | 1319 | if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { |
60fc332c | 1320 | attrs->color_key = overlay->color_key; |
02e792fb | 1321 | attrs->brightness = overlay->brightness; |
60fc332c | 1322 | attrs->contrast = overlay->contrast; |
02e792fb DV |
1323 | attrs->saturation = overlay->saturation; |
1324 | ||
1ee8da6d | 1325 | if (!IS_GEN2(dev_priv)) { |
02e792fb DV |
1326 | attrs->gamma0 = I915_READ(OGAMC0); |
1327 | attrs->gamma1 = I915_READ(OGAMC1); | |
1328 | attrs->gamma2 = I915_READ(OGAMC2); | |
1329 | attrs->gamma3 = I915_READ(OGAMC3); | |
1330 | attrs->gamma4 = I915_READ(OGAMC4); | |
1331 | attrs->gamma5 = I915_READ(OGAMC5); | |
1332 | } | |
02e792fb | 1333 | } else { |
60fc332c | 1334 | if (attrs->brightness < -128 || attrs->brightness > 127) |
02e792fb | 1335 | goto out_unlock; |
60fc332c | 1336 | if (attrs->contrast > 255) |
02e792fb | 1337 | goto out_unlock; |
60fc332c | 1338 | if (attrs->saturation > 1023) |
02e792fb | 1339 | goto out_unlock; |
02e792fb | 1340 | |
60fc332c CW |
1341 | overlay->color_key = attrs->color_key; |
1342 | overlay->brightness = attrs->brightness; | |
1343 | overlay->contrast = attrs->contrast; | |
1344 | overlay->saturation = attrs->saturation; | |
02e792fb | 1345 | |
8d74f656 | 1346 | regs = intel_overlay_map_regs(overlay); |
02e792fb DV |
1347 | if (!regs) { |
1348 | ret = -ENOMEM; | |
1349 | goto out_unlock; | |
1350 | } | |
1351 | ||
1352 | update_reg_attrs(overlay, regs); | |
1353 | ||
9bb2ff73 | 1354 | intel_overlay_unmap_regs(overlay, regs); |
02e792fb DV |
1355 | |
1356 | if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { | |
1ee8da6d | 1357 | if (IS_GEN2(dev_priv)) |
02e792fb | 1358 | goto out_unlock; |
02e792fb DV |
1359 | |
1360 | if (overlay->active) { | |
1361 | ret = -EBUSY; | |
1362 | goto out_unlock; | |
1363 | } | |
1364 | ||
1365 | ret = check_gamma(attrs); | |
60fc332c | 1366 | if (ret) |
02e792fb DV |
1367 | goto out_unlock; |
1368 | ||
1369 | I915_WRITE(OGAMC0, attrs->gamma0); | |
1370 | I915_WRITE(OGAMC1, attrs->gamma1); | |
1371 | I915_WRITE(OGAMC2, attrs->gamma2); | |
1372 | I915_WRITE(OGAMC3, attrs->gamma3); | |
1373 | I915_WRITE(OGAMC4, attrs->gamma4); | |
1374 | I915_WRITE(OGAMC5, attrs->gamma5); | |
1375 | } | |
02e792fb | 1376 | } |
ea9da4e4 | 1377 | overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; |
02e792fb | 1378 | |
60fc332c | 1379 | ret = 0; |
02e792fb DV |
1380 | out_unlock: |
1381 | mutex_unlock(&dev->struct_mutex); | |
a0e99e68 | 1382 | drm_modeset_unlock_all(dev); |
02e792fb DV |
1383 | |
1384 | return ret; | |
1385 | } | |
1386 | ||
1ee8da6d | 1387 | void intel_setup_overlay(struct drm_i915_private *dev_priv) |
02e792fb | 1388 | { |
02e792fb | 1389 | struct intel_overlay *overlay; |
05394f39 | 1390 | struct drm_i915_gem_object *reg_bo; |
75020bc1 | 1391 | struct overlay_registers __iomem *regs; |
058d88c4 | 1392 | struct i915_vma *vma = NULL; |
02e792fb DV |
1393 | int ret; |
1394 | ||
1ee8da6d | 1395 | if (!HAS_OVERLAY(dev_priv)) |
02e792fb DV |
1396 | return; |
1397 | ||
b14c5679 | 1398 | overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); |
02e792fb DV |
1399 | if (!overlay) |
1400 | return; | |
79d24273 | 1401 | |
91c8a326 | 1402 | mutex_lock(&dev_priv->drm.struct_mutex); |
79d24273 CW |
1403 | if (WARN_ON(dev_priv->overlay)) |
1404 | goto out_free; | |
1405 | ||
1ee8da6d | 1406 | overlay->i915 = dev_priv; |
02e792fb | 1407 | |
f63a484c | 1408 | reg_bo = NULL; |
1ee8da6d | 1409 | if (!OVERLAY_NEEDS_PHYSICAL(dev_priv)) |
187685cb | 1410 | reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE); |
80405138 | 1411 | if (reg_bo == NULL) |
12d79d78 | 1412 | reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE); |
fe3db79b | 1413 | if (IS_ERR(reg_bo)) |
02e792fb | 1414 | goto out_free; |
05394f39 | 1415 | overlay->reg_bo = reg_bo; |
02e792fb | 1416 | |
1ee8da6d | 1417 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) { |
00731155 | 1418 | ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); |
0206e353 AJ |
1419 | if (ret) { |
1420 | DRM_ERROR("failed to attach phys overlay regs\n"); | |
1421 | goto out_free_bo; | |
1422 | } | |
00731155 | 1423 | overlay->flip_addr = reg_bo->phys_handle->busaddr; |
31578148 | 1424 | } else { |
058d88c4 | 1425 | vma = i915_gem_object_ggtt_pin(reg_bo, NULL, |
de895082 | 1426 | 0, PAGE_SIZE, PIN_MAPPABLE); |
058d88c4 | 1427 | if (IS_ERR(vma)) { |
0206e353 | 1428 | DRM_ERROR("failed to pin overlay register bo\n"); |
058d88c4 | 1429 | ret = PTR_ERR(vma); |
0206e353 AJ |
1430 | goto out_free_bo; |
1431 | } | |
bde13ebd | 1432 | overlay->flip_addr = i915_ggtt_offset(vma); |
0ddc1289 CW |
1433 | |
1434 | ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); | |
1435 | if (ret) { | |
0206e353 AJ |
1436 | DRM_ERROR("failed to move overlay register bo into the GTT\n"); |
1437 | goto out_unpin_bo; | |
1438 | } | |
02e792fb DV |
1439 | } |
1440 | ||
1441 | /* init all values */ | |
1442 | overlay->color_key = 0x0101fe; | |
ea9da4e4 | 1443 | overlay->color_key_enabled = true; |
02e792fb DV |
1444 | overlay->brightness = -19; |
1445 | overlay->contrast = 75; | |
1446 | overlay->saturation = 146; | |
1447 | ||
330afdb1 VS |
1448 | init_request_active(&overlay->last_flip, NULL); |
1449 | ||
8d74f656 | 1450 | regs = intel_overlay_map_regs(overlay); |
02e792fb | 1451 | if (!regs) |
79d24273 | 1452 | goto out_unpin_bo; |
02e792fb | 1453 | |
75020bc1 | 1454 | memset_io(regs, 0, sizeof(struct overlay_registers)); |
02e792fb | 1455 | update_polyphase_filter(regs); |
02e792fb DV |
1456 | update_reg_attrs(overlay, regs); |
1457 | ||
9bb2ff73 | 1458 | intel_overlay_unmap_regs(overlay, regs); |
02e792fb DV |
1459 | |
1460 | dev_priv->overlay = overlay; | |
91c8a326 | 1461 | mutex_unlock(&dev_priv->drm.struct_mutex); |
02e792fb DV |
1462 | DRM_INFO("initialized overlay support\n"); |
1463 | return; | |
1464 | ||
0ddc1289 | 1465 | out_unpin_bo: |
058d88c4 CW |
1466 | if (vma) |
1467 | i915_vma_unpin(vma); | |
02e792fb | 1468 | out_free_bo: |
f8c417cd | 1469 | i915_gem_object_put(reg_bo); |
02e792fb | 1470 | out_free: |
91c8a326 | 1471 | mutex_unlock(&dev_priv->drm.struct_mutex); |
02e792fb DV |
1472 | kfree(overlay); |
1473 | return; | |
1474 | } | |
1475 | ||
1ee8da6d | 1476 | void intel_cleanup_overlay(struct drm_i915_private *dev_priv) |
02e792fb | 1477 | { |
62cf4e6f CW |
1478 | if (!dev_priv->overlay) |
1479 | return; | |
02e792fb | 1480 | |
62cf4e6f CW |
1481 | /* The bo's should be free'd by the generic code already. |
1482 | * Furthermore modesetting teardown happens beforehand so the | |
1483 | * hardware should be off already */ | |
77589f56 | 1484 | WARN_ON(dev_priv->overlay->active); |
62cf4e6f | 1485 | |
f0cd5182 | 1486 | i915_gem_object_put(dev_priv->overlay->reg_bo); |
62cf4e6f | 1487 | kfree(dev_priv->overlay); |
02e792fb | 1488 | } |
6ef3d427 | 1489 | |
98a2f411 CW |
1490 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
1491 | ||
6ef3d427 CW |
1492 | struct intel_overlay_error_state { |
1493 | struct overlay_registers regs; | |
1494 | unsigned long base; | |
1495 | u32 dovsta; | |
1496 | u32 isr; | |
1497 | }; | |
1498 | ||
75020bc1 | 1499 | static struct overlay_registers __iomem * |
c48c43e4 | 1500 | intel_overlay_map_regs_atomic(struct intel_overlay *overlay) |
3bd3c932 | 1501 | { |
1ee8da6d | 1502 | struct drm_i915_private *dev_priv = overlay->i915; |
75020bc1 | 1503 | struct overlay_registers __iomem *regs; |
3bd3c932 | 1504 | |
1ee8da6d | 1505 | if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) |
75020bc1 BW |
1506 | /* Cast to make sparse happy, but it's wc memory anyway, so |
1507 | * equivalent to the wc io mapping on X86. */ | |
1508 | regs = (struct overlay_registers __iomem *) | |
00731155 | 1509 | overlay->reg_bo->phys_handle->vaddr; |
3bd3c932 | 1510 | else |
b06f4c80 | 1511 | regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.iomap, |
da6ca034 | 1512 | overlay->flip_addr); |
3bd3c932 CW |
1513 | |
1514 | return regs; | |
1515 | } | |
1516 | ||
1517 | static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, | |
75020bc1 | 1518 | struct overlay_registers __iomem *regs) |
3bd3c932 | 1519 | { |
1ee8da6d | 1520 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) |
c48c43e4 | 1521 | io_mapping_unmap_atomic(regs); |
3bd3c932 CW |
1522 | } |
1523 | ||
6ef3d427 | 1524 | struct intel_overlay_error_state * |
c033666a | 1525 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) |
6ef3d427 | 1526 | { |
6ef3d427 CW |
1527 | struct intel_overlay *overlay = dev_priv->overlay; |
1528 | struct intel_overlay_error_state *error; | |
1529 | struct overlay_registers __iomem *regs; | |
1530 | ||
1531 | if (!overlay || !overlay->active) | |
1532 | return NULL; | |
1533 | ||
1534 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
1535 | if (error == NULL) | |
1536 | return NULL; | |
1537 | ||
1538 | error->dovsta = I915_READ(DOVSTA); | |
1539 | error->isr = I915_READ(ISR); | |
da6ca034 | 1540 | error->base = overlay->flip_addr; |
6ef3d427 CW |
1541 | |
1542 | regs = intel_overlay_map_regs_atomic(overlay); | |
1543 | if (!regs) | |
1544 | goto err; | |
1545 | ||
1546 | memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); | |
c48c43e4 | 1547 | intel_overlay_unmap_regs_atomic(overlay, regs); |
6ef3d427 CW |
1548 | |
1549 | return error; | |
1550 | ||
1551 | err: | |
1552 | kfree(error); | |
1553 | return NULL; | |
1554 | } | |
1555 | ||
1556 | void | |
edc3d884 MK |
1557 | intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, |
1558 | struct intel_overlay_error_state *error) | |
6ef3d427 | 1559 | { |
edc3d884 MK |
1560 | i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", |
1561 | error->dovsta, error->isr); | |
1562 | i915_error_printf(m, " Register file at 0x%08lx:\n", | |
1563 | error->base); | |
6ef3d427 | 1564 | |
edc3d884 | 1565 | #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) |
6ef3d427 CW |
1566 | P(OBUF_0Y); |
1567 | P(OBUF_1Y); | |
1568 | P(OBUF_0U); | |
1569 | P(OBUF_0V); | |
1570 | P(OBUF_1U); | |
1571 | P(OBUF_1V); | |
1572 | P(OSTRIDE); | |
1573 | P(YRGB_VPH); | |
1574 | P(UV_VPH); | |
1575 | P(HORZ_PH); | |
1576 | P(INIT_PHS); | |
1577 | P(DWINPOS); | |
1578 | P(DWINSZ); | |
1579 | P(SWIDTH); | |
1580 | P(SWIDTHSW); | |
1581 | P(SHEIGHT); | |
1582 | P(YRGBSCALE); | |
1583 | P(UVSCALE); | |
1584 | P(OCLRC0); | |
1585 | P(OCLRC1); | |
1586 | P(DCLRKV); | |
1587 | P(DCLRKM); | |
1588 | P(SCLRKVH); | |
1589 | P(SCLRKVL); | |
1590 | P(SCLRKEN); | |
1591 | P(OCONFIG); | |
1592 | P(OCMD); | |
1593 | P(OSTART_0Y); | |
1594 | P(OSTART_1Y); | |
1595 | P(OSTART_0U); | |
1596 | P(OSTART_0V); | |
1597 | P(OSTART_1U); | |
1598 | P(OSTART_1V); | |
1599 | P(OTILEOFF_0Y); | |
1600 | P(OTILEOFF_1Y); | |
1601 | P(OTILEOFF_0U); | |
1602 | P(OTILEOFF_0V); | |
1603 | P(OTILEOFF_1U); | |
1604 | P(OTILEOFF_1V); | |
1605 | P(FASTHSCALE); | |
1606 | P(UVSCALEV); | |
1607 | #undef P | |
1608 | } | |
98a2f411 CW |
1609 | |
1610 | #endif |