arch/powerpc/mm/tlb-radix.c

   1 /*
   2  * TLB flush routines for radix kernels.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/mm.h>
  13 #include <linux/hugetlb.h>
  14 #include <linux/memblock.h>
  15 #include <asm/ppc-opcode.h>
  16
  17 #include <asm/tlb.h>
  18 #include <asm/tlbflush.h>
  19
  20 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
  21
  22 #define RIC_FLUSH_TLB 0
  23 #define RIC_FLUSH_PWC 1
  24 #define RIC_FLUSH_ALL 2
  25
  26 static inline void __tlbiel_pid(unsigned long pid, int set,
  27                                 unsigned long ric)
  28 {
  29         unsigned long rb,rs,prs,r;
  30
  31         rb = PPC_BIT(53); /* IS = 1 */
  32         rb |= set << PPC_BITLSHIFT(51);
  33         rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
  34         prs = 1; /* process scoped */
  35         r = 1;   /* raidx format */
  36
  37         asm volatile("ptesync": : :"memory");
  38         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  39                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  40         asm volatile("ptesync": : :"memory");
  41 }
  42
  43 /*
  44  * We use 128 set in radix mode and 256 set in hpt mode.
  45  */
  46 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
  47 {
  48         int set;
  49
  50         for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
  51                 __tlbiel_pid(pid, set, ric);
  52         }
  53         return;
  54 }
  55
  56 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
  57 {
  58         unsigned long rb,rs,prs,r;
  59
  60         rb = PPC_BIT(53); /* IS = 1 */
  61         rs = pid << PPC_BITLSHIFT(31);
  62         prs = 1; /* process scoped */
  63         r = 1;   /* raidx format */
  64
  65         asm volatile("ptesync": : :"memory");
  66         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
  67                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  68         asm volatile("eieio; tlbsync; ptesync": : :"memory");
  69 }
  70
  71 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
  72                               unsigned long ap, unsigned long ric)
  73 {
  74         unsigned long rb,rs,prs,r;
  75
  76         rb = va & ~(PPC_BITMASK(52, 63));
  77         rb |= ap << PPC_BITLSHIFT(58);
  78         rs = pid << PPC_BITLSHIFT(31);
  79         prs = 1; /* process scoped */
  80         r = 1;   /* raidx format */
  81
  82         asm volatile("ptesync": : :"memory");
  83         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  84                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  85         asm volatile("ptesync": : :"memory");
  86 }
  87
  88 static inline void _tlbie_va(unsigned long va, unsigned long pid,
  89                              unsigned long ap, unsigned long ric)
  90 {
  91         unsigned long rb,rs,prs,r;
  92
  93         rb = va & ~(PPC_BITMASK(52, 63));
  94         rb |= ap << PPC_BITLSHIFT(58);
  95         rs = pid << PPC_BITLSHIFT(31);
  96         prs = 1; /* process scoped */
  97         r = 1;   /* raidx format */
  98
  99         asm volatile("ptesync": : :"memory");
 100         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 101                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 102         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 103 }
 104
 105 /*
 106  * Base TLB flushing operations:
 107  *
 108  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 109  *  - flush_tlb_page(vma, vmaddr) flushes one page
 110  *  - flush_tlb_range(vma, start, end) flushes a range of pages
 111  *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 112  *
 113  *  - local_* variants of page and mm only apply to the current
 114  *    processor
 115  */
 116 void radix__local_flush_tlb_mm(struct mm_struct *mm)
 117 {
 118         unsigned long pid;
 119
 120         preempt_disable();
 121         pid = mm->context.id;
 122         if (pid != MMU_NO_CONTEXT)
 123                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 124         preempt_enable();
 125 }
 126 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
 127
 128 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 129 {
 130         unsigned long pid;
 131         struct mm_struct *mm = tlb->mm;
 132
 133         preempt_disable();
 134
 135         pid = mm->context.id;
 136         if (pid != MMU_NO_CONTEXT)
 137                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 138
 139         preempt_enable();
 140 }
 141 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
 142
 143 void radix___local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
 144                             unsigned long ap, int nid)
 145 {
 146         unsigned long pid;
 147
 148         preempt_disable();
 149         pid = mm ? mm->context.id : 0;
 150         if (pid != MMU_NO_CONTEXT)
 151                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 152         preempt_enable();
 153 }
 154
 155 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 156 {
 157 #ifdef CONFIG_HUGETLB_PAGE
 158         /* need the return fix for nohash.c */
 159         if (vma && is_vm_hugetlb_page(vma))
 160                 return __local_flush_hugetlb_page(vma, vmaddr);
 161 #endif
 162         radix___local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
 163                                mmu_get_ap(mmu_virtual_psize), 0);
 164 }
 165 EXPORT_SYMBOL(radix__local_flush_tlb_page);
 166
 167 #ifdef CONFIG_SMP
 168 static int mm_is_core_local(struct mm_struct *mm)
 169 {
 170         return cpumask_subset(mm_cpumask(mm),
 171                               topology_sibling_cpumask(smp_processor_id()));
 172 }
 173
 174 void radix__flush_tlb_mm(struct mm_struct *mm)
 175 {
 176         unsigned long pid;
 177
 178         preempt_disable();
 179         pid = mm->context.id;
 180         if (unlikely(pid == MMU_NO_CONTEXT))
 181                 goto no_context;
 182
 183         if (!mm_is_core_local(mm)) {
 184                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 185
 186                 if (lock_tlbie)
 187                         raw_spin_lock(&native_tlbie_lock);
 188                 _tlbie_pid(pid, RIC_FLUSH_ALL);
 189                 if (lock_tlbie)
 190                         raw_spin_unlock(&native_tlbie_lock);
 191         } else
 192                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 193 no_context:
 194         preempt_enable();
 195 }
 196 EXPORT_SYMBOL(radix__flush_tlb_mm);
 197
 198 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 199 {
 200         unsigned long pid;
 201         struct mm_struct *mm = tlb->mm;
 202
 203         preempt_disable();
 204
 205         pid = mm->context.id;
 206         if (unlikely(pid == MMU_NO_CONTEXT))
 207                 goto no_context;
 208
 209         if (!mm_is_core_local(mm)) {
 210                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 211
 212                 if (lock_tlbie)
 213                         raw_spin_lock(&native_tlbie_lock);
 214                 _tlbie_pid(pid, RIC_FLUSH_PWC);
 215                 if (lock_tlbie)
 216                         raw_spin_unlock(&native_tlbie_lock);
 217         } else
 218                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 219 no_context:
 220         preempt_enable();
 221 }
 222 EXPORT_SYMBOL(radix__flush_tlb_pwc);
 223
 224 void radix___flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
 225                        unsigned long ap, int nid)
 226 {
 227         unsigned long pid;
 228
 229         preempt_disable();
 230         pid = mm ? mm->context.id : 0;
 231         if (unlikely(pid == MMU_NO_CONTEXT))
 232                 goto bail;
 233         if (!mm_is_core_local(mm)) {
 234                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 235
 236                 if (lock_tlbie)
 237                         raw_spin_lock(&native_tlbie_lock);
 238                 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 239                 if (lock_tlbie)
 240                         raw_spin_unlock(&native_tlbie_lock);
 241         } else
 242                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 243 bail:
 244         preempt_enable();
 245 }
 246
 247 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 248 {
 249 #ifdef CONFIG_HUGETLB_PAGE
 250         if (vma && is_vm_hugetlb_page(vma))
 251                 return flush_hugetlb_page(vma, vmaddr);
 252 #endif
 253         radix___flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
 254                          mmu_get_ap(mmu_virtual_psize), 0);
 255 }
 256 EXPORT_SYMBOL(radix__flush_tlb_page);
 257
 258 #endif /* CONFIG_SMP */
 259
 260 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
 261 {
 262         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 263
 264         if (lock_tlbie)
 265                 raw_spin_lock(&native_tlbie_lock);
 266         _tlbie_pid(0, RIC_FLUSH_ALL);
 267         if (lock_tlbie)
 268                 raw_spin_unlock(&native_tlbie_lock);
 269 }
 270 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
 271
 272 /*
 273  * Currently, for range flushing, we just do a full mm flush. Because
 274  * we use this in code path where we don' track the page size.
 275  */
 276 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 277                      unsigned long end)
 278
 279 {
 280         struct mm_struct *mm = vma->vm_mm;
 281         radix__flush_tlb_mm(mm);
 282 }
 283 EXPORT_SYMBOL(radix__flush_tlb_range);
 284
 285
 286 void radix__tlb_flush(struct mmu_gather *tlb)
 287 {
 288         struct mm_struct *mm = tlb->mm;
 289         radix__flush_tlb_mm(mm);
 290 }