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powerpc/powernv/idoa: Remove unnecessary pcidev from pci_dn
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/msi.h>
24 #include <linux/memblock.h>
25 #include <linux/iommu.h>
26 #include <linux/rculist.h>
27 #include <linux/sizes.h>
28
29 #include <asm/sections.h>
30 #include <asm/io.h>
31 #include <asm/prom.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
35 #include <asm/ppc-pci.h>
36 #include <asm/opal.h>
37 #include <asm/iommu.h>
38 #include <asm/tce.h>
39 #include <asm/xics.h>
40 #include <asm/debugfs.h>
41 #include <asm/firmware.h>
42 #include <asm/pnv-pci.h>
43 #include <asm/mmzone.h>
44
45 #include <misc/cxl-base.h>
46
47 #include "powernv.h"
48 #include "pci.h"
49
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
53
54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
55 #define POWERNV_IOMMU_MAX_LEVELS 5
56
57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
58 "NPU_OCAPI" };
59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
60
61 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
62 const char *fmt, ...)
63 {
64 struct va_format vaf;
65 va_list args;
66 char pfix[32];
67
68 va_start(args, fmt);
69
70 vaf.fmt = fmt;
71 vaf.va = &args;
72
73 if (pe->flags & PNV_IODA_PE_DEV)
74 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
75 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
76 sprintf(pfix, "%04x:%02x ",
77 pci_domain_nr(pe->pbus), pe->pbus->number);
78 #ifdef CONFIG_PCI_IOV
79 else if (pe->flags & PNV_IODA_PE_VF)
80 sprintf(pfix, "%04x:%02x:%2x.%d",
81 pci_domain_nr(pe->parent_dev->bus),
82 (pe->rid & 0xff00) >> 8,
83 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
84 #endif /* CONFIG_PCI_IOV*/
85
86 printk("%spci %s: [PE# %.2x] %pV",
87 level, pfix, pe->pe_number, &vaf);
88
89 va_end(args);
90 }
91
92 static bool pnv_iommu_bypass_disabled __read_mostly;
93
94 static int __init iommu_setup(char *str)
95 {
96 if (!str)
97 return -EINVAL;
98
99 while (*str) {
100 if (!strncmp(str, "nobypass", 8)) {
101 pnv_iommu_bypass_disabled = true;
102 pr_info("PowerNV: IOMMU bypass window disabled.\n");
103 break;
104 }
105 str += strcspn(str, ",");
106 if (*str == ',')
107 str++;
108 }
109
110 return 0;
111 }
112 early_param("iommu", iommu_setup);
113
114 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
115 {
116 /*
117 * WARNING: We cannot rely on the resource flags. The Linux PCI
118 * allocation code sometimes decides to put a 64-bit prefetchable
119 * BAR in the 32-bit window, so we have to compare the addresses.
120 *
121 * For simplicity we only test resource start.
122 */
123 return (r->start >= phb->ioda.m64_base &&
124 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
125 }
126
127 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
128 {
129 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
130
131 return (resource_flags & flags) == flags;
132 }
133
134 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
135 {
136 s64 rc;
137
138 phb->ioda.pe_array[pe_no].phb = phb;
139 phb->ioda.pe_array[pe_no].pe_number = pe_no;
140
141 /*
142 * Clear the PE frozen state as it might be put into frozen state
143 * in the last PCI remove path. It's not harmful to do so when the
144 * PE is already in unfrozen state.
145 */
146 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
147 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
148 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
149 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
150 __func__, rc, phb->hose->global_number, pe_no);
151
152 return &phb->ioda.pe_array[pe_no];
153 }
154
155 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
156 {
157 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
158 pr_warn("%s: Invalid PE %x on PHB#%x\n",
159 __func__, pe_no, phb->hose->global_number);
160 return;
161 }
162
163 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
164 pr_debug("%s: PE %x was reserved on PHB#%x\n",
165 __func__, pe_no, phb->hose->global_number);
166
167 pnv_ioda_init_pe(phb, pe_no);
168 }
169
170 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
171 {
172 long pe;
173
174 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
175 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
176 return pnv_ioda_init_pe(phb, pe);
177 }
178
179 return NULL;
180 }
181
182 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
183 {
184 struct pnv_phb *phb = pe->phb;
185 unsigned int pe_num = pe->pe_number;
186
187 WARN_ON(pe->pdev);
188
189 memset(pe, 0, sizeof(struct pnv_ioda_pe));
190 clear_bit(pe_num, phb->ioda.pe_alloc);
191 }
192
193 /* The default M64 BAR is shared by all PEs */
194 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
195 {
196 const char *desc;
197 struct resource *r;
198 s64 rc;
199
200 /* Configure the default M64 BAR */
201 rc = opal_pci_set_phb_mem_window(phb->opal_id,
202 OPAL_M64_WINDOW_TYPE,
203 phb->ioda.m64_bar_idx,
204 phb->ioda.m64_base,
205 0, /* unused */
206 phb->ioda.m64_size);
207 if (rc != OPAL_SUCCESS) {
208 desc = "configuring";
209 goto fail;
210 }
211
212 /* Enable the default M64 BAR */
213 rc = opal_pci_phb_mmio_enable(phb->opal_id,
214 OPAL_M64_WINDOW_TYPE,
215 phb->ioda.m64_bar_idx,
216 OPAL_ENABLE_M64_SPLIT);
217 if (rc != OPAL_SUCCESS) {
218 desc = "enabling";
219 goto fail;
220 }
221
222 /*
223 * Exclude the segments for reserved and root bus PE, which
224 * are first or last two PEs.
225 */
226 r = &phb->hose->mem_resources[1];
227 if (phb->ioda.reserved_pe_idx == 0)
228 r->start += (2 * phb->ioda.m64_segsize);
229 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
230 r->end -= (2 * phb->ioda.m64_segsize);
231 else
232 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
233 phb->ioda.reserved_pe_idx);
234
235 return 0;
236
237 fail:
238 pr_warn(" Failure %lld %s M64 BAR#%d\n",
239 rc, desc, phb->ioda.m64_bar_idx);
240 opal_pci_phb_mmio_enable(phb->opal_id,
241 OPAL_M64_WINDOW_TYPE,
242 phb->ioda.m64_bar_idx,
243 OPAL_DISABLE_M64);
244 return -EIO;
245 }
246
247 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
248 unsigned long *pe_bitmap)
249 {
250 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
251 struct pnv_phb *phb = hose->private_data;
252 struct resource *r;
253 resource_size_t base, sgsz, start, end;
254 int segno, i;
255
256 base = phb->ioda.m64_base;
257 sgsz = phb->ioda.m64_segsize;
258 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
259 r = &pdev->resource[i];
260 if (!r->parent || !pnv_pci_is_m64(phb, r))
261 continue;
262
263 start = _ALIGN_DOWN(r->start - base, sgsz);
264 end = _ALIGN_UP(r->end - base, sgsz);
265 for (segno = start / sgsz; segno < end / sgsz; segno++) {
266 if (pe_bitmap)
267 set_bit(segno, pe_bitmap);
268 else
269 pnv_ioda_reserve_pe(phb, segno);
270 }
271 }
272 }
273
274 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
275 {
276 struct resource *r;
277 int index;
278
279 /*
280 * There are 16 M64 BARs, each of which has 8 segments. So
281 * there are as many M64 segments as the maximum number of
282 * PEs, which is 128.
283 */
284 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
285 unsigned long base, segsz = phb->ioda.m64_segsize;
286 int64_t rc;
287
288 base = phb->ioda.m64_base +
289 index * PNV_IODA1_M64_SEGS * segsz;
290 rc = opal_pci_set_phb_mem_window(phb->opal_id,
291 OPAL_M64_WINDOW_TYPE, index, base, 0,
292 PNV_IODA1_M64_SEGS * segsz);
293 if (rc != OPAL_SUCCESS) {
294 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
295 rc, phb->hose->global_number, index);
296 goto fail;
297 }
298
299 rc = opal_pci_phb_mmio_enable(phb->opal_id,
300 OPAL_M64_WINDOW_TYPE, index,
301 OPAL_ENABLE_M64_SPLIT);
302 if (rc != OPAL_SUCCESS) {
303 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
304 rc, phb->hose->global_number, index);
305 goto fail;
306 }
307 }
308
309 /*
310 * Exclude the segments for reserved and root bus PE, which
311 * are first or last two PEs.
312 */
313 r = &phb->hose->mem_resources[1];
314 if (phb->ioda.reserved_pe_idx == 0)
315 r->start += (2 * phb->ioda.m64_segsize);
316 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
317 r->end -= (2 * phb->ioda.m64_segsize);
318 else
319 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
320 phb->ioda.reserved_pe_idx, phb->hose->global_number);
321
322 return 0;
323
324 fail:
325 for ( ; index >= 0; index--)
326 opal_pci_phb_mmio_enable(phb->opal_id,
327 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
328
329 return -EIO;
330 }
331
332 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
333 unsigned long *pe_bitmap,
334 bool all)
335 {
336 struct pci_dev *pdev;
337
338 list_for_each_entry(pdev, &bus->devices, bus_list) {
339 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
340
341 if (all && pdev->subordinate)
342 pnv_ioda_reserve_m64_pe(pdev->subordinate,
343 pe_bitmap, all);
344 }
345 }
346
347 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
348 {
349 struct pci_controller *hose = pci_bus_to_host(bus);
350 struct pnv_phb *phb = hose->private_data;
351 struct pnv_ioda_pe *master_pe, *pe;
352 unsigned long size, *pe_alloc;
353 int i;
354
355 /* Root bus shouldn't use M64 */
356 if (pci_is_root_bus(bus))
357 return NULL;
358
359 /* Allocate bitmap */
360 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
361 pe_alloc = kzalloc(size, GFP_KERNEL);
362 if (!pe_alloc) {
363 pr_warn("%s: Out of memory !\n",
364 __func__);
365 return NULL;
366 }
367
368 /* Figure out reserved PE numbers by the PE */
369 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
370
371 /*
372 * the current bus might not own M64 window and that's all
373 * contributed by its child buses. For the case, we needn't
374 * pick M64 dependent PE#.
375 */
376 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
377 kfree(pe_alloc);
378 return NULL;
379 }
380
381 /*
382 * Figure out the master PE and put all slave PEs to master
383 * PE's list to form compound PE.
384 */
385 master_pe = NULL;
386 i = -1;
387 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
388 phb->ioda.total_pe_num) {
389 pe = &phb->ioda.pe_array[i];
390
391 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
392 if (!master_pe) {
393 pe->flags |= PNV_IODA_PE_MASTER;
394 INIT_LIST_HEAD(&pe->slaves);
395 master_pe = pe;
396 } else {
397 pe->flags |= PNV_IODA_PE_SLAVE;
398 pe->master = master_pe;
399 list_add_tail(&pe->list, &master_pe->slaves);
400 }
401
402 /*
403 * P7IOC supports M64DT, which helps mapping M64 segment
404 * to one particular PE#. However, PHB3 has fixed mapping
405 * between M64 segment and PE#. In order to have same logic
406 * for P7IOC and PHB3, we enforce fixed mapping between M64
407 * segment and PE# on P7IOC.
408 */
409 if (phb->type == PNV_PHB_IODA1) {
410 int64_t rc;
411
412 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
413 pe->pe_number, OPAL_M64_WINDOW_TYPE,
414 pe->pe_number / PNV_IODA1_M64_SEGS,
415 pe->pe_number % PNV_IODA1_M64_SEGS);
416 if (rc != OPAL_SUCCESS)
417 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
418 __func__, rc, phb->hose->global_number,
419 pe->pe_number);
420 }
421 }
422
423 kfree(pe_alloc);
424 return master_pe;
425 }
426
427 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
428 {
429 struct pci_controller *hose = phb->hose;
430 struct device_node *dn = hose->dn;
431 struct resource *res;
432 u32 m64_range[2], i;
433 const __be32 *r;
434 u64 pci_addr;
435
436 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
437 pr_info(" Not support M64 window\n");
438 return;
439 }
440
441 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
442 pr_info(" Firmware too old to support M64 window\n");
443 return;
444 }
445
446 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
447 if (!r) {
448 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
449 dn);
450 return;
451 }
452
453 /*
454 * Find the available M64 BAR range and pickup the last one for
455 * covering the whole 64-bits space. We support only one range.
456 */
457 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
458 m64_range, 2)) {
459 /* In absence of the property, assume 0..15 */
460 m64_range[0] = 0;
461 m64_range[1] = 16;
462 }
463 /* We only support 64 bits in our allocator */
464 if (m64_range[1] > 63) {
465 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
466 __func__, m64_range[1], phb->hose->global_number);
467 m64_range[1] = 63;
468 }
469 /* Empty range, no m64 */
470 if (m64_range[1] <= m64_range[0]) {
471 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
472 __func__, phb->hose->global_number);
473 return;
474 }
475
476 /* Configure M64 informations */
477 res = &hose->mem_resources[1];
478 res->name = dn->full_name;
479 res->start = of_translate_address(dn, r + 2);
480 res->end = res->start + of_read_number(r + 4, 2) - 1;
481 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
482 pci_addr = of_read_number(r, 2);
483 hose->mem_offset[1] = res->start - pci_addr;
484
485 phb->ioda.m64_size = resource_size(res);
486 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
487 phb->ioda.m64_base = pci_addr;
488
489 /* This lines up nicely with the display from processing OF ranges */
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
491 res->start, res->end, pci_addr, m64_range[0],
492 m64_range[0] + m64_range[1] - 1);
493
494 /* Mark all M64 used up by default */
495 phb->ioda.m64_bar_alloc = (unsigned long)-1;
496
497 /* Use last M64 BAR to cover M64 window */
498 m64_range[1]--;
499 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
500
501 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
502
503 /* Mark remaining ones free */
504 for (i = m64_range[0]; i < m64_range[1]; i++)
505 clear_bit(i, &phb->ioda.m64_bar_alloc);
506
507 /*
508 * Setup init functions for M64 based on IODA version, IODA3 uses
509 * the IODA2 code.
510 */
511 if (phb->type == PNV_PHB_IODA1)
512 phb->init_m64 = pnv_ioda1_init_m64;
513 else
514 phb->init_m64 = pnv_ioda2_init_m64;
515 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
516 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
517 }
518
519 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
520 {
521 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
522 struct pnv_ioda_pe *slave;
523 s64 rc;
524
525 /* Fetch master PE */
526 if (pe->flags & PNV_IODA_PE_SLAVE) {
527 pe = pe->master;
528 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
529 return;
530
531 pe_no = pe->pe_number;
532 }
533
534 /* Freeze master PE */
535 rc = opal_pci_eeh_freeze_set(phb->opal_id,
536 pe_no,
537 OPAL_EEH_ACTION_SET_FREEZE_ALL);
538 if (rc != OPAL_SUCCESS) {
539 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
540 __func__, rc, phb->hose->global_number, pe_no);
541 return;
542 }
543
544 /* Freeze slave PEs */
545 if (!(pe->flags & PNV_IODA_PE_MASTER))
546 return;
547
548 list_for_each_entry(slave, &pe->slaves, list) {
549 rc = opal_pci_eeh_freeze_set(phb->opal_id,
550 slave->pe_number,
551 OPAL_EEH_ACTION_SET_FREEZE_ALL);
552 if (rc != OPAL_SUCCESS)
553 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
554 __func__, rc, phb->hose->global_number,
555 slave->pe_number);
556 }
557 }
558
559 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
560 {
561 struct pnv_ioda_pe *pe, *slave;
562 s64 rc;
563
564 /* Find master PE */
565 pe = &phb->ioda.pe_array[pe_no];
566 if (pe->flags & PNV_IODA_PE_SLAVE) {
567 pe = pe->master;
568 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
569 pe_no = pe->pe_number;
570 }
571
572 /* Clear frozen state for master PE */
573 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
574 if (rc != OPAL_SUCCESS) {
575 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
576 __func__, rc, opt, phb->hose->global_number, pe_no);
577 return -EIO;
578 }
579
580 if (!(pe->flags & PNV_IODA_PE_MASTER))
581 return 0;
582
583 /* Clear frozen state for slave PEs */
584 list_for_each_entry(slave, &pe->slaves, list) {
585 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
586 slave->pe_number,
587 opt);
588 if (rc != OPAL_SUCCESS) {
589 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
590 __func__, rc, opt, phb->hose->global_number,
591 slave->pe_number);
592 return -EIO;
593 }
594 }
595
596 return 0;
597 }
598
599 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
600 {
601 struct pnv_ioda_pe *slave, *pe;
602 u8 fstate, state;
603 __be16 pcierr;
604 s64 rc;
605
606 /* Sanity check on PE number */
607 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
608 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
609
610 /*
611 * Fetch the master PE and the PE instance might be
612 * not initialized yet.
613 */
614 pe = &phb->ioda.pe_array[pe_no];
615 if (pe->flags & PNV_IODA_PE_SLAVE) {
616 pe = pe->master;
617 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
618 pe_no = pe->pe_number;
619 }
620
621 /* Check the master PE */
622 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
623 &state, &pcierr, NULL);
624 if (rc != OPAL_SUCCESS) {
625 pr_warn("%s: Failure %lld getting "
626 "PHB#%x-PE#%x state\n",
627 __func__, rc,
628 phb->hose->global_number, pe_no);
629 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
630 }
631
632 /* Check the slave PE */
633 if (!(pe->flags & PNV_IODA_PE_MASTER))
634 return state;
635
636 list_for_each_entry(slave, &pe->slaves, list) {
637 rc = opal_pci_eeh_freeze_status(phb->opal_id,
638 slave->pe_number,
639 &fstate,
640 &pcierr,
641 NULL);
642 if (rc != OPAL_SUCCESS) {
643 pr_warn("%s: Failure %lld getting "
644 "PHB#%x-PE#%x state\n",
645 __func__, rc,
646 phb->hose->global_number, slave->pe_number);
647 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
648 }
649
650 /*
651 * Override the result based on the ascending
652 * priority.
653 */
654 if (fstate > state)
655 state = fstate;
656 }
657
658 return state;
659 }
660
661 /* Currently those 2 are only used when MSIs are enabled, this will change
662 * but in the meantime, we need to protect them to avoid warnings
663 */
664 #ifdef CONFIG_PCI_MSI
665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
666 {
667 struct pci_controller *hose = pci_bus_to_host(dev->bus);
668 struct pnv_phb *phb = hose->private_data;
669 struct pci_dn *pdn = pci_get_pdn(dev);
670
671 if (!pdn)
672 return NULL;
673 if (pdn->pe_number == IODA_INVALID_PE)
674 return NULL;
675 return &phb->ioda.pe_array[pdn->pe_number];
676 }
677 #endif /* CONFIG_PCI_MSI */
678
679 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
680 struct pnv_ioda_pe *parent,
681 struct pnv_ioda_pe *child,
682 bool is_add)
683 {
684 const char *desc = is_add ? "adding" : "removing";
685 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
686 OPAL_REMOVE_PE_FROM_DOMAIN;
687 struct pnv_ioda_pe *slave;
688 long rc;
689
690 /* Parent PE affects child PE */
691 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
692 child->pe_number, op);
693 if (rc != OPAL_SUCCESS) {
694 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
695 rc, desc);
696 return -ENXIO;
697 }
698
699 if (!(child->flags & PNV_IODA_PE_MASTER))
700 return 0;
701
702 /* Compound case: parent PE affects slave PEs */
703 list_for_each_entry(slave, &child->slaves, list) {
704 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
705 slave->pe_number, op);
706 if (rc != OPAL_SUCCESS) {
707 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
708 rc, desc);
709 return -ENXIO;
710 }
711 }
712
713 return 0;
714 }
715
716 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
717 struct pnv_ioda_pe *pe,
718 bool is_add)
719 {
720 struct pnv_ioda_pe *slave;
721 struct pci_dev *pdev = NULL;
722 int ret;
723
724 /*
725 * Clear PE frozen state. If it's master PE, we need
726 * clear slave PE frozen state as well.
727 */
728 if (is_add) {
729 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
730 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
731 if (pe->flags & PNV_IODA_PE_MASTER) {
732 list_for_each_entry(slave, &pe->slaves, list)
733 opal_pci_eeh_freeze_clear(phb->opal_id,
734 slave->pe_number,
735 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
736 }
737 }
738
739 /*
740 * Associate PE in PELT. We need add the PE into the
741 * corresponding PELT-V as well. Otherwise, the error
742 * originated from the PE might contribute to other
743 * PEs.
744 */
745 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
746 if (ret)
747 return ret;
748
749 /* For compound PEs, any one affects all of them */
750 if (pe->flags & PNV_IODA_PE_MASTER) {
751 list_for_each_entry(slave, &pe->slaves, list) {
752 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
753 if (ret)
754 return ret;
755 }
756 }
757
758 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
759 pdev = pe->pbus->self;
760 else if (pe->flags & PNV_IODA_PE_DEV)
761 pdev = pe->pdev->bus->self;
762 #ifdef CONFIG_PCI_IOV
763 else if (pe->flags & PNV_IODA_PE_VF)
764 pdev = pe->parent_dev;
765 #endif /* CONFIG_PCI_IOV */
766 while (pdev) {
767 struct pci_dn *pdn = pci_get_pdn(pdev);
768 struct pnv_ioda_pe *parent;
769
770 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
771 parent = &phb->ioda.pe_array[pdn->pe_number];
772 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
773 if (ret)
774 return ret;
775 }
776
777 pdev = pdev->bus->self;
778 }
779
780 return 0;
781 }
782
783 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
784 {
785 struct pci_dev *parent;
786 uint8_t bcomp, dcomp, fcomp;
787 int64_t rc;
788 long rid_end, rid;
789
790 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
791 if (pe->pbus) {
792 int count;
793
794 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
795 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
796 parent = pe->pbus->self;
797 if (pe->flags & PNV_IODA_PE_BUS_ALL)
798 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
799 else
800 count = 1;
801
802 switch(count) {
803 case 1: bcomp = OpalPciBusAll; break;
804 case 2: bcomp = OpalPciBus7Bits; break;
805 case 4: bcomp = OpalPciBus6Bits; break;
806 case 8: bcomp = OpalPciBus5Bits; break;
807 case 16: bcomp = OpalPciBus4Bits; break;
808 case 32: bcomp = OpalPciBus3Bits; break;
809 default:
810 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
811 count);
812 /* Do an exact match only */
813 bcomp = OpalPciBusAll;
814 }
815 rid_end = pe->rid + (count << 8);
816 } else {
817 #ifdef CONFIG_PCI_IOV
818 if (pe->flags & PNV_IODA_PE_VF)
819 parent = pe->parent_dev;
820 else
821 #endif
822 parent = pe->pdev->bus->self;
823 bcomp = OpalPciBusAll;
824 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
825 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
826 rid_end = pe->rid + 1;
827 }
828
829 /* Clear the reverse map */
830 for (rid = pe->rid; rid < rid_end; rid++)
831 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
832
833 /* Release from all parents PELT-V */
834 while (parent) {
835 struct pci_dn *pdn = pci_get_pdn(parent);
836 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
837 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
838 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
839 /* XXX What to do in case of error ? */
840 }
841 parent = parent->bus->self;
842 }
843
844 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
845 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
846
847 /* Disassociate PE in PELT */
848 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
849 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
850 if (rc)
851 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
852 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
853 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
854 if (rc)
855 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
856
857 pe->pbus = NULL;
858 pe->pdev = NULL;
859 #ifdef CONFIG_PCI_IOV
860 pe->parent_dev = NULL;
861 #endif
862
863 return 0;
864 }
865
866 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
867 {
868 struct pci_dev *parent;
869 uint8_t bcomp, dcomp, fcomp;
870 long rc, rid_end, rid;
871
872 /* Bus validation ? */
873 if (pe->pbus) {
874 int count;
875
876 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
877 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
878 parent = pe->pbus->self;
879 if (pe->flags & PNV_IODA_PE_BUS_ALL)
880 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
881 else
882 count = 1;
883
884 switch(count) {
885 case 1: bcomp = OpalPciBusAll; break;
886 case 2: bcomp = OpalPciBus7Bits; break;
887 case 4: bcomp = OpalPciBus6Bits; break;
888 case 8: bcomp = OpalPciBus5Bits; break;
889 case 16: bcomp = OpalPciBus4Bits; break;
890 case 32: bcomp = OpalPciBus3Bits; break;
891 default:
892 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
893 count);
894 /* Do an exact match only */
895 bcomp = OpalPciBusAll;
896 }
897 rid_end = pe->rid + (count << 8);
898 } else {
899 #ifdef CONFIG_PCI_IOV
900 if (pe->flags & PNV_IODA_PE_VF)
901 parent = pe->parent_dev;
902 else
903 #endif /* CONFIG_PCI_IOV */
904 parent = pe->pdev->bus->self;
905 bcomp = OpalPciBusAll;
906 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
907 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
908 rid_end = pe->rid + 1;
909 }
910
911 /*
912 * Associate PE in PELT. We need add the PE into the
913 * corresponding PELT-V as well. Otherwise, the error
914 * originated from the PE might contribute to other
915 * PEs.
916 */
917 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
918 bcomp, dcomp, fcomp, OPAL_MAP_PE);
919 if (rc) {
920 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
921 return -ENXIO;
922 }
923
924 /*
925 * Configure PELTV. NPUs don't have a PELTV table so skip
926 * configuration on them.
927 */
928 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
929 pnv_ioda_set_peltv(phb, pe, true);
930
931 /* Setup reverse map */
932 for (rid = pe->rid; rid < rid_end; rid++)
933 phb->ioda.pe_rmap[rid] = pe->pe_number;
934
935 /* Setup one MVTs on IODA1 */
936 if (phb->type != PNV_PHB_IODA1) {
937 pe->mve_number = 0;
938 goto out;
939 }
940
941 pe->mve_number = pe->pe_number;
942 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
943 if (rc != OPAL_SUCCESS) {
944 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
945 rc, pe->mve_number);
946 pe->mve_number = -1;
947 } else {
948 rc = opal_pci_set_mve_enable(phb->opal_id,
949 pe->mve_number, OPAL_ENABLE_MVE);
950 if (rc) {
951 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
952 rc, pe->mve_number);
953 pe->mve_number = -1;
954 }
955 }
956
957 out:
958 return 0;
959 }
960
961 #ifdef CONFIG_PCI_IOV
962 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
963 {
964 struct pci_dn *pdn = pci_get_pdn(dev);
965 int i;
966 struct resource *res, res2;
967 resource_size_t size;
968 u16 num_vfs;
969
970 if (!dev->is_physfn)
971 return -EINVAL;
972
973 /*
974 * "offset" is in VFs. The M64 windows are sized so that when they
975 * are segmented, each segment is the same size as the IOV BAR.
976 * Each segment is in a separate PE, and the high order bits of the
977 * address are the PE number. Therefore, each VF's BAR is in a
978 * separate PE, and changing the IOV BAR start address changes the
979 * range of PEs the VFs are in.
980 */
981 num_vfs = pdn->num_vfs;
982 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
983 res = &dev->resource[i + PCI_IOV_RESOURCES];
984 if (!res->flags || !res->parent)
985 continue;
986
987 /*
988 * The actual IOV BAR range is determined by the start address
989 * and the actual size for num_vfs VFs BAR. This check is to
990 * make sure that after shifting, the range will not overlap
991 * with another device.
992 */
993 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
994 res2.flags = res->flags;
995 res2.start = res->start + (size * offset);
996 res2.end = res2.start + (size * num_vfs) - 1;
997
998 if (res2.end > res->end) {
999 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1000 i, &res2, res, num_vfs, offset);
1001 return -EBUSY;
1002 }
1003 }
1004
1005 /*
1006 * Since M64 BAR shares segments among all possible 256 PEs,
1007 * we have to shift the beginning of PF IOV BAR to make it start from
1008 * the segment which belongs to the PE number assigned to the first VF.
1009 * This creates a "hole" in the /proc/iomem which could be used for
1010 * allocating other resources so we reserve this area below and
1011 * release when IOV is released.
1012 */
1013 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1014 res = &dev->resource[i + PCI_IOV_RESOURCES];
1015 if (!res->flags || !res->parent)
1016 continue;
1017
1018 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1019 res2 = *res;
1020 res->start += size * offset;
1021
1022 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1023 i, &res2, res, (offset > 0) ? "En" : "Dis",
1024 num_vfs, offset);
1025
1026 if (offset < 0) {
1027 devm_release_resource(&dev->dev, &pdn->holes[i]);
1028 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1029 }
1030
1031 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1032
1033 if (offset > 0) {
1034 pdn->holes[i].start = res2.start;
1035 pdn->holes[i].end = res2.start + size * offset - 1;
1036 pdn->holes[i].flags = IORESOURCE_BUS;
1037 pdn->holes[i].name = "pnv_iov_reserved";
1038 devm_request_resource(&dev->dev, res->parent,
1039 &pdn->holes[i]);
1040 }
1041 }
1042 return 0;
1043 }
1044 #endif /* CONFIG_PCI_IOV */
1045
1046 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1047 {
1048 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1049 struct pnv_phb *phb = hose->private_data;
1050 struct pci_dn *pdn = pci_get_pdn(dev);
1051 struct pnv_ioda_pe *pe;
1052
1053 if (!pdn) {
1054 pr_err("%s: Device tree node not associated properly\n",
1055 pci_name(dev));
1056 return NULL;
1057 }
1058 if (pdn->pe_number != IODA_INVALID_PE)
1059 return NULL;
1060
1061 pe = pnv_ioda_alloc_pe(phb);
1062 if (!pe) {
1063 pr_warning("%s: Not enough PE# available, disabling device\n",
1064 pci_name(dev));
1065 return NULL;
1066 }
1067
1068 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1069 * pointer in the PE data structure, both should be destroyed at the
1070 * same time. However, this needs to be looked at more closely again
1071 * once we actually start removing things (Hotplug, SR-IOV, ...)
1072 *
1073 * At some point we want to remove the PDN completely anyways
1074 */
1075 pci_dev_get(dev);
1076 pdn->pe_number = pe->pe_number;
1077 pe->flags = PNV_IODA_PE_DEV;
1078 pe->pdev = dev;
1079 pe->pbus = NULL;
1080 pe->mve_number = -1;
1081 pe->rid = dev->bus->number << 8 | pdn->devfn;
1082
1083 pe_info(pe, "Associated device to PE\n");
1084
1085 if (pnv_ioda_configure_pe(phb, pe)) {
1086 /* XXX What do we do here ? */
1087 pnv_ioda_free_pe(pe);
1088 pdn->pe_number = IODA_INVALID_PE;
1089 pe->pdev = NULL;
1090 pci_dev_put(dev);
1091 return NULL;
1092 }
1093
1094 /* Put PE to the list */
1095 list_add_tail(&pe->list, &phb->ioda.pe_list);
1096
1097 return pe;
1098 }
1099
1100 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1101 {
1102 struct pci_dev *dev;
1103
1104 list_for_each_entry(dev, &bus->devices, bus_list) {
1105 struct pci_dn *pdn = pci_get_pdn(dev);
1106
1107 if (pdn == NULL) {
1108 pr_warn("%s: No device node associated with device !\n",
1109 pci_name(dev));
1110 continue;
1111 }
1112
1113 /*
1114 * In partial hotplug case, the PCI device might be still
1115 * associated with the PE and needn't attach it to the PE
1116 * again.
1117 */
1118 if (pdn->pe_number != IODA_INVALID_PE)
1119 continue;
1120
1121 pe->device_count++;
1122 pdn->pe_number = pe->pe_number;
1123 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1124 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1125 }
1126 }
1127
1128 /*
1129 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1130 * single PCI bus. Another one that contains the primary PCI bus and its
1131 * subordinate PCI devices and buses. The second type of PE is normally
1132 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1133 */
1134 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1135 {
1136 struct pci_controller *hose = pci_bus_to_host(bus);
1137 struct pnv_phb *phb = hose->private_data;
1138 struct pnv_ioda_pe *pe = NULL;
1139 unsigned int pe_num;
1140
1141 /*
1142 * In partial hotplug case, the PE instance might be still alive.
1143 * We should reuse it instead of allocating a new one.
1144 */
1145 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1146 if (pe_num != IODA_INVALID_PE) {
1147 pe = &phb->ioda.pe_array[pe_num];
1148 pnv_ioda_setup_same_PE(bus, pe);
1149 return NULL;
1150 }
1151
1152 /* PE number for root bus should have been reserved */
1153 if (pci_is_root_bus(bus) &&
1154 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1155 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1156
1157 /* Check if PE is determined by M64 */
1158 if (!pe && phb->pick_m64_pe)
1159 pe = phb->pick_m64_pe(bus, all);
1160
1161 /* The PE number isn't pinned by M64 */
1162 if (!pe)
1163 pe = pnv_ioda_alloc_pe(phb);
1164
1165 if (!pe) {
1166 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1167 __func__, pci_domain_nr(bus), bus->number);
1168 return NULL;
1169 }
1170
1171 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1172 pe->pbus = bus;
1173 pe->pdev = NULL;
1174 pe->mve_number = -1;
1175 pe->rid = bus->busn_res.start << 8;
1176
1177 if (all)
1178 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1179 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1180 else
1181 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1182 bus->busn_res.start, pe->pe_number);
1183
1184 if (pnv_ioda_configure_pe(phb, pe)) {
1185 /* XXX What do we do here ? */
1186 pnv_ioda_free_pe(pe);
1187 pe->pbus = NULL;
1188 return NULL;
1189 }
1190
1191 /* Associate it with all child devices */
1192 pnv_ioda_setup_same_PE(bus, pe);
1193
1194 /* Put PE to the list */
1195 list_add_tail(&pe->list, &phb->ioda.pe_list);
1196
1197 return pe;
1198 }
1199
1200 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1201 {
1202 int pe_num, found_pe = false, rc;
1203 long rid;
1204 struct pnv_ioda_pe *pe;
1205 struct pci_dev *gpu_pdev;
1206 struct pci_dn *npu_pdn;
1207 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1208 struct pnv_phb *phb = hose->private_data;
1209
1210 /*
1211 * Due to a hardware errata PE#0 on the NPU is reserved for
1212 * error handling. This means we only have three PEs remaining
1213 * which need to be assigned to four links, implying some
1214 * links must share PEs.
1215 *
1216 * To achieve this we assign PEs such that NPUs linking the
1217 * same GPU get assigned the same PE.
1218 */
1219 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1220 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1221 pe = &phb->ioda.pe_array[pe_num];
1222 if (!pe->pdev)
1223 continue;
1224
1225 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1226 /*
1227 * This device has the same peer GPU so should
1228 * be assigned the same PE as the existing
1229 * peer NPU.
1230 */
1231 dev_info(&npu_pdev->dev,
1232 "Associating to existing PE %x\n", pe_num);
1233 pci_dev_get(npu_pdev);
1234 npu_pdn = pci_get_pdn(npu_pdev);
1235 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1236 npu_pdn->pe_number = pe_num;
1237 phb->ioda.pe_rmap[rid] = pe->pe_number;
1238
1239 /* Map the PE to this link */
1240 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1241 OpalPciBusAll,
1242 OPAL_COMPARE_RID_DEVICE_NUMBER,
1243 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1244 OPAL_MAP_PE);
1245 WARN_ON(rc != OPAL_SUCCESS);
1246 found_pe = true;
1247 break;
1248 }
1249 }
1250
1251 if (!found_pe)
1252 /*
1253 * Could not find an existing PE so allocate a new
1254 * one.
1255 */
1256 return pnv_ioda_setup_dev_PE(npu_pdev);
1257 else
1258 return pe;
1259 }
1260
1261 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1262 {
1263 struct pci_dev *pdev;
1264
1265 list_for_each_entry(pdev, &bus->devices, bus_list)
1266 pnv_ioda_setup_npu_PE(pdev);
1267 }
1268
1269 static void pnv_pci_ioda_setup_PEs(void)
1270 {
1271 struct pci_controller *hose, *tmp;
1272 struct pnv_phb *phb;
1273 struct pci_bus *bus;
1274 struct pci_dev *pdev;
1275
1276 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1277 phb = hose->private_data;
1278 if (phb->type == PNV_PHB_NPU_NVLINK) {
1279 /* PE#0 is needed for error reporting */
1280 pnv_ioda_reserve_pe(phb, 0);
1281 pnv_ioda_setup_npu_PEs(hose->bus);
1282 if (phb->model == PNV_PHB_MODEL_NPU2)
1283 pnv_npu2_init(phb);
1284 }
1285 if (phb->type == PNV_PHB_NPU_OCAPI) {
1286 bus = hose->bus;
1287 list_for_each_entry(pdev, &bus->devices, bus_list)
1288 pnv_ioda_setup_dev_PE(pdev);
1289 }
1290 }
1291 }
1292
1293 #ifdef CONFIG_PCI_IOV
1294 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1295 {
1296 struct pci_bus *bus;
1297 struct pci_controller *hose;
1298 struct pnv_phb *phb;
1299 struct pci_dn *pdn;
1300 int i, j;
1301 int m64_bars;
1302
1303 bus = pdev->bus;
1304 hose = pci_bus_to_host(bus);
1305 phb = hose->private_data;
1306 pdn = pci_get_pdn(pdev);
1307
1308 if (pdn->m64_single_mode)
1309 m64_bars = num_vfs;
1310 else
1311 m64_bars = 1;
1312
1313 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1314 for (j = 0; j < m64_bars; j++) {
1315 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1316 continue;
1317 opal_pci_phb_mmio_enable(phb->opal_id,
1318 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1319 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1320 pdn->m64_map[j][i] = IODA_INVALID_M64;
1321 }
1322
1323 kfree(pdn->m64_map);
1324 return 0;
1325 }
1326
1327 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1328 {
1329 struct pci_bus *bus;
1330 struct pci_controller *hose;
1331 struct pnv_phb *phb;
1332 struct pci_dn *pdn;
1333 unsigned int win;
1334 struct resource *res;
1335 int i, j;
1336 int64_t rc;
1337 int total_vfs;
1338 resource_size_t size, start;
1339 int pe_num;
1340 int m64_bars;
1341
1342 bus = pdev->bus;
1343 hose = pci_bus_to_host(bus);
1344 phb = hose->private_data;
1345 pdn = pci_get_pdn(pdev);
1346 total_vfs = pci_sriov_get_totalvfs(pdev);
1347
1348 if (pdn->m64_single_mode)
1349 m64_bars = num_vfs;
1350 else
1351 m64_bars = 1;
1352
1353 pdn->m64_map = kmalloc_array(m64_bars,
1354 sizeof(*pdn->m64_map),
1355 GFP_KERNEL);
1356 if (!pdn->m64_map)
1357 return -ENOMEM;
1358 /* Initialize the m64_map to IODA_INVALID_M64 */
1359 for (i = 0; i < m64_bars ; i++)
1360 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1361 pdn->m64_map[i][j] = IODA_INVALID_M64;
1362
1363
1364 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1365 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1366 if (!res->flags || !res->parent)
1367 continue;
1368
1369 for (j = 0; j < m64_bars; j++) {
1370 do {
1371 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1372 phb->ioda.m64_bar_idx + 1, 0);
1373
1374 if (win >= phb->ioda.m64_bar_idx + 1)
1375 goto m64_failed;
1376 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1377
1378 pdn->m64_map[j][i] = win;
1379
1380 if (pdn->m64_single_mode) {
1381 size = pci_iov_resource_size(pdev,
1382 PCI_IOV_RESOURCES + i);
1383 start = res->start + size * j;
1384 } else {
1385 size = resource_size(res);
1386 start = res->start;
1387 }
1388
1389 /* Map the M64 here */
1390 if (pdn->m64_single_mode) {
1391 pe_num = pdn->pe_num_map[j];
1392 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1393 pe_num, OPAL_M64_WINDOW_TYPE,
1394 pdn->m64_map[j][i], 0);
1395 }
1396
1397 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1398 OPAL_M64_WINDOW_TYPE,
1399 pdn->m64_map[j][i],
1400 start,
1401 0, /* unused */
1402 size);
1403
1404
1405 if (rc != OPAL_SUCCESS) {
1406 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1407 win, rc);
1408 goto m64_failed;
1409 }
1410
1411 if (pdn->m64_single_mode)
1412 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1413 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1414 else
1415 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1416 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1417
1418 if (rc != OPAL_SUCCESS) {
1419 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1420 win, rc);
1421 goto m64_failed;
1422 }
1423 }
1424 }
1425 return 0;
1426
1427 m64_failed:
1428 pnv_pci_vf_release_m64(pdev, num_vfs);
1429 return -EBUSY;
1430 }
1431
1432 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1433 int num);
1434
1435 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1436 {
1437 struct iommu_table *tbl;
1438 int64_t rc;
1439
1440 tbl = pe->table_group.tables[0];
1441 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1442 if (rc)
1443 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1444
1445 pnv_pci_ioda2_set_bypass(pe, false);
1446 if (pe->table_group.group) {
1447 iommu_group_put(pe->table_group.group);
1448 BUG_ON(pe->table_group.group);
1449 }
1450 iommu_tce_table_put(tbl);
1451 }
1452
1453 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1454 {
1455 struct pci_bus *bus;
1456 struct pci_controller *hose;
1457 struct pnv_phb *phb;
1458 struct pnv_ioda_pe *pe, *pe_n;
1459 struct pci_dn *pdn;
1460
1461 bus = pdev->bus;
1462 hose = pci_bus_to_host(bus);
1463 phb = hose->private_data;
1464 pdn = pci_get_pdn(pdev);
1465
1466 if (!pdev->is_physfn)
1467 return;
1468
1469 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1470 if (pe->parent_dev != pdev)
1471 continue;
1472
1473 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1474
1475 /* Remove from list */
1476 mutex_lock(&phb->ioda.pe_list_mutex);
1477 list_del(&pe->list);
1478 mutex_unlock(&phb->ioda.pe_list_mutex);
1479
1480 pnv_ioda_deconfigure_pe(phb, pe);
1481
1482 pnv_ioda_free_pe(pe);
1483 }
1484 }
1485
1486 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1487 {
1488 struct pci_bus *bus;
1489 struct pci_controller *hose;
1490 struct pnv_phb *phb;
1491 struct pnv_ioda_pe *pe;
1492 struct pci_dn *pdn;
1493 u16 num_vfs, i;
1494
1495 bus = pdev->bus;
1496 hose = pci_bus_to_host(bus);
1497 phb = hose->private_data;
1498 pdn = pci_get_pdn(pdev);
1499 num_vfs = pdn->num_vfs;
1500
1501 /* Release VF PEs */
1502 pnv_ioda_release_vf_PE(pdev);
1503
1504 if (phb->type == PNV_PHB_IODA2) {
1505 if (!pdn->m64_single_mode)
1506 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1507
1508 /* Release M64 windows */
1509 pnv_pci_vf_release_m64(pdev, num_vfs);
1510
1511 /* Release PE numbers */
1512 if (pdn->m64_single_mode) {
1513 for (i = 0; i < num_vfs; i++) {
1514 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1515 continue;
1516
1517 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1518 pnv_ioda_free_pe(pe);
1519 }
1520 } else
1521 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1522 /* Releasing pe_num_map */
1523 kfree(pdn->pe_num_map);
1524 }
1525 }
1526
1527 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1528 struct pnv_ioda_pe *pe);
1529 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1530 {
1531 struct pci_bus *bus;
1532 struct pci_controller *hose;
1533 struct pnv_phb *phb;
1534 struct pnv_ioda_pe *pe;
1535 int pe_num;
1536 u16 vf_index;
1537 struct pci_dn *pdn;
1538
1539 bus = pdev->bus;
1540 hose = pci_bus_to_host(bus);
1541 phb = hose->private_data;
1542 pdn = pci_get_pdn(pdev);
1543
1544 if (!pdev->is_physfn)
1545 return;
1546
1547 /* Reserve PE for each VF */
1548 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1549 if (pdn->m64_single_mode)
1550 pe_num = pdn->pe_num_map[vf_index];
1551 else
1552 pe_num = *pdn->pe_num_map + vf_index;
1553
1554 pe = &phb->ioda.pe_array[pe_num];
1555 pe->pe_number = pe_num;
1556 pe->phb = phb;
1557 pe->flags = PNV_IODA_PE_VF;
1558 pe->pbus = NULL;
1559 pe->parent_dev = pdev;
1560 pe->mve_number = -1;
1561 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1562 pci_iov_virtfn_devfn(pdev, vf_index);
1563
1564 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1565 hose->global_number, pdev->bus->number,
1566 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1567 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1568
1569 if (pnv_ioda_configure_pe(phb, pe)) {
1570 /* XXX What do we do here ? */
1571 pnv_ioda_free_pe(pe);
1572 pe->pdev = NULL;
1573 continue;
1574 }
1575
1576 /* Put PE to the list */
1577 mutex_lock(&phb->ioda.pe_list_mutex);
1578 list_add_tail(&pe->list, &phb->ioda.pe_list);
1579 mutex_unlock(&phb->ioda.pe_list_mutex);
1580
1581 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1582 }
1583 }
1584
1585 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1586 {
1587 struct pci_bus *bus;
1588 struct pci_controller *hose;
1589 struct pnv_phb *phb;
1590 struct pnv_ioda_pe *pe;
1591 struct pci_dn *pdn;
1592 int ret;
1593 u16 i;
1594
1595 bus = pdev->bus;
1596 hose = pci_bus_to_host(bus);
1597 phb = hose->private_data;
1598 pdn = pci_get_pdn(pdev);
1599
1600 if (phb->type == PNV_PHB_IODA2) {
1601 if (!pdn->vfs_expanded) {
1602 dev_info(&pdev->dev, "don't support this SRIOV device"
1603 " with non 64bit-prefetchable IOV BAR\n");
1604 return -ENOSPC;
1605 }
1606
1607 /*
1608 * When M64 BARs functions in Single PE mode, the number of VFs
1609 * could be enabled must be less than the number of M64 BARs.
1610 */
1611 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1612 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1613 return -EBUSY;
1614 }
1615
1616 /* Allocating pe_num_map */
1617 if (pdn->m64_single_mode)
1618 pdn->pe_num_map = kmalloc_array(num_vfs,
1619 sizeof(*pdn->pe_num_map),
1620 GFP_KERNEL);
1621 else
1622 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1623
1624 if (!pdn->pe_num_map)
1625 return -ENOMEM;
1626
1627 if (pdn->m64_single_mode)
1628 for (i = 0; i < num_vfs; i++)
1629 pdn->pe_num_map[i] = IODA_INVALID_PE;
1630
1631 /* Calculate available PE for required VFs */
1632 if (pdn->m64_single_mode) {
1633 for (i = 0; i < num_vfs; i++) {
1634 pe = pnv_ioda_alloc_pe(phb);
1635 if (!pe) {
1636 ret = -EBUSY;
1637 goto m64_failed;
1638 }
1639
1640 pdn->pe_num_map[i] = pe->pe_number;
1641 }
1642 } else {
1643 mutex_lock(&phb->ioda.pe_alloc_mutex);
1644 *pdn->pe_num_map = bitmap_find_next_zero_area(
1645 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1646 0, num_vfs, 0);
1647 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1648 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1649 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1650 kfree(pdn->pe_num_map);
1651 return -EBUSY;
1652 }
1653 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1654 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1655 }
1656 pdn->num_vfs = num_vfs;
1657
1658 /* Assign M64 window accordingly */
1659 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1660 if (ret) {
1661 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1662 goto m64_failed;
1663 }
1664
1665 /*
1666 * When using one M64 BAR to map one IOV BAR, we need to shift
1667 * the IOV BAR according to the PE# allocated to the VFs.
1668 * Otherwise, the PE# for the VF will conflict with others.
1669 */
1670 if (!pdn->m64_single_mode) {
1671 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1672 if (ret)
1673 goto m64_failed;
1674 }
1675 }
1676
1677 /* Setup VF PEs */
1678 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1679
1680 return 0;
1681
1682 m64_failed:
1683 if (pdn->m64_single_mode) {
1684 for (i = 0; i < num_vfs; i++) {
1685 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1686 continue;
1687
1688 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1689 pnv_ioda_free_pe(pe);
1690 }
1691 } else
1692 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1693
1694 /* Releasing pe_num_map */
1695 kfree(pdn->pe_num_map);
1696
1697 return ret;
1698 }
1699
1700 int pcibios_sriov_disable(struct pci_dev *pdev)
1701 {
1702 pnv_pci_sriov_disable(pdev);
1703
1704 /* Release PCI data */
1705 remove_dev_pci_data(pdev);
1706 return 0;
1707 }
1708
1709 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1710 {
1711 /* Allocate PCI data */
1712 add_dev_pci_data(pdev);
1713
1714 return pnv_pci_sriov_enable(pdev, num_vfs);
1715 }
1716 #endif /* CONFIG_PCI_IOV */
1717
1718 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1719 {
1720 struct pci_dn *pdn = pci_get_pdn(pdev);
1721 struct pnv_ioda_pe *pe;
1722
1723 /*
1724 * The function can be called while the PE#
1725 * hasn't been assigned. Do nothing for the
1726 * case.
1727 */
1728 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1729 return;
1730
1731 pe = &phb->ioda.pe_array[pdn->pe_number];
1732 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1733 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1734 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1735 /*
1736 * Note: iommu_add_device() will fail here as
1737 * for physical PE: the device is already added by now;
1738 * for virtual PE: sysfs entries are not ready yet and
1739 * tce_iommu_bus_notifier will add the device to a group later.
1740 */
1741 }
1742
1743 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1744 {
1745 unsigned short vendor = 0;
1746 struct pci_dev *pdev;
1747
1748 if (pe->device_count == 1)
1749 return true;
1750
1751 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1752 if (!pe->pbus)
1753 return true;
1754
1755 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1756 if (!vendor) {
1757 vendor = pdev->vendor;
1758 continue;
1759 }
1760
1761 if (pdev->vendor != vendor)
1762 return false;
1763 }
1764
1765 return true;
1766 }
1767
1768 /*
1769 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1770 *
1771 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1772 * Devices can only access more than that if bit 59 of the PCI address is set
1773 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1774 * Many PCI devices are not capable of addressing that many bits, and as a
1775 * result are limited to the 4GB of virtual memory made available to 32-bit
1776 * devices in TVE#0.
1777 *
1778 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1779 * devices by configuring the virtual memory past the first 4GB inaccessible
1780 * by 64-bit DMAs. This should only be used by devices that want more than
1781 * 4GB, and only on PEs that have no 32-bit devices.
1782 *
1783 * Currently this will only work on PHB3 (POWER8).
1784 */
1785 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1786 {
1787 u64 window_size, table_size, tce_count, addr;
1788 struct page *table_pages;
1789 u64 tce_order = 28; /* 256MB TCEs */
1790 __be64 *tces;
1791 s64 rc;
1792
1793 /*
1794 * Window size needs to be a power of two, but needs to account for
1795 * shifting memory by the 4GB offset required to skip 32bit space.
1796 */
1797 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1798 tce_count = window_size >> tce_order;
1799 table_size = tce_count << 3;
1800
1801 if (table_size < PAGE_SIZE)
1802 table_size = PAGE_SIZE;
1803
1804 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1805 get_order(table_size));
1806 if (!table_pages)
1807 goto err;
1808
1809 tces = page_address(table_pages);
1810 if (!tces)
1811 goto err;
1812
1813 memset(tces, 0, table_size);
1814
1815 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1816 tces[(addr + (1ULL << 32)) >> tce_order] =
1817 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1818 }
1819
1820 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1821 pe->pe_number,
1822 /* reconfigure window 0 */
1823 (pe->pe_number << 1) + 0,
1824 1,
1825 __pa(tces),
1826 table_size,
1827 1 << tce_order);
1828 if (rc == OPAL_SUCCESS) {
1829 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1830 return 0;
1831 }
1832 err:
1833 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1834 return -EIO;
1835 }
1836
1837 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1838 {
1839 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1840 struct pnv_phb *phb = hose->private_data;
1841 struct pci_dn *pdn = pci_get_pdn(pdev);
1842 struct pnv_ioda_pe *pe;
1843 uint64_t top;
1844 bool bypass = false;
1845 s64 rc;
1846
1847 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1848 return -ENODEV;;
1849
1850 pe = &phb->ioda.pe_array[pdn->pe_number];
1851 if (pe->tce_bypass_enabled) {
1852 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1853 bypass = (dma_mask >= top);
1854 }
1855
1856 if (bypass) {
1857 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1858 set_dma_ops(&pdev->dev, &dma_direct_ops);
1859 } else {
1860 /*
1861 * If the device can't set the TCE bypass bit but still wants
1862 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1863 * bypass the 32-bit region and be usable for 64-bit DMAs.
1864 * The device needs to be able to address all of this space.
1865 */
1866 if (dma_mask >> 32 &&
1867 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1868 pnv_pci_ioda_pe_single_vendor(pe) &&
1869 phb->model == PNV_PHB_MODEL_PHB3) {
1870 /* Configure the bypass mode */
1871 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1872 if (rc)
1873 return rc;
1874 /* 4GB offset bypasses 32-bit space */
1875 set_dma_offset(&pdev->dev, (1ULL << 32));
1876 set_dma_ops(&pdev->dev, &dma_direct_ops);
1877 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1878 /*
1879 * Fail the request if a DMA mask between 32 and 64 bits
1880 * was requested but couldn't be fulfilled. Ideally we
1881 * would do this for 64-bits but historically we have
1882 * always fallen back to 32-bits.
1883 */
1884 return -ENOMEM;
1885 } else {
1886 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1887 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1888 }
1889 }
1890 *pdev->dev.dma_mask = dma_mask;
1891
1892 /* Update peer npu devices */
1893 pnv_npu_try_dma_set_bypass(pdev, bypass);
1894
1895 return 0;
1896 }
1897
1898 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1899 {
1900 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1901 struct pnv_phb *phb = hose->private_data;
1902 struct pci_dn *pdn = pci_get_pdn(pdev);
1903 struct pnv_ioda_pe *pe;
1904 u64 end, mask;
1905
1906 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1907 return 0;
1908
1909 pe = &phb->ioda.pe_array[pdn->pe_number];
1910 if (!pe->tce_bypass_enabled)
1911 return __dma_get_required_mask(&pdev->dev);
1912
1913
1914 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1915 mask = 1ULL << (fls64(end) - 1);
1916 mask += mask - 1;
1917
1918 return mask;
1919 }
1920
1921 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1922 struct pci_bus *bus,
1923 bool add_to_group)
1924 {
1925 struct pci_dev *dev;
1926
1927 list_for_each_entry(dev, &bus->devices, bus_list) {
1928 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1929 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1930 if (add_to_group)
1931 iommu_add_device(&dev->dev);
1932
1933 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1934 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1935 add_to_group);
1936 }
1937 }
1938
1939 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1940 bool real_mode)
1941 {
1942 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1943 (phb->regs + 0x210);
1944 }
1945
1946 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1947 unsigned long index, unsigned long npages, bool rm)
1948 {
1949 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1950 &tbl->it_group_list, struct iommu_table_group_link,
1951 next);
1952 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1953 struct pnv_ioda_pe, table_group);
1954 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1955 unsigned long start, end, inc;
1956
1957 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1958 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1959 npages - 1);
1960
1961 /* p7ioc-style invalidation, 2 TCEs per write */
1962 start |= (1ull << 63);
1963 end |= (1ull << 63);
1964 inc = 16;
1965 end |= inc - 1; /* round up end to be different than start */
1966
1967 mb(); /* Ensure above stores are visible */
1968 while (start <= end) {
1969 if (rm)
1970 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1971 else
1972 __raw_writeq(cpu_to_be64(start), invalidate);
1973 start += inc;
1974 }
1975
1976 /*
1977 * The iommu layer will do another mb() for us on build()
1978 * and we don't care on free()
1979 */
1980 }
1981
1982 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1983 long npages, unsigned long uaddr,
1984 enum dma_data_direction direction,
1985 unsigned long attrs)
1986 {
1987 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1988 attrs);
1989
1990 if (!ret)
1991 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1992
1993 return ret;
1994 }
1995
1996 #ifdef CONFIG_IOMMU_API
1997 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1998 unsigned long *hpa, enum dma_data_direction *direction)
1999 {
2000 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2001
2002 if (!ret)
2003 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2004
2005 return ret;
2006 }
2007
2008 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2009 unsigned long *hpa, enum dma_data_direction *direction)
2010 {
2011 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2012
2013 if (!ret)
2014 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2015
2016 return ret;
2017 }
2018 #endif
2019
2020 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2021 long npages)
2022 {
2023 pnv_tce_free(tbl, index, npages);
2024
2025 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2026 }
2027
2028 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2029 .set = pnv_ioda1_tce_build,
2030 #ifdef CONFIG_IOMMU_API
2031 .exchange = pnv_ioda1_tce_xchg,
2032 .exchange_rm = pnv_ioda1_tce_xchg_rm,
2033 #endif
2034 .clear = pnv_ioda1_tce_free,
2035 .get = pnv_tce_get,
2036 };
2037
2038 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
2039 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
2040 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
2041
2042 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2043 {
2044 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2045 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2046
2047 mb(); /* Ensure previous TCE table stores are visible */
2048 if (rm)
2049 __raw_rm_writeq(cpu_to_be64(val), invalidate);
2050 else
2051 __raw_writeq(cpu_to_be64(val), invalidate);
2052 }
2053
2054 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2055 {
2056 /* 01xb - invalidate TCEs that match the specified PE# */
2057 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2058 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2059
2060 mb(); /* Ensure above stores are visible */
2061 __raw_writeq(cpu_to_be64(val), invalidate);
2062 }
2063
2064 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2065 unsigned shift, unsigned long index,
2066 unsigned long npages)
2067 {
2068 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2069 unsigned long start, end, inc;
2070
2071 /* We'll invalidate DMA address in PE scope */
2072 start = PHB3_TCE_KILL_INVAL_ONE;
2073 start |= (pe->pe_number & 0xFF);
2074 end = start;
2075
2076 /* Figure out the start, end and step */
2077 start |= (index << shift);
2078 end |= ((index + npages - 1) << shift);
2079 inc = (0x1ull << shift);
2080 mb();
2081
2082 while (start <= end) {
2083 if (rm)
2084 __raw_rm_writeq(cpu_to_be64(start), invalidate);
2085 else
2086 __raw_writeq(cpu_to_be64(start), invalidate);
2087 start += inc;
2088 }
2089 }
2090
2091 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2092 {
2093 struct pnv_phb *phb = pe->phb;
2094
2095 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2096 pnv_pci_phb3_tce_invalidate_pe(pe);
2097 else
2098 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2099 pe->pe_number, 0, 0, 0);
2100 }
2101
2102 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2103 unsigned long index, unsigned long npages, bool rm)
2104 {
2105 struct iommu_table_group_link *tgl;
2106
2107 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2108 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2109 struct pnv_ioda_pe, table_group);
2110 struct pnv_phb *phb = pe->phb;
2111 unsigned int shift = tbl->it_page_shift;
2112
2113 /*
2114 * NVLink1 can use the TCE kill register directly as
2115 * it's the same as PHB3. NVLink2 is different and
2116 * should go via the OPAL call.
2117 */
2118 if (phb->model == PNV_PHB_MODEL_NPU) {
2119 /*
2120 * The NVLink hardware does not support TCE kill
2121 * per TCE entry so we have to invalidate
2122 * the entire cache for it.
2123 */
2124 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2125 continue;
2126 }
2127 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2128 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2129 index, npages);
2130 else
2131 opal_pci_tce_kill(phb->opal_id,
2132 OPAL_PCI_TCE_KILL_PAGES,
2133 pe->pe_number, 1u << shift,
2134 index << shift, npages);
2135 }
2136 }
2137
2138 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2139 {
2140 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2141 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2142 else
2143 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2144 }
2145
2146 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2147 long npages, unsigned long uaddr,
2148 enum dma_data_direction direction,
2149 unsigned long attrs)
2150 {
2151 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2152 attrs);
2153
2154 if (!ret)
2155 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2156
2157 return ret;
2158 }
2159
2160 #ifdef CONFIG_IOMMU_API
2161 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2162 unsigned long *hpa, enum dma_data_direction *direction)
2163 {
2164 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2165
2166 if (!ret)
2167 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2168
2169 return ret;
2170 }
2171
2172 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2173 unsigned long *hpa, enum dma_data_direction *direction)
2174 {
2175 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2176
2177 if (!ret)
2178 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2179
2180 return ret;
2181 }
2182 #endif
2183
2184 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2185 long npages)
2186 {
2187 pnv_tce_free(tbl, index, npages);
2188
2189 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2190 }
2191
2192 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2193 {
2194 pnv_pci_ioda2_table_free_pages(tbl);
2195 }
2196
2197 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2198 .set = pnv_ioda2_tce_build,
2199 #ifdef CONFIG_IOMMU_API
2200 .exchange = pnv_ioda2_tce_xchg,
2201 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2202 #endif
2203 .clear = pnv_ioda2_tce_free,
2204 .get = pnv_tce_get,
2205 .free = pnv_ioda2_table_free,
2206 };
2207
2208 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2209 {
2210 unsigned int *weight = (unsigned int *)data;
2211
2212 /* This is quite simplistic. The "base" weight of a device
2213 * is 10. 0 means no DMA is to be accounted for it.
2214 */
2215 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2216 return 0;
2217
2218 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2219 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2220 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2221 *weight += 3;
2222 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2223 *weight += 15;
2224 else
2225 *weight += 10;
2226
2227 return 0;
2228 }
2229
2230 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2231 {
2232 unsigned int weight = 0;
2233
2234 /* SRIOV VF has same DMA32 weight as its PF */
2235 #ifdef CONFIG_PCI_IOV
2236 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2237 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2238 return weight;
2239 }
2240 #endif
2241
2242 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2243 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2244 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2245 struct pci_dev *pdev;
2246
2247 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2248 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2249 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2250 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2251 }
2252
2253 return weight;
2254 }
2255
2256 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2257 struct pnv_ioda_pe *pe)
2258 {
2259
2260 struct page *tce_mem = NULL;
2261 struct iommu_table *tbl;
2262 unsigned int weight, total_weight = 0;
2263 unsigned int tce32_segsz, base, segs, avail, i;
2264 int64_t rc;
2265 void *addr;
2266
2267 /* XXX FIXME: Handle 64-bit only DMA devices */
2268 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2269 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2270 weight = pnv_pci_ioda_pe_dma_weight(pe);
2271 if (!weight)
2272 return;
2273
2274 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2275 &total_weight);
2276 segs = (weight * phb->ioda.dma32_count) / total_weight;
2277 if (!segs)
2278 segs = 1;
2279
2280 /*
2281 * Allocate contiguous DMA32 segments. We begin with the expected
2282 * number of segments. With one more attempt, the number of DMA32
2283 * segments to be allocated is decreased by one until one segment
2284 * is allocated successfully.
2285 */
2286 do {
2287 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2288 for (avail = 0, i = base; i < base + segs; i++) {
2289 if (phb->ioda.dma32_segmap[i] ==
2290 IODA_INVALID_PE)
2291 avail++;
2292 }
2293
2294 if (avail == segs)
2295 goto found;
2296 }
2297 } while (--segs);
2298
2299 if (!segs) {
2300 pe_warn(pe, "No available DMA32 segments\n");
2301 return;
2302 }
2303
2304 found:
2305 tbl = pnv_pci_table_alloc(phb->hose->node);
2306 if (WARN_ON(!tbl))
2307 return;
2308
2309 iommu_register_group(&pe->table_group, phb->hose->global_number,
2310 pe->pe_number);
2311 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2312
2313 /* Grab a 32-bit TCE table */
2314 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2315 weight, total_weight, base, segs);
2316 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2317 base * PNV_IODA1_DMA32_SEGSIZE,
2318 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2319
2320 /* XXX Currently, we allocate one big contiguous table for the
2321 * TCEs. We only really need one chunk per 256M of TCE space
2322 * (ie per segment) but that's an optimization for later, it
2323 * requires some added smarts with our get/put_tce implementation
2324 *
2325 * Each TCE page is 4KB in size and each TCE entry occupies 8
2326 * bytes
2327 */
2328 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2329 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2330 get_order(tce32_segsz * segs));
2331 if (!tce_mem) {
2332 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2333 goto fail;
2334 }
2335 addr = page_address(tce_mem);
2336 memset(addr, 0, tce32_segsz * segs);
2337
2338 /* Configure HW */
2339 for (i = 0; i < segs; i++) {
2340 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2341 pe->pe_number,
2342 base + i, 1,
2343 __pa(addr) + tce32_segsz * i,
2344 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2345 if (rc) {
2346 pe_err(pe, " Failed to configure 32-bit TCE table,"
2347 " err %ld\n", rc);
2348 goto fail;
2349 }
2350 }
2351
2352 /* Setup DMA32 segment mapping */
2353 for (i = base; i < base + segs; i++)
2354 phb->ioda.dma32_segmap[i] = pe->pe_number;
2355
2356 /* Setup linux iommu table */
2357 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2358 base * PNV_IODA1_DMA32_SEGSIZE,
2359 IOMMU_PAGE_SHIFT_4K);
2360
2361 tbl->it_ops = &pnv_ioda1_iommu_ops;
2362 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2363 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2364 iommu_init_table(tbl, phb->hose->node);
2365
2366 if (pe->flags & PNV_IODA_PE_DEV) {
2367 /*
2368 * Setting table base here only for carrying iommu_group
2369 * further down to let iommu_add_device() do the job.
2370 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2371 */
2372 set_iommu_table_base(&pe->pdev->dev, tbl);
2373 iommu_add_device(&pe->pdev->dev);
2374 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2375 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2376
2377 return;
2378 fail:
2379 /* XXX Failure: Try to fallback to 64-bit only ? */
2380 if (tce_mem)
2381 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2382 if (tbl) {
2383 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2384 iommu_tce_table_put(tbl);
2385 }
2386 }
2387
2388 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2389 int num, struct iommu_table *tbl)
2390 {
2391 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2392 table_group);
2393 struct pnv_phb *phb = pe->phb;
2394 int64_t rc;
2395 const unsigned long size = tbl->it_indirect_levels ?
2396 tbl->it_level_size : tbl->it_size;
2397 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2398 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2399
2400 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2401 start_addr, start_addr + win_size - 1,
2402 IOMMU_PAGE_SIZE(tbl));
2403
2404 /*
2405 * Map TCE table through TVT. The TVE index is the PE number
2406 * shifted by 1 bit for 32-bits DMA space.
2407 */
2408 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2409 pe->pe_number,
2410 (pe->pe_number << 1) + num,
2411 tbl->it_indirect_levels + 1,
2412 __pa(tbl->it_base),
2413 size << 3,
2414 IOMMU_PAGE_SIZE(tbl));
2415 if (rc) {
2416 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2417 return rc;
2418 }
2419
2420 pnv_pci_link_table_and_group(phb->hose->node, num,
2421 tbl, &pe->table_group);
2422 pnv_pci_ioda2_tce_invalidate_pe(pe);
2423
2424 return 0;
2425 }
2426
2427 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2428 {
2429 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2430 int64_t rc;
2431
2432 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2433 if (enable) {
2434 phys_addr_t top = memblock_end_of_DRAM();
2435
2436 top = roundup_pow_of_two(top);
2437 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2438 pe->pe_number,
2439 window_id,
2440 pe->tce_bypass_base,
2441 top);
2442 } else {
2443 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2444 pe->pe_number,
2445 window_id,
2446 pe->tce_bypass_base,
2447 0);
2448 }
2449 if (rc)
2450 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2451 else
2452 pe->tce_bypass_enabled = enable;
2453 }
2454
2455 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2456 __u32 page_shift, __u64 window_size, __u32 levels,
2457 struct iommu_table *tbl);
2458
2459 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2460 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2461 struct iommu_table **ptbl)
2462 {
2463 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2464 table_group);
2465 int nid = pe->phb->hose->node;
2466 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2467 long ret;
2468 struct iommu_table *tbl;
2469
2470 tbl = pnv_pci_table_alloc(nid);
2471 if (!tbl)
2472 return -ENOMEM;
2473
2474 tbl->it_ops = &pnv_ioda2_iommu_ops;
2475
2476 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2477 bus_offset, page_shift, window_size,
2478 levels, tbl);
2479 if (ret) {
2480 iommu_tce_table_put(tbl);
2481 return ret;
2482 }
2483
2484 *ptbl = tbl;
2485
2486 return 0;
2487 }
2488
2489 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2490 {
2491 struct iommu_table *tbl = NULL;
2492 long rc;
2493
2494 /*
2495 * crashkernel= specifies the kdump kernel's maximum memory at
2496 * some offset and there is no guaranteed the result is a power
2497 * of 2, which will cause errors later.
2498 */
2499 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2500
2501 /*
2502 * In memory constrained environments, e.g. kdump kernel, the
2503 * DMA window can be larger than available memory, which will
2504 * cause errors later.
2505 */
2506 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2507
2508 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2509 IOMMU_PAGE_SHIFT_4K,
2510 window_size,
2511 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2512 if (rc) {
2513 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2514 rc);
2515 return rc;
2516 }
2517
2518 iommu_init_table(tbl, pe->phb->hose->node);
2519
2520 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2521 if (rc) {
2522 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2523 rc);
2524 iommu_tce_table_put(tbl);
2525 return rc;
2526 }
2527
2528 if (!pnv_iommu_bypass_disabled)
2529 pnv_pci_ioda2_set_bypass(pe, true);
2530
2531 /*
2532 * Setting table base here only for carrying iommu_group
2533 * further down to let iommu_add_device() do the job.
2534 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2535 */
2536 if (pe->flags & PNV_IODA_PE_DEV)
2537 set_iommu_table_base(&pe->pdev->dev, tbl);
2538
2539 return 0;
2540 }
2541
2542 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2543 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2544 int num)
2545 {
2546 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2547 table_group);
2548 struct pnv_phb *phb = pe->phb;
2549 long ret;
2550
2551 pe_info(pe, "Removing DMA window #%d\n", num);
2552
2553 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2554 (pe->pe_number << 1) + num,
2555 0/* levels */, 0/* table address */,
2556 0/* table size */, 0/* page size */);
2557 if (ret)
2558 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2559 else
2560 pnv_pci_ioda2_tce_invalidate_pe(pe);
2561
2562 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2563
2564 return ret;
2565 }
2566 #endif
2567
2568 #ifdef CONFIG_IOMMU_API
2569 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2570 __u64 window_size, __u32 levels)
2571 {
2572 unsigned long bytes = 0;
2573 const unsigned window_shift = ilog2(window_size);
2574 unsigned entries_shift = window_shift - page_shift;
2575 unsigned table_shift = entries_shift + 3;
2576 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2577 unsigned long direct_table_size;
2578
2579 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2580 (window_size > memory_hotplug_max()) ||
2581 !is_power_of_2(window_size))
2582 return 0;
2583
2584 /* Calculate a direct table size from window_size and levels */
2585 entries_shift = (entries_shift + levels - 1) / levels;
2586 table_shift = entries_shift + 3;
2587 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2588 direct_table_size = 1UL << table_shift;
2589
2590 for ( ; levels; --levels) {
2591 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2592
2593 tce_table_size /= direct_table_size;
2594 tce_table_size <<= 3;
2595 tce_table_size = max_t(unsigned long,
2596 tce_table_size, direct_table_size);
2597 }
2598
2599 return bytes;
2600 }
2601
2602 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2603 {
2604 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2605 table_group);
2606 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2607 struct iommu_table *tbl = pe->table_group.tables[0];
2608
2609 pnv_pci_ioda2_set_bypass(pe, false);
2610 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2611 if (pe->pbus)
2612 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2613 iommu_tce_table_put(tbl);
2614 }
2615
2616 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2617 {
2618 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2619 table_group);
2620
2621 pnv_pci_ioda2_setup_default_config(pe);
2622 if (pe->pbus)
2623 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2624 }
2625
2626 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2627 .get_table_size = pnv_pci_ioda2_get_table_size,
2628 .create_table = pnv_pci_ioda2_create_table,
2629 .set_window = pnv_pci_ioda2_set_window,
2630 .unset_window = pnv_pci_ioda2_unset_window,
2631 .take_ownership = pnv_ioda2_take_ownership,
2632 .release_ownership = pnv_ioda2_release_ownership,
2633 };
2634
2635 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2636 {
2637 struct pci_controller *hose;
2638 struct pnv_phb *phb;
2639 struct pnv_ioda_pe **ptmppe = opaque;
2640 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2641 struct pci_dn *pdn = pci_get_pdn(pdev);
2642
2643 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2644 return 0;
2645
2646 hose = pci_bus_to_host(pdev->bus);
2647 phb = hose->private_data;
2648 if (phb->type != PNV_PHB_NPU_NVLINK)
2649 return 0;
2650
2651 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2652
2653 return 1;
2654 }
2655
2656 /*
2657 * This returns PE of associated NPU.
2658 * This assumes that NPU is in the same IOMMU group with GPU and there is
2659 * no other PEs.
2660 */
2661 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2662 struct iommu_table_group *table_group)
2663 {
2664 struct pnv_ioda_pe *npe = NULL;
2665 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2666 gpe_table_group_to_npe_cb);
2667
2668 BUG_ON(!ret || !npe);
2669
2670 return npe;
2671 }
2672
2673 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2674 int num, struct iommu_table *tbl)
2675 {
2676 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2677 int num2 = (num == 0) ? 1 : 0;
2678 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2679
2680 if (ret)
2681 return ret;
2682
2683 if (table_group->tables[num2])
2684 pnv_npu_unset_window(npe, num2);
2685
2686 ret = pnv_npu_set_window(npe, num, tbl);
2687 if (ret) {
2688 pnv_pci_ioda2_unset_window(table_group, num);
2689 if (table_group->tables[num2])
2690 pnv_npu_set_window(npe, num2,
2691 table_group->tables[num2]);
2692 }
2693
2694 return ret;
2695 }
2696
2697 static long pnv_pci_ioda2_npu_unset_window(
2698 struct iommu_table_group *table_group,
2699 int num)
2700 {
2701 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2702 int num2 = (num == 0) ? 1 : 0;
2703 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2704
2705 if (ret)
2706 return ret;
2707
2708 if (!npe->table_group.tables[num])
2709 return 0;
2710
2711 ret = pnv_npu_unset_window(npe, num);
2712 if (ret)
2713 return ret;
2714
2715 if (table_group->tables[num2])
2716 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
2717
2718 return ret;
2719 }
2720
2721 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2722 {
2723 /*
2724 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2725 * the iommu_table if 32bit DMA is enabled.
2726 */
2727 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2728 pnv_ioda2_take_ownership(table_group);
2729 }
2730
2731 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2732 .get_table_size = pnv_pci_ioda2_get_table_size,
2733 .create_table = pnv_pci_ioda2_create_table,
2734 .set_window = pnv_pci_ioda2_npu_set_window,
2735 .unset_window = pnv_pci_ioda2_npu_unset_window,
2736 .take_ownership = pnv_ioda2_npu_take_ownership,
2737 .release_ownership = pnv_ioda2_release_ownership,
2738 };
2739
2740 static void pnv_pci_ioda_setup_iommu_api(void)
2741 {
2742 struct pci_controller *hose, *tmp;
2743 struct pnv_phb *phb;
2744 struct pnv_ioda_pe *pe, *gpe;
2745
2746 /*
2747 * Now we have all PHBs discovered, time to add NPU devices to
2748 * the corresponding IOMMU groups.
2749 */
2750 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2751 phb = hose->private_data;
2752
2753 if (phb->type != PNV_PHB_NPU_NVLINK)
2754 continue;
2755
2756 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2757 gpe = pnv_pci_npu_setup_iommu(pe);
2758 if (gpe)
2759 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2760 }
2761 }
2762 }
2763 #else /* !CONFIG_IOMMU_API */
2764 static void pnv_pci_ioda_setup_iommu_api(void) { };
2765 #endif
2766
2767 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2768 unsigned levels, unsigned long limit,
2769 unsigned long *current_offset, unsigned long *total_allocated)
2770 {
2771 struct page *tce_mem = NULL;
2772 __be64 *addr, *tmp;
2773 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2774 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2775 unsigned entries = 1UL << (shift - 3);
2776 long i;
2777
2778 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2779 if (!tce_mem) {
2780 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2781 return NULL;
2782 }
2783 addr = page_address(tce_mem);
2784 memset(addr, 0, allocated);
2785 *total_allocated += allocated;
2786
2787 --levels;
2788 if (!levels) {
2789 *current_offset += allocated;
2790 return addr;
2791 }
2792
2793 for (i = 0; i < entries; ++i) {
2794 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2795 levels, limit, current_offset, total_allocated);
2796 if (!tmp)
2797 break;
2798
2799 addr[i] = cpu_to_be64(__pa(tmp) |
2800 TCE_PCI_READ | TCE_PCI_WRITE);
2801
2802 if (*current_offset >= limit)
2803 break;
2804 }
2805
2806 return addr;
2807 }
2808
2809 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2810 unsigned long size, unsigned level);
2811
2812 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2813 __u32 page_shift, __u64 window_size, __u32 levels,
2814 struct iommu_table *tbl)
2815 {
2816 void *addr;
2817 unsigned long offset = 0, level_shift, total_allocated = 0;
2818 const unsigned window_shift = ilog2(window_size);
2819 unsigned entries_shift = window_shift - page_shift;
2820 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2821 const unsigned long tce_table_size = 1UL << table_shift;
2822
2823 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2824 return -EINVAL;
2825
2826 if (!is_power_of_2(window_size))
2827 return -EINVAL;
2828
2829 /* Adjust direct table size from window_size and levels */
2830 entries_shift = (entries_shift + levels - 1) / levels;
2831 level_shift = entries_shift + 3;
2832 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2833
2834 if ((level_shift - 3) * levels + page_shift >= 60)
2835 return -EINVAL;
2836
2837 /* Allocate TCE table */
2838 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2839 levels, tce_table_size, &offset, &total_allocated);
2840
2841 /* addr==NULL means that the first level allocation failed */
2842 if (!addr)
2843 return -ENOMEM;
2844
2845 /*
2846 * First level was allocated but some lower level failed as
2847 * we did not allocate as much as we wanted,
2848 * release partially allocated table.
2849 */
2850 if (offset < tce_table_size) {
2851 pnv_pci_ioda2_table_do_free_pages(addr,
2852 1ULL << (level_shift - 3), levels - 1);
2853 return -ENOMEM;
2854 }
2855
2856 /* Setup linux iommu table */
2857 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2858 page_shift);
2859 tbl->it_level_size = 1ULL << (level_shift - 3);
2860 tbl->it_indirect_levels = levels - 1;
2861 tbl->it_allocated_size = total_allocated;
2862
2863 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2864 window_size, tce_table_size, bus_offset);
2865
2866 return 0;
2867 }
2868
2869 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2870 unsigned long size, unsigned level)
2871 {
2872 const unsigned long addr_ul = (unsigned long) addr &
2873 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2874
2875 if (level) {
2876 long i;
2877 u64 *tmp = (u64 *) addr_ul;
2878
2879 for (i = 0; i < size; ++i) {
2880 unsigned long hpa = be64_to_cpu(tmp[i]);
2881
2882 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2883 continue;
2884
2885 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2886 level - 1);
2887 }
2888 }
2889
2890 free_pages(addr_ul, get_order(size << 3));
2891 }
2892
2893 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2894 {
2895 const unsigned long size = tbl->it_indirect_levels ?
2896 tbl->it_level_size : tbl->it_size;
2897
2898 if (!tbl->it_size)
2899 return;
2900
2901 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2902 tbl->it_indirect_levels);
2903 }
2904
2905 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2906 struct pnv_ioda_pe *pe)
2907 {
2908 int64_t rc;
2909
2910 if (!pnv_pci_ioda_pe_dma_weight(pe))
2911 return;
2912
2913 /* TVE #1 is selected by PCI address bit 59 */
2914 pe->tce_bypass_base = 1ull << 59;
2915
2916 iommu_register_group(&pe->table_group, phb->hose->global_number,
2917 pe->pe_number);
2918
2919 /* The PE will reserve all possible 32-bits space */
2920 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2921 phb->ioda.m32_pci_base);
2922
2923 /* Setup linux iommu table */
2924 pe->table_group.tce32_start = 0;
2925 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2926 pe->table_group.max_dynamic_windows_supported =
2927 IOMMU_TABLE_GROUP_MAX_TABLES;
2928 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2929 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2930 #ifdef CONFIG_IOMMU_API
2931 pe->table_group.ops = &pnv_pci_ioda2_ops;
2932 #endif
2933
2934 rc = pnv_pci_ioda2_setup_default_config(pe);
2935 if (rc)
2936 return;
2937
2938 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2939 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2940 }
2941
2942 #ifdef CONFIG_PCI_MSI
2943 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2944 {
2945 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2946 ioda.irq_chip);
2947
2948 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2949 }
2950
2951 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2952 {
2953 int64_t rc;
2954 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2955 struct irq_chip *chip = irq_data_get_irq_chip(d);
2956
2957 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2958 WARN_ON_ONCE(rc);
2959
2960 icp_native_eoi(d);
2961 }
2962
2963
2964 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2965 {
2966 struct irq_data *idata;
2967 struct irq_chip *ichip;
2968
2969 /* The MSI EOI OPAL call is only needed on PHB3 */
2970 if (phb->model != PNV_PHB_MODEL_PHB3)
2971 return;
2972
2973 if (!phb->ioda.irq_chip_init) {
2974 /*
2975 * First time we setup an MSI IRQ, we need to setup the
2976 * corresponding IRQ chip to route correctly.
2977 */
2978 idata = irq_get_irq_data(virq);
2979 ichip = irq_data_get_irq_chip(idata);
2980 phb->ioda.irq_chip_init = 1;
2981 phb->ioda.irq_chip = *ichip;
2982 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2983 }
2984 irq_set_chip(virq, &phb->ioda.irq_chip);
2985 }
2986
2987 /*
2988 * Returns true iff chip is something that we could call
2989 * pnv_opal_pci_msi_eoi for.
2990 */
2991 bool is_pnv_opal_msi(struct irq_chip *chip)
2992 {
2993 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2994 }
2995 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2996
2997 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2998 unsigned int hwirq, unsigned int virq,
2999 unsigned int is_64, struct msi_msg *msg)
3000 {
3001 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
3002 unsigned int xive_num = hwirq - phb->msi_base;
3003 __be32 data;
3004 int rc;
3005
3006 /* No PE assigned ? bail out ... no MSI for you ! */
3007 if (pe == NULL)
3008 return -ENXIO;
3009
3010 /* Check if we have an MVE */
3011 if (pe->mve_number < 0)
3012 return -ENXIO;
3013
3014 /* Force 32-bit MSI on some broken devices */
3015 if (dev->no_64bit_msi)
3016 is_64 = 0;
3017
3018 /* Assign XIVE to PE */
3019 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
3020 if (rc) {
3021 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
3022 pci_name(dev), rc, xive_num);
3023 return -EIO;
3024 }
3025
3026 if (is_64) {
3027 __be64 addr64;
3028
3029 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
3030 &addr64, &data);
3031 if (rc) {
3032 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
3033 pci_name(dev), rc);
3034 return -EIO;
3035 }
3036 msg->address_hi = be64_to_cpu(addr64) >> 32;
3037 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
3038 } else {
3039 __be32 addr32;
3040
3041 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
3042 &addr32, &data);
3043 if (rc) {
3044 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
3045 pci_name(dev), rc);
3046 return -EIO;
3047 }
3048 msg->address_hi = 0;
3049 msg->address_lo = be32_to_cpu(addr32);
3050 }
3051 msg->data = be32_to_cpu(data);
3052
3053 pnv_set_msi_irq_chip(phb, virq);
3054
3055 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
3056 " address=%x_%08x data=%x PE# %x\n",
3057 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
3058 msg->address_hi, msg->address_lo, data, pe->pe_number);
3059
3060 return 0;
3061 }
3062
3063 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
3064 {
3065 unsigned int count;
3066 const __be32 *prop = of_get_property(phb->hose->dn,
3067 "ibm,opal-msi-ranges", NULL);
3068 if (!prop) {
3069 /* BML Fallback */
3070 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
3071 }
3072 if (!prop)
3073 return;
3074
3075 phb->msi_base = be32_to_cpup(prop);
3076 count = be32_to_cpup(prop + 1);
3077 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
3078 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
3079 phb->hose->global_number);
3080 return;
3081 }
3082
3083 phb->msi_setup = pnv_pci_ioda_msi_setup;
3084 phb->msi32_support = 1;
3085 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
3086 count, phb->msi_base);
3087 }
3088 #else
3089 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
3090 #endif /* CONFIG_PCI_MSI */
3091
3092 #ifdef CONFIG_PCI_IOV
3093 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
3094 {
3095 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3096 struct pnv_phb *phb = hose->private_data;
3097 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
3098 struct resource *res;
3099 int i;
3100 resource_size_t size, total_vf_bar_sz;
3101 struct pci_dn *pdn;
3102 int mul, total_vfs;
3103
3104 if (!pdev->is_physfn || pdev->is_added)
3105 return;
3106
3107 pdn = pci_get_pdn(pdev);
3108 pdn->vfs_expanded = 0;
3109 pdn->m64_single_mode = false;
3110
3111 total_vfs = pci_sriov_get_totalvfs(pdev);
3112 mul = phb->ioda.total_pe_num;
3113 total_vf_bar_sz = 0;
3114
3115 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3116 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3117 if (!res->flags || res->parent)
3118 continue;
3119 if (!pnv_pci_is_m64_flags(res->flags)) {
3120 dev_warn(&pdev->dev, "Don't support SR-IOV with"
3121 " non M64 VF BAR%d: %pR. \n",
3122 i, res);
3123 goto truncate_iov;
3124 }
3125
3126 total_vf_bar_sz += pci_iov_resource_size(pdev,
3127 i + PCI_IOV_RESOURCES);
3128
3129 /*
3130 * If bigger than quarter of M64 segment size, just round up
3131 * power of two.
3132 *
3133 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3134 * with other devices, IOV BAR size is expanded to be
3135 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
3136 * segment size , the expanded size would equal to half of the
3137 * whole M64 space size, which will exhaust the M64 Space and
3138 * limit the system flexibility. This is a design decision to
3139 * set the boundary to quarter of the M64 segment size.
3140 */
3141 if (total_vf_bar_sz > gate) {
3142 mul = roundup_pow_of_two(total_vfs);
3143 dev_info(&pdev->dev,
3144 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3145 total_vf_bar_sz, gate, mul);
3146 pdn->m64_single_mode = true;
3147 break;
3148 }
3149 }
3150
3151 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3152 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3153 if (!res->flags || res->parent)
3154 continue;
3155
3156 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3157 /*
3158 * On PHB3, the minimum size alignment of M64 BAR in single
3159 * mode is 32MB.
3160 */
3161 if (pdn->m64_single_mode && (size < SZ_32M))
3162 goto truncate_iov;
3163 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3164 res->end = res->start + size * mul - 1;
3165 dev_dbg(&pdev->dev, " %pR\n", res);
3166 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3167 i, res, mul);
3168 }
3169 pdn->vfs_expanded = mul;
3170
3171 return;
3172
3173 truncate_iov:
3174 /* To save MMIO space, IOV BAR is truncated. */
3175 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3176 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3177 res->flags = 0;
3178 res->end = res->start - 1;
3179 }
3180 }
3181 #endif /* CONFIG_PCI_IOV */
3182
3183 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3184 struct resource *res)
3185 {
3186 struct pnv_phb *phb = pe->phb;
3187 struct pci_bus_region region;
3188 int index;
3189 int64_t rc;
3190
3191 if (!res || !res->flags || res->start > res->end)
3192 return;
3193
3194 if (res->flags & IORESOURCE_IO) {
3195 region.start = res->start - phb->ioda.io_pci_base;
3196 region.end = res->end - phb->ioda.io_pci_base;
3197 index = region.start / phb->ioda.io_segsize;
3198
3199 while (index < phb->ioda.total_pe_num &&
3200 region.start <= region.end) {
3201 phb->ioda.io_segmap[index] = pe->pe_number;
3202 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3203 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3204 if (rc != OPAL_SUCCESS) {
3205 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3206 __func__, rc, index, pe->pe_number);
3207 break;
3208 }
3209
3210 region.start += phb->ioda.io_segsize;
3211 index++;
3212 }
3213 } else if ((res->flags & IORESOURCE_MEM) &&
3214 !pnv_pci_is_m64(phb, res)) {
3215 region.start = res->start -
3216 phb->hose->mem_offset[0] -
3217 phb->ioda.m32_pci_base;
3218 region.end = res->end -
3219 phb->hose->mem_offset[0] -
3220 phb->ioda.m32_pci_base;
3221 index = region.start / phb->ioda.m32_segsize;
3222
3223 while (index < phb->ioda.total_pe_num &&
3224 region.start <= region.end) {
3225 phb->ioda.m32_segmap[index] = pe->pe_number;
3226 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3227 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3228 if (rc != OPAL_SUCCESS) {
3229 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3230 __func__, rc, index, pe->pe_number);
3231 break;
3232 }
3233
3234 region.start += phb->ioda.m32_segsize;
3235 index++;
3236 }
3237 }
3238 }
3239
3240 /*
3241 * This function is supposed to be called on basis of PE from top
3242 * to bottom style. So the the I/O or MMIO segment assigned to
3243 * parent PE could be overridden by its child PEs if necessary.
3244 */
3245 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3246 {
3247 struct pci_dev *pdev;
3248 int i;
3249
3250 /*
3251 * NOTE: We only care PCI bus based PE for now. For PCI
3252 * device based PE, for example SRIOV sensitive VF should
3253 * be figured out later.
3254 */
3255 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3256
3257 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3258 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3259 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3260
3261 /*
3262 * If the PE contains all subordinate PCI buses, the
3263 * windows of the child bridges should be mapped to
3264 * the PE as well.
3265 */
3266 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3267 continue;
3268 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3269 pnv_ioda_setup_pe_res(pe,
3270 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3271 }
3272 }
3273
3274 #ifdef CONFIG_DEBUG_FS
3275 static int pnv_pci_diag_data_set(void *data, u64 val)
3276 {
3277 struct pci_controller *hose;
3278 struct pnv_phb *phb;
3279 s64 ret;
3280
3281 if (val != 1ULL)
3282 return -EINVAL;
3283
3284 hose = (struct pci_controller *)data;
3285 if (!hose || !hose->private_data)
3286 return -ENODEV;
3287
3288 phb = hose->private_data;
3289
3290 /* Retrieve the diag data from firmware */
3291 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3292 phb->diag_data_size);
3293 if (ret != OPAL_SUCCESS)
3294 return -EIO;
3295
3296 /* Print the diag data to the kernel log */
3297 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3298 return 0;
3299 }
3300
3301 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3302 pnv_pci_diag_data_set, "%llu\n");
3303
3304 #endif /* CONFIG_DEBUG_FS */
3305
3306 static void pnv_pci_ioda_create_dbgfs(void)
3307 {
3308 #ifdef CONFIG_DEBUG_FS
3309 struct pci_controller *hose, *tmp;
3310 struct pnv_phb *phb;
3311 char name[16];
3312
3313 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3314 phb = hose->private_data;
3315
3316 /* Notify initialization of PHB done */
3317 phb->initialized = 1;
3318
3319 sprintf(name, "PCI%04x", hose->global_number);
3320 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3321 if (!phb->dbgfs) {
3322 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3323 __func__, hose->global_number);
3324 continue;
3325 }
3326
3327 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3328 &pnv_pci_diag_data_fops);
3329 }
3330 #endif /* CONFIG_DEBUG_FS */
3331 }
3332
3333 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3334 {
3335 struct pci_dev *dev = bus->self;
3336 struct pci_bus *child;
3337
3338 /* Empty bus ? bail */
3339 if (list_empty(&bus->devices))
3340 return;
3341
3342 /*
3343 * If there's a bridge associated with that bus enable it. This works
3344 * around races in the generic code if the enabling is done during
3345 * parallel probing. This can be removed once those races have been
3346 * fixed.
3347 */
3348 if (dev) {
3349 int rc = pci_enable_device(dev);
3350 if (rc)
3351 dev_err(&dev->dev, "Error enabling bridge (%d)\n", rc);
3352 pci_set_master(dev);
3353 }
3354
3355 /* Perform the same to child busses */
3356 list_for_each_entry(child, &bus->children, node)
3357 pnv_pci_enable_bridge(child);
3358 }
3359
3360 static void pnv_pci_enable_bridges(void)
3361 {
3362 struct pci_controller *hose;
3363
3364 list_for_each_entry(hose, &hose_list, list_node)
3365 pnv_pci_enable_bridge(hose->bus);
3366 }
3367
3368 static void pnv_pci_ioda_fixup(void)
3369 {
3370 pnv_pci_ioda_setup_PEs();
3371 pnv_pci_ioda_setup_iommu_api();
3372 pnv_pci_ioda_create_dbgfs();
3373
3374 pnv_pci_enable_bridges();
3375
3376 #ifdef CONFIG_EEH
3377 pnv_eeh_post_init();
3378 #endif
3379 }
3380
3381 /*
3382 * Returns the alignment for I/O or memory windows for P2P
3383 * bridges. That actually depends on how PEs are segmented.
3384 * For now, we return I/O or M32 segment size for PE sensitive
3385 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3386 * 1MiB for memory) will be returned.
3387 *
3388 * The current PCI bus might be put into one PE, which was
3389 * create against the parent PCI bridge. For that case, we
3390 * needn't enlarge the alignment so that we can save some
3391 * resources.
3392 */
3393 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3394 unsigned long type)
3395 {
3396 struct pci_dev *bridge;
3397 struct pci_controller *hose = pci_bus_to_host(bus);
3398 struct pnv_phb *phb = hose->private_data;
3399 int num_pci_bridges = 0;
3400
3401 bridge = bus->self;
3402 while (bridge) {
3403 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3404 num_pci_bridges++;
3405 if (num_pci_bridges >= 2)
3406 return 1;
3407 }
3408
3409 bridge = bridge->bus->self;
3410 }
3411
3412 /*
3413 * We fall back to M32 if M64 isn't supported. We enforce the M64
3414 * alignment for any 64-bit resource, PCIe doesn't care and
3415 * bridges only do 64-bit prefetchable anyway.
3416 */
3417 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3418 return phb->ioda.m64_segsize;
3419 if (type & IORESOURCE_MEM)
3420 return phb->ioda.m32_segsize;
3421
3422 return phb->ioda.io_segsize;
3423 }
3424
3425 /*
3426 * We are updating root port or the upstream port of the
3427 * bridge behind the root port with PHB's windows in order
3428 * to accommodate the changes on required resources during
3429 * PCI (slot) hotplug, which is connected to either root
3430 * port or the downstream ports of PCIe switch behind the
3431 * root port.
3432 */
3433 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3434 unsigned long type)
3435 {
3436 struct pci_controller *hose = pci_bus_to_host(bus);
3437 struct pnv_phb *phb = hose->private_data;
3438 struct pci_dev *bridge = bus->self;
3439 struct resource *r, *w;
3440 bool msi_region = false;
3441 int i;
3442
3443 /* Check if we need apply fixup to the bridge's windows */
3444 if (!pci_is_root_bus(bridge->bus) &&
3445 !pci_is_root_bus(bridge->bus->self->bus))
3446 return;
3447
3448 /* Fixup the resources */
3449 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3450 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3451 if (!r->flags || !r->parent)
3452 continue;
3453
3454 w = NULL;
3455 if (r->flags & type & IORESOURCE_IO)
3456 w = &hose->io_resource;
3457 else if (pnv_pci_is_m64(phb, r) &&
3458 (type & IORESOURCE_PREFETCH) &&
3459 phb->ioda.m64_segsize)
3460 w = &hose->mem_resources[1];
3461 else if (r->flags & type & IORESOURCE_MEM) {
3462 w = &hose->mem_resources[0];
3463 msi_region = true;
3464 }
3465
3466 r->start = w->start;
3467 r->end = w->end;
3468
3469 /* The 64KB 32-bits MSI region shouldn't be included in
3470 * the 32-bits bridge window. Otherwise, we can see strange
3471 * issues. One of them is EEH error observed on Garrison.
3472 *
3473 * Exclude top 1MB region which is the minimal alignment of
3474 * 32-bits bridge window.
3475 */
3476 if (msi_region) {
3477 r->end += 0x10000;
3478 r->end -= 0x100000;
3479 }
3480 }
3481 }
3482
3483 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3484 {
3485 struct pci_controller *hose = pci_bus_to_host(bus);
3486 struct pnv_phb *phb = hose->private_data;
3487 struct pci_dev *bridge = bus->self;
3488 struct pnv_ioda_pe *pe;
3489 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3490
3491 /* Extend bridge's windows if necessary */
3492 pnv_pci_fixup_bridge_resources(bus, type);
3493
3494 /* The PE for root bus should be realized before any one else */
3495 if (!phb->ioda.root_pe_populated) {
3496 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3497 if (pe) {
3498 phb->ioda.root_pe_idx = pe->pe_number;
3499 phb->ioda.root_pe_populated = true;
3500 }
3501 }
3502
3503 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3504 if (list_empty(&bus->devices))
3505 return;
3506
3507 /* Reserve PEs according to used M64 resources */
3508 if (phb->reserve_m64_pe)
3509 phb->reserve_m64_pe(bus, NULL, all);
3510
3511 /*
3512 * Assign PE. We might run here because of partial hotplug.
3513 * For the case, we just pick up the existing PE and should
3514 * not allocate resources again.
3515 */
3516 pe = pnv_ioda_setup_bus_PE(bus, all);
3517 if (!pe)
3518 return;
3519
3520 pnv_ioda_setup_pe_seg(pe);
3521 switch (phb->type) {
3522 case PNV_PHB_IODA1:
3523 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3524 break;
3525 case PNV_PHB_IODA2:
3526 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3527 break;
3528 default:
3529 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3530 __func__, phb->hose->global_number, phb->type);
3531 }
3532 }
3533
3534 static resource_size_t pnv_pci_default_alignment(void)
3535 {
3536 return PAGE_SIZE;
3537 }
3538
3539 #ifdef CONFIG_PCI_IOV
3540 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3541 int resno)
3542 {
3543 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3544 struct pnv_phb *phb = hose->private_data;
3545 struct pci_dn *pdn = pci_get_pdn(pdev);
3546 resource_size_t align;
3547
3548 /*
3549 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3550 * SR-IOV. While from hardware perspective, the range mapped by M64
3551 * BAR should be size aligned.
3552 *
3553 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3554 * powernv-specific hardware restriction is gone. But if just use the
3555 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3556 * in one segment of M64 #15, which introduces the PE conflict between
3557 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3558 * m64_segsize.
3559 *
3560 * This function returns the total IOV BAR size if M64 BAR is in
3561 * Shared PE mode or just VF BAR size if not.
3562 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3563 * M64 segment size if IOV BAR size is less.
3564 */
3565 align = pci_iov_resource_size(pdev, resno);
3566 if (!pdn->vfs_expanded)
3567 return align;
3568 if (pdn->m64_single_mode)
3569 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3570
3571 return pdn->vfs_expanded * align;
3572 }
3573 #endif /* CONFIG_PCI_IOV */
3574
3575 /* Prevent enabling devices for which we couldn't properly
3576 * assign a PE
3577 */
3578 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3579 {
3580 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3581 struct pnv_phb *phb = hose->private_data;
3582 struct pci_dn *pdn;
3583
3584 /* The function is probably called while the PEs have
3585 * not be created yet. For example, resource reassignment
3586 * during PCI probe period. We just skip the check if
3587 * PEs isn't ready.
3588 */
3589 if (!phb->initialized)
3590 return true;
3591
3592 pdn = pci_get_pdn(dev);
3593 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3594 return false;
3595
3596 return true;
3597 }
3598
3599 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3600 int num)
3601 {
3602 struct pnv_ioda_pe *pe = container_of(table_group,
3603 struct pnv_ioda_pe, table_group);
3604 struct pnv_phb *phb = pe->phb;
3605 unsigned int idx;
3606 long rc;
3607
3608 pe_info(pe, "Removing DMA window #%d\n", num);
3609 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3610 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3611 continue;
3612
3613 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3614 idx, 0, 0ul, 0ul, 0ul);
3615 if (rc != OPAL_SUCCESS) {
3616 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3617 rc, idx);
3618 return rc;
3619 }
3620
3621 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3622 }
3623
3624 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3625 return OPAL_SUCCESS;
3626 }
3627
3628 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3629 {
3630 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3631 struct iommu_table *tbl = pe->table_group.tables[0];
3632 int64_t rc;
3633
3634 if (!weight)
3635 return;
3636
3637 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3638 if (rc != OPAL_SUCCESS)
3639 return;
3640
3641 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3642 if (pe->table_group.group) {
3643 iommu_group_put(pe->table_group.group);
3644 WARN_ON(pe->table_group.group);
3645 }
3646
3647 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3648 iommu_tce_table_put(tbl);
3649 }
3650
3651 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3652 {
3653 struct iommu_table *tbl = pe->table_group.tables[0];
3654 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3655 #ifdef CONFIG_IOMMU_API
3656 int64_t rc;
3657 #endif
3658
3659 if (!weight)
3660 return;
3661
3662 #ifdef CONFIG_IOMMU_API
3663 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3664 if (rc)
3665 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3666 #endif
3667
3668 pnv_pci_ioda2_set_bypass(pe, false);
3669 if (pe->table_group.group) {
3670 iommu_group_put(pe->table_group.group);
3671 WARN_ON(pe->table_group.group);
3672 }
3673
3674 iommu_tce_table_put(tbl);
3675 }
3676
3677 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3678 unsigned short win,
3679 unsigned int *map)
3680 {
3681 struct pnv_phb *phb = pe->phb;
3682 int idx;
3683 int64_t rc;
3684
3685 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3686 if (map[idx] != pe->pe_number)
3687 continue;
3688
3689 if (win == OPAL_M64_WINDOW_TYPE)
3690 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3691 phb->ioda.reserved_pe_idx, win,
3692 idx / PNV_IODA1_M64_SEGS,
3693 idx % PNV_IODA1_M64_SEGS);
3694 else
3695 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3696 phb->ioda.reserved_pe_idx, win, 0, idx);
3697
3698 if (rc != OPAL_SUCCESS)
3699 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3700 rc, win, idx);
3701
3702 map[idx] = IODA_INVALID_PE;
3703 }
3704 }
3705
3706 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3707 {
3708 struct pnv_phb *phb = pe->phb;
3709
3710 if (phb->type == PNV_PHB_IODA1) {
3711 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3712 phb->ioda.io_segmap);
3713 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3714 phb->ioda.m32_segmap);
3715 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3716 phb->ioda.m64_segmap);
3717 } else if (phb->type == PNV_PHB_IODA2) {
3718 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3719 phb->ioda.m32_segmap);
3720 }
3721 }
3722
3723 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3724 {
3725 struct pnv_phb *phb = pe->phb;
3726 struct pnv_ioda_pe *slave, *tmp;
3727
3728 list_del(&pe->list);
3729 switch (phb->type) {
3730 case PNV_PHB_IODA1:
3731 pnv_pci_ioda1_release_pe_dma(pe);
3732 break;
3733 case PNV_PHB_IODA2:
3734 pnv_pci_ioda2_release_pe_dma(pe);
3735 break;
3736 default:
3737 WARN_ON(1);
3738 }
3739
3740 pnv_ioda_release_pe_seg(pe);
3741 pnv_ioda_deconfigure_pe(pe->phb, pe);
3742
3743 /* Release slave PEs in the compound PE */
3744 if (pe->flags & PNV_IODA_PE_MASTER) {
3745 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3746 list_del(&slave->list);
3747 pnv_ioda_free_pe(slave);
3748 }
3749 }
3750
3751 /*
3752 * The PE for root bus can be removed because of hotplug in EEH
3753 * recovery for fenced PHB error. We need to mark the PE dead so
3754 * that it can be populated again in PCI hot add path. The PE
3755 * shouldn't be destroyed as it's the global reserved resource.
3756 */
3757 if (phb->ioda.root_pe_populated &&
3758 phb->ioda.root_pe_idx == pe->pe_number)
3759 phb->ioda.root_pe_populated = false;
3760 else
3761 pnv_ioda_free_pe(pe);
3762 }
3763
3764 static void pnv_pci_release_device(struct pci_dev *pdev)
3765 {
3766 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3767 struct pnv_phb *phb = hose->private_data;
3768 struct pci_dn *pdn = pci_get_pdn(pdev);
3769 struct pnv_ioda_pe *pe;
3770
3771 if (pdev->is_virtfn)
3772 return;
3773
3774 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3775 return;
3776
3777 /*
3778 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3779 * isn't removed and added afterwards in this scenario. We should
3780 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3781 * device count is decreased on removing devices while failing to
3782 * be increased on adding devices. It leads to unbalanced PE's device
3783 * count and eventually make normal PCI hotplug path broken.
3784 */
3785 pe = &phb->ioda.pe_array[pdn->pe_number];
3786 pdn->pe_number = IODA_INVALID_PE;
3787
3788 WARN_ON(--pe->device_count < 0);
3789 if (pe->device_count == 0)
3790 pnv_ioda_release_pe(pe);
3791 }
3792
3793 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3794 {
3795 struct pnv_phb *phb = hose->private_data;
3796
3797 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3798 OPAL_ASSERT_RESET);
3799 }
3800
3801 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3802 .dma_dev_setup = pnv_pci_dma_dev_setup,
3803 .dma_bus_setup = pnv_pci_dma_bus_setup,
3804 #ifdef CONFIG_PCI_MSI
3805 .setup_msi_irqs = pnv_setup_msi_irqs,
3806 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3807 #endif
3808 .enable_device_hook = pnv_pci_enable_device_hook,
3809 .release_device = pnv_pci_release_device,
3810 .window_alignment = pnv_pci_window_alignment,
3811 .setup_bridge = pnv_pci_setup_bridge,
3812 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3813 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3814 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3815 .shutdown = pnv_pci_ioda_shutdown,
3816 };
3817
3818 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3819 {
3820 dev_err_once(&npdev->dev,
3821 "%s operation unsupported for NVLink devices\n",
3822 __func__);
3823 return -EPERM;
3824 }
3825
3826 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3827 .dma_dev_setup = pnv_pci_dma_dev_setup,
3828 #ifdef CONFIG_PCI_MSI
3829 .setup_msi_irqs = pnv_setup_msi_irqs,
3830 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3831 #endif
3832 .enable_device_hook = pnv_pci_enable_device_hook,
3833 .window_alignment = pnv_pci_window_alignment,
3834 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3835 .dma_set_mask = pnv_npu_dma_set_mask,
3836 .shutdown = pnv_pci_ioda_shutdown,
3837 };
3838
3839 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3840 .enable_device_hook = pnv_pci_enable_device_hook,
3841 .window_alignment = pnv_pci_window_alignment,
3842 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3843 .shutdown = pnv_pci_ioda_shutdown,
3844 };
3845
3846 #ifdef CONFIG_CXL_BASE
3847 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3848 .dma_dev_setup = pnv_pci_dma_dev_setup,
3849 .dma_bus_setup = pnv_pci_dma_bus_setup,
3850 #ifdef CONFIG_PCI_MSI
3851 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3852 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3853 #endif
3854 .enable_device_hook = pnv_cxl_enable_device_hook,
3855 .disable_device = pnv_cxl_disable_device,
3856 .release_device = pnv_pci_release_device,
3857 .window_alignment = pnv_pci_window_alignment,
3858 .setup_bridge = pnv_pci_setup_bridge,
3859 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3860 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3861 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3862 .shutdown = pnv_pci_ioda_shutdown,
3863 };
3864 #endif
3865
3866 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3867 u64 hub_id, int ioda_type)
3868 {
3869 struct pci_controller *hose;
3870 struct pnv_phb *phb;
3871 unsigned long size, m64map_off, m32map_off, pemap_off;
3872 unsigned long iomap_off = 0, dma32map_off = 0;
3873 struct resource r;
3874 const __be64 *prop64;
3875 const __be32 *prop32;
3876 int len;
3877 unsigned int segno;
3878 u64 phb_id;
3879 void *aux;
3880 long rc;
3881
3882 if (!of_device_is_available(np))
3883 return;
3884
3885 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3886
3887 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3888 if (!prop64) {
3889 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3890 return;
3891 }
3892 phb_id = be64_to_cpup(prop64);
3893 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3894
3895 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3896
3897 /* Allocate PCI controller */
3898 phb->hose = hose = pcibios_alloc_controller(np);
3899 if (!phb->hose) {
3900 pr_err(" Can't allocate PCI controller for %pOF\n",
3901 np);
3902 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3903 return;
3904 }
3905
3906 spin_lock_init(&phb->lock);
3907 prop32 = of_get_property(np, "bus-range", &len);
3908 if (prop32 && len == 8) {
3909 hose->first_busno = be32_to_cpu(prop32[0]);
3910 hose->last_busno = be32_to_cpu(prop32[1]);
3911 } else {
3912 pr_warn(" Broken <bus-range> on %pOF\n", np);
3913 hose->first_busno = 0;
3914 hose->last_busno = 0xff;
3915 }
3916 hose->private_data = phb;
3917 phb->hub_id = hub_id;
3918 phb->opal_id = phb_id;
3919 phb->type = ioda_type;
3920 mutex_init(&phb->ioda.pe_alloc_mutex);
3921
3922 /* Detect specific models for error handling */
3923 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3924 phb->model = PNV_PHB_MODEL_P7IOC;
3925 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3926 phb->model = PNV_PHB_MODEL_PHB3;
3927 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3928 phb->model = PNV_PHB_MODEL_NPU;
3929 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3930 phb->model = PNV_PHB_MODEL_NPU2;
3931 else
3932 phb->model = PNV_PHB_MODEL_UNKNOWN;
3933
3934 /* Initialize diagnostic data buffer */
3935 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3936 if (prop32)
3937 phb->diag_data_size = be32_to_cpup(prop32);
3938 else
3939 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3940
3941 phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0);
3942
3943 /* Parse 32-bit and IO ranges (if any) */
3944 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3945
3946 /* Get registers */
3947 if (!of_address_to_resource(np, 0, &r)) {
3948 phb->regs_phys = r.start;
3949 phb->regs = ioremap(r.start, resource_size(&r));
3950 if (phb->regs == NULL)
3951 pr_err(" Failed to map registers !\n");
3952 }
3953
3954 /* Initialize more IODA stuff */
3955 phb->ioda.total_pe_num = 1;
3956 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3957 if (prop32)
3958 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3959 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3960 if (prop32)
3961 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3962
3963 /* Invalidate RID to PE# mapping */
3964 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3965 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3966
3967 /* Parse 64-bit MMIO range */
3968 pnv_ioda_parse_m64_window(phb);
3969
3970 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3971 /* FW Has already off top 64k of M32 space (MSI space) */
3972 phb->ioda.m32_size += 0x10000;
3973
3974 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3975 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3976 phb->ioda.io_size = hose->pci_io_size;
3977 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3978 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3979
3980 /* Calculate how many 32-bit TCE segments we have */
3981 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3982 PNV_IODA1_DMA32_SEGSIZE;
3983
3984 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3985 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3986 sizeof(unsigned long));
3987 m64map_off = size;
3988 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3989 m32map_off = size;
3990 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3991 if (phb->type == PNV_PHB_IODA1) {
3992 iomap_off = size;
3993 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3994 dma32map_off = size;
3995 size += phb->ioda.dma32_count *
3996 sizeof(phb->ioda.dma32_segmap[0]);
3997 }
3998 pemap_off = size;
3999 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
4000 aux = memblock_virt_alloc(size, 0);
4001 phb->ioda.pe_alloc = aux;
4002 phb->ioda.m64_segmap = aux + m64map_off;
4003 phb->ioda.m32_segmap = aux + m32map_off;
4004 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
4005 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
4006 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
4007 }
4008 if (phb->type == PNV_PHB_IODA1) {
4009 phb->ioda.io_segmap = aux + iomap_off;
4010 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
4011 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
4012
4013 phb->ioda.dma32_segmap = aux + dma32map_off;
4014 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
4015 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
4016 }
4017 phb->ioda.pe_array = aux + pemap_off;
4018
4019 /*
4020 * Choose PE number for root bus, which shouldn't have
4021 * M64 resources consumed by its child devices. To pick
4022 * the PE number adjacent to the reserved one if possible.
4023 */
4024 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
4025 if (phb->ioda.reserved_pe_idx == 0) {
4026 phb->ioda.root_pe_idx = 1;
4027 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
4028 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
4029 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
4030 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
4031 } else {
4032 phb->ioda.root_pe_idx = IODA_INVALID_PE;
4033 }
4034
4035 INIT_LIST_HEAD(&phb->ioda.pe_list);
4036 mutex_init(&phb->ioda.pe_list_mutex);
4037
4038 /* Calculate how many 32-bit TCE segments we have */
4039 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
4040 PNV_IODA1_DMA32_SEGSIZE;
4041
4042 #if 0 /* We should really do that ... */
4043 rc = opal_pci_set_phb_mem_window(opal->phb_id,
4044 window_type,
4045 window_num,
4046 starting_real_address,
4047 starting_pci_address,
4048 segment_size);
4049 #endif
4050
4051 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
4052 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
4053 phb->ioda.m32_size, phb->ioda.m32_segsize);
4054 if (phb->ioda.m64_size)
4055 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
4056 phb->ioda.m64_size, phb->ioda.m64_segsize);
4057 if (phb->ioda.io_size)
4058 pr_info(" IO: 0x%x [segment=0x%x]\n",
4059 phb->ioda.io_size, phb->ioda.io_segsize);
4060
4061
4062 phb->hose->ops = &pnv_pci_ops;
4063 phb->get_pe_state = pnv_ioda_get_pe_state;
4064 phb->freeze_pe = pnv_ioda_freeze_pe;
4065 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
4066
4067 /* Setup MSI support */
4068 pnv_pci_init_ioda_msis(phb);
4069
4070 /*
4071 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
4072 * to let the PCI core do resource assignment. It's supposed
4073 * that the PCI core will do correct I/O and MMIO alignment
4074 * for the P2P bridge bars so that each PCI bus (excluding
4075 * the child P2P bridges) can form individual PE.
4076 */
4077 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
4078
4079 switch (phb->type) {
4080 case PNV_PHB_NPU_NVLINK:
4081 hose->controller_ops = pnv_npu_ioda_controller_ops;
4082 break;
4083 case PNV_PHB_NPU_OCAPI:
4084 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
4085 break;
4086 default:
4087 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
4088 hose->controller_ops = pnv_pci_ioda_controller_ops;
4089 }
4090
4091 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
4092
4093 #ifdef CONFIG_PCI_IOV
4094 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
4095 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
4096 #endif
4097
4098 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
4099
4100 /* Reset IODA tables to a clean state */
4101 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
4102 if (rc)
4103 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
4104
4105 /*
4106 * If we're running in kdump kernel, the previous kernel never
4107 * shutdown PCI devices correctly. We already got IODA table
4108 * cleaned out. So we have to issue PHB reset to stop all PCI
4109 * transactions from previous kernel.
4110 */
4111 if (is_kdump_kernel()) {
4112 pr_info(" Issue PHB reset ...\n");
4113 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
4114 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
4115 }
4116
4117 /* Remove M64 resource if we can't configure it successfully */
4118 if (!phb->init_m64 || phb->init_m64(phb))
4119 hose->mem_resources[1].flags = 0;
4120 }
4121
4122 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4123 {
4124 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4125 }
4126
4127 void __init pnv_pci_init_npu_phb(struct device_node *np)
4128 {
4129 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
4130 }
4131
4132 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
4133 {
4134 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
4135 }
4136
4137 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
4138 {
4139 struct pci_controller *hose = pci_bus_to_host(dev->bus);
4140 struct pnv_phb *phb = hose->private_data;
4141
4142 if (!machine_is(powernv))
4143 return;
4144
4145 if (phb->type == PNV_PHB_NPU_OCAPI)
4146 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4147 }
4148 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
4149
4150 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4151 {
4152 struct device_node *phbn;
4153 const __be64 *prop64;
4154 u64 hub_id;
4155
4156 pr_info("Probing IODA IO-Hub %pOF\n", np);
4157
4158 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4159 if (!prop64) {
4160 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4161 return;
4162 }
4163 hub_id = be64_to_cpup(prop64);
4164 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4165
4166 /* Count child PHBs */
4167 for_each_child_of_node(np, phbn) {
4168 /* Look for IODA1 PHBs */
4169 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4170 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4171 }
4172 }
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