2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
32 #include <asm/stacktrace.h>
35 #include <asm/alternative.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/timer.h>
41 #include <asm/unwind.h>
43 #include "perf_event.h"
45 struct x86_pmu x86_pmu __read_mostly
;
47 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
51 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
53 u64 __read_mostly hw_cache_event_ids
54 [PERF_COUNT_HW_CACHE_MAX
]
55 [PERF_COUNT_HW_CACHE_OP_MAX
]
56 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
57 u64 __read_mostly hw_cache_extra_regs
58 [PERF_COUNT_HW_CACHE_MAX
]
59 [PERF_COUNT_HW_CACHE_OP_MAX
]
60 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
63 * Propagate event elapsed time into the generic event.
64 * Can only be executed on the CPU where the event is active.
65 * Returns the delta events processed.
67 u64
x86_perf_event_update(struct perf_event
*event
)
69 struct hw_perf_event
*hwc
= &event
->hw
;
70 int shift
= 64 - x86_pmu
.cntval_bits
;
71 u64 prev_raw_count
, new_raw_count
;
75 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
79 * Careful: an NMI might modify the previous event value.
81 * Our tactic to handle this is to first atomically read and
82 * exchange a new raw count - then add that new-prev delta
83 * count to the generic event atomically:
86 prev_raw_count
= local64_read(&hwc
->prev_count
);
87 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
89 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
90 new_raw_count
) != prev_raw_count
)
94 * Now we have the new raw value and have updated the prev
95 * timestamp already. We can now calculate the elapsed delta
96 * (event-)time and add that to the generic event.
98 * Careful, not all hw sign-extends above the physical width
101 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
104 local64_add(delta
, &event
->count
);
105 local64_sub(delta
, &hwc
->period_left
);
107 return new_raw_count
;
111 * Find and validate any extra registers to set up.
113 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
115 struct hw_perf_event_extra
*reg
;
116 struct extra_reg
*er
;
118 reg
= &event
->hw
.extra_reg
;
120 if (!x86_pmu
.extra_regs
)
123 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
124 if (er
->event
!= (config
& er
->config_mask
))
126 if (event
->attr
.config1
& ~er
->valid_mask
)
128 /* Check if the extra msrs can be safely accessed*/
129 if (!er
->extra_msr_access
)
133 reg
->config
= event
->attr
.config1
;
140 static atomic_t active_events
;
141 static atomic_t pmc_refcount
;
142 static DEFINE_MUTEX(pmc_reserve_mutex
);
144 #ifdef CONFIG_X86_LOCAL_APIC
146 static bool reserve_pmc_hardware(void)
150 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
151 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
155 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
156 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
163 for (i
--; i
>= 0; i
--)
164 release_evntsel_nmi(x86_pmu_config_addr(i
));
166 i
= x86_pmu
.num_counters
;
169 for (i
--; i
>= 0; i
--)
170 release_perfctr_nmi(x86_pmu_event_addr(i
));
175 static void release_pmc_hardware(void)
179 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
180 release_perfctr_nmi(x86_pmu_event_addr(i
));
181 release_evntsel_nmi(x86_pmu_config_addr(i
));
187 static bool reserve_pmc_hardware(void) { return true; }
188 static void release_pmc_hardware(void) {}
192 static bool check_hw_exists(void)
194 u64 val
, val_fail
= -1, val_new
= ~0;
195 int i
, reg
, reg_fail
= -1, ret
= 0;
200 * Check to see if the BIOS enabled any of the counters, if so
203 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
204 reg
= x86_pmu_config_addr(i
);
205 ret
= rdmsrl_safe(reg
, &val
);
208 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
217 if (x86_pmu
.num_counters_fixed
) {
218 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
219 ret
= rdmsrl_safe(reg
, &val
);
222 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
223 if (val
& (0x03 << i
*4)) {
232 * If all the counters are enabled, the below test will always
233 * fail. The tools will also become useless in this scenario.
234 * Just fail and disable the hardware counters.
237 if (reg_safe
== -1) {
243 * Read the current value, change it and read it back to see if it
244 * matches, this is needed to detect certain hardware emulators
245 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
247 reg
= x86_pmu_event_addr(reg_safe
);
248 if (rdmsrl_safe(reg
, &val
))
251 ret
= wrmsrl_safe(reg
, val
);
252 ret
|= rdmsrl_safe(reg
, &val_new
);
253 if (ret
|| val
!= val_new
)
257 * We still allow the PMU driver to operate:
260 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
261 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
268 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
269 pr_cont("PMU not available due to virtualization, using software events only.\n");
271 pr_cont("Broken PMU hardware detected, using software events only.\n");
272 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
279 static void hw_perf_event_destroy(struct perf_event
*event
)
281 x86_release_hardware();
282 atomic_dec(&active_events
);
285 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
287 hw_perf_event_destroy(event
);
289 /* undo the lbr/bts event accounting */
290 x86_del_exclusive(x86_lbr_exclusive_lbr
);
293 static inline int x86_pmu_initialized(void)
295 return x86_pmu
.handle_irq
!= NULL
;
299 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
301 struct perf_event_attr
*attr
= &event
->attr
;
302 unsigned int cache_type
, cache_op
, cache_result
;
305 config
= attr
->config
;
307 cache_type
= (config
>> 0) & 0xff;
308 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
310 cache_type
= array_index_nospec(cache_type
, PERF_COUNT_HW_CACHE_MAX
);
312 cache_op
= (config
>> 8) & 0xff;
313 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
315 cache_op
= array_index_nospec(cache_op
, PERF_COUNT_HW_CACHE_OP_MAX
);
317 cache_result
= (config
>> 16) & 0xff;
318 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
320 cache_result
= array_index_nospec(cache_result
, PERF_COUNT_HW_CACHE_RESULT_MAX
);
322 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
331 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
332 return x86_pmu_extra_regs(val
, event
);
335 int x86_reserve_hardware(void)
339 if (!atomic_inc_not_zero(&pmc_refcount
)) {
340 mutex_lock(&pmc_reserve_mutex
);
341 if (atomic_read(&pmc_refcount
) == 0) {
342 if (!reserve_pmc_hardware())
345 reserve_ds_buffers();
348 atomic_inc(&pmc_refcount
);
349 mutex_unlock(&pmc_reserve_mutex
);
355 void x86_release_hardware(void)
357 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
358 release_pmc_hardware();
359 release_ds_buffers();
360 mutex_unlock(&pmc_reserve_mutex
);
365 * Check if we can create event of a certain type (that no conflicting events
368 int x86_add_exclusive(unsigned int what
)
373 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
374 * LBR and BTS are still mutually exclusive.
376 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
379 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
380 mutex_lock(&pmc_reserve_mutex
);
381 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
382 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
385 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
386 mutex_unlock(&pmc_reserve_mutex
);
389 atomic_inc(&active_events
);
393 mutex_unlock(&pmc_reserve_mutex
);
397 void x86_del_exclusive(unsigned int what
)
399 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
402 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
403 atomic_dec(&active_events
);
406 int x86_setup_perfctr(struct perf_event
*event
)
408 struct perf_event_attr
*attr
= &event
->attr
;
409 struct hw_perf_event
*hwc
= &event
->hw
;
412 if (!is_sampling_event(event
)) {
413 hwc
->sample_period
= x86_pmu
.max_period
;
414 hwc
->last_period
= hwc
->sample_period
;
415 local64_set(&hwc
->period_left
, hwc
->sample_period
);
418 if (attr
->type
== PERF_TYPE_RAW
)
419 return x86_pmu_extra_regs(event
->attr
.config
, event
);
421 if (attr
->type
== PERF_TYPE_HW_CACHE
)
422 return set_ext_hw_attr(hwc
, event
);
424 if (attr
->config
>= x86_pmu
.max_events
)
430 config
= x86_pmu
.event_map(attr
->config
);
441 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
442 !attr
->freq
&& hwc
->sample_period
== 1) {
443 /* BTS is not supported by this architecture. */
444 if (!x86_pmu
.bts_active
)
447 /* BTS is currently only allowed for user-mode. */
448 if (!attr
->exclude_kernel
)
451 /* disallow bts if conflicting events are present */
452 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
455 event
->destroy
= hw_perf_lbr_event_destroy
;
458 hwc
->config
|= config
;
464 * check that branch_sample_type is compatible with
465 * settings needed for precise_ip > 1 which implies
466 * using the LBR to capture ALL taken branches at the
467 * priv levels of the measurement
469 static inline int precise_br_compat(struct perf_event
*event
)
471 u64 m
= event
->attr
.branch_sample_type
;
474 /* must capture all branches */
475 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
478 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
480 if (!event
->attr
.exclude_user
)
481 b
|= PERF_SAMPLE_BRANCH_USER
;
483 if (!event
->attr
.exclude_kernel
)
484 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
487 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
493 int x86_pmu_max_precise(void)
497 /* Support for constant skid */
498 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
501 /* Support for IP fixup */
502 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
505 if (x86_pmu
.pebs_prec_dist
)
511 int x86_pmu_hw_config(struct perf_event
*event
)
513 if (event
->attr
.precise_ip
) {
514 int precise
= x86_pmu_max_precise();
516 if (event
->attr
.precise_ip
> precise
)
519 /* There's no sense in having PEBS for non sampling events: */
520 if (!is_sampling_event(event
))
524 * check that PEBS LBR correction does not conflict with
525 * whatever the user is asking with attr->branch_sample_type
527 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
528 u64
*br_type
= &event
->attr
.branch_sample_type
;
530 if (has_branch_stack(event
)) {
531 if (!precise_br_compat(event
))
534 /* branch_sample_type is compatible */
538 * user did not specify branch_sample_type
540 * For PEBS fixups, we capture all
541 * the branches at the priv level of the
544 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
546 if (!event
->attr
.exclude_user
)
547 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
549 if (!event
->attr
.exclude_kernel
)
550 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
554 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
555 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
559 * (keep 'enabled' bit clear for now)
561 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
564 * Count user and OS events unless requested not to
566 if (!event
->attr
.exclude_user
)
567 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
568 if (!event
->attr
.exclude_kernel
)
569 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
571 if (event
->attr
.type
== PERF_TYPE_RAW
)
572 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
574 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
575 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
576 event
->attr
.sample_period
)
580 return x86_setup_perfctr(event
);
584 * Setup the hardware configuration for a given attr_type
586 static int __x86_pmu_event_init(struct perf_event
*event
)
590 if (!x86_pmu_initialized())
593 err
= x86_reserve_hardware();
597 atomic_inc(&active_events
);
598 event
->destroy
= hw_perf_event_destroy
;
601 event
->hw
.last_cpu
= -1;
602 event
->hw
.last_tag
= ~0ULL;
605 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
606 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
608 return x86_pmu
.hw_config(event
);
611 void x86_pmu_disable_all(void)
613 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
616 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
619 if (!test_bit(idx
, cpuc
->active_mask
))
621 rdmsrl(x86_pmu_config_addr(idx
), val
);
622 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
624 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
625 wrmsrl(x86_pmu_config_addr(idx
), val
);
630 * There may be PMI landing after enabled=0. The PMI hitting could be before or
633 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
634 * It will not be re-enabled in the NMI handler again, because enabled=0. After
635 * handling the NMI, disable_all will be called, which will not change the
636 * state either. If PMI hits after disable_all, the PMU is already disabled
637 * before entering NMI handler. The NMI handler will not change the state
640 * So either situation is harmless.
642 static void x86_pmu_disable(struct pmu
*pmu
)
644 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
646 if (!x86_pmu_initialized())
656 x86_pmu
.disable_all();
659 void x86_pmu_enable_all(int added
)
661 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
664 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
665 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
667 if (!test_bit(idx
, cpuc
->active_mask
))
670 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
674 static struct pmu pmu
;
676 static inline int is_x86_event(struct perf_event
*event
)
678 return event
->pmu
== &pmu
;
682 * Event scheduler state:
684 * Assign events iterating over all events and counters, beginning
685 * with events with least weights first. Keep the current iterator
686 * state in struct sched_state.
690 int event
; /* event index */
691 int counter
; /* counter index */
692 int unassigned
; /* number of events to be assigned left */
693 int nr_gp
; /* number of GP counters used */
694 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
697 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
698 #define SCHED_STATES_MAX 2
705 struct event_constraint
**constraints
;
706 struct sched_state state
;
707 struct sched_state saved
[SCHED_STATES_MAX
];
711 * Initialize interator that runs through all events and counters.
713 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
714 int num
, int wmin
, int wmax
, int gpmax
)
718 memset(sched
, 0, sizeof(*sched
));
719 sched
->max_events
= num
;
720 sched
->max_weight
= wmax
;
721 sched
->max_gp
= gpmax
;
722 sched
->constraints
= constraints
;
724 for (idx
= 0; idx
< num
; idx
++) {
725 if (constraints
[idx
]->weight
== wmin
)
729 sched
->state
.event
= idx
; /* start with min weight */
730 sched
->state
.weight
= wmin
;
731 sched
->state
.unassigned
= num
;
734 static void perf_sched_save_state(struct perf_sched
*sched
)
736 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
739 sched
->saved
[sched
->saved_states
] = sched
->state
;
740 sched
->saved_states
++;
743 static bool perf_sched_restore_state(struct perf_sched
*sched
)
745 if (!sched
->saved_states
)
748 sched
->saved_states
--;
749 sched
->state
= sched
->saved
[sched
->saved_states
];
751 /* continue with next counter: */
752 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
758 * Select a counter for the current event to schedule. Return true on
761 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
763 struct event_constraint
*c
;
766 if (!sched
->state
.unassigned
)
769 if (sched
->state
.event
>= sched
->max_events
)
772 c
= sched
->constraints
[sched
->state
.event
];
773 /* Prefer fixed purpose counters */
774 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
775 idx
= INTEL_PMC_IDX_FIXED
;
776 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
777 if (!__test_and_set_bit(idx
, sched
->state
.used
))
782 /* Grab the first unused counter starting with idx */
783 idx
= sched
->state
.counter
;
784 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
785 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
786 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
796 sched
->state
.counter
= idx
;
799 perf_sched_save_state(sched
);
804 static bool perf_sched_find_counter(struct perf_sched
*sched
)
806 while (!__perf_sched_find_counter(sched
)) {
807 if (!perf_sched_restore_state(sched
))
815 * Go through all unassigned events and find the next one to schedule.
816 * Take events with the least weight first. Return true on success.
818 static bool perf_sched_next_event(struct perf_sched
*sched
)
820 struct event_constraint
*c
;
822 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
827 sched
->state
.event
++;
828 if (sched
->state
.event
>= sched
->max_events
) {
830 sched
->state
.event
= 0;
831 sched
->state
.weight
++;
832 if (sched
->state
.weight
> sched
->max_weight
)
835 c
= sched
->constraints
[sched
->state
.event
];
836 } while (c
->weight
!= sched
->state
.weight
);
838 sched
->state
.counter
= 0; /* start with first counter */
844 * Assign a counter for each event.
846 int perf_assign_events(struct event_constraint
**constraints
, int n
,
847 int wmin
, int wmax
, int gpmax
, int *assign
)
849 struct perf_sched sched
;
851 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
854 if (!perf_sched_find_counter(&sched
))
857 assign
[sched
.state
.event
] = sched
.state
.counter
;
858 } while (perf_sched_next_event(&sched
));
860 return sched
.state
.unassigned
;
862 EXPORT_SYMBOL_GPL(perf_assign_events
);
864 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
866 struct event_constraint
*c
;
867 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
868 struct perf_event
*e
;
869 int i
, wmin
, wmax
, unsched
= 0;
870 struct hw_perf_event
*hwc
;
872 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
874 if (x86_pmu
.start_scheduling
)
875 x86_pmu
.start_scheduling(cpuc
);
877 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
878 cpuc
->event_constraint
[i
] = NULL
;
879 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
880 cpuc
->event_constraint
[i
] = c
;
882 wmin
= min(wmin
, c
->weight
);
883 wmax
= max(wmax
, c
->weight
);
887 * fastpath, try to reuse previous register
889 for (i
= 0; i
< n
; i
++) {
890 hwc
= &cpuc
->event_list
[i
]->hw
;
891 c
= cpuc
->event_constraint
[i
];
897 /* constraint still honored */
898 if (!test_bit(hwc
->idx
, c
->idxmsk
))
901 /* not already used */
902 if (test_bit(hwc
->idx
, used_mask
))
905 __set_bit(hwc
->idx
, used_mask
);
907 assign
[i
] = hwc
->idx
;
912 int gpmax
= x86_pmu
.num_counters
;
915 * Do not allow scheduling of more than half the available
918 * This helps avoid counter starvation of sibling thread by
919 * ensuring at most half the counters cannot be in exclusive
920 * mode. There is no designated counters for the limits. Any
921 * N/2 counters can be used. This helps with events with
922 * specific counter constraints.
924 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
925 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
928 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
929 wmax
, gpmax
, assign
);
933 * In case of success (unsched = 0), mark events as committed,
934 * so we do not put_constraint() in case new events are added
935 * and fail to be scheduled
937 * We invoke the lower level commit callback to lock the resource
939 * We do not need to do all of this in case we are called to
940 * validate an event group (assign == NULL)
942 if (!unsched
&& assign
) {
943 for (i
= 0; i
< n
; i
++) {
944 e
= cpuc
->event_list
[i
];
945 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
946 if (x86_pmu
.commit_scheduling
)
947 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
950 for (i
= 0; i
< n
; i
++) {
951 e
= cpuc
->event_list
[i
];
953 * do not put_constraint() on comitted events,
954 * because they are good to go
956 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
960 * release events that failed scheduling
962 if (x86_pmu
.put_event_constraints
)
963 x86_pmu
.put_event_constraints(cpuc
, e
);
967 if (x86_pmu
.stop_scheduling
)
968 x86_pmu
.stop_scheduling(cpuc
);
970 return unsched
? -EINVAL
: 0;
974 * dogrp: true if must collect siblings events (group)
975 * returns total number of events and error code
977 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
979 struct perf_event
*event
;
982 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
984 /* current number of events already accepted */
987 if (is_x86_event(leader
)) {
990 cpuc
->event_list
[n
] = leader
;
996 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
997 if (!is_x86_event(event
) ||
998 event
->state
<= PERF_EVENT_STATE_OFF
)
1004 cpuc
->event_list
[n
] = event
;
1010 static inline void x86_assign_hw_event(struct perf_event
*event
,
1011 struct cpu_hw_events
*cpuc
, int i
)
1013 struct hw_perf_event
*hwc
= &event
->hw
;
1015 hwc
->idx
= cpuc
->assign
[i
];
1016 hwc
->last_cpu
= smp_processor_id();
1017 hwc
->last_tag
= ++cpuc
->tags
[i
];
1019 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1020 hwc
->config_base
= 0;
1021 hwc
->event_base
= 0;
1022 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1023 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1024 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1025 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1027 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1028 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1029 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1033 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1034 struct cpu_hw_events
*cpuc
,
1037 return hwc
->idx
== cpuc
->assign
[i
] &&
1038 hwc
->last_cpu
== smp_processor_id() &&
1039 hwc
->last_tag
== cpuc
->tags
[i
];
1042 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1044 static void x86_pmu_enable(struct pmu
*pmu
)
1046 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1047 struct perf_event
*event
;
1048 struct hw_perf_event
*hwc
;
1049 int i
, added
= cpuc
->n_added
;
1051 if (!x86_pmu_initialized())
1057 if (cpuc
->n_added
) {
1058 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1060 * apply assignment obtained either from
1061 * hw_perf_group_sched_in() or x86_pmu_enable()
1063 * step1: save events moving to new counters
1065 for (i
= 0; i
< n_running
; i
++) {
1066 event
= cpuc
->event_list
[i
];
1070 * we can avoid reprogramming counter if:
1071 * - assigned same counter as last time
1072 * - running on same CPU as last time
1073 * - no other event has used the counter since
1075 if (hwc
->idx
== -1 ||
1076 match_prev_assignment(hwc
, cpuc
, i
))
1080 * Ensure we don't accidentally enable a stopped
1081 * counter simply because we rescheduled.
1083 if (hwc
->state
& PERF_HES_STOPPED
)
1084 hwc
->state
|= PERF_HES_ARCH
;
1086 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1090 * step2: reprogram moved events into new counters
1092 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1093 event
= cpuc
->event_list
[i
];
1096 if (!match_prev_assignment(hwc
, cpuc
, i
))
1097 x86_assign_hw_event(event
, cpuc
, i
);
1098 else if (i
< n_running
)
1101 if (hwc
->state
& PERF_HES_ARCH
)
1104 x86_pmu_start(event
, PERF_EF_RELOAD
);
1107 perf_events_lapic_init();
1113 x86_pmu
.enable_all(added
);
1116 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1119 * Set the next IRQ period, based on the hwc->period_left value.
1120 * To be called with the event disabled in hw:
1122 int x86_perf_event_set_period(struct perf_event
*event
)
1124 struct hw_perf_event
*hwc
= &event
->hw
;
1125 s64 left
= local64_read(&hwc
->period_left
);
1126 s64 period
= hwc
->sample_period
;
1127 int ret
= 0, idx
= hwc
->idx
;
1129 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1133 * If we are way outside a reasonable range then just skip forward:
1135 if (unlikely(left
<= -period
)) {
1137 local64_set(&hwc
->period_left
, left
);
1138 hwc
->last_period
= period
;
1142 if (unlikely(left
<= 0)) {
1144 local64_set(&hwc
->period_left
, left
);
1145 hwc
->last_period
= period
;
1149 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1151 if (unlikely(left
< 2))
1154 if (left
> x86_pmu
.max_period
)
1155 left
= x86_pmu
.max_period
;
1157 if (x86_pmu
.limit_period
)
1158 left
= x86_pmu
.limit_period(event
, left
);
1160 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1162 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1163 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1165 * The hw event starts counting from this event offset,
1166 * mark it to be able to extra future deltas:
1168 local64_set(&hwc
->prev_count
, (u64
)-left
);
1170 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1174 * Due to erratum on certan cpu we need
1175 * a second write to be sure the register
1176 * is updated properly
1178 if (x86_pmu
.perfctr_second_write
) {
1179 wrmsrl(hwc
->event_base
,
1180 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1183 perf_event_update_userpage(event
);
1188 void x86_pmu_enable_event(struct perf_event
*event
)
1190 if (__this_cpu_read(cpu_hw_events
.enabled
))
1191 __x86_pmu_enable_event(&event
->hw
,
1192 ARCH_PERFMON_EVENTSEL_ENABLE
);
1196 * Add a single event to the PMU.
1198 * The event is added to the group of enabled events
1199 * but only if it can be scehduled with existing events.
1201 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1203 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1204 struct hw_perf_event
*hwc
;
1205 int assign
[X86_PMC_IDX_MAX
];
1210 n0
= cpuc
->n_events
;
1211 ret
= n
= collect_events(cpuc
, event
, false);
1215 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1216 if (!(flags
& PERF_EF_START
))
1217 hwc
->state
|= PERF_HES_ARCH
;
1220 * If group events scheduling transaction was started,
1221 * skip the schedulability test here, it will be performed
1222 * at commit time (->commit_txn) as a whole.
1224 * If commit fails, we'll call ->del() on all events
1225 * for which ->add() was called.
1227 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1230 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1234 * copy new assignment, now we know it is possible
1235 * will be used by hw_perf_enable()
1237 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1241 * Commit the collect_events() state. See x86_pmu_del() and
1245 cpuc
->n_added
+= n
- n0
;
1246 cpuc
->n_txn
+= n
- n0
;
1250 * This is before x86_pmu_enable() will call x86_pmu_start(),
1251 * so we enable LBRs before an event needs them etc..
1261 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1263 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1264 int idx
= event
->hw
.idx
;
1266 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1269 if (WARN_ON_ONCE(idx
== -1))
1272 if (flags
& PERF_EF_RELOAD
) {
1273 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1274 x86_perf_event_set_period(event
);
1277 event
->hw
.state
= 0;
1279 cpuc
->events
[idx
] = event
;
1280 __set_bit(idx
, cpuc
->active_mask
);
1281 __set_bit(idx
, cpuc
->running
);
1282 x86_pmu
.enable(event
);
1283 perf_event_update_userpage(event
);
1286 void perf_event_print_debug(void)
1288 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1290 struct cpu_hw_events
*cpuc
;
1291 unsigned long flags
;
1294 if (!x86_pmu
.num_counters
)
1297 local_irq_save(flags
);
1299 cpu
= smp_processor_id();
1300 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1302 if (x86_pmu
.version
>= 2) {
1303 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1304 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1305 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1306 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1309 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1310 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1311 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1312 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1313 if (x86_pmu
.pebs_constraints
) {
1314 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1315 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1317 if (x86_pmu
.lbr_nr
) {
1318 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1319 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1322 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1324 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1325 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1326 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1328 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1330 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1331 cpu
, idx
, pmc_ctrl
);
1332 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1333 cpu
, idx
, pmc_count
);
1334 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1335 cpu
, idx
, prev_left
);
1337 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1338 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1340 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1341 cpu
, idx
, pmc_count
);
1343 local_irq_restore(flags
);
1346 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1348 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1349 struct hw_perf_event
*hwc
= &event
->hw
;
1351 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1352 x86_pmu
.disable(event
);
1353 cpuc
->events
[hwc
->idx
] = NULL
;
1354 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1355 hwc
->state
|= PERF_HES_STOPPED
;
1358 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1360 * Drain the remaining delta count out of a event
1361 * that we are disabling:
1363 x86_perf_event_update(event
);
1364 hwc
->state
|= PERF_HES_UPTODATE
;
1368 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1370 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1374 * event is descheduled
1376 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1379 * If we're called during a txn, we only need to undo x86_pmu.add.
1380 * The events never got scheduled and ->cancel_txn will truncate
1383 * XXX assumes any ->del() called during a TXN will only be on
1384 * an event added during that same TXN.
1386 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1390 * Not a TXN, therefore cleanup properly.
1392 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1394 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1395 if (event
== cpuc
->event_list
[i
])
1399 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1402 /* If we have a newly added event; make sure to decrease n_added. */
1403 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1406 if (x86_pmu
.put_event_constraints
)
1407 x86_pmu
.put_event_constraints(cpuc
, event
);
1409 /* Delete the array entry. */
1410 while (++i
< cpuc
->n_events
) {
1411 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1412 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1416 perf_event_update_userpage(event
);
1421 * This is after x86_pmu_stop(); so we disable LBRs after any
1422 * event can need them etc..
1428 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1430 struct perf_sample_data data
;
1431 struct cpu_hw_events
*cpuc
;
1432 struct perf_event
*event
;
1433 int idx
, handled
= 0;
1436 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1439 * Some chipsets need to unmask the LVTPC in a particular spot
1440 * inside the nmi handler. As a result, the unmasking was pushed
1441 * into all the nmi handlers.
1443 * This generic handler doesn't seem to have any issues where the
1444 * unmasking occurs so it was left at the top.
1446 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1448 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1449 if (!test_bit(idx
, cpuc
->active_mask
)) {
1451 * Though we deactivated the counter some cpus
1452 * might still deliver spurious interrupts still
1453 * in flight. Catch them:
1455 if (__test_and_clear_bit(idx
, cpuc
->running
))
1460 event
= cpuc
->events
[idx
];
1462 val
= x86_perf_event_update(event
);
1463 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1470 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1472 if (!x86_perf_event_set_period(event
))
1475 if (perf_event_overflow(event
, &data
, regs
))
1476 x86_pmu_stop(event
, 0);
1480 inc_irq_stat(apic_perf_irqs
);
1485 void perf_events_lapic_init(void)
1487 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1491 * Always use NMI for PMU
1493 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1497 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1504 * All PMUs/events that share this PMI handler should make sure to
1505 * increment active_events for their events.
1507 if (!atomic_read(&active_events
))
1510 start_clock
= sched_clock();
1511 ret
= x86_pmu
.handle_irq(regs
);
1512 finish_clock
= sched_clock();
1514 perf_sample_event_took(finish_clock
- start_clock
);
1518 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1520 struct event_constraint emptyconstraint
;
1521 struct event_constraint unconstrained
;
1523 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1525 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1528 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1529 cpuc
->kfree_on_online
[i
] = NULL
;
1530 if (x86_pmu
.cpu_prepare
)
1531 return x86_pmu
.cpu_prepare(cpu
);
1535 static int x86_pmu_dead_cpu(unsigned int cpu
)
1537 if (x86_pmu
.cpu_dead
)
1538 x86_pmu
.cpu_dead(cpu
);
1542 static int x86_pmu_online_cpu(unsigned int cpu
)
1544 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1547 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1548 kfree(cpuc
->kfree_on_online
[i
]);
1549 cpuc
->kfree_on_online
[i
] = NULL
;
1554 static int x86_pmu_starting_cpu(unsigned int cpu
)
1556 if (x86_pmu
.cpu_starting
)
1557 x86_pmu
.cpu_starting(cpu
);
1561 static int x86_pmu_dying_cpu(unsigned int cpu
)
1563 if (x86_pmu
.cpu_dying
)
1564 x86_pmu
.cpu_dying(cpu
);
1568 static void __init
pmu_check_apic(void)
1570 if (boot_cpu_has(X86_FEATURE_APIC
))
1574 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1575 pr_info("no hardware sampling interrupt available.\n");
1578 * If we have a PMU initialized but no APIC
1579 * interrupts, we cannot sample hardware
1580 * events (user-space has to fall back and
1581 * sample via a hrtimer based software event):
1583 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1587 static struct attribute_group x86_pmu_format_group
= {
1593 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1594 * out of events_attr attributes.
1596 static void __init
filter_events(struct attribute
**attrs
)
1598 struct device_attribute
*d
;
1599 struct perf_pmu_events_attr
*pmu_attr
;
1603 for (i
= 0; attrs
[i
]; i
++) {
1604 d
= (struct device_attribute
*)attrs
[i
];
1605 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1607 if (pmu_attr
->event_str
)
1609 if (x86_pmu
.event_map(i
+ offset
))
1612 for (j
= i
; attrs
[j
]; j
++)
1613 attrs
[j
] = attrs
[j
+ 1];
1615 /* Check the shifted attr. */
1619 * event_map() is index based, the attrs array is organized
1620 * by increasing event index. If we shift the events, then
1621 * we need to compensate for the event_map(), otherwise
1622 * we are looking up the wrong event in the map
1628 /* Merge two pointer arrays */
1629 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1631 struct attribute
**new;
1634 for (j
= 0; a
[j
]; j
++)
1636 for (i
= 0; b
[i
]; i
++)
1640 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1645 for (i
= 0; a
[i
]; i
++)
1647 for (i
= 0; b
[i
]; i
++)
1654 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1656 struct perf_pmu_events_attr
*pmu_attr
= \
1657 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1658 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1660 /* string trumps id */
1661 if (pmu_attr
->event_str
)
1662 return sprintf(page
, "%s", pmu_attr
->event_str
);
1664 return x86_pmu
.events_sysfs_show(page
, config
);
1666 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1668 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1671 struct perf_pmu_events_ht_attr
*pmu_attr
=
1672 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1675 * Report conditional events depending on Hyper-Threading.
1677 * This is overly conservative as usually the HT special
1678 * handling is not needed if the other CPU thread is idle.
1680 * Note this does not (and cannot) handle the case when thread
1681 * siblings are invisible, for example with virtualization
1682 * if they are owned by some other guest. The user tool
1683 * has to re-read when a thread sibling gets onlined later.
1685 return sprintf(page
, "%s",
1686 topology_max_smt_threads() > 1 ?
1687 pmu_attr
->event_str_ht
:
1688 pmu_attr
->event_str_noht
);
1691 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1692 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1693 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1694 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1695 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1696 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1697 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1698 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1699 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1700 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1702 static struct attribute
*empty_attrs
;
1704 static struct attribute
*events_attr
[] = {
1705 EVENT_PTR(CPU_CYCLES
),
1706 EVENT_PTR(INSTRUCTIONS
),
1707 EVENT_PTR(CACHE_REFERENCES
),
1708 EVENT_PTR(CACHE_MISSES
),
1709 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1710 EVENT_PTR(BRANCH_MISSES
),
1711 EVENT_PTR(BUS_CYCLES
),
1712 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1713 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1714 EVENT_PTR(REF_CPU_CYCLES
),
1718 static struct attribute_group x86_pmu_events_group
= {
1720 .attrs
= events_attr
,
1723 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1725 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1726 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1727 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1728 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1729 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1730 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1734 * We have whole page size to spend and just little data
1735 * to write, so we can safely use sprintf.
1737 ret
= sprintf(page
, "event=0x%02llx", event
);
1740 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1743 ret
+= sprintf(page
+ ret
, ",edge");
1746 ret
+= sprintf(page
+ ret
, ",pc");
1749 ret
+= sprintf(page
+ ret
, ",any");
1752 ret
+= sprintf(page
+ ret
, ",inv");
1755 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1757 ret
+= sprintf(page
+ ret
, "\n");
1762 static struct attribute_group x86_pmu_attr_group
;
1763 static struct attribute_group x86_pmu_caps_group
;
1765 static int __init
init_hw_perf_events(void)
1767 struct x86_pmu_quirk
*quirk
;
1770 pr_info("Performance Events: ");
1772 switch (boot_cpu_data
.x86_vendor
) {
1773 case X86_VENDOR_INTEL
:
1774 err
= intel_pmu_init();
1776 case X86_VENDOR_AMD
:
1777 err
= amd_pmu_init();
1783 pr_cont("no PMU driver, software events only.\n");
1789 /* sanity check that the hardware exists or is emulated */
1790 if (!check_hw_exists())
1793 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1795 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1797 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1800 if (!x86_pmu
.intel_ctrl
)
1801 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1803 perf_events_lapic_init();
1804 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1806 unconstrained
= (struct event_constraint
)
1807 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1808 0, x86_pmu
.num_counters
, 0, 0);
1810 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1812 if (x86_pmu
.caps_attrs
) {
1813 struct attribute
**tmp
;
1815 tmp
= merge_attr(x86_pmu_caps_group
.attrs
, x86_pmu
.caps_attrs
);
1817 x86_pmu_caps_group
.attrs
= tmp
;
1820 if (x86_pmu
.event_attrs
)
1821 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1823 if (!x86_pmu
.events_sysfs_show
)
1824 x86_pmu_events_group
.attrs
= &empty_attrs
;
1826 filter_events(x86_pmu_events_group
.attrs
);
1828 if (x86_pmu
.cpu_events
) {
1829 struct attribute
**tmp
;
1831 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1833 x86_pmu_events_group
.attrs
= tmp
;
1836 if (x86_pmu
.attrs
) {
1837 struct attribute
**tmp
;
1839 tmp
= merge_attr(x86_pmu_attr_group
.attrs
, x86_pmu
.attrs
);
1841 x86_pmu_attr_group
.attrs
= tmp
;
1844 pr_info("... version: %d\n", x86_pmu
.version
);
1845 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1846 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1847 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1848 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1849 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1850 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1853 * Install callbacks. Core will call them for each online
1856 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "perf/x86:prepare",
1857 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1861 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1862 "perf/x86:starting", x86_pmu_starting_cpu
,
1867 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "perf/x86:online",
1868 x86_pmu_online_cpu
, NULL
);
1872 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1879 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1881 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1883 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1886 early_initcall(init_hw_perf_events
);
1888 static inline void x86_pmu_read(struct perf_event
*event
)
1890 x86_perf_event_update(event
);
1894 * Start group events scheduling transaction
1895 * Set the flag to make pmu::enable() not perform the
1896 * schedulability test, it will be performed at commit time
1898 * We only support PERF_PMU_TXN_ADD transactions. Save the
1899 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1902 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1904 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1906 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1908 cpuc
->txn_flags
= txn_flags
;
1909 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1912 perf_pmu_disable(pmu
);
1913 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1917 * Stop group events scheduling transaction
1918 * Clear the flag and pmu::enable() will perform the
1919 * schedulability test.
1921 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1923 unsigned int txn_flags
;
1924 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1926 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1928 txn_flags
= cpuc
->txn_flags
;
1929 cpuc
->txn_flags
= 0;
1930 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1934 * Truncate collected array by the number of events added in this
1935 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1937 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1938 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1939 perf_pmu_enable(pmu
);
1943 * Commit group events scheduling transaction
1944 * Perform the group schedulability test as a whole
1945 * Return 0 if success
1947 * Does not cancel the transaction on failure; expects the caller to do this.
1949 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1951 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1952 int assign
[X86_PMC_IDX_MAX
];
1955 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1957 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1958 cpuc
->txn_flags
= 0;
1964 if (!x86_pmu_initialized())
1967 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1972 * copy new assignment, now we know it is possible
1973 * will be used by hw_perf_enable()
1975 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1977 cpuc
->txn_flags
= 0;
1978 perf_pmu_enable(pmu
);
1982 * a fake_cpuc is used to validate event groups. Due to
1983 * the extra reg logic, we need to also allocate a fake
1984 * per_core and per_cpu structure. Otherwise, group events
1985 * using extra reg may conflict without the kernel being
1986 * able to catch this when the last event gets added to
1989 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1991 kfree(cpuc
->shared_regs
);
1995 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1997 struct cpu_hw_events
*cpuc
;
1998 int cpu
= raw_smp_processor_id();
2000 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
2002 return ERR_PTR(-ENOMEM
);
2004 /* only needed, if we have extra_regs */
2005 if (x86_pmu
.extra_regs
) {
2006 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
2007 if (!cpuc
->shared_regs
)
2013 free_fake_cpuc(cpuc
);
2014 return ERR_PTR(-ENOMEM
);
2018 * validate that we can schedule this event
2020 static int validate_event(struct perf_event
*event
)
2022 struct cpu_hw_events
*fake_cpuc
;
2023 struct event_constraint
*c
;
2026 fake_cpuc
= allocate_fake_cpuc();
2027 if (IS_ERR(fake_cpuc
))
2028 return PTR_ERR(fake_cpuc
);
2030 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
2032 if (!c
|| !c
->weight
)
2035 if (x86_pmu
.put_event_constraints
)
2036 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
2038 free_fake_cpuc(fake_cpuc
);
2044 * validate a single event group
2046 * validation include:
2047 * - check events are compatible which each other
2048 * - events do not compete for the same counter
2049 * - number of events <= number of counters
2051 * validation ensures the group can be loaded onto the
2052 * PMU if it was the only group available.
2054 static int validate_group(struct perf_event
*event
)
2056 struct perf_event
*leader
= event
->group_leader
;
2057 struct cpu_hw_events
*fake_cpuc
;
2058 int ret
= -EINVAL
, n
;
2060 fake_cpuc
= allocate_fake_cpuc();
2061 if (IS_ERR(fake_cpuc
))
2062 return PTR_ERR(fake_cpuc
);
2064 * the event is not yet connected with its
2065 * siblings therefore we must first collect
2066 * existing siblings, then add the new event
2067 * before we can simulate the scheduling
2069 n
= collect_events(fake_cpuc
, leader
, true);
2073 fake_cpuc
->n_events
= n
;
2074 n
= collect_events(fake_cpuc
, event
, false);
2078 fake_cpuc
->n_events
= n
;
2080 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2083 free_fake_cpuc(fake_cpuc
);
2087 static int x86_pmu_event_init(struct perf_event
*event
)
2092 switch (event
->attr
.type
) {
2094 case PERF_TYPE_HARDWARE
:
2095 case PERF_TYPE_HW_CACHE
:
2102 err
= __x86_pmu_event_init(event
);
2105 * we temporarily connect event to its pmu
2106 * such that validate_group() can classify
2107 * it as an x86 event using is_x86_event()
2112 if (event
->group_leader
!= event
)
2113 err
= validate_group(event
);
2115 err
= validate_event(event
);
2121 event
->destroy(event
);
2124 if (READ_ONCE(x86_pmu
.attr_rdpmc
))
2125 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2130 static void refresh_pce(void *ignored
)
2132 load_mm_cr4(this_cpu_read(cpu_tlbstate
.loaded_mm
));
2135 static void x86_pmu_event_mapped(struct perf_event
*event
, struct mm_struct
*mm
)
2137 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2141 * This function relies on not being called concurrently in two
2142 * tasks in the same mm. Otherwise one task could observe
2143 * perf_rdpmc_allowed > 1 and return all the way back to
2144 * userspace with CR4.PCE clear while another task is still
2145 * doing on_each_cpu_mask() to propagate CR4.PCE.
2147 * For now, this can't happen because all callers hold mmap_sem
2148 * for write. If this changes, we'll need a different solution.
2150 lockdep_assert_held_exclusive(&mm
->mmap_sem
);
2152 if (atomic_inc_return(&mm
->context
.perf_rdpmc_allowed
) == 1)
2153 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2156 static void x86_pmu_event_unmapped(struct perf_event
*event
, struct mm_struct
*mm
)
2159 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2162 if (atomic_dec_and_test(&mm
->context
.perf_rdpmc_allowed
))
2163 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2166 static int x86_pmu_event_idx(struct perf_event
*event
)
2168 int idx
= event
->hw
.idx
;
2170 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2173 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2174 idx
-= INTEL_PMC_IDX_FIXED
;
2181 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2182 struct device_attribute
*attr
,
2185 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2188 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2189 struct device_attribute
*attr
,
2190 const char *buf
, size_t count
)
2195 ret
= kstrtoul(buf
, 0, &val
);
2202 if (x86_pmu
.attr_rdpmc_broken
)
2205 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2207 * Changing into or out of always available, aka
2208 * perf-event-bypassing mode. This path is extremely slow,
2209 * but only root can trigger it, so it's okay.
2212 static_key_slow_inc(&rdpmc_always_available
);
2214 static_key_slow_dec(&rdpmc_always_available
);
2215 on_each_cpu(refresh_pce
, NULL
, 1);
2218 x86_pmu
.attr_rdpmc
= val
;
2223 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2225 static struct attribute
*x86_pmu_attrs
[] = {
2226 &dev_attr_rdpmc
.attr
,
2230 static struct attribute_group x86_pmu_attr_group
= {
2231 .attrs
= x86_pmu_attrs
,
2234 static ssize_t
max_precise_show(struct device
*cdev
,
2235 struct device_attribute
*attr
,
2238 return snprintf(buf
, PAGE_SIZE
, "%d\n", x86_pmu_max_precise());
2241 static DEVICE_ATTR_RO(max_precise
);
2243 static struct attribute
*x86_pmu_caps_attrs
[] = {
2244 &dev_attr_max_precise
.attr
,
2248 static struct attribute_group x86_pmu_caps_group
= {
2250 .attrs
= x86_pmu_caps_attrs
,
2253 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2254 &x86_pmu_attr_group
,
2255 &x86_pmu_format_group
,
2256 &x86_pmu_events_group
,
2257 &x86_pmu_caps_group
,
2261 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2263 if (x86_pmu
.sched_task
)
2264 x86_pmu
.sched_task(ctx
, sched_in
);
2267 void perf_check_microcode(void)
2269 if (x86_pmu
.check_microcode
)
2270 x86_pmu
.check_microcode();
2273 static struct pmu pmu
= {
2274 .pmu_enable
= x86_pmu_enable
,
2275 .pmu_disable
= x86_pmu_disable
,
2277 .attr_groups
= x86_pmu_attr_groups
,
2279 .event_init
= x86_pmu_event_init
,
2281 .event_mapped
= x86_pmu_event_mapped
,
2282 .event_unmapped
= x86_pmu_event_unmapped
,
2286 .start
= x86_pmu_start
,
2287 .stop
= x86_pmu_stop
,
2288 .read
= x86_pmu_read
,
2290 .start_txn
= x86_pmu_start_txn
,
2291 .cancel_txn
= x86_pmu_cancel_txn
,
2292 .commit_txn
= x86_pmu_commit_txn
,
2294 .event_idx
= x86_pmu_event_idx
,
2295 .sched_task
= x86_pmu_sched_task
,
2296 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2299 void arch_perf_update_userpage(struct perf_event
*event
,
2300 struct perf_event_mmap_page
*userpg
, u64 now
)
2302 struct cyc2ns_data data
;
2305 userpg
->cap_user_time
= 0;
2306 userpg
->cap_user_time_zero
= 0;
2307 userpg
->cap_user_rdpmc
=
2308 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2309 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2311 if (!using_native_sched_clock() || !sched_clock_stable())
2314 cyc2ns_read_begin(&data
);
2316 offset
= data
.cyc2ns_offset
+ __sched_clock_offset
;
2319 * Internal timekeeping for enabled/running/stopped times
2320 * is always in the local_clock domain.
2322 userpg
->cap_user_time
= 1;
2323 userpg
->time_mult
= data
.cyc2ns_mul
;
2324 userpg
->time_shift
= data
.cyc2ns_shift
;
2325 userpg
->time_offset
= offset
- now
;
2328 * cap_user_time_zero doesn't make sense when we're using a different
2329 * time base for the records.
2331 if (!event
->attr
.use_clockid
) {
2332 userpg
->cap_user_time_zero
= 1;
2333 userpg
->time_zero
= offset
;
2340 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2342 struct unwind_state state
;
2345 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2346 /* TODO: We don't support guest os callchain now */
2350 if (perf_callchain_store(entry
, regs
->ip
))
2353 for (unwind_start(&state
, current
, regs
, NULL
); !unwind_done(&state
);
2354 unwind_next_frame(&state
)) {
2355 addr
= unwind_get_return_address(&state
);
2356 if (!addr
|| perf_callchain_store(entry
, addr
))
2362 valid_user_frame(const void __user
*fp
, unsigned long size
)
2364 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2367 static unsigned long get_segment_base(unsigned int segment
)
2369 struct desc_struct
*desc
;
2370 unsigned int idx
= segment
>> 3;
2372 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2373 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2374 struct ldt_struct
*ldt
;
2376 /* IRQs are off, so this synchronizes with smp_store_release */
2377 ldt
= READ_ONCE(current
->active_mm
->context
.ldt
);
2378 if (!ldt
|| idx
>= ldt
->nr_entries
)
2381 desc
= &ldt
->entries
[idx
];
2386 if (idx
>= GDT_ENTRIES
)
2389 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2392 return get_desc_base(desc
);
2395 #ifdef CONFIG_IA32_EMULATION
2397 #include <asm/compat.h>
2400 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2402 /* 32-bit process in 64-bit kernel. */
2403 unsigned long ss_base
, cs_base
;
2404 struct stack_frame_ia32 frame
;
2405 const void __user
*fp
;
2407 if (!test_thread_flag(TIF_IA32
))
2410 cs_base
= get_segment_base(regs
->cs
);
2411 ss_base
= get_segment_base(regs
->ss
);
2413 fp
= compat_ptr(ss_base
+ regs
->bp
);
2414 pagefault_disable();
2415 while (entry
->nr
< entry
->max_stack
) {
2416 unsigned long bytes
;
2417 frame
.next_frame
= 0;
2418 frame
.return_address
= 0;
2420 if (!valid_user_frame(fp
, sizeof(frame
)))
2423 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2426 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2430 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2431 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2438 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2445 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2447 struct stack_frame frame
;
2448 const unsigned long __user
*fp
;
2450 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2451 /* TODO: We don't support guest os callchain now */
2456 * We don't know what to do with VM86 stacks.. ignore them for now.
2458 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2461 fp
= (unsigned long __user
*)regs
->bp
;
2463 perf_callchain_store(entry
, regs
->ip
);
2468 if (perf_callchain_user32(regs
, entry
))
2471 pagefault_disable();
2472 while (entry
->nr
< entry
->max_stack
) {
2473 unsigned long bytes
;
2475 frame
.next_frame
= NULL
;
2476 frame
.return_address
= 0;
2478 if (!valid_user_frame(fp
, sizeof(frame
)))
2481 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2484 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2488 perf_callchain_store(entry
, frame
.return_address
);
2489 fp
= (void __user
*)frame
.next_frame
;
2495 * Deal with code segment offsets for the various execution modes:
2497 * VM86 - the good olde 16 bit days, where the linear address is
2498 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2500 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2501 * to figure out what the 32bit base address is.
2503 * X32 - has TIF_X32 set, but is running in x86_64
2505 * X86_64 - CS,DS,SS,ES are all zero based.
2507 static unsigned long code_segment_base(struct pt_regs
*regs
)
2510 * For IA32 we look at the GDT/LDT segment base to convert the
2511 * effective IP to a linear address.
2514 #ifdef CONFIG_X86_32
2516 * If we are in VM86 mode, add the segment offset to convert to a
2519 if (regs
->flags
& X86_VM_MASK
)
2520 return 0x10 * regs
->cs
;
2522 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2523 return get_segment_base(regs
->cs
);
2525 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2526 regs
->cs
!= __USER32_CS
)
2527 return get_segment_base(regs
->cs
);
2532 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2534 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2535 return perf_guest_cbs
->get_guest_ip();
2537 return regs
->ip
+ code_segment_base(regs
);
2540 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2544 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2545 if (perf_guest_cbs
->is_user_mode())
2546 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2548 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2550 if (user_mode(regs
))
2551 misc
|= PERF_RECORD_MISC_USER
;
2553 misc
|= PERF_RECORD_MISC_KERNEL
;
2556 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2557 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2562 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2564 cap
->version
= x86_pmu
.version
;
2565 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2566 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2567 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2568 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2569 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2570 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2572 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);