arch/x86/include/asm/desc.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_DESC_H
   3 #define _ASM_X86_DESC_H
   4
   5 #include <asm/desc_defs.h>
   6 #include <asm/ldt.h>
   7 #include <asm/mmu.h>
   8 #include <asm/fixmap.h>
   9 #include <asm/irq_vectors.h>
  10
  11 #include <linux/smp.h>
  12 #include <linux/percpu.h>
  13
  14 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
  15 {
  16         desc->limit0            = info->limit & 0x0ffff;
  17
  18         desc->base0             = (info->base_addr & 0x0000ffff);
  19         desc->base1             = (info->base_addr & 0x00ff0000) >> 16;
  20
  21         desc->type              = (info->read_exec_only ^ 1) << 1;
  22         desc->type             |= info->contents << 2;
  23
  24         desc->s                 = 1;
  25         desc->dpl               = 0x3;
  26         desc->p                 = info->seg_not_present ^ 1;
  27         desc->limit1            = (info->limit & 0xf0000) >> 16;
  28         desc->avl               = info->useable;
  29         desc->d                 = info->seg_32bit;
  30         desc->g                 = info->limit_in_pages;
  31
  32         desc->base2             = (info->base_addr & 0xff000000) >> 24;
  33         /*
  34          * Don't allow setting of the lm bit. It would confuse
  35          * user_64bit_mode and would get overridden by sysret anyway.
  36          */
  37         desc->l                 = 0;
  38 }
  39
  40 extern struct desc_ptr idt_descr;
  41 extern gate_desc idt_table[];
  42 extern const struct desc_ptr debug_idt_descr;
  43 extern gate_desc debug_idt_table[];
  44
  45 struct gdt_page {
  46         struct desc_struct gdt[GDT_ENTRIES];
  47 } __attribute__((aligned(PAGE_SIZE)));
  48
  49 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
  50
  51 /* Provide the original GDT */
  52 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
  53 {
  54         return per_cpu(gdt_page, cpu).gdt;
  55 }
  56
  57 /* Provide the current original GDT */
  58 static inline struct desc_struct *get_current_gdt_rw(void)
  59 {
  60         return this_cpu_ptr(&gdt_page)->gdt;
  61 }
  62
  63 /* Provide the fixmap address of the remapped GDT */
  64 static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
  65 {
  66         return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
  67 }
  68
  69 /* Provide the current read-only GDT */
  70 static inline struct desc_struct *get_current_gdt_ro(void)
  71 {
  72         return get_cpu_gdt_ro(smp_processor_id());
  73 }
  74
  75 /* Provide the physical address of the GDT page. */
  76 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
  77 {
  78         return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
  79 }
  80
  81 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
  82                              unsigned dpl, unsigned ist, unsigned seg)
  83 {
  84         gate->offset_low        = (u16) func;
  85         gate->bits.p            = 1;
  86         gate->bits.dpl          = dpl;
  87         gate->bits.zero         = 0;
  88         gate->bits.type         = type;
  89         gate->offset_middle     = (u16) (func >> 16);
  90 #ifdef CONFIG_X86_64
  91         gate->segment           = __KERNEL_CS;
  92         gate->bits.ist          = ist;
  93         gate->reserved          = 0;
  94         gate->offset_high       = (u32) (func >> 32);
  95 #else
  96         gate->segment           = seg;
  97         gate->bits.ist          = 0;
  98 #endif
  99 }
 100
 101 static inline int desc_empty(const void *ptr)
 102 {
 103         const u32 *desc = ptr;
 104
 105         return !(desc[0] | desc[1]);
 106 }
 107
 108 #ifdef CONFIG_PARAVIRT
 109 #include <asm/paravirt.h>
 110 #else
 111 #define load_TR_desc()                          native_load_tr_desc()
 112 #define load_gdt(dtr)                           native_load_gdt(dtr)
 113 #define load_idt(dtr)                           native_load_idt(dtr)
 114 #define load_tr(tr)                             asm volatile("ltr %0"::"m" (tr))
 115 #define load_ldt(ldt)                           asm volatile("lldt %0"::"m" (ldt))
 116
 117 #define store_gdt(dtr)                          native_store_gdt(dtr)
 118 #define store_tr(tr)                            (tr = native_store_tr())
 119
 120 #define load_TLS(t, cpu)                        native_load_tls(t, cpu)
 121 #define set_ldt                                 native_set_ldt
 122
 123 #define write_ldt_entry(dt, entry, desc)        native_write_ldt_entry(dt, entry, desc)
 124 #define write_gdt_entry(dt, entry, desc, type)  native_write_gdt_entry(dt, entry, desc, type)
 125 #define write_idt_entry(dt, entry, g)           native_write_idt_entry(dt, entry, g)
 126
 127 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 128 {
 129 }
 130
 131 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 132 {
 133 }
 134 #endif  /* CONFIG_PARAVIRT */
 135
 136 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
 137
 138 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
 139 {
 140         memcpy(&idt[entry], gate, sizeof(*gate));
 141 }
 142
 143 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
 144 {
 145         memcpy(&ldt[entry], desc, 8);
 146 }
 147
 148 static inline void
 149 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
 150 {
 151         unsigned int size;
 152
 153         switch (type) {
 154         case DESC_TSS:  size = sizeof(tss_desc);        break;
 155         case DESC_LDT:  size = sizeof(ldt_desc);        break;
 156         default:        size = sizeof(*gdt);            break;
 157         }
 158
 159         memcpy(&gdt[entry], desc, size);
 160 }
 161
 162 static inline void set_tssldt_descriptor(void *d, unsigned long addr,
 163                                          unsigned type, unsigned size)
 164 {
 165         struct ldttss_desc *desc = d;
 166
 167         memset(desc, 0, sizeof(*desc));
 168
 169         desc->limit0            = (u16) size;
 170         desc->base0             = (u16) addr;
 171         desc->base1             = (addr >> 16) & 0xFF;
 172         desc->type              = type;
 173         desc->p                 = 1;
 174         desc->limit1            = (size >> 16) & 0xF;
 175         desc->base2             = (addr >> 24) & 0xFF;
 176 #ifdef CONFIG_X86_64
 177         desc->base3             = (u32) (addr >> 32);
 178 #endif
 179 }
 180
 181 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
 182 {
 183         struct desc_struct *d = get_cpu_gdt_rw(cpu);
 184         tss_desc tss;
 185
 186         set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
 187                               __KERNEL_TSS_LIMIT);
 188         write_gdt_entry(d, entry, &tss, DESC_TSS);
 189 }
 190
 191 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
 192
 193 static inline void native_set_ldt(const void *addr, unsigned int entries)
 194 {
 195         if (likely(entries == 0))
 196                 asm volatile("lldt %w0"::"q" (0));
 197         else {
 198                 unsigned cpu = smp_processor_id();
 199                 ldt_desc ldt;
 200
 201                 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
 202                                       entries * LDT_ENTRY_SIZE - 1);
 203                 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
 204                                 &ldt, DESC_LDT);
 205                 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
 206         }
 207 }
 208
 209 static inline void native_load_gdt(const struct desc_ptr *dtr)
 210 {
 211         asm volatile("lgdt %0"::"m" (*dtr));
 212 }
 213
 214 static inline void native_load_idt(const struct desc_ptr *dtr)
 215 {
 216         asm volatile("lidt %0"::"m" (*dtr));
 217 }
 218
 219 static inline void native_store_gdt(struct desc_ptr *dtr)
 220 {
 221         asm volatile("sgdt %0":"=m" (*dtr));
 222 }
 223
 224 static inline void store_idt(struct desc_ptr *dtr)
 225 {
 226         asm volatile("sidt %0":"=m" (*dtr));
 227 }
 228
 229 /*
 230  * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
 231  * a read-only remapping. To prevent a page fault, the GDT is switched to the
 232  * original writeable version when needed.
 233  */
 234 #ifdef CONFIG_X86_64
 235 static inline void native_load_tr_desc(void)
 236 {
 237         struct desc_ptr gdt;
 238         int cpu = raw_smp_processor_id();
 239         bool restore = 0;
 240         struct desc_struct *fixmap_gdt;
 241
 242         native_store_gdt(&gdt);
 243         fixmap_gdt = get_cpu_gdt_ro(cpu);
 244
 245         /*
 246          * If the current GDT is the read-only fixmap, swap to the original
 247          * writeable version. Swap back at the end.
 248          */
 249         if (gdt.address == (unsigned long)fixmap_gdt) {
 250                 load_direct_gdt(cpu);
 251                 restore = 1;
 252         }
 253         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 254         if (restore)
 255                 load_fixmap_gdt(cpu);
 256 }
 257 #else
 258 static inline void native_load_tr_desc(void)
 259 {
 260         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 261 }
 262 #endif
 263
 264 static inline unsigned long native_store_tr(void)
 265 {
 266         unsigned long tr;
 267
 268         asm volatile("str %0":"=r" (tr));
 269
 270         return tr;
 271 }
 272
 273 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 274 {
 275         struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
 276         unsigned int i;
 277
 278         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
 279                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
 280 }
 281
 282 DECLARE_PER_CPU(bool, __tss_limit_invalid);
 283
 284 static inline void force_reload_TR(void)
 285 {
 286         struct desc_struct *d = get_current_gdt_rw();
 287         tss_desc tss;
 288
 289         memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
 290
 291         /*
 292          * LTR requires an available TSS, and the TSS is currently
 293          * busy.  Make it be available so that LTR will work.
 294          */
 295         tss.type = DESC_TSS;
 296         write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
 297
 298         load_TR_desc();
 299         this_cpu_write(__tss_limit_invalid, false);
 300 }
 301
 302 /*
 303  * Call this if you need the TSS limit to be correct, which should be the case
 304  * if and only if you have TIF_IO_BITMAP set or you're switching to a task
 305  * with TIF_IO_BITMAP set.
 306  */
 307 static inline void refresh_tss_limit(void)
 308 {
 309         DEBUG_LOCKS_WARN_ON(preemptible());
 310
 311         if (unlikely(this_cpu_read(__tss_limit_invalid)))
 312                 force_reload_TR();
 313 }
 314
 315 /*
 316  * If you do something evil that corrupts the cached TSS limit (I'm looking
 317  * at you, VMX exits), call this function.
 318  *
 319  * The optimization here is that the TSS limit only matters for Linux if the
 320  * IO bitmap is in use.  If the TSS limit gets forced to its minimum value,
 321  * everything works except that IO bitmap will be ignored and all CPL 3 IO
 322  * instructions will #GP, which is exactly what we want for normal tasks.
 323  */
 324 static inline void invalidate_tss_limit(void)
 325 {
 326         DEBUG_LOCKS_WARN_ON(preemptible());
 327
 328         if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
 329                 force_reload_TR();
 330         else
 331                 this_cpu_write(__tss_limit_invalid, true);
 332 }
 333
 334 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
 335 #define LDT_empty(info)                                 \
 336         ((info)->base_addr              == 0    &&      \
 337          (info)->limit                  == 0    &&      \
 338          (info)->contents               == 0    &&      \
 339          (info)->read_exec_only         == 1    &&      \
 340          (info)->seg_32bit              == 0    &&      \
 341          (info)->limit_in_pages         == 0    &&      \
 342          (info)->seg_not_present        == 1    &&      \
 343          (info)->useable                == 0)
 344
 345 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
 346 static inline bool LDT_zero(const struct user_desc *info)
 347 {
 348         return (info->base_addr         == 0 &&
 349                 info->limit             == 0 &&
 350                 info->contents          == 0 &&
 351                 info->read_exec_only    == 0 &&
 352                 info->seg_32bit         == 0 &&
 353                 info->limit_in_pages    == 0 &&
 354                 info->seg_not_present   == 0 &&
 355                 info->useable           == 0);
 356 }
 357
 358 static inline void clear_LDT(void)
 359 {
 360         set_ldt(NULL, 0);
 361 }
 362
 363 static inline unsigned long get_desc_base(const struct desc_struct *desc)
 364 {
 365         return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
 366 }
 367
 368 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
 369 {
 370         desc->base0 = base & 0xffff;
 371         desc->base1 = (base >> 16) & 0xff;
 372         desc->base2 = (base >> 24) & 0xff;
 373 }
 374
 375 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 376 {
 377         return desc->limit0 | (desc->limit1 << 16);
 378 }
 379
 380 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
 381 {
 382         desc->limit0 = limit & 0xffff;
 383         desc->limit1 = (limit >> 16) & 0xf;
 384 }
 385
 386 void update_intr_gate(unsigned int n, const void *addr);
 387 void alloc_intr_gate(unsigned int n, const void *addr);
 388
 389 extern unsigned long used_vectors[];
 390
 391 #ifdef CONFIG_X86_64
 392 DECLARE_PER_CPU(u32, debug_idt_ctr);
 393 static inline bool is_debug_idt_enabled(void)
 394 {
 395         if (this_cpu_read(debug_idt_ctr))
 396                 return true;
 397
 398         return false;
 399 }
 400
 401 static inline void load_debug_idt(void)
 402 {
 403         load_idt((const struct desc_ptr *)&debug_idt_descr);
 404 }
 405 #else
 406 static inline bool is_debug_idt_enabled(void)
 407 {
 408         return false;
 409 }
 410
 411 static inline void load_debug_idt(void)
 412 {
 413 }
 414 #endif
 415
 416 /*
 417  * The load_current_idt() must be called with interrupts disabled
 418  * to avoid races. That way the IDT will always be set back to the expected
 419  * descriptor. It's also called when a CPU is being initialized, and
 420  * that doesn't need to disable interrupts, as nothing should be
 421  * bothering the CPU then.
 422  */
 423 static inline void load_current_idt(void)
 424 {
 425         if (is_debug_idt_enabled())
 426                 load_debug_idt();
 427         else
 428                 load_idt((const struct desc_ptr *)&idt_descr);
 429 }
 430
 431 extern void idt_setup_early_handler(void);
 432 extern void idt_setup_early_traps(void);
 433 extern void idt_setup_traps(void);
 434 extern void idt_setup_apic_and_irq_gates(void);
 435
 436 #ifdef CONFIG_X86_64
 437 extern void idt_setup_early_pf(void);
 438 extern void idt_setup_ist_traps(void);
 439 extern void idt_setup_debugidt_traps(void);
 440 #else
 441 static inline void idt_setup_early_pf(void) { }
 442 static inline void idt_setup_ist_traps(void) { }
 443 static inline void idt_setup_debugidt_traps(void) { }
 444 #endif
 445
 446 extern void idt_invalidate(void *addr);
 447
 448 #endif /* _ASM_X86_DESC_H */