arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13
  14 #include <asm/apic.h>
  15 #include <asm/io_apic.h>
  16 #include <asm/irq.h>
  17 #include <asm/idle.h>
  18 #include <asm/mce.h>
  19 #include <asm/hw_irq.h>
  20 #include <asm/trace/irq_vectors.h>
  21
  22 atomic_t irq_err_count;
  23
  24 /* Function pointer for generic interrupt vector handling */
  25 void (*x86_platform_ipi_callback)(void) = NULL;
  26
  27 /*
  28  * 'what should we do if we get a hw irq event on an illegal vector'.
  29  * each architecture has to answer this themselves.
  30  */
  31 void ack_bad_irq(unsigned int irq)
  32 {
  33         if (printk_ratelimit())
  34                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  35
  36         /*
  37          * Currently unexpected vectors happen only on SMP and APIC.
  38          * We _must_ ack these because every local APIC has only N
  39          * irq slots per priority level, and a 'hanging, unacked' IRQ
  40          * holds up an irq slot - in excessive cases (when multiple
  41          * unexpected vectors occur) that might lock up the APIC
  42          * completely.
  43          * But only ack when the APIC is enabled -AK
  44          */
  45         ack_APIC_irq();
  46 }
  47
  48 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  49 /*
  50  * /proc/interrupts printing for arch specific interrupts
  51  */
  52 int arch_show_interrupts(struct seq_file *p, int prec)
  53 {
  54         int j;
  55
  56         seq_printf(p, "%*s: ", prec, "NMI");
  57         for_each_online_cpu(j)
  58                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  59         seq_printf(p, "  Non-maskable interrupts\n");
  60 #ifdef CONFIG_X86_LOCAL_APIC
  61         seq_printf(p, "%*s: ", prec, "LOC");
  62         for_each_online_cpu(j)
  63                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  64         seq_printf(p, "  Local timer interrupts\n");
  65
  66         seq_printf(p, "%*s: ", prec, "SPU");
  67         for_each_online_cpu(j)
  68                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  69         seq_printf(p, "  Spurious interrupts\n");
  70         seq_printf(p, "%*s: ", prec, "PMI");
  71         for_each_online_cpu(j)
  72                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  73         seq_printf(p, "  Performance monitoring interrupts\n");
  74         seq_printf(p, "%*s: ", prec, "IWI");
  75         for_each_online_cpu(j)
  76                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  77         seq_printf(p, "  IRQ work interrupts\n");
  78         seq_printf(p, "%*s: ", prec, "RTR");
  79         for_each_online_cpu(j)
  80                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  81         seq_printf(p, "  APIC ICR read retries\n");
  82 #endif
  83         if (x86_platform_ipi_callback) {
  84                 seq_printf(p, "%*s: ", prec, "PLT");
  85                 for_each_online_cpu(j)
  86                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  87                 seq_printf(p, "  Platform interrupts\n");
  88         }
  89 #ifdef CONFIG_SMP
  90         seq_printf(p, "%*s: ", prec, "RES");
  91         for_each_online_cpu(j)
  92                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
  93         seq_printf(p, "  Rescheduling interrupts\n");
  94         seq_printf(p, "%*s: ", prec, "CAL");
  95         for_each_online_cpu(j)
  96                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
  97                                         irq_stats(j)->irq_tlb_count);
  98         seq_printf(p, "  Function call interrupts\n");
  99         seq_printf(p, "%*s: ", prec, "TLB");
 100         for_each_online_cpu(j)
 101                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 102         seq_printf(p, "  TLB shootdowns\n");
 103 #endif
 104 #ifdef CONFIG_X86_THERMAL_VECTOR
 105         seq_printf(p, "%*s: ", prec, "TRM");
 106         for_each_online_cpu(j)
 107                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 108         seq_printf(p, "  Thermal event interrupts\n");
 109 #endif
 110 #ifdef CONFIG_X86_MCE_THRESHOLD
 111         seq_printf(p, "%*s: ", prec, "THR");
 112         for_each_online_cpu(j)
 113                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 114         seq_printf(p, "  Threshold APIC interrupts\n");
 115 #endif
 116 #ifdef CONFIG_X86_MCE
 117         seq_printf(p, "%*s: ", prec, "MCE");
 118         for_each_online_cpu(j)
 119                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 120         seq_printf(p, "  Machine check exceptions\n");
 121         seq_printf(p, "%*s: ", prec, "MCP");
 122         for_each_online_cpu(j)
 123                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 124         seq_printf(p, "  Machine check polls\n");
 125 #endif
 126         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 127 #if defined(CONFIG_X86_IO_APIC)
 128         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 129 #endif
 130         return 0;
 131 }
 132
 133 /*
 134  * /proc/stat helpers
 135  */
 136 u64 arch_irq_stat_cpu(unsigned int cpu)
 137 {
 138         u64 sum = irq_stats(cpu)->__nmi_count;
 139
 140 #ifdef CONFIG_X86_LOCAL_APIC
 141         sum += irq_stats(cpu)->apic_timer_irqs;
 142         sum += irq_stats(cpu)->irq_spurious_count;
 143         sum += irq_stats(cpu)->apic_perf_irqs;
 144         sum += irq_stats(cpu)->apic_irq_work_irqs;
 145         sum += irq_stats(cpu)->icr_read_retry_count;
 146 #endif
 147         if (x86_platform_ipi_callback)
 148                 sum += irq_stats(cpu)->x86_platform_ipis;
 149 #ifdef CONFIG_SMP
 150         sum += irq_stats(cpu)->irq_resched_count;
 151         sum += irq_stats(cpu)->irq_call_count;
 152 #endif
 153 #ifdef CONFIG_X86_THERMAL_VECTOR
 154         sum += irq_stats(cpu)->irq_thermal_count;
 155 #endif
 156 #ifdef CONFIG_X86_MCE_THRESHOLD
 157         sum += irq_stats(cpu)->irq_threshold_count;
 158 #endif
 159 #ifdef CONFIG_X86_MCE
 160         sum += per_cpu(mce_exception_count, cpu);
 161         sum += per_cpu(mce_poll_count, cpu);
 162 #endif
 163         return sum;
 164 }
 165
 166 u64 arch_irq_stat(void)
 167 {
 168         u64 sum = atomic_read(&irq_err_count);
 169         return sum;
 170 }
 171
 172
 173 /*
 174  * do_IRQ handles all normal device IRQ's (the special
 175  * SMP cross-CPU interrupts have their own specific
 176  * handlers).
 177  */
 178 unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 179 {
 180         struct pt_regs *old_regs = set_irq_regs(regs);
 181
 182         /* high bit used in ret_from_ code  */
 183         unsigned vector = ~regs->orig_ax;
 184         unsigned irq;
 185
 186         irq_enter();
 187         exit_idle();
 188
 189         irq = __this_cpu_read(vector_irq[vector]);
 190
 191         if (!handle_irq(irq, regs)) {
 192                 ack_APIC_irq();
 193
 194                 if (printk_ratelimit())
 195                         pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
 196                                 __func__, smp_processor_id(), vector, irq);
 197         }
 198
 199         irq_exit();
 200
 201         set_irq_regs(old_regs);
 202         return 1;
 203 }
 204
 205 /*
 206  * Handler for X86_PLATFORM_IPI_VECTOR.
 207  */
 208 void __smp_x86_platform_ipi(void)
 209 {
 210         inc_irq_stat(x86_platform_ipis);
 211
 212         if (x86_platform_ipi_callback)
 213                 x86_platform_ipi_callback();
 214 }
 215
 216 void smp_x86_platform_ipi(struct pt_regs *regs)
 217 {
 218         struct pt_regs *old_regs = set_irq_regs(regs);
 219
 220         entering_ack_irq();
 221         __smp_x86_platform_ipi();
 222         exiting_irq();
 223         set_irq_regs(old_regs);
 224 }
 225
 226 #ifdef CONFIG_HAVE_KVM
 227 /*
 228  * Handler for POSTED_INTERRUPT_VECTOR.
 229  */
 230 void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 231 {
 232         struct pt_regs *old_regs = set_irq_regs(regs);
 233
 234         ack_APIC_irq();
 235
 236         irq_enter();
 237
 238         exit_idle();
 239
 240         inc_irq_stat(kvm_posted_intr_ipis);
 241
 242         irq_exit();
 243
 244         set_irq_regs(old_regs);
 245 }
 246 #endif
 247
 248 void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 249 {
 250         struct pt_regs *old_regs = set_irq_regs(regs);
 251
 252         entering_ack_irq();
 253         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 254         __smp_x86_platform_ipi();
 255         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 256         exiting_irq();
 257         set_irq_regs(old_regs);
 258 }
 259
 260 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 261
 262 #ifdef CONFIG_HOTPLUG_CPU
 263 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 264 void fixup_irqs(void)
 265 {
 266         unsigned int irq, vector;
 267         static int warned;
 268         struct irq_desc *desc;
 269         struct irq_data *data;
 270         struct irq_chip *chip;
 271
 272         for_each_irq_desc(irq, desc) {
 273                 int break_affinity = 0;
 274                 int set_affinity = 1;
 275                 const struct cpumask *affinity;
 276
 277                 if (!desc)
 278                         continue;
 279                 if (irq == 2)
 280                         continue;
 281
 282                 /* interrupt's are disabled at this point */
 283                 raw_spin_lock(&desc->lock);
 284
 285                 data = irq_desc_get_irq_data(desc);
 286                 affinity = data->affinity;
 287                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 288                     cpumask_subset(affinity, cpu_online_mask)) {
 289                         raw_spin_unlock(&desc->lock);
 290                         continue;
 291                 }
 292
 293                 /*
 294                  * Complete the irq move. This cpu is going down and for
 295                  * non intr-remapping case, we can't wait till this interrupt
 296                  * arrives at this cpu before completing the irq move.
 297                  */
 298                 irq_force_complete_move(irq);
 299
 300                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 301                         break_affinity = 1;
 302                         affinity = cpu_online_mask;
 303                 }
 304
 305                 chip = irq_data_get_irq_chip(data);
 306                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 307                         chip->irq_mask(data);
 308
 309                 if (chip->irq_set_affinity)
 310                         chip->irq_set_affinity(data, affinity, true);
 311                 else if (!(warned++))
 312                         set_affinity = 0;
 313
 314                 /*
 315                  * We unmask if the irq was not marked masked by the
 316                  * core code. That respects the lazy irq disable
 317                  * behaviour.
 318                  */
 319                 if (!irqd_can_move_in_process_context(data) &&
 320                     !irqd_irq_masked(data) && chip->irq_unmask)
 321                         chip->irq_unmask(data);
 322
 323                 raw_spin_unlock(&desc->lock);
 324
 325                 if (break_affinity && set_affinity)
 326                         pr_notice("Broke affinity for irq %i\n", irq);
 327                 else if (!set_affinity)
 328                         pr_notice("Cannot set affinity for irq %i\n", irq);
 329         }
 330
 331         /*
 332          * We can remove mdelay() and then send spuriuous interrupts to
 333          * new cpu targets for all the irqs that were handled previously by
 334          * this cpu. While it works, I have seen spurious interrupt messages
 335          * (nothing wrong but still...).
 336          *
 337          * So for now, retain mdelay(1) and check the IRR and then send those
 338          * interrupts to new targets as this cpu is already offlined...
 339          */
 340         mdelay(1);
 341
 342         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 343                 unsigned int irr;
 344
 345                 if (__this_cpu_read(vector_irq[vector]) < 0)
 346                         continue;
 347
 348                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 349                 if (irr  & (1 << (vector % 32))) {
 350                         irq = __this_cpu_read(vector_irq[vector]);
 351
 352                         desc = irq_to_desc(irq);
 353                         data = irq_desc_get_irq_data(desc);
 354                         chip = irq_data_get_irq_chip(data);
 355                         raw_spin_lock(&desc->lock);
 356                         if (chip->irq_retrigger)
 357                                 chip->irq_retrigger(data);
 358                         raw_spin_unlock(&desc->lock);
 359                 }
 360                 __this_cpu_write(vector_irq[vector], -1);
 361         }
 362 }
 363 #endif