2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/microcode.h>
49 #include <asm/spec-ctrl.h>
51 #include <asm/virtext.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id svm_cpu_id
[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
63 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
65 #define IOPM_ALLOC_ORDER 2
66 #define MSRPM_ALLOC_ORDER 1
68 #define SEG_TYPE_LDT 2
69 #define SEG_TYPE_BUSY_TSS16 3
71 #define SVM_FEATURE_NPT (1 << 0)
72 #define SVM_FEATURE_LBRV (1 << 1)
73 #define SVM_FEATURE_SVML (1 << 2)
74 #define SVM_FEATURE_NRIP (1 << 3)
75 #define SVM_FEATURE_TSC_RATE (1 << 4)
76 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
77 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
78 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
79 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
81 #define SVM_AVIC_DOORBELL 0xc001011b
83 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
84 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
85 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
87 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
89 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
90 #define TSC_RATIO_MIN 0x0000000000000001ULL
91 #define TSC_RATIO_MAX 0x000000ffffffffffULL
93 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
96 * 0xff is broadcast, so the max index allowed for physical APIC ID
97 * table is 0xfe. APIC IDs above 0xff are reserved.
99 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
101 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
102 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
103 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
105 /* AVIC GATAG is encoded using VM and VCPU IDs */
106 #define AVIC_VCPU_ID_BITS 8
107 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
109 #define AVIC_VM_ID_BITS 24
110 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
111 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
113 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
114 (y & AVIC_VCPU_ID_MASK))
115 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
116 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
118 static bool erratum_383_found __read_mostly
;
120 static const u32 host_save_user_msrs
[] = {
122 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
125 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
129 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
133 struct nested_state
{
139 /* These are the merged vectors */
142 /* gpa pointers to the real vectors */
146 /* A VMEXIT is required but not yet emulated */
149 /* cache for intercepts of the guest */
152 u32 intercept_exceptions
;
155 /* Nested Paging related state */
159 #define MSRPM_OFFSETS 16
160 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
163 * Set osvw_len to higher value when updated Revision Guides
164 * are published and we know what the new status bits are
166 static uint64_t osvw_len
= 4, osvw_status
;
169 struct kvm_vcpu vcpu
;
171 unsigned long vmcb_pa
;
172 struct svm_cpu_data
*svm_data
;
173 uint64_t asid_generation
;
174 uint64_t sysenter_esp
;
175 uint64_t sysenter_eip
;
180 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
190 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
191 * translated into the appropriate L2_CFG bits on the host to
192 * perform speculative control.
200 struct nested_state nested
;
203 u64 nmi_singlestep_guest_rflags
;
205 unsigned int3_injected
;
206 unsigned long int3_rip
;
208 /* cached guest cpuid flags for faster access */
209 bool nrips_enabled
: 1;
212 struct page
*avic_backing_page
;
213 u64
*avic_physical_id_cache
;
214 bool avic_is_running
;
217 * Per-vcpu list of struct amd_svm_iommu_ir:
218 * This is used mainly to store interrupt remapping information used
219 * when update the vcpu affinity. This avoids the need to scan for
220 * IRTE and try to match ga_tag in the IOMMU driver.
222 struct list_head ir_list
;
223 spinlock_t ir_list_lock
;
227 * This is a wrapper of struct amd_iommu_ir_data.
229 struct amd_svm_iommu_ir
{
230 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
231 void *data
; /* Storing pointer to struct amd_ir_data */
234 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
235 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
237 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
238 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
239 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
240 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
242 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
243 #define TSC_RATIO_DEFAULT 0x0100000000ULL
245 #define MSR_INVALID 0xffffffffU
247 static const struct svm_direct_access_msrs
{
248 u32 index
; /* Index of the MSR */
249 bool always
; /* True if intercept is always on */
250 } direct_access_msrs
[] = {
251 { .index
= MSR_STAR
, .always
= true },
252 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
254 { .index
= MSR_GS_BASE
, .always
= true },
255 { .index
= MSR_FS_BASE
, .always
= true },
256 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
257 { .index
= MSR_LSTAR
, .always
= true },
258 { .index
= MSR_CSTAR
, .always
= true },
259 { .index
= MSR_SYSCALL_MASK
, .always
= true },
261 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
262 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
263 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
264 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
265 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
266 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
267 { .index
= MSR_INVALID
, .always
= false },
270 /* enable NPT for AMD64 and X86 with PAE */
271 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
272 static bool npt_enabled
= true;
274 static bool npt_enabled
;
277 /* allow nested paging (virtualized MMU) for all guests */
278 static int npt
= true;
279 module_param(npt
, int, S_IRUGO
);
281 /* allow nested virtualization in KVM/SVM */
282 static int nested
= true;
283 module_param(nested
, int, S_IRUGO
);
285 /* enable / disable AVIC */
287 #ifdef CONFIG_X86_LOCAL_APIC
288 module_param(avic
, int, S_IRUGO
);
291 /* enable/disable Virtual VMLOAD VMSAVE */
292 static int vls
= true;
293 module_param(vls
, int, 0444);
295 /* enable/disable Virtual GIF */
296 static int vgif
= true;
297 module_param(vgif
, int, 0444);
299 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
300 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
301 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
303 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
304 static int nested_svm_intercept(struct vcpu_svm
*svm
);
305 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
306 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
307 bool has_error_code
, u32 error_code
);
310 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
311 pause filter count */
312 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
313 VMCB_ASID
, /* ASID */
314 VMCB_INTR
, /* int_ctl, int_vector */
315 VMCB_NPT
, /* npt_en, nCR3, gPAT */
316 VMCB_CR
, /* CR0, CR3, CR4, EFER */
317 VMCB_DR
, /* DR6, DR7 */
318 VMCB_DT
, /* GDT, IDT */
319 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
320 VMCB_CR2
, /* CR2 only */
321 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
322 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
323 * AVIC PHYSICAL_TABLE pointer,
324 * AVIC LOGICAL_TABLE pointer
329 /* TPR and CR2 are always written before VMRUN */
330 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
332 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
334 static inline void mark_all_dirty(struct vmcb
*vmcb
)
336 vmcb
->control
.clean
= 0;
339 static inline void mark_all_clean(struct vmcb
*vmcb
)
341 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
342 & ~VMCB_ALWAYS_DIRTY_MASK
;
345 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
347 vmcb
->control
.clean
&= ~(1 << bit
);
350 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
352 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
355 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
357 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
358 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
361 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
363 struct vcpu_svm
*svm
= to_svm(vcpu
);
364 u64
*entry
= svm
->avic_physical_id_cache
;
369 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
372 static void recalc_intercepts(struct vcpu_svm
*svm
)
374 struct vmcb_control_area
*c
, *h
;
375 struct nested_state
*g
;
377 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
379 if (!is_guest_mode(&svm
->vcpu
))
382 c
= &svm
->vmcb
->control
;
383 h
= &svm
->nested
.hsave
->control
;
386 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
387 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
388 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
389 c
->intercept
= h
->intercept
| g
->intercept
;
392 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
394 if (is_guest_mode(&svm
->vcpu
))
395 return svm
->nested
.hsave
;
400 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
402 struct vmcb
*vmcb
= get_host_vmcb(svm
);
404 vmcb
->control
.intercept_cr
|= (1U << bit
);
406 recalc_intercepts(svm
);
409 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
411 struct vmcb
*vmcb
= get_host_vmcb(svm
);
413 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
415 recalc_intercepts(svm
);
418 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
420 struct vmcb
*vmcb
= get_host_vmcb(svm
);
422 return vmcb
->control
.intercept_cr
& (1U << bit
);
425 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
427 struct vmcb
*vmcb
= get_host_vmcb(svm
);
429 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
430 | (1 << INTERCEPT_DR1_READ
)
431 | (1 << INTERCEPT_DR2_READ
)
432 | (1 << INTERCEPT_DR3_READ
)
433 | (1 << INTERCEPT_DR4_READ
)
434 | (1 << INTERCEPT_DR5_READ
)
435 | (1 << INTERCEPT_DR6_READ
)
436 | (1 << INTERCEPT_DR7_READ
)
437 | (1 << INTERCEPT_DR0_WRITE
)
438 | (1 << INTERCEPT_DR1_WRITE
)
439 | (1 << INTERCEPT_DR2_WRITE
)
440 | (1 << INTERCEPT_DR3_WRITE
)
441 | (1 << INTERCEPT_DR4_WRITE
)
442 | (1 << INTERCEPT_DR5_WRITE
)
443 | (1 << INTERCEPT_DR6_WRITE
)
444 | (1 << INTERCEPT_DR7_WRITE
);
446 recalc_intercepts(svm
);
449 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
451 struct vmcb
*vmcb
= get_host_vmcb(svm
);
453 vmcb
->control
.intercept_dr
= 0;
455 recalc_intercepts(svm
);
458 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
460 struct vmcb
*vmcb
= get_host_vmcb(svm
);
462 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
464 recalc_intercepts(svm
);
467 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
469 struct vmcb
*vmcb
= get_host_vmcb(svm
);
471 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
473 recalc_intercepts(svm
);
476 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
478 struct vmcb
*vmcb
= get_host_vmcb(svm
);
480 vmcb
->control
.intercept
|= (1ULL << bit
);
482 recalc_intercepts(svm
);
485 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
487 struct vmcb
*vmcb
= get_host_vmcb(svm
);
489 vmcb
->control
.intercept
&= ~(1ULL << bit
);
491 recalc_intercepts(svm
);
494 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
496 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
499 static inline void enable_gif(struct vcpu_svm
*svm
)
501 if (vgif_enabled(svm
))
502 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
504 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
507 static inline void disable_gif(struct vcpu_svm
*svm
)
509 if (vgif_enabled(svm
))
510 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
512 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
515 static inline bool gif_set(struct vcpu_svm
*svm
)
517 if (vgif_enabled(svm
))
518 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
520 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
523 static unsigned long iopm_base
;
525 struct kvm_ldttss_desc
{
528 unsigned base1
:8, type
:5, dpl
:2, p
:1;
529 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
532 } __attribute__((packed
));
534 struct svm_cpu_data
{
540 struct kvm_ldttss_desc
*tss_desc
;
542 struct page
*save_area
;
543 struct vmcb
*current_vmcb
;
546 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
548 struct svm_init_data
{
553 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
555 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
556 #define MSRS_RANGE_SIZE 2048
557 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
559 static u32
svm_msrpm_offset(u32 msr
)
564 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
565 if (msr
< msrpm_ranges
[i
] ||
566 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
569 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
570 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
572 /* Now we have the u8 offset - but need the u32 offset */
576 /* MSR not in any range */
580 #define MAX_INST_SIZE 15
582 static inline void clgi(void)
584 asm volatile (__ex(SVM_CLGI
));
587 static inline void stgi(void)
589 asm volatile (__ex(SVM_STGI
));
592 static inline void invlpga(unsigned long addr
, u32 asid
)
594 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
597 static int get_npt_level(struct kvm_vcpu
*vcpu
)
600 return PT64_ROOT_4LEVEL
;
602 return PT32E_ROOT_LEVEL
;
606 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
608 vcpu
->arch
.efer
= efer
;
609 if (!npt_enabled
&& !(efer
& EFER_LMA
))
612 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
613 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
616 static int is_external_interrupt(u32 info
)
618 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
619 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
622 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
624 struct vcpu_svm
*svm
= to_svm(vcpu
);
627 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
628 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
632 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
634 struct vcpu_svm
*svm
= to_svm(vcpu
);
637 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
639 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
643 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
645 struct vcpu_svm
*svm
= to_svm(vcpu
);
647 if (svm
->vmcb
->control
.next_rip
!= 0) {
648 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
649 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
652 if (!svm
->next_rip
) {
653 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
655 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
658 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
659 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
660 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
662 kvm_rip_write(vcpu
, svm
->next_rip
);
663 svm_set_interrupt_shadow(vcpu
, 0);
666 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
668 struct vcpu_svm
*svm
= to_svm(vcpu
);
669 unsigned nr
= vcpu
->arch
.exception
.nr
;
670 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
671 bool reinject
= vcpu
->arch
.exception
.injected
;
672 u32 error_code
= vcpu
->arch
.exception
.error_code
;
675 * If we are within a nested VM we'd better #VMEXIT and let the guest
676 * handle the exception
679 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
682 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
683 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
686 * For guest debugging where we have to reinject #BP if some
687 * INT3 is guest-owned:
688 * Emulate nRIP by moving RIP forward. Will fail if injection
689 * raises a fault that is not intercepted. Still better than
690 * failing in all cases.
692 skip_emulated_instruction(&svm
->vcpu
);
693 rip
= kvm_rip_read(&svm
->vcpu
);
694 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
695 svm
->int3_injected
= rip
- old_rip
;
698 svm
->vmcb
->control
.event_inj
= nr
700 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
701 | SVM_EVTINJ_TYPE_EXEPT
;
702 svm
->vmcb
->control
.event_inj_err
= error_code
;
705 static void svm_init_erratum_383(void)
711 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
714 /* Use _safe variants to not break nested virtualization */
715 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
721 low
= lower_32_bits(val
);
722 high
= upper_32_bits(val
);
724 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
726 erratum_383_found
= true;
729 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
732 * Guests should see errata 400 and 415 as fixed (assuming that
733 * HLT and IO instructions are intercepted).
735 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
736 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
739 * By increasing VCPU's osvw.length to 3 we are telling the guest that
740 * all osvw.status bits inside that length, including bit 0 (which is
741 * reserved for erratum 298), are valid. However, if host processor's
742 * osvw_len is 0 then osvw_status[0] carries no information. We need to
743 * be conservative here and therefore we tell the guest that erratum 298
744 * is present (because we really don't know).
746 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
747 vcpu
->arch
.osvw
.status
|= 1;
750 static int has_svm(void)
754 if (!cpu_has_svm(&msg
)) {
755 printk(KERN_INFO
"has_svm: %s\n", msg
);
762 static void svm_hardware_disable(void)
764 /* Make sure we clean up behind us */
765 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
766 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
770 amd_pmu_disable_virt();
773 static int svm_hardware_enable(void)
776 struct svm_cpu_data
*sd
;
778 struct desc_struct
*gdt
;
779 int me
= raw_smp_processor_id();
781 rdmsrl(MSR_EFER
, efer
);
782 if (efer
& EFER_SVME
)
786 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
789 sd
= per_cpu(svm_data
, me
);
791 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
795 sd
->asid_generation
= 1;
796 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
797 sd
->next_asid
= sd
->max_asid
+ 1;
799 gdt
= get_current_gdt_rw();
800 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
802 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
804 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
806 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
807 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
808 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
815 * Note that it is possible to have a system with mixed processor
816 * revisions and therefore different OSVW bits. If bits are not the same
817 * on different processors then choose the worst case (i.e. if erratum
818 * is present on one processor and not on another then assume that the
819 * erratum is present everywhere).
821 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
822 uint64_t len
, status
= 0;
825 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
827 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
831 osvw_status
= osvw_len
= 0;
835 osvw_status
|= status
;
836 osvw_status
&= (1ULL << osvw_len
) - 1;
839 osvw_status
= osvw_len
= 0;
841 svm_init_erratum_383();
843 amd_pmu_enable_virt();
848 static void svm_cpu_uninit(int cpu
)
850 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
855 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
856 __free_page(sd
->save_area
);
860 static int svm_cpu_init(int cpu
)
862 struct svm_cpu_data
*sd
;
865 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
869 sd
->save_area
= alloc_page(GFP_KERNEL
);
874 per_cpu(svm_data
, cpu
) = sd
;
884 static bool valid_msr_intercept(u32 index
)
888 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
889 if (direct_access_msrs
[i
].index
== index
)
895 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, unsigned msr
)
902 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
905 offset
= svm_msrpm_offset(msr
);
906 bit_write
= 2 * (msr
& 0x0f) + 1;
909 BUG_ON(offset
== MSR_INVALID
);
911 return !!test_bit(bit_write
, &tmp
);
914 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
917 u8 bit_read
, bit_write
;
922 * If this warning triggers extend the direct_access_msrs list at the
923 * beginning of the file
925 WARN_ON(!valid_msr_intercept(msr
));
927 offset
= svm_msrpm_offset(msr
);
928 bit_read
= 2 * (msr
& 0x0f);
929 bit_write
= 2 * (msr
& 0x0f) + 1;
932 BUG_ON(offset
== MSR_INVALID
);
934 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
935 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
940 static void svm_vcpu_init_msrpm(u32
*msrpm
)
944 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
946 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
947 if (!direct_access_msrs
[i
].always
)
950 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
954 static void add_msr_offset(u32 offset
)
958 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
960 /* Offset already in list? */
961 if (msrpm_offsets
[i
] == offset
)
964 /* Slot used by another offset? */
965 if (msrpm_offsets
[i
] != MSR_INVALID
)
968 /* Add offset to list */
969 msrpm_offsets
[i
] = offset
;
975 * If this BUG triggers the msrpm_offsets table has an overflow. Just
976 * increase MSRPM_OFFSETS in this case.
981 static void init_msrpm_offsets(void)
985 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
987 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
990 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
991 BUG_ON(offset
== MSR_INVALID
);
993 add_msr_offset(offset
);
997 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
999 u32
*msrpm
= svm
->msrpm
;
1001 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
1002 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
1003 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
1004 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
1005 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
1008 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
1010 u32
*msrpm
= svm
->msrpm
;
1012 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
1013 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
1014 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
1015 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
1016 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
1019 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
1021 svm
->nmi_singlestep
= false;
1023 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
1024 /* Clear our flags if they were not set by the guest */
1025 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1026 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
1027 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1028 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1033 * This hash table is used to map VM_ID to a struct kvm_arch,
1034 * when handling AMD IOMMU GALOG notification to schedule in
1035 * a particular vCPU.
1037 #define SVM_VM_DATA_HASH_BITS 8
1038 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1039 static u32 next_vm_id
= 0;
1040 static bool next_vm_id_wrapped
= 0;
1041 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1044 * This function is called from IOMMU driver to notify
1045 * SVM to schedule in a particular vCPU of a particular VM.
1047 static int avic_ga_log_notifier(u32 ga_tag
)
1049 unsigned long flags
;
1050 struct kvm_arch
*ka
= NULL
;
1051 struct kvm_vcpu
*vcpu
= NULL
;
1052 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1053 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1055 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1057 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1058 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
1059 struct kvm
*kvm
= container_of(ka
, struct kvm
, arch
);
1060 struct kvm_arch
*vm_data
= &kvm
->arch
;
1062 if (vm_data
->avic_vm_id
!= vm_id
)
1064 vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
1067 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1070 * At this point, the IOMMU should have already set the pending
1071 * bit in the vAPIC backing page. So, we just need to schedule
1075 kvm_vcpu_wake_up(vcpu
);
1080 static __init
int svm_hardware_setup(void)
1083 struct page
*iopm_pages
;
1087 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1092 iopm_va
= page_address(iopm_pages
);
1093 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1094 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1096 init_msrpm_offsets();
1098 if (boot_cpu_has(X86_FEATURE_NX
))
1099 kvm_enable_efer_bits(EFER_NX
);
1101 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1102 kvm_enable_efer_bits(EFER_FFXSR
);
1104 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1105 kvm_has_tsc_control
= true;
1106 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1107 kvm_tsc_scaling_ratio_frac_bits
= 32;
1111 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1112 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1115 for_each_possible_cpu(cpu
) {
1116 r
= svm_cpu_init(cpu
);
1121 if (!boot_cpu_has(X86_FEATURE_NPT
))
1122 npt_enabled
= false;
1124 if (npt_enabled
&& !npt
) {
1125 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1126 npt_enabled
= false;
1130 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1137 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1138 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1141 pr_info("AVIC enabled\n");
1143 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1149 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1150 !IS_ENABLED(CONFIG_X86_64
)) {
1153 pr_info("Virtual VMLOAD VMSAVE supported\n");
1158 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1161 pr_info("Virtual GIF supported\n");
1167 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1172 static __exit
void svm_hardware_unsetup(void)
1176 for_each_possible_cpu(cpu
)
1177 svm_cpu_uninit(cpu
);
1179 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1183 static void init_seg(struct vmcb_seg
*seg
)
1186 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1187 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1188 seg
->limit
= 0xffff;
1192 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1195 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1196 seg
->limit
= 0xffff;
1200 static u64
svm_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
1202 struct vcpu_svm
*svm
= to_svm(vcpu
);
1204 if (is_guest_mode(vcpu
))
1205 return svm
->nested
.hsave
->control
.tsc_offset
;
1207 return vcpu
->arch
.tsc_offset
;
1210 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1212 struct vcpu_svm
*svm
= to_svm(vcpu
);
1213 u64 g_tsc_offset
= 0;
1215 if (is_guest_mode(vcpu
)) {
1216 /* Write L1's TSC offset. */
1217 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1218 svm
->nested
.hsave
->control
.tsc_offset
;
1219 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1221 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1222 svm
->vmcb
->control
.tsc_offset
,
1225 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1227 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1230 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1232 struct vmcb
*vmcb
= svm
->vmcb
;
1233 struct kvm_arch
*vm_data
= &svm
->vcpu
.kvm
->arch
;
1234 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1235 phys_addr_t lpa
= __sme_set(page_to_phys(vm_data
->avic_logical_id_table_page
));
1236 phys_addr_t ppa
= __sme_set(page_to_phys(vm_data
->avic_physical_id_table_page
));
1238 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1239 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1240 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1241 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1242 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1245 static void init_vmcb(struct vcpu_svm
*svm
)
1247 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1248 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1250 svm
->vcpu
.arch
.hflags
= 0;
1252 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1253 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1254 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1255 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1256 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1257 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1258 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1259 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1261 set_dr_intercepts(svm
);
1263 set_exception_intercept(svm
, PF_VECTOR
);
1264 set_exception_intercept(svm
, UD_VECTOR
);
1265 set_exception_intercept(svm
, MC_VECTOR
);
1266 set_exception_intercept(svm
, AC_VECTOR
);
1267 set_exception_intercept(svm
, DB_VECTOR
);
1269 set_intercept(svm
, INTERCEPT_INTR
);
1270 set_intercept(svm
, INTERCEPT_NMI
);
1271 set_intercept(svm
, INTERCEPT_SMI
);
1272 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1273 set_intercept(svm
, INTERCEPT_RDPMC
);
1274 set_intercept(svm
, INTERCEPT_CPUID
);
1275 set_intercept(svm
, INTERCEPT_INVD
);
1276 set_intercept(svm
, INTERCEPT_HLT
);
1277 set_intercept(svm
, INTERCEPT_INVLPG
);
1278 set_intercept(svm
, INTERCEPT_INVLPGA
);
1279 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1280 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1281 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1282 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1283 set_intercept(svm
, INTERCEPT_VMRUN
);
1284 set_intercept(svm
, INTERCEPT_VMMCALL
);
1285 set_intercept(svm
, INTERCEPT_VMLOAD
);
1286 set_intercept(svm
, INTERCEPT_VMSAVE
);
1287 set_intercept(svm
, INTERCEPT_STGI
);
1288 set_intercept(svm
, INTERCEPT_CLGI
);
1289 set_intercept(svm
, INTERCEPT_SKINIT
);
1290 set_intercept(svm
, INTERCEPT_WBINVD
);
1291 set_intercept(svm
, INTERCEPT_XSETBV
);
1293 if (!kvm_mwait_in_guest()) {
1294 set_intercept(svm
, INTERCEPT_MONITOR
);
1295 set_intercept(svm
, INTERCEPT_MWAIT
);
1298 control
->iopm_base_pa
= __sme_set(iopm_base
);
1299 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1300 control
->int_ctl
= V_INTR_MASKING_MASK
;
1302 init_seg(&save
->es
);
1303 init_seg(&save
->ss
);
1304 init_seg(&save
->ds
);
1305 init_seg(&save
->fs
);
1306 init_seg(&save
->gs
);
1308 save
->cs
.selector
= 0xf000;
1309 save
->cs
.base
= 0xffff0000;
1310 /* Executable/Readable Code Segment */
1311 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1312 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1313 save
->cs
.limit
= 0xffff;
1315 save
->gdtr
.limit
= 0xffff;
1316 save
->idtr
.limit
= 0xffff;
1318 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1319 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1321 svm_set_efer(&svm
->vcpu
, 0);
1322 save
->dr6
= 0xffff0ff0;
1323 kvm_set_rflags(&svm
->vcpu
, 2);
1324 save
->rip
= 0x0000fff0;
1325 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1328 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1329 * It also updates the guest-visible cr0 value.
1331 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1332 kvm_mmu_reset_context(&svm
->vcpu
);
1334 save
->cr4
= X86_CR4_PAE
;
1338 /* Setup VMCB for Nested Paging */
1339 control
->nested_ctl
= 1;
1340 clr_intercept(svm
, INTERCEPT_INVLPG
);
1341 clr_exception_intercept(svm
, PF_VECTOR
);
1342 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1343 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1344 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1348 svm
->asid_generation
= 0;
1350 svm
->nested
.vmcb
= 0;
1351 svm
->vcpu
.arch
.hflags
= 0;
1353 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1354 control
->pause_filter_count
= 3000;
1355 set_intercept(svm
, INTERCEPT_PAUSE
);
1358 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1359 avic_init_vmcb(svm
);
1362 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1363 * in VMCB and clear intercepts to avoid #VMEXIT.
1366 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1367 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1368 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1372 clr_intercept(svm
, INTERCEPT_STGI
);
1373 clr_intercept(svm
, INTERCEPT_CLGI
);
1374 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1377 mark_all_dirty(svm
->vmcb
);
1383 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1386 u64
*avic_physical_id_table
;
1387 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
1389 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1392 avic_physical_id_table
= page_address(vm_data
->avic_physical_id_table_page
);
1394 return &avic_physical_id_table
[index
];
1399 * AVIC hardware walks the nested page table to check permissions,
1400 * but does not use the SPA address specified in the leaf page
1401 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1402 * field of the VMCB. Therefore, we set up the
1403 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1405 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1407 struct kvm
*kvm
= vcpu
->kvm
;
1410 if (kvm
->arch
.apic_access_page_done
)
1413 ret
= x86_set_memory_region(kvm
,
1414 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1415 APIC_DEFAULT_PHYS_BASE
,
1420 kvm
->arch
.apic_access_page_done
= true;
1424 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1427 u64
*entry
, new_entry
;
1428 int id
= vcpu
->vcpu_id
;
1429 struct vcpu_svm
*svm
= to_svm(vcpu
);
1431 ret
= avic_init_access_page(vcpu
);
1435 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1438 if (!svm
->vcpu
.arch
.apic
->regs
)
1441 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1443 /* Setting AVIC backing page address in the phy APIC ID table */
1444 entry
= avic_get_physical_id_entry(vcpu
, id
);
1448 new_entry
= READ_ONCE(*entry
);
1449 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1450 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1451 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1452 WRITE_ONCE(*entry
, new_entry
);
1454 svm
->avic_physical_id_cache
= entry
;
1459 static void avic_vm_destroy(struct kvm
*kvm
)
1461 unsigned long flags
;
1462 struct kvm_arch
*vm_data
= &kvm
->arch
;
1467 if (vm_data
->avic_logical_id_table_page
)
1468 __free_page(vm_data
->avic_logical_id_table_page
);
1469 if (vm_data
->avic_physical_id_table_page
)
1470 __free_page(vm_data
->avic_physical_id_table_page
);
1472 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1473 hash_del(&vm_data
->hnode
);
1474 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1477 static int avic_vm_init(struct kvm
*kvm
)
1479 unsigned long flags
;
1481 struct kvm_arch
*vm_data
= &kvm
->arch
;
1482 struct page
*p_page
;
1483 struct page
*l_page
;
1484 struct kvm_arch
*ka
;
1490 /* Allocating physical APIC ID table (4KB) */
1491 p_page
= alloc_page(GFP_KERNEL
);
1495 vm_data
->avic_physical_id_table_page
= p_page
;
1496 clear_page(page_address(p_page
));
1498 /* Allocating logical APIC ID table (4KB) */
1499 l_page
= alloc_page(GFP_KERNEL
);
1503 vm_data
->avic_logical_id_table_page
= l_page
;
1504 clear_page(page_address(l_page
));
1506 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1508 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1509 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1510 next_vm_id_wrapped
= 1;
1513 /* Is it still in use? Only possible if wrapped at least once */
1514 if (next_vm_id_wrapped
) {
1515 hash_for_each_possible(svm_vm_data_hash
, ka
, hnode
, vm_id
) {
1516 struct kvm
*k2
= container_of(ka
, struct kvm
, arch
);
1517 struct kvm_arch
*vd2
= &k2
->arch
;
1518 if (vd2
->avic_vm_id
== vm_id
)
1522 vm_data
->avic_vm_id
= vm_id
;
1523 hash_add(svm_vm_data_hash
, &vm_data
->hnode
, vm_data
->avic_vm_id
);
1524 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1529 avic_vm_destroy(kvm
);
1534 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1537 unsigned long flags
;
1538 struct amd_svm_iommu_ir
*ir
;
1539 struct vcpu_svm
*svm
= to_svm(vcpu
);
1541 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1545 * Here, we go through the per-vcpu ir_list to update all existing
1546 * interrupt remapping table entry targeting this vcpu.
1548 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1550 if (list_empty(&svm
->ir_list
))
1553 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1554 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
1559 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
1563 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1566 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1567 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
1568 struct vcpu_svm
*svm
= to_svm(vcpu
);
1570 if (!kvm_vcpu_apicv_active(vcpu
))
1573 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
1576 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1577 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
1579 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
1580 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
1582 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1583 if (svm
->avic_is_running
)
1584 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1586 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1587 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
1588 svm
->avic_is_running
);
1591 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
1594 struct vcpu_svm
*svm
= to_svm(vcpu
);
1596 if (!kvm_vcpu_apicv_active(vcpu
))
1599 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
1600 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
1601 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
1603 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
1604 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
1608 * This function is called during VCPU halt/unhalt.
1610 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
1612 struct vcpu_svm
*svm
= to_svm(vcpu
);
1614 svm
->avic_is_running
= is_run
;
1616 avic_vcpu_load(vcpu
, vcpu
->cpu
);
1618 avic_vcpu_put(vcpu
);
1621 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
1623 struct vcpu_svm
*svm
= to_svm(vcpu
);
1628 svm
->virt_spec_ctrl
= 0;
1631 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
1632 MSR_IA32_APICBASE_ENABLE
;
1633 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
1634 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1638 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
1639 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
1641 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
1642 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
1645 static int avic_init_vcpu(struct vcpu_svm
*svm
)
1649 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1652 ret
= avic_init_backing_page(&svm
->vcpu
);
1656 INIT_LIST_HEAD(&svm
->ir_list
);
1657 spin_lock_init(&svm
->ir_list_lock
);
1662 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1664 struct vcpu_svm
*svm
;
1666 struct page
*msrpm_pages
;
1667 struct page
*hsave_page
;
1668 struct page
*nested_msrpm_pages
;
1671 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1677 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1682 page
= alloc_page(GFP_KERNEL
);
1686 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1690 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1691 if (!nested_msrpm_pages
)
1694 hsave_page
= alloc_page(GFP_KERNEL
);
1698 err
= avic_init_vcpu(svm
);
1702 /* We initialize this flag to true to make sure that the is_running
1703 * bit would be set the first time the vcpu is loaded.
1705 svm
->avic_is_running
= true;
1707 svm
->nested
.hsave
= page_address(hsave_page
);
1709 svm
->msrpm
= page_address(msrpm_pages
);
1710 svm_vcpu_init_msrpm(svm
->msrpm
);
1712 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1713 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1715 svm
->vmcb
= page_address(page
);
1716 clear_page(svm
->vmcb
);
1717 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
1718 svm
->asid_generation
= 0;
1721 svm_init_osvw(&svm
->vcpu
);
1726 __free_page(hsave_page
);
1728 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1730 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1734 kvm_vcpu_uninit(&svm
->vcpu
);
1736 kmem_cache_free(kvm_vcpu_cache
, svm
);
1738 return ERR_PTR(err
);
1741 static void svm_clear_current_vmcb(struct vmcb
*vmcb
)
1745 for_each_online_cpu(i
)
1746 cmpxchg(&per_cpu(svm_data
, i
)->current_vmcb
, vmcb
, NULL
);
1749 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1751 struct vcpu_svm
*svm
= to_svm(vcpu
);
1754 * The vmcb page can be recycled, causing a false negative in
1755 * svm_vcpu_load(). So, ensure that no logical CPU has this
1756 * vmcb page recorded as its current vmcb.
1758 svm_clear_current_vmcb(svm
->vmcb
);
1760 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
1761 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1762 __free_page(virt_to_page(svm
->nested
.hsave
));
1763 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1764 kvm_vcpu_uninit(vcpu
);
1765 kmem_cache_free(kvm_vcpu_cache
, svm
);
1768 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1770 struct vcpu_svm
*svm
= to_svm(vcpu
);
1771 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
1774 if (unlikely(cpu
!= vcpu
->cpu
)) {
1775 svm
->asid_generation
= 0;
1776 mark_all_dirty(svm
->vmcb
);
1779 #ifdef CONFIG_X86_64
1780 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1782 savesegment(fs
, svm
->host
.fs
);
1783 savesegment(gs
, svm
->host
.gs
);
1784 svm
->host
.ldt
= kvm_read_ldt();
1786 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1787 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1789 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1790 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
1791 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
1792 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
1793 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
1796 /* This assumes that the kernel never uses MSR_TSC_AUX */
1797 if (static_cpu_has(X86_FEATURE_RDTSCP
))
1798 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
1800 if (sd
->current_vmcb
!= svm
->vmcb
) {
1801 sd
->current_vmcb
= svm
->vmcb
;
1802 indirect_branch_prediction_barrier();
1804 avic_vcpu_load(vcpu
, cpu
);
1807 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1809 struct vcpu_svm
*svm
= to_svm(vcpu
);
1812 avic_vcpu_put(vcpu
);
1814 ++vcpu
->stat
.host_state_reload
;
1815 kvm_load_ldt(svm
->host
.ldt
);
1816 #ifdef CONFIG_X86_64
1817 loadsegment(fs
, svm
->host
.fs
);
1818 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
1819 load_gs_index(svm
->host
.gs
);
1821 #ifdef CONFIG_X86_32_LAZY_GS
1822 loadsegment(gs
, svm
->host
.gs
);
1825 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1826 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1829 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
1831 avic_set_running(vcpu
, false);
1834 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
1836 avic_set_running(vcpu
, true);
1839 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1841 struct vcpu_svm
*svm
= to_svm(vcpu
);
1842 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
1844 if (svm
->nmi_singlestep
) {
1845 /* Hide our flags if they were not set by the guest */
1846 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1847 rflags
&= ~X86_EFLAGS_TF
;
1848 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1849 rflags
&= ~X86_EFLAGS_RF
;
1854 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1856 if (to_svm(vcpu
)->nmi_singlestep
)
1857 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1860 * Any change of EFLAGS.VM is accompanied by a reload of SS
1861 * (caused by either a task switch or an inter-privilege IRET),
1862 * so we do not need to update the CPL here.
1864 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1867 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1870 case VCPU_EXREG_PDPTR
:
1871 BUG_ON(!npt_enabled
);
1872 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1879 static void svm_set_vintr(struct vcpu_svm
*svm
)
1881 set_intercept(svm
, INTERCEPT_VINTR
);
1884 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1886 clr_intercept(svm
, INTERCEPT_VINTR
);
1889 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1891 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1894 case VCPU_SREG_CS
: return &save
->cs
;
1895 case VCPU_SREG_DS
: return &save
->ds
;
1896 case VCPU_SREG_ES
: return &save
->es
;
1897 case VCPU_SREG_FS
: return &save
->fs
;
1898 case VCPU_SREG_GS
: return &save
->gs
;
1899 case VCPU_SREG_SS
: return &save
->ss
;
1900 case VCPU_SREG_TR
: return &save
->tr
;
1901 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1907 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1909 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1914 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1915 struct kvm_segment
*var
, int seg
)
1917 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1919 var
->base
= s
->base
;
1920 var
->limit
= s
->limit
;
1921 var
->selector
= s
->selector
;
1922 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1923 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1924 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1925 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1926 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1927 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1928 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1931 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1932 * However, the SVM spec states that the G bit is not observed by the
1933 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1934 * So let's synthesize a legal G bit for all segments, this helps
1935 * running KVM nested. It also helps cross-vendor migration, because
1936 * Intel's vmentry has a check on the 'G' bit.
1938 var
->g
= s
->limit
> 0xfffff;
1941 * AMD's VMCB does not have an explicit unusable field, so emulate it
1942 * for cross vendor migration purposes by "not present"
1944 var
->unusable
= !var
->present
;
1949 * Work around a bug where the busy flag in the tr selector
1959 * The accessed bit must always be set in the segment
1960 * descriptor cache, although it can be cleared in the
1961 * descriptor, the cached bit always remains at 1. Since
1962 * Intel has a check on this, set it here to support
1963 * cross-vendor migration.
1970 * On AMD CPUs sometimes the DB bit in the segment
1971 * descriptor is left as 1, although the whole segment has
1972 * been made unusable. Clear it here to pass an Intel VMX
1973 * entry check when cross vendor migrating.
1977 /* This is symmetric with svm_set_segment() */
1978 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
1983 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1985 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1990 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1992 struct vcpu_svm
*svm
= to_svm(vcpu
);
1994 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1995 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1998 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2000 struct vcpu_svm
*svm
= to_svm(vcpu
);
2002 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
2003 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
2004 mark_dirty(svm
->vmcb
, VMCB_DT
);
2007 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2009 struct vcpu_svm
*svm
= to_svm(vcpu
);
2011 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
2012 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
2015 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2017 struct vcpu_svm
*svm
= to_svm(vcpu
);
2019 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
2020 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
2021 mark_dirty(svm
->vmcb
, VMCB_DT
);
2024 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2028 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
2032 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2036 static void update_cr0_intercept(struct vcpu_svm
*svm
)
2038 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
2039 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
2041 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
2042 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
2044 mark_dirty(svm
->vmcb
, VMCB_CR
);
2046 if (gcr0
== *hcr0
) {
2047 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2048 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2050 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2051 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2055 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2057 struct vcpu_svm
*svm
= to_svm(vcpu
);
2059 #ifdef CONFIG_X86_64
2060 if (vcpu
->arch
.efer
& EFER_LME
) {
2061 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
2062 vcpu
->arch
.efer
|= EFER_LMA
;
2063 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2066 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2067 vcpu
->arch
.efer
&= ~EFER_LMA
;
2068 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2072 vcpu
->arch
.cr0
= cr0
;
2075 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2078 * re-enable caching here because the QEMU bios
2079 * does not do it - this results in some delay at
2082 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2083 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2084 svm
->vmcb
->save
.cr0
= cr0
;
2085 mark_dirty(svm
->vmcb
, VMCB_CR
);
2086 update_cr0_intercept(svm
);
2089 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2091 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2092 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2094 if (cr4
& X86_CR4_VMXE
)
2097 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2098 svm_flush_tlb(vcpu
);
2100 vcpu
->arch
.cr4
= cr4
;
2103 cr4
|= host_cr4_mce
;
2104 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2105 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2109 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2110 struct kvm_segment
*var
, int seg
)
2112 struct vcpu_svm
*svm
= to_svm(vcpu
);
2113 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2115 s
->base
= var
->base
;
2116 s
->limit
= var
->limit
;
2117 s
->selector
= var
->selector
;
2118 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2119 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2120 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2121 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2122 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2123 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2124 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2125 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2128 * This is always accurate, except if SYSRET returned to a segment
2129 * with SS.DPL != 3. Intel does not have this quirk, and always
2130 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2131 * would entail passing the CPL to userspace and back.
2133 if (seg
== VCPU_SREG_SS
)
2134 /* This is symmetric with svm_get_segment() */
2135 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2137 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2140 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2142 struct vcpu_svm
*svm
= to_svm(vcpu
);
2144 clr_exception_intercept(svm
, BP_VECTOR
);
2146 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2147 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2148 set_exception_intercept(svm
, BP_VECTOR
);
2150 vcpu
->guest_debug
= 0;
2153 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2155 if (sd
->next_asid
> sd
->max_asid
) {
2156 ++sd
->asid_generation
;
2158 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2161 svm
->asid_generation
= sd
->asid_generation
;
2162 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2164 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2167 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2169 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2172 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2174 struct vcpu_svm
*svm
= to_svm(vcpu
);
2176 svm
->vmcb
->save
.dr6
= value
;
2177 mark_dirty(svm
->vmcb
, VMCB_DR
);
2180 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2182 struct vcpu_svm
*svm
= to_svm(vcpu
);
2184 get_debugreg(vcpu
->arch
.db
[0], 0);
2185 get_debugreg(vcpu
->arch
.db
[1], 1);
2186 get_debugreg(vcpu
->arch
.db
[2], 2);
2187 get_debugreg(vcpu
->arch
.db
[3], 3);
2188 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2189 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2191 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2192 set_dr_intercepts(svm
);
2195 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2197 struct vcpu_svm
*svm
= to_svm(vcpu
);
2199 svm
->vmcb
->save
.dr7
= value
;
2200 mark_dirty(svm
->vmcb
, VMCB_DR
);
2203 static int pf_interception(struct vcpu_svm
*svm
)
2205 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2206 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2208 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2209 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2210 svm
->vmcb
->control
.insn_bytes
: NULL
,
2211 svm
->vmcb
->control
.insn_len
);
2214 static int npf_interception(struct vcpu_svm
*svm
)
2216 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
2217 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2219 trace_kvm_page_fault(fault_address
, error_code
);
2220 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2221 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2222 svm
->vmcb
->control
.insn_bytes
: NULL
,
2223 svm
->vmcb
->control
.insn_len
);
2226 static int db_interception(struct vcpu_svm
*svm
)
2228 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2230 if (!(svm
->vcpu
.guest_debug
&
2231 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2232 !svm
->nmi_singlestep
) {
2233 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2237 if (svm
->nmi_singlestep
) {
2238 disable_nmi_singlestep(svm
);
2241 if (svm
->vcpu
.guest_debug
&
2242 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2243 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2244 kvm_run
->debug
.arch
.pc
=
2245 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2246 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2253 static int bp_interception(struct vcpu_svm
*svm
)
2255 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2257 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2258 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2259 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2263 static int ud_interception(struct vcpu_svm
*svm
)
2267 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
2268 if (er
== EMULATE_USER_EXIT
)
2270 if (er
!= EMULATE_DONE
)
2271 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2275 static int ac_interception(struct vcpu_svm
*svm
)
2277 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2281 static bool is_erratum_383(void)
2286 if (!erratum_383_found
)
2289 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2293 /* Bit 62 may or may not be set for this mce */
2294 value
&= ~(1ULL << 62);
2296 if (value
!= 0xb600000000010015ULL
)
2299 /* Clear MCi_STATUS registers */
2300 for (i
= 0; i
< 6; ++i
)
2301 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2303 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2307 value
&= ~(1ULL << 2);
2308 low
= lower_32_bits(value
);
2309 high
= upper_32_bits(value
);
2311 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2314 /* Flush tlb to evict multi-match entries */
2320 static void svm_handle_mce(struct vcpu_svm
*svm
)
2322 if (is_erratum_383()) {
2324 * Erratum 383 triggered. Guest state is corrupt so kill the
2327 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2329 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2335 * On an #MC intercept the MCE handler is not called automatically in
2336 * the host. So do it by hand here.
2340 /* not sure if we ever come back to this point */
2345 static int mc_interception(struct vcpu_svm
*svm
)
2350 static int shutdown_interception(struct vcpu_svm
*svm
)
2352 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2355 * VMCB is undefined after a SHUTDOWN intercept
2356 * so reinitialize it.
2358 clear_page(svm
->vmcb
);
2361 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2365 static int io_interception(struct vcpu_svm
*svm
)
2367 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2368 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2369 int size
, in
, string
, ret
;
2372 ++svm
->vcpu
.stat
.io_exits
;
2373 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2374 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2376 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2378 port
= io_info
>> 16;
2379 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2380 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2381 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
2384 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2385 * KVM_EXIT_DEBUG here.
2388 return kvm_fast_pio_in(vcpu
, size
, port
) && ret
;
2390 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
2393 static int nmi_interception(struct vcpu_svm
*svm
)
2398 static int intr_interception(struct vcpu_svm
*svm
)
2400 ++svm
->vcpu
.stat
.irq_exits
;
2404 static int nop_on_interception(struct vcpu_svm
*svm
)
2409 static int halt_interception(struct vcpu_svm
*svm
)
2411 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2412 return kvm_emulate_halt(&svm
->vcpu
);
2415 static int vmmcall_interception(struct vcpu_svm
*svm
)
2417 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2418 return kvm_emulate_hypercall(&svm
->vcpu
);
2421 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2423 struct vcpu_svm
*svm
= to_svm(vcpu
);
2425 return svm
->nested
.nested_cr3
;
2428 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2430 struct vcpu_svm
*svm
= to_svm(vcpu
);
2431 u64 cr3
= svm
->nested
.nested_cr3
;
2435 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2436 offset_in_page(cr3
) + index
* 8, 8);
2442 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2445 struct vcpu_svm
*svm
= to_svm(vcpu
);
2447 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2448 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2449 svm_flush_tlb(vcpu
);
2452 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2453 struct x86_exception
*fault
)
2455 struct vcpu_svm
*svm
= to_svm(vcpu
);
2457 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2459 * TODO: track the cause of the nested page fault, and
2460 * correctly fill in the high bits of exit_info_1.
2462 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2463 svm
->vmcb
->control
.exit_code_hi
= 0;
2464 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2465 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2468 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2469 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2472 * The present bit is always zero for page structure faults on real
2475 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2476 svm
->vmcb
->control
.exit_info_1
&= ~1;
2478 nested_svm_vmexit(svm
);
2481 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2483 WARN_ON(mmu_is_nested(vcpu
));
2484 kvm_init_shadow_mmu(vcpu
);
2485 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2486 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2487 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2488 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2489 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level(vcpu
);
2490 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2491 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2494 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2496 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2499 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2501 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2502 !is_paging(&svm
->vcpu
)) {
2503 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2507 if (svm
->vmcb
->save
.cpl
) {
2508 kvm_inject_gp(&svm
->vcpu
, 0);
2515 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2516 bool has_error_code
, u32 error_code
)
2520 if (!is_guest_mode(&svm
->vcpu
))
2523 vmexit
= nested_svm_intercept(svm
);
2524 if (vmexit
!= NESTED_EXIT_DONE
)
2527 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2528 svm
->vmcb
->control
.exit_code_hi
= 0;
2529 svm
->vmcb
->control
.exit_info_1
= error_code
;
2532 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2533 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2534 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2535 * written only when inject_pending_event runs (DR6 would written here
2536 * too). This should be conditional on a new capability---if the
2537 * capability is disabled, kvm_multiple_exception would write the
2538 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2540 if (svm
->vcpu
.arch
.exception
.nested_apf
)
2541 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
2543 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2545 svm
->nested
.exit_required
= true;
2549 /* This function returns true if it is save to enable the irq window */
2550 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2552 if (!is_guest_mode(&svm
->vcpu
))
2555 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2558 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2562 * if vmexit was already requested (by intercepted exception
2563 * for instance) do not overwrite it with "external interrupt"
2566 if (svm
->nested
.exit_required
)
2569 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2570 svm
->vmcb
->control
.exit_info_1
= 0;
2571 svm
->vmcb
->control
.exit_info_2
= 0;
2573 if (svm
->nested
.intercept
& 1ULL) {
2575 * The #vmexit can't be emulated here directly because this
2576 * code path runs with irqs and preemption disabled. A
2577 * #vmexit emulation might sleep. Only signal request for
2580 svm
->nested
.exit_required
= true;
2581 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2588 /* This function returns true if it is save to enable the nmi window */
2589 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2591 if (!is_guest_mode(&svm
->vcpu
))
2594 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2597 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2598 svm
->nested
.exit_required
= true;
2603 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2609 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
2610 if (is_error_page(page
))
2618 kvm_inject_gp(&svm
->vcpu
, 0);
2623 static void nested_svm_unmap(struct page
*page
)
2626 kvm_release_page_dirty(page
);
2629 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2631 unsigned port
, size
, iopm_len
;
2636 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2637 return NESTED_EXIT_HOST
;
2639 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2640 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
2641 SVM_IOIO_SIZE_SHIFT
;
2642 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2643 start_bit
= port
% 8;
2644 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
2645 mask
= (0xf >> (4 - size
)) << start_bit
;
2648 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
2649 return NESTED_EXIT_DONE
;
2651 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2654 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2656 u32 offset
, msr
, value
;
2659 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2660 return NESTED_EXIT_HOST
;
2662 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2663 offset
= svm_msrpm_offset(msr
);
2664 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2665 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2667 if (offset
== MSR_INVALID
)
2668 return NESTED_EXIT_DONE
;
2670 /* Offset is in 32 bit units but need in 8 bit units */
2673 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2674 return NESTED_EXIT_DONE
;
2676 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2679 /* DB exceptions for our internal use must not cause vmexit */
2680 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
2684 /* if we're not singlestepping, it's not ours */
2685 if (!svm
->nmi_singlestep
)
2686 return NESTED_EXIT_DONE
;
2688 /* if it's not a singlestep exception, it's not ours */
2689 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
2690 return NESTED_EXIT_DONE
;
2691 if (!(dr6
& DR6_BS
))
2692 return NESTED_EXIT_DONE
;
2694 /* if the guest is singlestepping, it should get the vmexit */
2695 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
2696 disable_nmi_singlestep(svm
);
2697 return NESTED_EXIT_DONE
;
2700 /* it's ours, the nested hypervisor must not see this one */
2701 return NESTED_EXIT_HOST
;
2704 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2706 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2708 switch (exit_code
) {
2711 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2712 return NESTED_EXIT_HOST
;
2714 /* For now we are always handling NPFs when using them */
2716 return NESTED_EXIT_HOST
;
2718 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2719 /* When we're shadowing, trap PFs, but not async PF */
2720 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
2721 return NESTED_EXIT_HOST
;
2727 return NESTED_EXIT_CONTINUE
;
2731 * If this function returns true, this #vmexit was already handled
2733 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2735 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2736 int vmexit
= NESTED_EXIT_HOST
;
2738 switch (exit_code
) {
2740 vmexit
= nested_svm_exit_handled_msr(svm
);
2743 vmexit
= nested_svm_intercept_ioio(svm
);
2745 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2746 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2747 if (svm
->nested
.intercept_cr
& bit
)
2748 vmexit
= NESTED_EXIT_DONE
;
2751 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2752 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2753 if (svm
->nested
.intercept_dr
& bit
)
2754 vmexit
= NESTED_EXIT_DONE
;
2757 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2758 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2759 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
2760 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
2761 vmexit
= nested_svm_intercept_db(svm
);
2763 vmexit
= NESTED_EXIT_DONE
;
2765 /* async page fault always cause vmexit */
2766 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2767 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
2768 vmexit
= NESTED_EXIT_DONE
;
2771 case SVM_EXIT_ERR
: {
2772 vmexit
= NESTED_EXIT_DONE
;
2776 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2777 if (svm
->nested
.intercept
& exit_bits
)
2778 vmexit
= NESTED_EXIT_DONE
;
2785 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2789 vmexit
= nested_svm_intercept(svm
);
2791 if (vmexit
== NESTED_EXIT_DONE
)
2792 nested_svm_vmexit(svm
);
2797 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2799 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2800 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2802 dst
->intercept_cr
= from
->intercept_cr
;
2803 dst
->intercept_dr
= from
->intercept_dr
;
2804 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2805 dst
->intercept
= from
->intercept
;
2806 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2807 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2808 dst
->tsc_offset
= from
->tsc_offset
;
2809 dst
->asid
= from
->asid
;
2810 dst
->tlb_ctl
= from
->tlb_ctl
;
2811 dst
->int_ctl
= from
->int_ctl
;
2812 dst
->int_vector
= from
->int_vector
;
2813 dst
->int_state
= from
->int_state
;
2814 dst
->exit_code
= from
->exit_code
;
2815 dst
->exit_code_hi
= from
->exit_code_hi
;
2816 dst
->exit_info_1
= from
->exit_info_1
;
2817 dst
->exit_info_2
= from
->exit_info_2
;
2818 dst
->exit_int_info
= from
->exit_int_info
;
2819 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2820 dst
->nested_ctl
= from
->nested_ctl
;
2821 dst
->event_inj
= from
->event_inj
;
2822 dst
->event_inj_err
= from
->event_inj_err
;
2823 dst
->nested_cr3
= from
->nested_cr3
;
2824 dst
->virt_ext
= from
->virt_ext
;
2827 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2829 struct vmcb
*nested_vmcb
;
2830 struct vmcb
*hsave
= svm
->nested
.hsave
;
2831 struct vmcb
*vmcb
= svm
->vmcb
;
2834 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2835 vmcb
->control
.exit_info_1
,
2836 vmcb
->control
.exit_info_2
,
2837 vmcb
->control
.exit_int_info
,
2838 vmcb
->control
.exit_int_info_err
,
2841 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2845 /* Exit Guest-Mode */
2846 leave_guest_mode(&svm
->vcpu
);
2847 svm
->nested
.vmcb
= 0;
2849 /* Give the current vmcb to the guest */
2852 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2853 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2854 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2855 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2856 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2857 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2858 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2859 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2860 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2861 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2862 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2863 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2864 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2865 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2866 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2867 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2868 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2869 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2871 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2872 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2873 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2874 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2875 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2876 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2877 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2878 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2879 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2881 if (svm
->nrips_enabled
)
2882 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2885 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2886 * to make sure that we do not lose injected events. So check event_inj
2887 * here and copy it to exit_int_info if it is valid.
2888 * Exit_int_info and event_inj can't be both valid because the case
2889 * below only happens on a VMRUN instruction intercept which has
2890 * no valid exit_int_info set.
2892 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2893 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2895 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2896 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2899 nested_vmcb
->control
.tlb_ctl
= 0;
2900 nested_vmcb
->control
.event_inj
= 0;
2901 nested_vmcb
->control
.event_inj_err
= 0;
2903 /* We always set V_INTR_MASKING and remember the old value in hflags */
2904 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2905 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2907 /* Restore the original control entries */
2908 copy_vmcb_control_area(vmcb
, hsave
);
2910 svm
->vcpu
.arch
.tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2911 kvm_clear_exception_queue(&svm
->vcpu
);
2912 kvm_clear_interrupt_queue(&svm
->vcpu
);
2914 svm
->nested
.nested_cr3
= 0;
2916 /* Restore selected save entries */
2917 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2918 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2919 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2920 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2921 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2922 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2923 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2924 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2925 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2926 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2928 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2929 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2931 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2933 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2934 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2935 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2936 svm
->vmcb
->save
.dr7
= 0;
2937 svm
->vmcb
->save
.cpl
= 0;
2938 svm
->vmcb
->control
.exit_int_info
= 0;
2940 mark_all_dirty(svm
->vmcb
);
2942 nested_svm_unmap(page
);
2944 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2945 kvm_mmu_reset_context(&svm
->vcpu
);
2946 kvm_mmu_load(&svm
->vcpu
);
2951 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2954 * This function merges the msr permission bitmaps of kvm and the
2955 * nested vmcb. It is optimized in that it only merges the parts where
2956 * the kvm msr permission bitmap may contain zero bits
2960 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2963 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2967 if (msrpm_offsets
[i
] == 0xffffffff)
2970 p
= msrpm_offsets
[i
];
2971 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2973 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
2976 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2979 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
2984 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2986 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2989 if (vmcb
->control
.asid
== 0)
2992 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2998 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
2999 struct vmcb
*nested_vmcb
, struct page
*page
)
3001 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
3002 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
3004 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
3006 if (nested_vmcb
->control
.nested_ctl
) {
3007 kvm_mmu_unload(&svm
->vcpu
);
3008 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
3009 nested_svm_init_mmu_context(&svm
->vcpu
);
3012 /* Load the nested guest state */
3013 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
3014 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
3015 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
3016 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
3017 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
3018 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
3019 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
3020 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3021 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3022 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3024 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3025 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3027 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3029 /* Guest paging mode is active - reset mmu */
3030 kvm_mmu_reset_context(&svm
->vcpu
);
3032 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3033 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
3034 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
3035 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
3037 /* In case we don't even reach vcpu_run, the fields are not updated */
3038 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3039 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3040 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3041 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3042 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3043 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3045 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3046 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3048 /* cache intercepts */
3049 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3050 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3051 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3052 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3054 svm_flush_tlb(&svm
->vcpu
);
3055 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3056 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3057 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3059 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3061 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3062 /* We only want the cr8 intercept bits of the guest */
3063 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3064 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3067 /* We don't want to see VMMCALLs from a nested guest */
3068 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3070 svm
->vcpu
.arch
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3071 svm
->vmcb
->control
.tsc_offset
= svm
->vcpu
.arch
.tsc_offset
;
3073 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3074 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3075 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3076 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3077 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3079 nested_svm_unmap(page
);
3081 /* Enter Guest-Mode */
3082 enter_guest_mode(&svm
->vcpu
);
3085 * Merge guest and host intercepts - must be called with vcpu in
3086 * guest-mode to take affect here
3088 recalc_intercepts(svm
);
3090 svm
->nested
.vmcb
= vmcb_gpa
;
3094 mark_all_dirty(svm
->vmcb
);
3097 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3099 struct vmcb
*nested_vmcb
;
3100 struct vmcb
*hsave
= svm
->nested
.hsave
;
3101 struct vmcb
*vmcb
= svm
->vmcb
;
3105 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3107 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3111 if (!nested_vmcb_checks(nested_vmcb
)) {
3112 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3113 nested_vmcb
->control
.exit_code_hi
= 0;
3114 nested_vmcb
->control
.exit_info_1
= 0;
3115 nested_vmcb
->control
.exit_info_2
= 0;
3117 nested_svm_unmap(page
);
3122 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3123 nested_vmcb
->save
.rip
,
3124 nested_vmcb
->control
.int_ctl
,
3125 nested_vmcb
->control
.event_inj
,
3126 nested_vmcb
->control
.nested_ctl
);
3128 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3129 nested_vmcb
->control
.intercept_cr
>> 16,
3130 nested_vmcb
->control
.intercept_exceptions
,
3131 nested_vmcb
->control
.intercept
);
3133 /* Clear internal status */
3134 kvm_clear_exception_queue(&svm
->vcpu
);
3135 kvm_clear_interrupt_queue(&svm
->vcpu
);
3138 * Save the old vmcb, so we don't need to pick what we save, but can
3139 * restore everything when a VMEXIT occurs
3141 hsave
->save
.es
= vmcb
->save
.es
;
3142 hsave
->save
.cs
= vmcb
->save
.cs
;
3143 hsave
->save
.ss
= vmcb
->save
.ss
;
3144 hsave
->save
.ds
= vmcb
->save
.ds
;
3145 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3146 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3147 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3148 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3149 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3150 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3151 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3152 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3153 hsave
->save
.rax
= vmcb
->save
.rax
;
3155 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3157 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3159 copy_vmcb_control_area(hsave
, vmcb
);
3161 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, page
);
3166 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3168 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3169 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3170 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3171 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3172 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3173 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3174 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3175 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3176 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3177 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3178 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3179 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3182 static int vmload_interception(struct vcpu_svm
*svm
)
3184 struct vmcb
*nested_vmcb
;
3188 if (nested_svm_check_permissions(svm
))
3191 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3195 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3196 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3198 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3199 nested_svm_unmap(page
);
3204 static int vmsave_interception(struct vcpu_svm
*svm
)
3206 struct vmcb
*nested_vmcb
;
3210 if (nested_svm_check_permissions(svm
))
3213 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3217 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3218 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3220 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3221 nested_svm_unmap(page
);
3226 static int vmrun_interception(struct vcpu_svm
*svm
)
3228 if (nested_svm_check_permissions(svm
))
3231 /* Save rip after vmrun instruction */
3232 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3234 if (!nested_svm_vmrun(svm
))
3237 if (!nested_svm_vmrun_msrpm(svm
))
3244 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3245 svm
->vmcb
->control
.exit_code_hi
= 0;
3246 svm
->vmcb
->control
.exit_info_1
= 0;
3247 svm
->vmcb
->control
.exit_info_2
= 0;
3249 nested_svm_vmexit(svm
);
3254 static int stgi_interception(struct vcpu_svm
*svm
)
3258 if (nested_svm_check_permissions(svm
))
3262 * If VGIF is enabled, the STGI intercept is only added to
3263 * detect the opening of the SMI/NMI window; remove it now.
3265 if (vgif_enabled(svm
))
3266 clr_intercept(svm
, INTERCEPT_STGI
);
3268 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3269 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3270 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3277 static int clgi_interception(struct vcpu_svm
*svm
)
3281 if (nested_svm_check_permissions(svm
))
3284 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3285 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3289 /* After a CLGI no interrupts should come */
3290 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3291 svm_clear_vintr(svm
);
3292 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3293 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3299 static int invlpga_interception(struct vcpu_svm
*svm
)
3301 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3303 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3304 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3306 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3307 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3309 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3310 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3313 static int skinit_interception(struct vcpu_svm
*svm
)
3315 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3317 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3321 static int wbinvd_interception(struct vcpu_svm
*svm
)
3323 return kvm_emulate_wbinvd(&svm
->vcpu
);
3326 static int xsetbv_interception(struct vcpu_svm
*svm
)
3328 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3329 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3331 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3332 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3333 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3339 static int task_switch_interception(struct vcpu_svm
*svm
)
3343 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3344 SVM_EXITINTINFO_TYPE_MASK
;
3345 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3347 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3349 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3350 bool has_error_code
= false;
3353 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3355 if (svm
->vmcb
->control
.exit_info_2
&
3356 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3357 reason
= TASK_SWITCH_IRET
;
3358 else if (svm
->vmcb
->control
.exit_info_2
&
3359 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3360 reason
= TASK_SWITCH_JMP
;
3362 reason
= TASK_SWITCH_GATE
;
3364 reason
= TASK_SWITCH_CALL
;
3366 if (reason
== TASK_SWITCH_GATE
) {
3368 case SVM_EXITINTINFO_TYPE_NMI
:
3369 svm
->vcpu
.arch
.nmi_injected
= false;
3371 case SVM_EXITINTINFO_TYPE_EXEPT
:
3372 if (svm
->vmcb
->control
.exit_info_2
&
3373 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3374 has_error_code
= true;
3376 (u32
)svm
->vmcb
->control
.exit_info_2
;
3378 kvm_clear_exception_queue(&svm
->vcpu
);
3380 case SVM_EXITINTINFO_TYPE_INTR
:
3381 kvm_clear_interrupt_queue(&svm
->vcpu
);
3388 if (reason
!= TASK_SWITCH_GATE
||
3389 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3390 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3391 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3392 skip_emulated_instruction(&svm
->vcpu
);
3394 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3397 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3398 has_error_code
, error_code
) == EMULATE_FAIL
) {
3399 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3400 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3401 svm
->vcpu
.run
->internal
.ndata
= 0;
3407 static int cpuid_interception(struct vcpu_svm
*svm
)
3409 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3410 return kvm_emulate_cpuid(&svm
->vcpu
);
3413 static int iret_interception(struct vcpu_svm
*svm
)
3415 ++svm
->vcpu
.stat
.nmi_window_exits
;
3416 clr_intercept(svm
, INTERCEPT_IRET
);
3417 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3418 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3419 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3423 static int invlpg_interception(struct vcpu_svm
*svm
)
3425 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3426 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3428 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3429 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3432 static int emulate_on_interception(struct vcpu_svm
*svm
)
3434 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3437 static int rdpmc_interception(struct vcpu_svm
*svm
)
3441 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3442 return emulate_on_interception(svm
);
3444 err
= kvm_rdpmc(&svm
->vcpu
);
3445 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3448 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3451 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3455 intercept
= svm
->nested
.intercept
;
3457 if (!is_guest_mode(&svm
->vcpu
) ||
3458 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3461 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3462 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3465 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3466 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3472 #define CR_VALID (1ULL << 63)
3474 static int cr_interception(struct vcpu_svm
*svm
)
3480 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3481 return emulate_on_interception(svm
);
3483 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3484 return emulate_on_interception(svm
);
3486 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3487 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3488 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3490 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3493 if (cr
>= 16) { /* mov to cr */
3495 val
= kvm_register_read(&svm
->vcpu
, reg
);
3498 if (!check_selective_cr0_intercepted(svm
, val
))
3499 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3505 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3508 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3511 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3514 WARN(1, "unhandled write to CR%d", cr
);
3515 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3518 } else { /* mov from cr */
3521 val
= kvm_read_cr0(&svm
->vcpu
);
3524 val
= svm
->vcpu
.arch
.cr2
;
3527 val
= kvm_read_cr3(&svm
->vcpu
);
3530 val
= kvm_read_cr4(&svm
->vcpu
);
3533 val
= kvm_get_cr8(&svm
->vcpu
);
3536 WARN(1, "unhandled read from CR%d", cr
);
3537 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3540 kvm_register_write(&svm
->vcpu
, reg
, val
);
3542 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3545 static int dr_interception(struct vcpu_svm
*svm
)
3550 if (svm
->vcpu
.guest_debug
== 0) {
3552 * No more DR vmexits; force a reload of the debug registers
3553 * and reenter on this instruction. The next vmexit will
3554 * retrieve the full state of the debug registers.
3556 clr_dr_intercepts(svm
);
3557 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3561 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3562 return emulate_on_interception(svm
);
3564 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3565 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3567 if (dr
>= 16) { /* mov to DRn */
3568 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3570 val
= kvm_register_read(&svm
->vcpu
, reg
);
3571 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
3573 if (!kvm_require_dr(&svm
->vcpu
, dr
))
3575 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
3576 kvm_register_write(&svm
->vcpu
, reg
, val
);
3579 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3582 static int cr8_write_interception(struct vcpu_svm
*svm
)
3584 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3587 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
3588 /* instruction emulation calls kvm_set_cr8() */
3589 r
= cr_interception(svm
);
3590 if (lapic_in_kernel(&svm
->vcpu
))
3592 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
3594 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
3598 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
3603 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3605 struct vcpu_svm
*svm
= to_svm(vcpu
);
3607 switch (msr_info
->index
) {
3609 msr_info
->data
= svm
->vmcb
->save
.star
;
3611 #ifdef CONFIG_X86_64
3613 msr_info
->data
= svm
->vmcb
->save
.lstar
;
3616 msr_info
->data
= svm
->vmcb
->save
.cstar
;
3618 case MSR_KERNEL_GS_BASE
:
3619 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
3621 case MSR_SYSCALL_MASK
:
3622 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
3625 case MSR_IA32_SYSENTER_CS
:
3626 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
3628 case MSR_IA32_SYSENTER_EIP
:
3629 msr_info
->data
= svm
->sysenter_eip
;
3631 case MSR_IA32_SYSENTER_ESP
:
3632 msr_info
->data
= svm
->sysenter_esp
;
3635 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3637 msr_info
->data
= svm
->tsc_aux
;
3640 * Nobody will change the following 5 values in the VMCB so we can
3641 * safely return them on rdmsr. They will always be 0 until LBRV is
3644 case MSR_IA32_DEBUGCTLMSR
:
3645 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
3647 case MSR_IA32_LASTBRANCHFROMIP
:
3648 msr_info
->data
= svm
->vmcb
->save
.br_from
;
3650 case MSR_IA32_LASTBRANCHTOIP
:
3651 msr_info
->data
= svm
->vmcb
->save
.br_to
;
3653 case MSR_IA32_LASTINTFROMIP
:
3654 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
3656 case MSR_IA32_LASTINTTOIP
:
3657 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
3659 case MSR_VM_HSAVE_PA
:
3660 msr_info
->data
= svm
->nested
.hsave_msr
;
3663 msr_info
->data
= svm
->nested
.vm_cr_msr
;
3665 case MSR_IA32_SPEC_CTRL
:
3666 if (!msr_info
->host_initiated
&&
3667 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
3668 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
3671 msr_info
->data
= svm
->spec_ctrl
;
3673 case MSR_IA32_UCODE_REV
:
3674 msr_info
->data
= 0x01000065;
3676 case MSR_AMD64_VIRT_SPEC_CTRL
:
3677 if (!msr_info
->host_initiated
&&
3678 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
3681 msr_info
->data
= svm
->virt_spec_ctrl
;
3683 case MSR_F15H_IC_CFG
: {
3687 family
= guest_cpuid_family(vcpu
);
3688 model
= guest_cpuid_model(vcpu
);
3690 if (family
< 0 || model
< 0)
3691 return kvm_get_msr_common(vcpu
, msr_info
);
3695 if (family
== 0x15 &&
3696 (model
>= 0x2 && model
< 0x20))
3697 msr_info
->data
= 0x1E;
3701 return kvm_get_msr_common(vcpu
, msr_info
);
3706 static int rdmsr_interception(struct vcpu_svm
*svm
)
3708 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3709 struct msr_data msr_info
;
3711 msr_info
.index
= ecx
;
3712 msr_info
.host_initiated
= false;
3713 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
3714 trace_kvm_msr_read_ex(ecx
);
3715 kvm_inject_gp(&svm
->vcpu
, 0);
3718 trace_kvm_msr_read(ecx
, msr_info
.data
);
3720 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
3721 msr_info
.data
& 0xffffffff);
3722 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
3723 msr_info
.data
>> 32);
3724 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3725 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3729 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3731 struct vcpu_svm
*svm
= to_svm(vcpu
);
3732 int svm_dis
, chg_mask
;
3734 if (data
& ~SVM_VM_CR_VALID_MASK
)
3737 chg_mask
= SVM_VM_CR_VALID_MASK
;
3739 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3740 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3742 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3743 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3745 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3747 /* check for svm_disable while efer.svme is set */
3748 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3754 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
3756 struct vcpu_svm
*svm
= to_svm(vcpu
);
3758 u32 ecx
= msr
->index
;
3759 u64 data
= msr
->data
;
3761 case MSR_IA32_CR_PAT
:
3762 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3764 vcpu
->arch
.pat
= data
;
3765 svm
->vmcb
->save
.g_pat
= data
;
3766 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3768 case MSR_IA32_SPEC_CTRL
:
3769 if (!msr
->host_initiated
&&
3770 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
3771 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
3774 /* The STIBP bit doesn't fault even if it's not advertised */
3775 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
3778 svm
->spec_ctrl
= data
;
3785 * When it's written (to non-zero) for the first time, pass
3789 * The handling of the MSR bitmap for L2 guests is done in
3790 * nested_svm_vmrun_msrpm.
3791 * We update the L1 MSR bit as well since it will end up
3792 * touching the MSR anyway now.
3794 set_msr_interception(svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
3796 case MSR_IA32_PRED_CMD
:
3797 if (!msr
->host_initiated
&&
3798 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBPB
))
3801 if (data
& ~PRED_CMD_IBPB
)
3807 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
3808 if (is_guest_mode(vcpu
))
3810 set_msr_interception(svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
3812 case MSR_AMD64_VIRT_SPEC_CTRL
:
3813 if (!msr
->host_initiated
&&
3814 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
3817 if (data
& ~SPEC_CTRL_SSBD
)
3820 svm
->virt_spec_ctrl
= data
;
3823 svm
->vmcb
->save
.star
= data
;
3825 #ifdef CONFIG_X86_64
3827 svm
->vmcb
->save
.lstar
= data
;
3830 svm
->vmcb
->save
.cstar
= data
;
3832 case MSR_KERNEL_GS_BASE
:
3833 svm
->vmcb
->save
.kernel_gs_base
= data
;
3835 case MSR_SYSCALL_MASK
:
3836 svm
->vmcb
->save
.sfmask
= data
;
3839 case MSR_IA32_SYSENTER_CS
:
3840 svm
->vmcb
->save
.sysenter_cs
= data
;
3842 case MSR_IA32_SYSENTER_EIP
:
3843 svm
->sysenter_eip
= data
;
3844 svm
->vmcb
->save
.sysenter_eip
= data
;
3846 case MSR_IA32_SYSENTER_ESP
:
3847 svm
->sysenter_esp
= data
;
3848 svm
->vmcb
->save
.sysenter_esp
= data
;
3851 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
3855 * This is rare, so we update the MSR here instead of using
3856 * direct_access_msrs. Doing that would require a rdmsr in
3859 svm
->tsc_aux
= data
;
3860 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
3862 case MSR_IA32_DEBUGCTLMSR
:
3863 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3864 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3868 if (data
& DEBUGCTL_RESERVED_BITS
)
3871 svm
->vmcb
->save
.dbgctl
= data
;
3872 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3873 if (data
& (1ULL<<0))
3874 svm_enable_lbrv(svm
);
3876 svm_disable_lbrv(svm
);
3878 case MSR_VM_HSAVE_PA
:
3879 svm
->nested
.hsave_msr
= data
;
3882 return svm_set_vm_cr(vcpu
, data
);
3884 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3886 case MSR_IA32_APICBASE
:
3887 if (kvm_vcpu_apicv_active(vcpu
))
3888 avic_update_vapic_bar(to_svm(vcpu
), data
);
3889 /* Follow through */
3891 return kvm_set_msr_common(vcpu
, msr
);
3896 static int wrmsr_interception(struct vcpu_svm
*svm
)
3898 struct msr_data msr
;
3899 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3900 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
3904 msr
.host_initiated
= false;
3906 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3907 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
3908 trace_kvm_msr_write_ex(ecx
, data
);
3909 kvm_inject_gp(&svm
->vcpu
, 0);
3912 trace_kvm_msr_write(ecx
, data
);
3913 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3917 static int msr_interception(struct vcpu_svm
*svm
)
3919 if (svm
->vmcb
->control
.exit_info_1
)
3920 return wrmsr_interception(svm
);
3922 return rdmsr_interception(svm
);
3925 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3927 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3928 svm_clear_vintr(svm
);
3929 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3930 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3931 ++svm
->vcpu
.stat
.irq_window_exits
;
3935 static int pause_interception(struct vcpu_svm
*svm
)
3937 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3938 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
3940 kvm_vcpu_on_spin(vcpu
, in_kernel
);
3944 static int nop_interception(struct vcpu_svm
*svm
)
3946 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
3949 static int monitor_interception(struct vcpu_svm
*svm
)
3951 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
3952 return nop_interception(svm
);
3955 static int mwait_interception(struct vcpu_svm
*svm
)
3957 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
3958 return nop_interception(svm
);
3961 enum avic_ipi_failure_cause
{
3962 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
3963 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
3964 AVIC_IPI_FAILURE_INVALID_TARGET
,
3965 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
3968 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
3970 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
3971 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
3972 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
3973 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
3974 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
3976 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
3979 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
3981 * AVIC hardware handles the generation of
3982 * IPIs when the specified Message Type is Fixed
3983 * (also known as fixed delivery mode) and
3984 * the Trigger Mode is edge-triggered. The hardware
3985 * also supports self and broadcast delivery modes
3986 * specified via the Destination Shorthand(DSH)
3987 * field of the ICRL. Logical and physical APIC ID
3988 * formats are supported. All other IPI types cause
3989 * a #VMEXIT, which needs to emulated.
3991 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
3992 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
3994 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
3996 struct kvm_vcpu
*vcpu
;
3997 struct kvm
*kvm
= svm
->vcpu
.kvm
;
3998 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4001 * At this point, we expect that the AVIC HW has already
4002 * set the appropriate IRR bits on the valid target
4003 * vcpus. So, we just need to kick the appropriate vcpu.
4005 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
4006 bool m
= kvm_apic_match_dest(vcpu
, apic
,
4007 icrl
& KVM_APIC_SHORT_MASK
,
4008 GET_APIC_DEST_FIELD(icrh
),
4009 icrl
& KVM_APIC_DEST_MASK
);
4011 if (m
&& !avic_vcpu_is_running(vcpu
))
4012 kvm_vcpu_wake_up(vcpu
);
4016 case AVIC_IPI_FAILURE_INVALID_TARGET
:
4018 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
4019 WARN_ONCE(1, "Invalid backing page\n");
4022 pr_err("Unknown IPI interception\n");
4028 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
4030 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
4032 u32
*logical_apic_id_table
;
4033 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
4038 if (flat
) { /* flat */
4039 index
= ffs(dlid
) - 1;
4042 } else { /* cluster */
4043 int cluster
= (dlid
& 0xf0) >> 4;
4044 int apic
= ffs(dlid
& 0x0f) - 1;
4046 if ((apic
< 0) || (apic
> 7) ||
4049 index
= (cluster
<< 2) + apic
;
4052 logical_apic_id_table
= (u32
*) page_address(vm_data
->avic_logical_id_table_page
);
4054 return &logical_apic_id_table
[index
];
4057 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
4061 u32
*entry
, new_entry
;
4063 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
4064 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
4068 new_entry
= READ_ONCE(*entry
);
4069 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
4070 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
4072 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4074 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4075 WRITE_ONCE(*entry
, new_entry
);
4080 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
4083 struct vcpu_svm
*svm
= to_svm(vcpu
);
4084 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
4089 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
4090 if (ret
&& svm
->ldr_reg
) {
4091 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
4099 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
4102 struct vcpu_svm
*svm
= to_svm(vcpu
);
4103 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
4104 u32 id
= (apic_id_reg
>> 24) & 0xff;
4106 if (vcpu
->vcpu_id
== id
)
4109 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
4110 new = avic_get_physical_id_entry(vcpu
, id
);
4114 /* We need to move physical_id_entry to new offset */
4117 to_svm(vcpu
)->avic_physical_id_cache
= new;
4120 * Also update the guest physical APIC ID in the logical
4121 * APIC ID table entry if already setup the LDR.
4124 avic_handle_ldr_update(vcpu
);
4129 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
4131 struct vcpu_svm
*svm
= to_svm(vcpu
);
4132 struct kvm_arch
*vm_data
= &vcpu
->kvm
->arch
;
4133 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
4134 u32 mod
= (dfr
>> 28) & 0xf;
4137 * We assume that all local APICs are using the same type.
4138 * If this changes, we need to flush the AVIC logical
4141 if (vm_data
->ldr_mode
== mod
)
4144 clear_page(page_address(vm_data
->avic_logical_id_table_page
));
4145 vm_data
->ldr_mode
= mod
;
4148 avic_handle_ldr_update(vcpu
);
4152 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4154 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4155 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4156 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4160 if (avic_handle_apic_id_update(&svm
->vcpu
))
4164 if (avic_handle_ldr_update(&svm
->vcpu
))
4168 avic_handle_dfr_update(&svm
->vcpu
);
4174 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4179 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4208 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4211 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4212 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4213 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4214 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4215 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4216 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4217 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4219 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4220 trap
, write
, vector
);
4223 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4224 ret
= avic_unaccel_trap_write(svm
);
4226 /* Handling Fault */
4227 ret
= (emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4233 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4234 [SVM_EXIT_READ_CR0
] = cr_interception
,
4235 [SVM_EXIT_READ_CR3
] = cr_interception
,
4236 [SVM_EXIT_READ_CR4
] = cr_interception
,
4237 [SVM_EXIT_READ_CR8
] = cr_interception
,
4238 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4239 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4240 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4241 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4242 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4243 [SVM_EXIT_READ_DR0
] = dr_interception
,
4244 [SVM_EXIT_READ_DR1
] = dr_interception
,
4245 [SVM_EXIT_READ_DR2
] = dr_interception
,
4246 [SVM_EXIT_READ_DR3
] = dr_interception
,
4247 [SVM_EXIT_READ_DR4
] = dr_interception
,
4248 [SVM_EXIT_READ_DR5
] = dr_interception
,
4249 [SVM_EXIT_READ_DR6
] = dr_interception
,
4250 [SVM_EXIT_READ_DR7
] = dr_interception
,
4251 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4252 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4253 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4254 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4255 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4256 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4257 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4258 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4259 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4260 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4261 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4262 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4263 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4264 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4265 [SVM_EXIT_INTR
] = intr_interception
,
4266 [SVM_EXIT_NMI
] = nmi_interception
,
4267 [SVM_EXIT_SMI
] = nop_on_interception
,
4268 [SVM_EXIT_INIT
] = nop_on_interception
,
4269 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4270 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4271 [SVM_EXIT_CPUID
] = cpuid_interception
,
4272 [SVM_EXIT_IRET
] = iret_interception
,
4273 [SVM_EXIT_INVD
] = emulate_on_interception
,
4274 [SVM_EXIT_PAUSE
] = pause_interception
,
4275 [SVM_EXIT_HLT
] = halt_interception
,
4276 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4277 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4278 [SVM_EXIT_IOIO
] = io_interception
,
4279 [SVM_EXIT_MSR
] = msr_interception
,
4280 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4281 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4282 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4283 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4284 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4285 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4286 [SVM_EXIT_STGI
] = stgi_interception
,
4287 [SVM_EXIT_CLGI
] = clgi_interception
,
4288 [SVM_EXIT_SKINIT
] = skinit_interception
,
4289 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4290 [SVM_EXIT_MONITOR
] = monitor_interception
,
4291 [SVM_EXIT_MWAIT
] = mwait_interception
,
4292 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4293 [SVM_EXIT_NPF
] = npf_interception
,
4294 [SVM_EXIT_RSM
] = emulate_on_interception
,
4295 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4296 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4299 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4301 struct vcpu_svm
*svm
= to_svm(vcpu
);
4302 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4303 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4305 pr_err("VMCB Control Area:\n");
4306 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4307 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4308 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4309 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4310 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4311 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4312 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4313 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4314 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4315 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4316 pr_err("%-20s%d\n", "asid:", control
->asid
);
4317 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4318 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4319 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4320 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4321 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4322 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4323 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4324 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4325 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4326 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4327 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4328 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4329 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4330 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4331 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4332 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4333 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4334 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4335 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4336 pr_err("VMCB State Save Area:\n");
4337 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4339 save
->es
.selector
, save
->es
.attrib
,
4340 save
->es
.limit
, save
->es
.base
);
4341 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4343 save
->cs
.selector
, save
->cs
.attrib
,
4344 save
->cs
.limit
, save
->cs
.base
);
4345 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4347 save
->ss
.selector
, save
->ss
.attrib
,
4348 save
->ss
.limit
, save
->ss
.base
);
4349 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4351 save
->ds
.selector
, save
->ds
.attrib
,
4352 save
->ds
.limit
, save
->ds
.base
);
4353 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4355 save
->fs
.selector
, save
->fs
.attrib
,
4356 save
->fs
.limit
, save
->fs
.base
);
4357 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4359 save
->gs
.selector
, save
->gs
.attrib
,
4360 save
->gs
.limit
, save
->gs
.base
);
4361 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4363 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4364 save
->gdtr
.limit
, save
->gdtr
.base
);
4365 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4367 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4368 save
->ldtr
.limit
, save
->ldtr
.base
);
4369 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4371 save
->idtr
.selector
, save
->idtr
.attrib
,
4372 save
->idtr
.limit
, save
->idtr
.base
);
4373 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4375 save
->tr
.selector
, save
->tr
.attrib
,
4376 save
->tr
.limit
, save
->tr
.base
);
4377 pr_err("cpl: %d efer: %016llx\n",
4378 save
->cpl
, save
->efer
);
4379 pr_err("%-15s %016llx %-13s %016llx\n",
4380 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4381 pr_err("%-15s %016llx %-13s %016llx\n",
4382 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4383 pr_err("%-15s %016llx %-13s %016llx\n",
4384 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4385 pr_err("%-15s %016llx %-13s %016llx\n",
4386 "rip:", save
->rip
, "rflags:", save
->rflags
);
4387 pr_err("%-15s %016llx %-13s %016llx\n",
4388 "rsp:", save
->rsp
, "rax:", save
->rax
);
4389 pr_err("%-15s %016llx %-13s %016llx\n",
4390 "star:", save
->star
, "lstar:", save
->lstar
);
4391 pr_err("%-15s %016llx %-13s %016llx\n",
4392 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4393 pr_err("%-15s %016llx %-13s %016llx\n",
4394 "kernel_gs_base:", save
->kernel_gs_base
,
4395 "sysenter_cs:", save
->sysenter_cs
);
4396 pr_err("%-15s %016llx %-13s %016llx\n",
4397 "sysenter_esp:", save
->sysenter_esp
,
4398 "sysenter_eip:", save
->sysenter_eip
);
4399 pr_err("%-15s %016llx %-13s %016llx\n",
4400 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4401 pr_err("%-15s %016llx %-13s %016llx\n",
4402 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4403 pr_err("%-15s %016llx %-13s %016llx\n",
4404 "excp_from:", save
->last_excp_from
,
4405 "excp_to:", save
->last_excp_to
);
4408 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4410 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4412 *info1
= control
->exit_info_1
;
4413 *info2
= control
->exit_info_2
;
4416 static int handle_exit(struct kvm_vcpu
*vcpu
)
4418 struct vcpu_svm
*svm
= to_svm(vcpu
);
4419 struct kvm_run
*kvm_run
= vcpu
->run
;
4420 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4422 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4424 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4425 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4427 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4429 if (unlikely(svm
->nested
.exit_required
)) {
4430 nested_svm_vmexit(svm
);
4431 svm
->nested
.exit_required
= false;
4436 if (is_guest_mode(vcpu
)) {
4439 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4440 svm
->vmcb
->control
.exit_info_1
,
4441 svm
->vmcb
->control
.exit_info_2
,
4442 svm
->vmcb
->control
.exit_int_info
,
4443 svm
->vmcb
->control
.exit_int_info_err
,
4446 vmexit
= nested_svm_exit_special(svm
);
4448 if (vmexit
== NESTED_EXIT_CONTINUE
)
4449 vmexit
= nested_svm_exit_handled(svm
);
4451 if (vmexit
== NESTED_EXIT_DONE
)
4455 svm_complete_interrupts(svm
);
4457 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4458 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4459 kvm_run
->fail_entry
.hardware_entry_failure_reason
4460 = svm
->vmcb
->control
.exit_code
;
4461 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4466 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4467 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4468 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4469 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4470 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4472 __func__
, svm
->vmcb
->control
.exit_int_info
,
4475 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4476 || !svm_exit_handlers
[exit_code
]) {
4477 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4478 kvm_queue_exception(vcpu
, UD_VECTOR
);
4482 return svm_exit_handlers
[exit_code
](svm
);
4485 static void reload_tss(struct kvm_vcpu
*vcpu
)
4487 int cpu
= raw_smp_processor_id();
4489 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4490 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4494 static void pre_svm_run(struct vcpu_svm
*svm
)
4496 int cpu
= raw_smp_processor_id();
4498 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4500 /* FIXME: handle wraparound of asid_generation */
4501 if (svm
->asid_generation
!= sd
->asid_generation
)
4505 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
4507 struct vcpu_svm
*svm
= to_svm(vcpu
);
4509 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
4510 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
4511 set_intercept(svm
, INTERCEPT_IRET
);
4512 ++vcpu
->stat
.nmi_injections
;
4515 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
4517 struct vmcb_control_area
*control
;
4519 /* The following fields are ignored when AVIC is enabled */
4520 control
= &svm
->vmcb
->control
;
4521 control
->int_vector
= irq
;
4522 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
4523 control
->int_ctl
|= V_IRQ_MASK
|
4524 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
4525 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4528 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
4530 struct vcpu_svm
*svm
= to_svm(vcpu
);
4532 BUG_ON(!(gif_set(svm
)));
4534 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
4535 ++vcpu
->stat
.irq_injections
;
4537 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
4538 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
4541 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
4543 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
4546 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
4548 struct vcpu_svm
*svm
= to_svm(vcpu
);
4550 if (svm_nested_virtualize_tpr(vcpu
) ||
4551 kvm_vcpu_apicv_active(vcpu
))
4554 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4560 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
4563 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
4568 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
4570 return avic
&& irqchip_split(vcpu
->kvm
);
4573 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
4577 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
4581 /* Note: Currently only used by Hyper-V. */
4582 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4584 struct vcpu_svm
*svm
= to_svm(vcpu
);
4585 struct vmcb
*vmcb
= svm
->vmcb
;
4587 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
4590 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
4591 mark_dirty(vmcb
, VMCB_INTR
);
4594 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
4599 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
4601 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
4602 smp_mb__after_atomic();
4604 if (avic_vcpu_is_running(vcpu
))
4605 wrmsrl(SVM_AVIC_DOORBELL
,
4606 kvm_cpu_get_apicid(vcpu
->cpu
));
4608 kvm_vcpu_wake_up(vcpu
);
4611 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4613 unsigned long flags
;
4614 struct amd_svm_iommu_ir
*cur
;
4616 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4617 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
4618 if (cur
->data
!= pi
->ir_data
)
4620 list_del(&cur
->node
);
4624 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4627 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
4630 unsigned long flags
;
4631 struct amd_svm_iommu_ir
*ir
;
4634 * In some cases, the existing irte is updaed and re-set,
4635 * so we need to check here if it's already been * added
4638 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
4639 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4640 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
4641 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
4642 struct vcpu_svm
*prev_svm
;
4649 prev_svm
= to_svm(prev_vcpu
);
4650 svm_ir_list_del(prev_svm
, pi
);
4654 * Allocating new amd_iommu_pi_data, which will get
4655 * add to the per-vcpu ir_list.
4657 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
4662 ir
->data
= pi
->ir_data
;
4664 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
4665 list_add(&ir
->node
, &svm
->ir_list
);
4666 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
4673 * The HW cannot support posting multicast/broadcast
4674 * interrupts to a vCPU. So, we still use legacy interrupt
4675 * remapping for these kind of interrupts.
4677 * For lowest-priority interrupts, we only support
4678 * those with single CPU as the destination, e.g. user
4679 * configures the interrupts via /proc/irq or uses
4680 * irqbalance to make the interrupts single-CPU.
4683 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
4684 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
4686 struct kvm_lapic_irq irq
;
4687 struct kvm_vcpu
*vcpu
= NULL
;
4689 kvm_set_msi_irq(kvm
, e
, &irq
);
4691 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
4692 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4693 __func__
, irq
.vector
);
4697 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
4699 *svm
= to_svm(vcpu
);
4700 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
4701 vcpu_info
->vector
= irq
.vector
;
4707 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4710 * @host_irq: host irq of the interrupt
4711 * @guest_irq: gsi of the interrupt
4712 * @set: set or unset PI
4713 * returns 0 on success, < 0 on failure
4715 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
4716 uint32_t guest_irq
, bool set
)
4718 struct kvm_kernel_irq_routing_entry
*e
;
4719 struct kvm_irq_routing_table
*irq_rt
;
4720 int idx
, ret
= -EINVAL
;
4722 if (!kvm_arch_has_assigned_device(kvm
) ||
4723 !irq_remapping_cap(IRQ_POSTING_CAP
))
4726 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4727 __func__
, host_irq
, guest_irq
, set
);
4729 idx
= srcu_read_lock(&kvm
->irq_srcu
);
4730 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
4731 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
4733 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
4734 struct vcpu_data vcpu_info
;
4735 struct vcpu_svm
*svm
= NULL
;
4737 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
4741 * Here, we setup with legacy mode in the following cases:
4742 * 1. When cannot target interrupt to a specific vcpu.
4743 * 2. Unsetting posted interrupt.
4744 * 3. APIC virtialization is disabled for the vcpu.
4746 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
4747 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
4748 struct amd_iommu_pi_data pi
;
4750 /* Try to enable guest_mode in IRTE */
4751 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
4753 pi
.ga_tag
= AVIC_GATAG(kvm
->arch
.avic_vm_id
,
4755 pi
.is_guest_mode
= true;
4756 pi
.vcpu_data
= &vcpu_info
;
4757 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4760 * Here, we successfully setting up vcpu affinity in
4761 * IOMMU guest mode. Now, we need to store the posted
4762 * interrupt information in a per-vcpu ir_list so that
4763 * we can reference to them directly when we update vcpu
4764 * scheduling information in IOMMU irte.
4766 if (!ret
&& pi
.is_guest_mode
)
4767 svm_ir_list_add(svm
, &pi
);
4769 /* Use legacy mode in IRTE */
4770 struct amd_iommu_pi_data pi
;
4773 * Here, pi is used to:
4774 * - Tell IOMMU to use legacy mode for this interrupt.
4775 * - Retrieve ga_tag of prior interrupt remapping data.
4777 pi
.is_guest_mode
= false;
4778 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
4781 * Check if the posted interrupt was previously
4782 * setup with the guest_mode by checking if the ga_tag
4783 * was cached. If so, we need to clean up the per-vcpu
4786 if (!ret
&& pi
.prev_ga_tag
) {
4787 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
4788 struct kvm_vcpu
*vcpu
;
4790 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
4792 svm_ir_list_del(to_svm(vcpu
), &pi
);
4797 trace_kvm_pi_irte_update(host_irq
, svm
->vcpu
.vcpu_id
,
4798 e
->gsi
, vcpu_info
.vector
,
4799 vcpu_info
.pi_desc_addr
, set
);
4803 pr_err("%s: failed to update PI IRTE\n", __func__
);
4810 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
4814 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
4816 struct vcpu_svm
*svm
= to_svm(vcpu
);
4817 struct vmcb
*vmcb
= svm
->vmcb
;
4819 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
4820 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4821 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
4826 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4828 struct vcpu_svm
*svm
= to_svm(vcpu
);
4830 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
4833 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4835 struct vcpu_svm
*svm
= to_svm(vcpu
);
4838 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
4839 set_intercept(svm
, INTERCEPT_IRET
);
4841 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
4842 clr_intercept(svm
, INTERCEPT_IRET
);
4846 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4848 struct vcpu_svm
*svm
= to_svm(vcpu
);
4849 struct vmcb
*vmcb
= svm
->vmcb
;
4852 if (!gif_set(svm
) ||
4853 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
4856 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
4858 if (is_guest_mode(vcpu
))
4859 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
4864 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4866 struct vcpu_svm
*svm
= to_svm(vcpu
);
4868 if (kvm_vcpu_apicv_active(vcpu
))
4872 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4873 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4874 * get that intercept, this function will be called again though and
4875 * we'll get the vintr intercept. However, if the vGIF feature is
4876 * enabled, the STGI interception will not occur. Enable the irq
4877 * window under the assumption that the hardware will set the GIF.
4879 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
4881 svm_inject_irq(svm
, 0x0);
4885 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4887 struct vcpu_svm
*svm
= to_svm(vcpu
);
4889 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
4891 return; /* IRET will cause a vm exit */
4893 if (!gif_set(svm
)) {
4894 if (vgif_enabled(svm
))
4895 set_intercept(svm
, INTERCEPT_STGI
);
4896 return; /* STGI will cause a vm exit */
4899 if (svm
->nested
.exit_required
)
4900 return; /* we're not going to run the guest yet */
4903 * Something prevents NMI from been injected. Single step over possible
4904 * problem (IRET or exception injection or interrupt shadow)
4906 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
4907 svm
->nmi_singlestep
= true;
4908 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
4911 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4916 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
4918 struct vcpu_svm
*svm
= to_svm(vcpu
);
4920 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
4921 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4923 svm
->asid_generation
--;
4926 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
4930 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
4932 struct vcpu_svm
*svm
= to_svm(vcpu
);
4934 if (svm_nested_virtualize_tpr(vcpu
))
4937 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
4938 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
4939 kvm_set_cr8(vcpu
, cr8
);
4943 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
4945 struct vcpu_svm
*svm
= to_svm(vcpu
);
4948 if (svm_nested_virtualize_tpr(vcpu
) ||
4949 kvm_vcpu_apicv_active(vcpu
))
4952 cr8
= kvm_get_cr8(vcpu
);
4953 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
4954 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
4957 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
4961 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
4962 unsigned int3_injected
= svm
->int3_injected
;
4964 svm
->int3_injected
= 0;
4967 * If we've made progress since setting HF_IRET_MASK, we've
4968 * executed an IRET and can allow NMI injection.
4970 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
4971 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
4972 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
4973 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4976 svm
->vcpu
.arch
.nmi_injected
= false;
4977 kvm_clear_exception_queue(&svm
->vcpu
);
4978 kvm_clear_interrupt_queue(&svm
->vcpu
);
4980 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
4983 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4985 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
4986 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
4989 case SVM_EXITINTINFO_TYPE_NMI
:
4990 svm
->vcpu
.arch
.nmi_injected
= true;
4992 case SVM_EXITINTINFO_TYPE_EXEPT
:
4994 * In case of software exceptions, do not reinject the vector,
4995 * but re-execute the instruction instead. Rewind RIP first
4996 * if we emulated INT3 before.
4998 if (kvm_exception_is_soft(vector
)) {
4999 if (vector
== BP_VECTOR
&& int3_injected
&&
5000 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
5001 kvm_rip_write(&svm
->vcpu
,
5002 kvm_rip_read(&svm
->vcpu
) -
5006 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
5007 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
5008 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
5011 kvm_requeue_exception(&svm
->vcpu
, vector
);
5013 case SVM_EXITINTINFO_TYPE_INTR
:
5014 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
5021 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
5023 struct vcpu_svm
*svm
= to_svm(vcpu
);
5024 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
5026 control
->exit_int_info
= control
->event_inj
;
5027 control
->exit_int_info_err
= control
->event_inj_err
;
5028 control
->event_inj
= 0;
5029 svm_complete_interrupts(svm
);
5032 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
5034 struct vcpu_svm
*svm
= to_svm(vcpu
);
5036 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5037 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5038 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5041 * A vmexit emulation is required before the vcpu can be executed
5044 if (unlikely(svm
->nested
.exit_required
))
5048 * Disable singlestep if we're injecting an interrupt/exception.
5049 * We don't want our modified rflags to be pushed on the stack where
5050 * we might not be able to easily reset them if we disabled NMI
5053 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
5055 * Event injection happens before external interrupts cause a
5056 * vmexit and interrupts are disabled here, so smp_send_reschedule
5057 * is enough to force an immediate vmexit.
5059 disable_nmi_singlestep(svm
);
5060 smp_send_reschedule(vcpu
->cpu
);
5065 sync_lapic_to_cr8(vcpu
);
5067 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
5072 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5073 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5074 * is no need to worry about the conditional branch over the wrmsr
5075 * being speculatively taken.
5077 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5082 "push %%" _ASM_BP
"; \n\t"
5083 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
5084 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
5085 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
5086 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
5087 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
5088 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
5089 #ifdef CONFIG_X86_64
5090 "mov %c[r8](%[svm]), %%r8 \n\t"
5091 "mov %c[r9](%[svm]), %%r9 \n\t"
5092 "mov %c[r10](%[svm]), %%r10 \n\t"
5093 "mov %c[r11](%[svm]), %%r11 \n\t"
5094 "mov %c[r12](%[svm]), %%r12 \n\t"
5095 "mov %c[r13](%[svm]), %%r13 \n\t"
5096 "mov %c[r14](%[svm]), %%r14 \n\t"
5097 "mov %c[r15](%[svm]), %%r15 \n\t"
5100 /* Enter guest mode */
5101 "push %%" _ASM_AX
" \n\t"
5102 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
5103 __ex(SVM_VMLOAD
) "\n\t"
5104 __ex(SVM_VMRUN
) "\n\t"
5105 __ex(SVM_VMSAVE
) "\n\t"
5106 "pop %%" _ASM_AX
" \n\t"
5108 /* Save guest registers, load host registers */
5109 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
5110 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
5111 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
5112 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
5113 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
5114 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
5115 #ifdef CONFIG_X86_64
5116 "mov %%r8, %c[r8](%[svm]) \n\t"
5117 "mov %%r9, %c[r9](%[svm]) \n\t"
5118 "mov %%r10, %c[r10](%[svm]) \n\t"
5119 "mov %%r11, %c[r11](%[svm]) \n\t"
5120 "mov %%r12, %c[r12](%[svm]) \n\t"
5121 "mov %%r13, %c[r13](%[svm]) \n\t"
5122 "mov %%r14, %c[r14](%[svm]) \n\t"
5123 "mov %%r15, %c[r15](%[svm]) \n\t"
5126 * Clear host registers marked as clobbered to prevent
5129 "xor %%" _ASM_BX
", %%" _ASM_BX
" \n\t"
5130 "xor %%" _ASM_CX
", %%" _ASM_CX
" \n\t"
5131 "xor %%" _ASM_DX
", %%" _ASM_DX
" \n\t"
5132 "xor %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
5133 "xor %%" _ASM_DI
", %%" _ASM_DI
" \n\t"
5134 #ifdef CONFIG_X86_64
5135 "xor %%r8, %%r8 \n\t"
5136 "xor %%r9, %%r9 \n\t"
5137 "xor %%r10, %%r10 \n\t"
5138 "xor %%r11, %%r11 \n\t"
5139 "xor %%r12, %%r12 \n\t"
5140 "xor %%r13, %%r13 \n\t"
5141 "xor %%r14, %%r14 \n\t"
5142 "xor %%r15, %%r15 \n\t"
5147 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
5148 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5149 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5150 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5151 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5152 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5153 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
5154 #ifdef CONFIG_X86_64
5155 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5156 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5157 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5158 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5159 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5160 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5161 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5162 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
5165 #ifdef CONFIG_X86_64
5166 , "rbx", "rcx", "rdx", "rsi", "rdi"
5167 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5169 , "ebx", "ecx", "edx", "esi", "edi"
5173 /* Eliminate branch target predictions from guest mode */
5176 #ifdef CONFIG_X86_64
5177 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5179 loadsegment(fs
, svm
->host
.fs
);
5180 #ifndef CONFIG_X86_32_LAZY_GS
5181 loadsegment(gs
, svm
->host
.gs
);
5186 * We do not use IBRS in the kernel. If this vCPU has used the
5187 * SPEC_CTRL MSR it may have left it on; save the value and
5188 * turn it off. This is much more efficient than blindly adding
5189 * it to the atomic save/restore list. Especially as the former
5190 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5192 * For non-nested case:
5193 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5197 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5200 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
5201 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
5205 local_irq_disable();
5207 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5209 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5210 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5211 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5212 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5214 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5215 kvm_before_handle_nmi(&svm
->vcpu
);
5219 /* Any pending NMI will happen here */
5221 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5222 kvm_after_handle_nmi(&svm
->vcpu
);
5224 sync_cr8_to_lapic(vcpu
);
5228 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5230 /* if exit due to PF check for async PF */
5231 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5232 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5235 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5236 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5240 * We need to handle MC intercepts here before the vcpu has a chance to
5241 * change the physical cpu
5243 if (unlikely(svm
->vmcb
->control
.exit_code
==
5244 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5245 svm_handle_mce(svm
);
5247 mark_all_clean(svm
->vmcb
);
5249 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5251 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5253 struct vcpu_svm
*svm
= to_svm(vcpu
);
5255 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5256 mark_dirty(svm
->vmcb
, VMCB_CR
);
5257 svm_flush_tlb(vcpu
);
5260 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5262 struct vcpu_svm
*svm
= to_svm(vcpu
);
5264 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5265 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5267 /* Also sync guest cr3 here in case we live migrate */
5268 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5269 mark_dirty(svm
->vmcb
, VMCB_CR
);
5271 svm_flush_tlb(vcpu
);
5274 static int is_disabled(void)
5278 rdmsrl(MSR_VM_CR
, vm_cr
);
5279 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5286 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5289 * Patch in the VMMCALL instruction:
5291 hypercall
[0] = 0x0f;
5292 hypercall
[1] = 0x01;
5293 hypercall
[2] = 0xd9;
5296 static void svm_check_processor_compat(void *rtn
)
5301 static bool svm_cpu_has_accelerated_tpr(void)
5306 static bool svm_has_emulated_msr(int index
)
5311 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5316 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5318 struct vcpu_svm
*svm
= to_svm(vcpu
);
5320 /* Update nrips enabled cache */
5321 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5323 if (!kvm_vcpu_apicv_active(vcpu
))
5326 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5329 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5334 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5338 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5341 entry
->eax
= 1; /* SVM revision 1 */
5342 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5343 ASID emulation to nested SVM */
5344 entry
->ecx
= 0; /* Reserved */
5345 entry
->edx
= 0; /* Per default do not support any
5346 additional features */
5348 /* Support next_rip if host supports it */
5349 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5350 entry
->edx
|= SVM_FEATURE_NRIP
;
5352 /* Support NPT for the guest if enabled */
5354 entry
->edx
|= SVM_FEATURE_NPT
;
5360 static int svm_get_lpage_level(void)
5362 return PT_PDPE_LEVEL
;
5365 static bool svm_rdtscp_supported(void)
5367 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5370 static bool svm_invpcid_supported(void)
5375 static bool svm_mpx_supported(void)
5380 static bool svm_xsaves_supported(void)
5385 static bool svm_has_wbinvd_exit(void)
5390 #define PRE_EX(exit) { .exit_code = (exit), \
5391 .stage = X86_ICPT_PRE_EXCEPT, }
5392 #define POST_EX(exit) { .exit_code = (exit), \
5393 .stage = X86_ICPT_POST_EXCEPT, }
5394 #define POST_MEM(exit) { .exit_code = (exit), \
5395 .stage = X86_ICPT_POST_MEMACCESS, }
5397 static const struct __x86_intercept
{
5399 enum x86_intercept_stage stage
;
5400 } x86_intercept_map
[] = {
5401 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5402 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5403 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5404 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5405 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5406 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5407 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5408 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5409 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5410 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5411 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5412 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5413 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5414 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5415 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5416 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5417 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5418 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5419 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5420 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5421 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5422 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5423 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5424 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5425 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5426 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5427 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5428 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5429 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5430 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5431 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5432 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5433 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5434 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5435 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5436 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5437 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5438 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5439 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5440 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5441 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5442 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5443 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5444 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5445 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5446 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5453 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5454 struct x86_instruction_info
*info
,
5455 enum x86_intercept_stage stage
)
5457 struct vcpu_svm
*svm
= to_svm(vcpu
);
5458 int vmexit
, ret
= X86EMUL_CONTINUE
;
5459 struct __x86_intercept icpt_info
;
5460 struct vmcb
*vmcb
= svm
->vmcb
;
5462 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5465 icpt_info
= x86_intercept_map
[info
->intercept
];
5467 if (stage
!= icpt_info
.stage
)
5470 switch (icpt_info
.exit_code
) {
5471 case SVM_EXIT_READ_CR0
:
5472 if (info
->intercept
== x86_intercept_cr_read
)
5473 icpt_info
.exit_code
+= info
->modrm_reg
;
5475 case SVM_EXIT_WRITE_CR0
: {
5476 unsigned long cr0
, val
;
5479 if (info
->intercept
== x86_intercept_cr_write
)
5480 icpt_info
.exit_code
+= info
->modrm_reg
;
5482 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
5483 info
->intercept
== x86_intercept_clts
)
5486 intercept
= svm
->nested
.intercept
;
5488 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
5491 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
5492 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
5494 if (info
->intercept
== x86_intercept_lmsw
) {
5497 /* lmsw can't clear PE - catch this here */
5498 if (cr0
& X86_CR0_PE
)
5503 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
5507 case SVM_EXIT_READ_DR0
:
5508 case SVM_EXIT_WRITE_DR0
:
5509 icpt_info
.exit_code
+= info
->modrm_reg
;
5512 if (info
->intercept
== x86_intercept_wrmsr
)
5513 vmcb
->control
.exit_info_1
= 1;
5515 vmcb
->control
.exit_info_1
= 0;
5517 case SVM_EXIT_PAUSE
:
5519 * We get this for NOP only, but pause
5520 * is rep not, check this here
5522 if (info
->rep_prefix
!= REPE_PREFIX
)
5525 case SVM_EXIT_IOIO
: {
5529 if (info
->intercept
== x86_intercept_in
||
5530 info
->intercept
== x86_intercept_ins
) {
5531 exit_info
= ((info
->src_val
& 0xffff) << 16) |
5533 bytes
= info
->dst_bytes
;
5535 exit_info
= (info
->dst_val
& 0xffff) << 16;
5536 bytes
= info
->src_bytes
;
5539 if (info
->intercept
== x86_intercept_outs
||
5540 info
->intercept
== x86_intercept_ins
)
5541 exit_info
|= SVM_IOIO_STR_MASK
;
5543 if (info
->rep_prefix
)
5544 exit_info
|= SVM_IOIO_REP_MASK
;
5546 bytes
= min(bytes
, 4u);
5548 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
5550 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
5552 vmcb
->control
.exit_info_1
= exit_info
;
5553 vmcb
->control
.exit_info_2
= info
->next_rip
;
5561 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5562 if (static_cpu_has(X86_FEATURE_NRIPS
))
5563 vmcb
->control
.next_rip
= info
->next_rip
;
5564 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
5565 vmexit
= nested_svm_exit_handled(svm
);
5567 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
5574 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
5578 * We must have an instruction with interrupts enabled, so
5579 * the timer interrupt isn't delayed by the interrupt shadow.
5582 local_irq_disable();
5585 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
5589 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
5591 if (avic_handle_apic_id_update(vcpu
) != 0)
5593 if (avic_handle_dfr_update(vcpu
) != 0)
5595 avic_handle_ldr_update(vcpu
);
5598 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
5600 /* [63:9] are reserved. */
5601 vcpu
->arch
.mcg_cap
&= 0x1ff;
5604 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
5606 struct vcpu_svm
*svm
= to_svm(vcpu
);
5608 /* Per APM Vol.2 15.22.2 "Response to SMI" */
5612 if (is_guest_mode(&svm
->vcpu
) &&
5613 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
5614 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
5615 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
5616 svm
->nested
.exit_required
= true;
5623 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
5625 struct vcpu_svm
*svm
= to_svm(vcpu
);
5628 if (is_guest_mode(vcpu
)) {
5629 /* FED8h - SVM Guest */
5630 put_smstate(u64
, smstate
, 0x7ed8, 1);
5631 /* FEE0h - SVM Guest VMCB Physical Address */
5632 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
5634 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5635 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5636 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5638 ret
= nested_svm_vmexit(svm
);
5645 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
5647 struct vcpu_svm
*svm
= to_svm(vcpu
);
5648 struct vmcb
*nested_vmcb
;
5656 ret
= kvm_vcpu_read_guest(vcpu
, smbase
+ 0xfed8, &svm_state_save
,
5657 sizeof(svm_state_save
));
5661 if (svm_state_save
.guest
) {
5662 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
5663 nested_vmcb
= nested_svm_map(svm
, svm_state_save
.vmcb
, &page
);
5665 enter_svm_guest_mode(svm
, svm_state_save
.vmcb
, nested_vmcb
, page
);
5668 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
5673 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
5675 struct vcpu_svm
*svm
= to_svm(vcpu
);
5677 if (!gif_set(svm
)) {
5678 if (vgif_enabled(svm
))
5679 set_intercept(svm
, INTERCEPT_STGI
);
5680 /* STGI will cause a vm exit */
5686 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
5687 .cpu_has_kvm_support
= has_svm
,
5688 .disabled_by_bios
= is_disabled
,
5689 .hardware_setup
= svm_hardware_setup
,
5690 .hardware_unsetup
= svm_hardware_unsetup
,
5691 .check_processor_compatibility
= svm_check_processor_compat
,
5692 .hardware_enable
= svm_hardware_enable
,
5693 .hardware_disable
= svm_hardware_disable
,
5694 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
5695 .has_emulated_msr
= svm_has_emulated_msr
,
5697 .vcpu_create
= svm_create_vcpu
,
5698 .vcpu_free
= svm_free_vcpu
,
5699 .vcpu_reset
= svm_vcpu_reset
,
5701 .vm_init
= avic_vm_init
,
5702 .vm_destroy
= avic_vm_destroy
,
5704 .prepare_guest_switch
= svm_prepare_guest_switch
,
5705 .vcpu_load
= svm_vcpu_load
,
5706 .vcpu_put
= svm_vcpu_put
,
5707 .vcpu_blocking
= svm_vcpu_blocking
,
5708 .vcpu_unblocking
= svm_vcpu_unblocking
,
5710 .update_bp_intercept
= update_bp_intercept
,
5711 .get_msr_feature
= svm_get_msr_feature
,
5712 .get_msr
= svm_get_msr
,
5713 .set_msr
= svm_set_msr
,
5714 .get_segment_base
= svm_get_segment_base
,
5715 .get_segment
= svm_get_segment
,
5716 .set_segment
= svm_set_segment
,
5717 .get_cpl
= svm_get_cpl
,
5718 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
5719 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
5720 .decache_cr3
= svm_decache_cr3
,
5721 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
5722 .set_cr0
= svm_set_cr0
,
5723 .set_cr3
= svm_set_cr3
,
5724 .set_cr4
= svm_set_cr4
,
5725 .set_efer
= svm_set_efer
,
5726 .get_idt
= svm_get_idt
,
5727 .set_idt
= svm_set_idt
,
5728 .get_gdt
= svm_get_gdt
,
5729 .set_gdt
= svm_set_gdt
,
5730 .get_dr6
= svm_get_dr6
,
5731 .set_dr6
= svm_set_dr6
,
5732 .set_dr7
= svm_set_dr7
,
5733 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
5734 .cache_reg
= svm_cache_reg
,
5735 .get_rflags
= svm_get_rflags
,
5736 .set_rflags
= svm_set_rflags
,
5738 .tlb_flush
= svm_flush_tlb
,
5740 .run
= svm_vcpu_run
,
5741 .handle_exit
= handle_exit
,
5742 .skip_emulated_instruction
= skip_emulated_instruction
,
5743 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
5744 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
5745 .patch_hypercall
= svm_patch_hypercall
,
5746 .set_irq
= svm_set_irq
,
5747 .set_nmi
= svm_inject_nmi
,
5748 .queue_exception
= svm_queue_exception
,
5749 .cancel_injection
= svm_cancel_injection
,
5750 .interrupt_allowed
= svm_interrupt_allowed
,
5751 .nmi_allowed
= svm_nmi_allowed
,
5752 .get_nmi_mask
= svm_get_nmi_mask
,
5753 .set_nmi_mask
= svm_set_nmi_mask
,
5754 .enable_nmi_window
= enable_nmi_window
,
5755 .enable_irq_window
= enable_irq_window
,
5756 .update_cr8_intercept
= update_cr8_intercept
,
5757 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
5758 .get_enable_apicv
= svm_get_enable_apicv
,
5759 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
5760 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
5761 .hwapic_irr_update
= svm_hwapic_irr_update
,
5762 .hwapic_isr_update
= svm_hwapic_isr_update
,
5763 .apicv_post_state_restore
= avic_post_state_restore
,
5765 .set_tss_addr
= svm_set_tss_addr
,
5766 .get_tdp_level
= get_npt_level
,
5767 .get_mt_mask
= svm_get_mt_mask
,
5769 .get_exit_info
= svm_get_exit_info
,
5771 .get_lpage_level
= svm_get_lpage_level
,
5773 .cpuid_update
= svm_cpuid_update
,
5775 .rdtscp_supported
= svm_rdtscp_supported
,
5776 .invpcid_supported
= svm_invpcid_supported
,
5777 .mpx_supported
= svm_mpx_supported
,
5778 .xsaves_supported
= svm_xsaves_supported
,
5780 .set_supported_cpuid
= svm_set_supported_cpuid
,
5782 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
5784 .read_l1_tsc_offset
= svm_read_l1_tsc_offset
,
5785 .write_tsc_offset
= svm_write_tsc_offset
,
5787 .set_tdp_cr3
= set_tdp_cr3
,
5789 .check_intercept
= svm_check_intercept
,
5790 .handle_external_intr
= svm_handle_external_intr
,
5792 .sched_in
= svm_sched_in
,
5794 .pmu_ops
= &amd_pmu_ops
,
5795 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
5796 .update_pi_irte
= svm_update_pi_irte
,
5797 .setup_mce
= svm_setup_mce
,
5799 .smi_allowed
= svm_smi_allowed
,
5800 .pre_enter_smm
= svm_pre_enter_smm
,
5801 .pre_leave_smm
= svm_pre_leave_smm
,
5802 .enable_smi_window
= enable_smi_window
,
5805 static int __init
svm_init(void)
5807 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
5808 __alignof__(struct vcpu_svm
), THIS_MODULE
);
5811 static void __exit
svm_exit(void)
5816 module_init(svm_init
)
5817 module_exit(svm_exit
)